Jiafei Pan | 33d4af4 | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <debug.h> |
| 8 | #include "ls_16550.h" |
| 9 | #include "plat_ls.h" |
| 10 | #include "../../../bl1/bl1_private.h" |
| 11 | |
| 12 | /* Data structure which holds the extents of the trusted SRAM for BL1*/ |
| 13 | static meminfo_t bl1_tzram_layout; |
| 14 | |
| 15 | meminfo_t *bl1_plat_sec_mem_layout(void) |
| 16 | { |
| 17 | return &bl1_tzram_layout; |
| 18 | } |
| 19 | |
| 20 | /******************************************************************************* |
| 21 | * BL1 specific platform actions shared between ARM standard platforms. |
| 22 | ******************************************************************************/ |
| 23 | void ls_bl1_early_platform_setup(void) |
| 24 | { |
| 25 | static console_ls_16550_t console; |
| 26 | |
| 27 | #if !LS1043_DISABLE_TRUSTED_WDOG |
| 28 | /* TODO: Enable watchdog */ |
| 29 | |
| 30 | #endif |
| 31 | |
| 32 | /* Initialize the console to provide early debug support */ |
| 33 | console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK, |
| 34 | LS_TF_UART_BAUDRATE, &console); |
| 35 | |
| 36 | /* Allow BL1 to see the whole Trusted RAM */ |
| 37 | bl1_tzram_layout.total_base = LS_SRAM_BASE; |
| 38 | bl1_tzram_layout.total_size = LS_SRAM_SIZE; |
| 39 | } |
| 40 | |
| 41 | /****************************************************************************** |
| 42 | * Perform the very early platform specific architecture setup shared between |
| 43 | * ARM standard platforms. This only does basic initialization. Later |
| 44 | * architectural setup (bl1_arch_setup()) does not do anything platform |
| 45 | * specific. |
| 46 | *****************************************************************************/ |
| 47 | void ls_bl1_plat_arch_setup(void) |
| 48 | { |
| 49 | ls_setup_page_tables(bl1_tzram_layout.total_base, |
| 50 | bl1_tzram_layout.total_size, |
| 51 | BL_CODE_BASE, |
| 52 | BL1_CODE_END, |
| 53 | BL1_RO_DATA_BASE, |
| 54 | BL1_RO_DATA_END |
| 55 | #if USE_COHERENT_MEM |
| 56 | , BL_COHERENT_RAM_BASE, |
| 57 | BL_COHERENT_RAM_END |
| 58 | #endif |
| 59 | ); |
| 60 | VERBOSE("After setup the page tables\n"); |
| 61 | #ifdef AARCH32 |
Antonio Nino Diaz | 4c72c3f | 2018-08-07 16:35:54 +0100 | [diff] [blame^] | 62 | enable_mmu_svc_mon(0); |
Jiafei Pan | 33d4af4 | 2018-03-02 07:23:30 +0000 | [diff] [blame] | 63 | #else |
| 64 | enable_mmu_el3(0); |
| 65 | #endif /* AARCH32 */ |
| 66 | VERBOSE("After MMU enabled\n"); |
| 67 | } |
| 68 | |
| 69 | void bl1_plat_arch_setup(void) |
| 70 | { |
| 71 | ls_bl1_plat_arch_setup(); |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * Perform the platform specific architecture setup shared between |
| 76 | * ARM standard platforms. |
| 77 | */ |
| 78 | void ls_bl1_platform_setup(void) |
| 79 | { |
| 80 | /* Initialise the IO layer and register platform IO devices */ |
| 81 | plat_ls_io_setup(); |
| 82 | } |
| 83 | |
| 84 | void bl1_plat_prepare_exit(entry_point_info_t *ep_info) |
| 85 | { |
| 86 | #if !LS1043_DISABLE_TRUSTED_WDOG |
| 87 | /*TODO: Disable watchdog before leaving BL1 */ |
| 88 | #endif |
| 89 | } |