Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 34 | #include <bl_common.h> |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 35 | #include <bl31.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 36 | #include <context.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 37 | #include <context_mgmt.h> |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 38 | #include <interrupt_mgmt.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 39 | #include <platform.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame^] | 40 | #include <platform_def.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 41 | #include <runtime_svc.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 42 | |
| 43 | /******************************************************************************* |
| 44 | * Data structure which holds the pointers to non-secure and secure security |
| 45 | * state contexts for each cpu. It is aligned to the cache line boundary to |
| 46 | * allow efficient concurrent manipulation of these pointers on different cpus |
| 47 | ******************************************************************************/ |
| 48 | typedef struct { |
| 49 | void *ptr[2]; |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 50 | } __aligned (CACHE_WRITEBACK_GRANULE) context_info_t; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 51 | |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 52 | static context_info_t cm_context_info[PLATFORM_CORE_COUNT]; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 53 | |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 54 | /* The per_cpu_ptr_cache_t space allocation */ |
| 55 | static per_cpu_ptr_cache_t per_cpu_ptr_cache_space[PLATFORM_CORE_COUNT]; |
| 56 | |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 57 | /******************************************************************************* |
| 58 | * Context management library initialisation routine. This library is used by |
| 59 | * runtime services to share pointers to 'cpu_context' structures for the secure |
| 60 | * and non-secure states. Management of the structures and their associated |
| 61 | * memory is not done by the context management library e.g. the PSCI service |
| 62 | * manages the cpu context used for entry from and exit to the non-secure state. |
| 63 | * The Secure payload dispatcher service manages the context(s) corresponding to |
| 64 | * the secure state. It also uses this library to get access to the non-secure |
| 65 | * state cpu context pointers. |
| 66 | * Lastly, this library provides the api to make SP_EL3 point to the cpu context |
| 67 | * which will used for programming an entry into a lower EL. The same context |
| 68 | * will used to save state upon exception entry from that EL. |
| 69 | ******************************************************************************/ |
| 70 | void cm_init() |
| 71 | { |
| 72 | /* |
| 73 | * The context management library has only global data to intialize, but |
| 74 | * that will be done when the BSS is zeroed out |
| 75 | */ |
| 76 | } |
| 77 | |
| 78 | /******************************************************************************* |
| 79 | * This function returns a pointer to the most recent 'cpu_context' structure |
| 80 | * that was set as the context for the specified security state. NULL is |
| 81 | * returned if no such structure has been specified. |
| 82 | ******************************************************************************/ |
| 83 | void *cm_get_context(uint64_t mpidr, uint32_t security_state) |
| 84 | { |
| 85 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 86 | |
| 87 | assert(security_state <= NON_SECURE); |
| 88 | |
| 89 | return cm_context_info[linear_id].ptr[security_state]; |
| 90 | } |
| 91 | |
| 92 | /******************************************************************************* |
| 93 | * This function sets the pointer to the current 'cpu_context' structure for the |
| 94 | * specified security state. |
| 95 | ******************************************************************************/ |
| 96 | void cm_set_context(uint64_t mpidr, void *context, uint32_t security_state) |
| 97 | { |
| 98 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 99 | |
| 100 | assert(security_state <= NON_SECURE); |
| 101 | |
| 102 | cm_context_info[linear_id].ptr[security_state] = context; |
| 103 | } |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * The next four functions are used by runtime services to save and restore EL3 |
| 107 | * and EL1 contexts on the 'cpu_context' structure for the specified security |
| 108 | * state. |
| 109 | ******************************************************************************/ |
| 110 | void cm_el3_sysregs_context_save(uint32_t security_state) |
| 111 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 112 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 113 | |
| 114 | ctx = cm_get_context(read_mpidr(), security_state); |
| 115 | assert(ctx); |
| 116 | |
| 117 | el3_sysregs_context_save(get_el3state_ctx(ctx)); |
| 118 | } |
| 119 | |
| 120 | void cm_el3_sysregs_context_restore(uint32_t security_state) |
| 121 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 122 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 123 | |
| 124 | ctx = cm_get_context(read_mpidr(), security_state); |
| 125 | assert(ctx); |
| 126 | |
| 127 | el3_sysregs_context_restore(get_el3state_ctx(ctx)); |
| 128 | } |
| 129 | |
| 130 | void cm_el1_sysregs_context_save(uint32_t security_state) |
| 131 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 132 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 133 | |
| 134 | ctx = cm_get_context(read_mpidr(), security_state); |
| 135 | assert(ctx); |
| 136 | |
| 137 | el1_sysregs_context_save(get_sysregs_ctx(ctx)); |
| 138 | } |
| 139 | |
| 140 | void cm_el1_sysregs_context_restore(uint32_t security_state) |
| 141 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 142 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 143 | |
| 144 | ctx = cm_get_context(read_mpidr(), security_state); |
| 145 | assert(ctx); |
| 146 | |
| 147 | el1_sysregs_context_restore(get_sysregs_ctx(ctx)); |
| 148 | } |
| 149 | |
| 150 | /******************************************************************************* |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 151 | * This function populates 'cpu_context' pertaining to the given security state |
| 152 | * with the entrypoint, SPSR and SCR values so that an ERET from this security |
| 153 | * state correctly restores corresponding values to drop the CPU to the next |
| 154 | * exception level |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 155 | ******************************************************************************/ |
| 156 | void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint, |
| 157 | uint32_t spsr, uint32_t scr) |
| 158 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 159 | cpu_context_t *ctx; |
| 160 | el3_state_t *state; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 161 | |
| 162 | ctx = cm_get_context(read_mpidr(), security_state); |
| 163 | assert(ctx); |
| 164 | |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 165 | /* Program the interrupt routing model for this security state */ |
| 166 | scr &= ~SCR_FIQ_BIT; |
| 167 | scr &= ~SCR_IRQ_BIT; |
| 168 | scr |= get_scr_el3_from_routing_model(security_state); |
| 169 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 170 | /* Populate EL3 state so that we've the right context before doing ERET */ |
| 171 | state = get_el3state_ctx(ctx); |
| 172 | write_ctx_reg(state, CTX_SPSR_EL3, spsr); |
| 173 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
| 174 | write_ctx_reg(state, CTX_SCR_EL3, scr); |
| 175 | } |
| 176 | |
| 177 | /******************************************************************************* |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 178 | * This function populates ELR_EL3 member of 'cpu_context' pertaining to the |
| 179 | * given security state with the given entrypoint |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 180 | ******************************************************************************/ |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 181 | void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 182 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 183 | cpu_context_t *ctx; |
| 184 | el3_state_t *state; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 185 | |
| 186 | ctx = cm_get_context(read_mpidr(), security_state); |
| 187 | assert(ctx); |
| 188 | |
| 189 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 190 | state = get_el3state_ctx(ctx); |
| 191 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
| 192 | } |
| 193 | |
| 194 | /******************************************************************************* |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 195 | * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' |
| 196 | * pertaining to the given security state using the value and bit position |
| 197 | * specified in the parameters. It preserves all other bits. |
| 198 | ******************************************************************************/ |
| 199 | void cm_write_scr_el3_bit(uint32_t security_state, |
| 200 | uint32_t bit_pos, |
| 201 | uint32_t value) |
| 202 | { |
| 203 | cpu_context_t *ctx; |
| 204 | el3_state_t *state; |
| 205 | uint32_t scr_el3; |
| 206 | |
| 207 | ctx = cm_get_context(read_mpidr(), security_state); |
| 208 | assert(ctx); |
| 209 | |
| 210 | /* Ensure that the bit position is a valid one */ |
| 211 | assert((1 << bit_pos) & SCR_VALID_BIT_MASK); |
| 212 | |
| 213 | /* Ensure that the 'value' is only a bit wide */ |
| 214 | assert(value <= 1); |
| 215 | |
| 216 | /* |
| 217 | * Get the SCR_EL3 value from the cpu context, clear the desired bit |
| 218 | * and set it to its new value. |
| 219 | */ |
| 220 | state = get_el3state_ctx(ctx); |
| 221 | scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); |
| 222 | scr_el3 &= ~(1 << bit_pos); |
| 223 | scr_el3 |= value << bit_pos; |
| 224 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 225 | } |
| 226 | |
| 227 | /******************************************************************************* |
| 228 | * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the |
| 229 | * given security state. |
| 230 | ******************************************************************************/ |
| 231 | uint32_t cm_get_scr_el3(uint32_t security_state) |
| 232 | { |
| 233 | cpu_context_t *ctx; |
| 234 | el3_state_t *state; |
| 235 | |
| 236 | ctx = cm_get_context(read_mpidr(), security_state); |
| 237 | assert(ctx); |
| 238 | |
| 239 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 240 | state = get_el3state_ctx(ctx); |
| 241 | return read_ctx_reg(state, CTX_SCR_EL3); |
| 242 | } |
| 243 | |
| 244 | /******************************************************************************* |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 245 | * This function is used to program the context that's used for exception |
| 246 | * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for |
| 247 | * the required security state |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 248 | ******************************************************************************/ |
| 249 | void cm_set_next_eret_context(uint32_t security_state) |
| 250 | { |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 251 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 252 | #if DEBUG |
| 253 | uint64_t sp_mode; |
| 254 | #endif |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 255 | |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 256 | ctx = cm_get_context(read_mpidr(), security_state); |
| 257 | assert(ctx); |
| 258 | |
| 259 | #if DEBUG |
| 260 | /* |
| 261 | * Check that this function is called with SP_EL0 as the stack |
| 262 | * pointer |
| 263 | */ |
| 264 | __asm__ volatile("mrs %0, SPSel\n" |
| 265 | : "=r" (sp_mode)); |
| 266 | |
| 267 | assert(sp_mode == MODE_SP_EL0); |
| 268 | #endif |
| 269 | |
| 270 | __asm__ volatile("msr spsel, #1\n" |
| 271 | "mov sp, %0\n" |
| 272 | "msr spsel, #0\n" |
| 273 | : : "r" (ctx)); |
| 274 | } |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 275 | |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 276 | /************************************************************************ |
| 277 | * The following function is used to populate the per cpu pointer cache. |
| 278 | * The pointer will be stored in the tpidr_el3 register. |
| 279 | *************************************************************************/ |
| 280 | void cm_init_pcpu_ptr_cache() |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 281 | { |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 282 | unsigned long mpidr = read_mpidr(); |
| 283 | uint32_t linear_id = platform_get_core_pos(mpidr); |
| 284 | per_cpu_ptr_cache_t *pcpu_ptr_cache; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 285 | |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 286 | pcpu_ptr_cache = &per_cpu_ptr_cache_space[linear_id]; |
| 287 | assert(pcpu_ptr_cache); |
| 288 | pcpu_ptr_cache->crash_stack = get_crash_stack(mpidr); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 289 | |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 290 | cm_set_pcpu_ptr_cache(pcpu_ptr_cache); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 291 | } |
Soby Mathew | a43d431 | 2014-04-07 15:28:55 +0100 | [diff] [blame] | 292 | |
| 293 | |
| 294 | void cm_set_pcpu_ptr_cache(const void *pcpu_ptr) |
| 295 | { |
| 296 | write_tpidr_el3((unsigned long)pcpu_ptr); |
| 297 | } |
| 298 | |
| 299 | void *cm_get_pcpu_ptr_cache(void) |
| 300 | { |
| 301 | return (void *)read_tpidr_el3(); |
| 302 | } |
| 303 | |