Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | 10bcd76 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __ARCH_H__ |
| 32 | #define __ARCH_H__ |
| 33 | |
Scott Branden | 53d9c9c | 2017-04-10 11:45:52 -0700 | [diff] [blame] | 34 | #include <utils_def.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| 36 | /******************************************************************************* |
| 37 | * MIDR bit definitions |
| 38 | ******************************************************************************/ |
Soby Mathew | 9b47684 | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 39 | #define MIDR_IMPL_MASK 0xff |
| 40 | #define MIDR_IMPL_SHIFT 0x18 |
Soby Mathew | d9bdaf2 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 41 | #define MIDR_VAR_SHIFT 20 |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 42 | #define MIDR_VAR_BITS 4 |
Jeenu Viswambharan | 10bcd76 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 43 | #define MIDR_VAR_MASK 0xf |
Soby Mathew | d9bdaf2 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 44 | #define MIDR_REV_SHIFT 0 |
Soby Mathew | 7395a72 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 45 | #define MIDR_REV_BITS 4 |
Jeenu Viswambharan | 10bcd76 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 46 | #define MIDR_REV_MASK 0xf |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | #define MIDR_PN_MASK 0xfff |
| 48 | #define MIDR_PN_SHIFT 0x4 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 49 | |
| 50 | /******************************************************************************* |
| 51 | * MPIDR macros |
| 52 | ******************************************************************************/ |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 53 | #define MPIDR_MT_MASK (1 << 24) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 54 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
| 55 | #define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS |
| 56 | #define MPIDR_AFFINITY_BITS 8 |
| 57 | #define MPIDR_AFFLVL_MASK 0xff |
| 58 | #define MPIDR_AFF0_SHIFT 0 |
| 59 | #define MPIDR_AFF1_SHIFT 8 |
| 60 | #define MPIDR_AFF2_SHIFT 16 |
| 61 | #define MPIDR_AFF3_SHIFT 32 |
| 62 | #define MPIDR_AFFINITY_MASK 0xff00ffffff |
| 63 | #define MPIDR_AFFLVL_SHIFT 3 |
| 64 | #define MPIDR_AFFLVL0 0 |
| 65 | #define MPIDR_AFFLVL1 1 |
| 66 | #define MPIDR_AFFLVL2 2 |
| 67 | #define MPIDR_AFFLVL3 3 |
Vikram Kanigiri | 4991ecd | 2015-02-26 15:25:58 +0000 | [diff] [blame] | 68 | #define MPIDR_AFFLVL0_VAL(mpidr) \ |
| 69 | ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
| 70 | #define MPIDR_AFFLVL1_VAL(mpidr) \ |
| 71 | ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
| 72 | #define MPIDR_AFFLVL2_VAL(mpidr) \ |
| 73 | ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
| 74 | #define MPIDR_AFFLVL3_VAL(mpidr) \ |
| 75 | ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) |
Soby Mathew | 235585b | 2014-12-04 14:14:12 +0000 | [diff] [blame] | 76 | /* |
| 77 | * The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
| 78 | * add one while using this macro to define array sizes. |
| 79 | * TODO: Support only the first 3 affinity levels for now. |
| 80 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | #define MPIDR_MAX_AFFLVL 2 |
| 82 | |
| 83 | /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ |
| 84 | #define FIRST_MPIDR 0 |
| 85 | |
| 86 | /******************************************************************************* |
Andrew Thoelke | 5c3272a | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 87 | * Definitions for CPU system register interface to GICv3 |
| 88 | ******************************************************************************/ |
| 89 | #define ICC_SRE_EL1 S3_0_C12_C12_5 |
| 90 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 91 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 92 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 93 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 94 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 95 | #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 |
| 96 | #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 |
| 97 | #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 |
| 98 | #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 |
| 99 | #define ICC_IAR0_EL1 S3_0_c12_c8_0 |
| 100 | #define ICC_IAR1_EL1 S3_0_c12_c12_0 |
| 101 | #define ICC_EOIR0_EL1 S3_0_c12_c8_1 |
| 102 | #define ICC_EOIR1_EL1 S3_0_c12_c12_1 |
Andrew Thoelke | 5c3272a | 2014-06-02 15:44:43 +0100 | [diff] [blame] | 103 | |
| 104 | /******************************************************************************* |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 105 | * Generic timer memory mapped registers & offsets |
| 106 | ******************************************************************************/ |
| 107 | #define CNTCR_OFF 0x000 |
| 108 | #define CNTFID_OFF 0x020 |
| 109 | |
| 110 | #define CNTCR_EN (1 << 0) |
| 111 | #define CNTCR_HDBG (1 << 1) |
Sandrine Bailleux | 9e86490 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 112 | #define CNTCR_FCREQ(x) ((x) << 8) |
Achin Gupta | c2b43af | 2013-10-31 11:27:43 +0000 | [diff] [blame] | 113 | |
| 114 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | * System register bit definitions |
| 116 | ******************************************************************************/ |
| 117 | /* CLIDR definitions */ |
| 118 | #define LOUIS_SHIFT 21 |
| 119 | #define LOC_SHIFT 24 |
| 120 | #define CLIDR_FIELD_WIDTH 3 |
| 121 | |
| 122 | /* CSSELR definitions */ |
| 123 | #define LEVEL_SHIFT 1 |
| 124 | |
| 125 | /* D$ set/way op type defines */ |
| 126 | #define DCISW 0x0 |
| 127 | #define DCCISW 0x1 |
| 128 | #define DCCSW 0x2 |
| 129 | |
| 130 | /* ID_AA64PFR0_EL1 definitions */ |
| 131 | #define ID_AA64PFR0_EL0_SHIFT 0 |
| 132 | #define ID_AA64PFR0_EL1_SHIFT 4 |
| 133 | #define ID_AA64PFR0_EL2_SHIFT 8 |
| 134 | #define ID_AA64PFR0_EL3_SHIFT 12 |
| 135 | #define ID_AA64PFR0_ELX_MASK 0xf |
| 136 | |
Achin Gupta | df37373 | 2015-09-03 14:18:02 +0100 | [diff] [blame] | 137 | #define ID_AA64PFR0_GIC_SHIFT 24 |
| 138 | #define ID_AA64PFR0_GIC_WIDTH 4 |
| 139 | #define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1) |
| 140 | |
Antonio Nino Diaz | 0029624 | 2016-12-13 15:28:54 +0000 | [diff] [blame] | 141 | /* ID_AA64MMFR0_EL1 definitions */ |
| 142 | #define ID_AA64MMFR0_EL1_PARANGE_MASK 0xf |
| 143 | |
| 144 | #define PARANGE_0000 32 |
| 145 | #define PARANGE_0001 36 |
| 146 | #define PARANGE_0010 40 |
| 147 | #define PARANGE_0011 42 |
| 148 | #define PARANGE_0100 44 |
| 149 | #define PARANGE_0101 48 |
| 150 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 151 | /* ID_PFR1_EL1 definitions */ |
| 152 | #define ID_PFR1_VIRTEXT_SHIFT 12 |
| 153 | #define ID_PFR1_VIRTEXT_MASK 0xf |
| 154 | #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ |
| 155 | & ID_PFR1_VIRTEXT_MASK) |
| 156 | |
| 157 | /* SCTLR definitions */ |
| 158 | #define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ |
| 159 | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ |
| 160 | (1 << 4)) |
| 161 | |
| 162 | #define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ |
Vikram Kanigiri | 6cd12da | 2015-07-22 11:53:52 +0100 | [diff] [blame] | 163 | (1 << 20) | (1 << 11)) |
Jens Wiklander | ae213ce | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 164 | #define SCTLR_AARCH32_EL1_RES1 \ |
| 165 | ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ |
| 166 | (1 << 3)) |
| 167 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | #define SCTLR_M_BIT (1 << 0) |
| 169 | #define SCTLR_A_BIT (1 << 1) |
| 170 | #define SCTLR_C_BIT (1 << 2) |
| 171 | #define SCTLR_SA_BIT (1 << 3) |
Soby Mathew | b7b0787 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 172 | #define SCTLR_CP15BEN_BIT (1 << 5) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 173 | #define SCTLR_I_BIT (1 << 12) |
Soby Mathew | b7b0787 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 174 | #define SCTLR_NTWI_BIT (1 << 16) |
| 175 | #define SCTLR_NTWE_BIT (1 << 18) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 176 | #define SCTLR_WXN_BIT (1 << 19) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | #define SCTLR_EE_BIT (1 << 25) |
| 178 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | /* CPACR_El1 definitions */ |
| 180 | #define CPACR_EL1_FPEN(x) (x << 20) |
| 181 | #define CPACR_EL1_FP_TRAP_EL0 0x1 |
| 182 | #define CPACR_EL1_FP_TRAP_ALL 0x2 |
| 183 | #define CPACR_EL1_FP_TRAP_NONE 0x3 |
| 184 | |
| 185 | /* SCR definitions */ |
| 186 | #define SCR_RES1_BITS ((1 << 4) | (1 << 5)) |
| 187 | #define SCR_TWE_BIT (1 << 13) |
| 188 | #define SCR_TWI_BIT (1 << 12) |
| 189 | #define SCR_ST_BIT (1 << 11) |
| 190 | #define SCR_RW_BIT (1 << 10) |
| 191 | #define SCR_SIF_BIT (1 << 9) |
| 192 | #define SCR_HCE_BIT (1 << 8) |
| 193 | #define SCR_SMD_BIT (1 << 7) |
| 194 | #define SCR_EA_BIT (1 << 3) |
| 195 | #define SCR_FIQ_BIT (1 << 2) |
| 196 | #define SCR_IRQ_BIT (1 << 1) |
| 197 | #define SCR_NS_BIT (1 << 0) |
Achin Gupta | c429b5e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 198 | #define SCR_VALID_BIT_MASK 0x2f8f |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | |
dp-arm | 85e93ba | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 200 | /* MDCR definitions */ |
| 201 | #define MDCR_SPD32(x) ((x) << 14) |
| 202 | #define MDCR_SPD32_LEGACY 0x0 |
| 203 | #define MDCR_SPD32_DISABLE 0x2 |
| 204 | #define MDCR_SPD32_ENABLE 0x3 |
| 205 | #define MDCR_SDD_BIT (1 << 16) |
| 206 | |
| 207 | #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) |
| 208 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | /* HCR definitions */ |
| 210 | #define HCR_RW_BIT (1ull << 31) |
| 211 | #define HCR_AMO_BIT (1 << 5) |
| 212 | #define HCR_IMO_BIT (1 << 4) |
| 213 | #define HCR_FMO_BIT (1 << 3) |
| 214 | |
Gerald Lejeune | 6b836cf | 2016-03-22 11:11:46 +0100 | [diff] [blame] | 215 | /* ISR definitions */ |
| 216 | #define ISR_A_SHIFT 8 |
| 217 | #define ISR_I_SHIFT 7 |
| 218 | #define ISR_F_SHIFT 6 |
| 219 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 220 | /* CNTHCTL_EL2 definitions */ |
Andrew Thoelke | 167a935 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 221 | #define EVNTEN_BIT (1 << 2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | #define EL1PCEN_BIT (1 << 1) |
| 223 | #define EL1PCTEN_BIT (1 << 0) |
| 224 | |
| 225 | /* CNTKCTL_EL1 definitions */ |
| 226 | #define EL0PTEN_BIT (1 << 9) |
| 227 | #define EL0VTEN_BIT (1 << 8) |
| 228 | #define EL0PCTEN_BIT (1 << 0) |
| 229 | #define EL0VCTEN_BIT (1 << 1) |
Sandrine Bailleux | 01b916b | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 230 | #define EVNTEN_BIT (1 << 2) |
| 231 | #define EVNTDIR_BIT (1 << 3) |
| 232 | #define EVNTI_SHIFT 4 |
| 233 | #define EVNTI_MASK 0xf |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 234 | |
| 235 | /* CPTR_EL3 definitions */ |
Harry Liebel | 4f60368 | 2014-01-14 18:11:48 +0000 | [diff] [blame] | 236 | #define TCPAC_BIT (1 << 31) |
| 237 | #define TTA_BIT (1 << 20) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 238 | #define TFP_BIT (1 << 10) |
| 239 | |
| 240 | /* CPSR/SPSR definitions */ |
| 241 | #define DAIF_FIQ_BIT (1 << 0) |
| 242 | #define DAIF_IRQ_BIT (1 << 1) |
| 243 | #define DAIF_ABT_BIT (1 << 2) |
| 244 | #define DAIF_DBG_BIT (1 << 3) |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 245 | #define SPSR_DAIF_SHIFT 6 |
| 246 | #define SPSR_DAIF_MASK 0xf |
| 247 | |
| 248 | #define SPSR_AIF_SHIFT 6 |
| 249 | #define SPSR_AIF_MASK 0x7 |
| 250 | |
| 251 | #define SPSR_E_SHIFT 9 |
| 252 | #define SPSR_E_MASK 0x1 |
| 253 | #define SPSR_E_LITTLE 0x0 |
| 254 | #define SPSR_E_BIG 0x1 |
| 255 | |
| 256 | #define SPSR_T_SHIFT 5 |
| 257 | #define SPSR_T_MASK 0x1 |
| 258 | #define SPSR_T_ARM 0x0 |
| 259 | #define SPSR_T_THUMB 0x1 |
| 260 | |
| 261 | #define DISABLE_ALL_EXCEPTIONS \ |
| 262 | (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) |
| 263 | |
Yatharth Kochar | 07570d5 | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 264 | /* |
| 265 | * RMR_EL3 definitions |
| 266 | */ |
| 267 | #define RMR_EL3_RR_BIT (1 << 1) |
| 268 | #define RMR_EL3_AA64_BIT (1 << 0) |
| 269 | |
| 270 | /* |
| 271 | * HI-VECTOR address for AArch32 state |
| 272 | */ |
| 273 | #define HI_VECTOR_BASE (0xFFFF0000) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 274 | |
| 275 | /* |
| 276 | * TCR defintions |
| 277 | */ |
| 278 | #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) |
Lin Ma | 73ad257 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 279 | #define TCR_EL1_IPS_SHIFT 32 |
| 280 | #define TCR_EL3_PS_SHIFT 16 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 281 | |
Antonio Nino Diaz | e871955 | 2016-08-02 09:21:41 +0100 | [diff] [blame] | 282 | #define TCR_TxSZ_MIN 16 |
| 283 | #define TCR_TxSZ_MAX 39 |
| 284 | |
Lin Ma | 73ad257 | 2014-06-27 16:56:30 -0700 | [diff] [blame] | 285 | /* (internal) physical address size bits in EL3/EL1 */ |
| 286 | #define TCR_PS_BITS_4GB (0x0) |
| 287 | #define TCR_PS_BITS_64GB (0x1) |
| 288 | #define TCR_PS_BITS_1TB (0x2) |
| 289 | #define TCR_PS_BITS_4TB (0x3) |
| 290 | #define TCR_PS_BITS_16TB (0x4) |
| 291 | #define TCR_PS_BITS_256TB (0x5) |
| 292 | |
| 293 | #define ADDR_MASK_48_TO_63 0xFFFF000000000000UL |
| 294 | #define ADDR_MASK_44_TO_47 0x0000F00000000000UL |
| 295 | #define ADDR_MASK_42_TO_43 0x00000C0000000000UL |
| 296 | #define ADDR_MASK_40_TO_41 0x0000030000000000UL |
| 297 | #define ADDR_MASK_36_TO_39 0x000000F000000000UL |
| 298 | #define ADDR_MASK_32_TO_35 0x0000000F00000000UL |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 299 | |
| 300 | #define TCR_RGN_INNER_NC (0x0 << 8) |
| 301 | #define TCR_RGN_INNER_WBA (0x1 << 8) |
| 302 | #define TCR_RGN_INNER_WT (0x2 << 8) |
| 303 | #define TCR_RGN_INNER_WBNA (0x3 << 8) |
| 304 | |
| 305 | #define TCR_RGN_OUTER_NC (0x0 << 10) |
| 306 | #define TCR_RGN_OUTER_WBA (0x1 << 10) |
| 307 | #define TCR_RGN_OUTER_WT (0x2 << 10) |
| 308 | #define TCR_RGN_OUTER_WBNA (0x3 << 10) |
| 309 | |
| 310 | #define TCR_SH_NON_SHAREABLE (0x0 << 12) |
| 311 | #define TCR_SH_OUTER_SHAREABLE (0x2 << 12) |
| 312 | #define TCR_SH_INNER_SHAREABLE (0x3 << 12) |
| 313 | |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 314 | #define MODE_SP_SHIFT 0x0 |
| 315 | #define MODE_SP_MASK 0x1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 316 | #define MODE_SP_EL0 0x0 |
| 317 | #define MODE_SP_ELX 0x1 |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 318 | |
| 319 | #define MODE_RW_SHIFT 0x4 |
| 320 | #define MODE_RW_MASK 0x1 |
| 321 | #define MODE_RW_64 0x0 |
| 322 | #define MODE_RW_32 0x1 |
| 323 | |
| 324 | #define MODE_EL_SHIFT 0x2 |
| 325 | #define MODE_EL_MASK 0x3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 326 | #define MODE_EL3 0x3 |
| 327 | #define MODE_EL2 0x2 |
| 328 | #define MODE_EL1 0x1 |
| 329 | #define MODE_EL0 0x0 |
| 330 | |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 331 | #define MODE32_SHIFT 0 |
| 332 | #define MODE32_MASK 0xf |
| 333 | #define MODE32_usr 0x0 |
| 334 | #define MODE32_fiq 0x1 |
| 335 | #define MODE32_irq 0x2 |
| 336 | #define MODE32_svc 0x3 |
| 337 | #define MODE32_mon 0x6 |
| 338 | #define MODE32_abt 0x7 |
| 339 | #define MODE32_hyp 0xa |
| 340 | #define MODE32_und 0xb |
| 341 | #define MODE32_sys 0xf |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 342 | |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 343 | #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) |
| 344 | #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) |
| 345 | #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) |
| 346 | #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 347 | |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 348 | #define SPSR_64(el, sp, daif) \ |
| 349 | (MODE_RW_64 << MODE_RW_SHIFT | \ |
| 350 | ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ |
| 351 | ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ |
| 352 | ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 353 | |
Vikram Kanigiri | 23ff9ba | 2014-05-13 14:42:08 +0100 | [diff] [blame] | 354 | #define SPSR_MODE32(mode, isa, endian, aif) \ |
| 355 | (MODE_RW_32 << MODE_RW_SHIFT | \ |
| 356 | ((mode) & MODE32_MASK) << MODE32_SHIFT | \ |
| 357 | ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ |
| 358 | ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ |
| 359 | ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) |
| 360 | |
Dan Handley | ce4c820 | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 361 | /* |
| 362 | * CTR_EL0 definitions |
| 363 | */ |
| 364 | #define CTR_CWG_SHIFT 24 |
| 365 | #define CTR_CWG_MASK 0xf |
| 366 | #define CTR_ERG_SHIFT 20 |
| 367 | #define CTR_ERG_MASK 0xf |
| 368 | #define CTR_DMINLINE_SHIFT 16 |
| 369 | #define CTR_DMINLINE_MASK 0xf |
| 370 | #define CTR_L1IP_SHIFT 14 |
| 371 | #define CTR_L1IP_MASK 0x3 |
| 372 | #define CTR_IMINLINE_SHIFT 0 |
| 373 | #define CTR_IMINLINE_MASK 0xf |
| 374 | |
| 375 | #define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 376 | |
Achin Gupta | fa9c08b | 2014-05-09 12:00:17 +0100 | [diff] [blame] | 377 | /* Physical timer control register bit fields shifts and masks */ |
| 378 | #define CNTP_CTL_ENABLE_SHIFT 0 |
| 379 | #define CNTP_CTL_IMASK_SHIFT 1 |
| 380 | #define CNTP_CTL_ISTATUS_SHIFT 2 |
| 381 | |
| 382 | #define CNTP_CTL_ENABLE_MASK 1 |
| 383 | #define CNTP_CTL_IMASK_MASK 1 |
| 384 | #define CNTP_CTL_ISTATUS_MASK 1 |
| 385 | |
| 386 | #define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ |
| 387 | CNTP_CTL_ENABLE_MASK) |
| 388 | #define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ |
| 389 | CNTP_CTL_IMASK_MASK) |
| 390 | #define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ |
| 391 | CNTP_CTL_ISTATUS_MASK) |
| 392 | |
| 393 | #define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) |
| 394 | #define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) |
| 395 | |
| 396 | #define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) |
| 397 | #define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) |
| 398 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 399 | /* Exception Syndrome register bits and bobs */ |
| 400 | #define ESR_EC_SHIFT 26 |
| 401 | #define ESR_EC_MASK 0x3f |
| 402 | #define ESR_EC_LENGTH 6 |
| 403 | #define EC_UNKNOWN 0x0 |
| 404 | #define EC_WFE_WFI 0x1 |
| 405 | #define EC_AARCH32_CP15_MRC_MCR 0x3 |
| 406 | #define EC_AARCH32_CP15_MRRC_MCRR 0x4 |
| 407 | #define EC_AARCH32_CP14_MRC_MCR 0x5 |
| 408 | #define EC_AARCH32_CP14_LDC_STC 0x6 |
| 409 | #define EC_FP_SIMD 0x7 |
| 410 | #define EC_AARCH32_CP10_MRC 0x8 |
| 411 | #define EC_AARCH32_CP14_MRRC_MCRR 0xc |
| 412 | #define EC_ILLEGAL 0xe |
| 413 | #define EC_AARCH32_SVC 0x11 |
| 414 | #define EC_AARCH32_HVC 0x12 |
| 415 | #define EC_AARCH32_SMC 0x13 |
| 416 | #define EC_AARCH64_SVC 0x15 |
| 417 | #define EC_AARCH64_HVC 0x16 |
| 418 | #define EC_AARCH64_SMC 0x17 |
| 419 | #define EC_AARCH64_SYS 0x18 |
| 420 | #define EC_IABORT_LOWER_EL 0x20 |
| 421 | #define EC_IABORT_CUR_EL 0x21 |
| 422 | #define EC_PC_ALIGN 0x22 |
| 423 | #define EC_DABORT_LOWER_EL 0x24 |
| 424 | #define EC_DABORT_CUR_EL 0x25 |
| 425 | #define EC_SP_ALIGN 0x26 |
| 426 | #define EC_AARCH32_FP 0x28 |
| 427 | #define EC_AARCH64_FP 0x2c |
| 428 | #define EC_SERROR 0x2f |
| 429 | |
| 430 | #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK |
| 431 | |
Vignesh Radhakrishnan | a9e0260 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 432 | /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ |
| 433 | #define RMR_RESET_REQUEST_SHIFT 0x1u |
| 434 | #define RMR_WARM_RESET_CPU (1u << RMR_RESET_REQUEST_SHIFT) |
| 435 | |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 436 | /******************************************************************************* |
Antonio Nino Diaz | 0b64f4e | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 437 | * Definitions of register offsets, fields and macros for CPU system |
| 438 | * instructions. |
| 439 | ******************************************************************************/ |
| 440 | |
| 441 | #define TLBI_ADDR_SHIFT 12 |
| 442 | #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) |
| 443 | #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) |
| 444 | |
| 445 | /******************************************************************************* |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 446 | * Definitions of register offsets and fields in the CNTCTLBase Frame of the |
| 447 | * system level implementation of the Generic Timer. |
| 448 | ******************************************************************************/ |
| 449 | #define CNTNSAR 0x4 |
| 450 | #define CNTNSAR_NS_SHIFT(x) x |
| 451 | |
| 452 | #define CNTACR_BASE(x) (0x40 + (x << 2)) |
| 453 | #define CNTACR_RPCT_SHIFT 0x0 |
| 454 | #define CNTACR_RVCT_SHIFT 0x1 |
| 455 | #define CNTACR_RFRQ_SHIFT 0x2 |
| 456 | #define CNTACR_RVOFF_SHIFT 0x3 |
| 457 | #define CNTACR_RWVT_SHIFT 0x4 |
| 458 | #define CNTACR_RWPT_SHIFT 0x5 |
| 459 | |
David Cunado | 495f3d3 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 460 | /* PMCR_EL0 definitions */ |
| 461 | #define PMCR_EL0_N_SHIFT 11 |
| 462 | #define PMCR_EL0_N_MASK 0x1f |
| 463 | #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) |
| 464 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 465 | #endif /* __ARCH_H__ */ |