Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | 26ea390 | 2018-01-10 15:00:20 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef INTERRUPT_MGMT_H |
| 8 | #define INTERRUPT_MGMT_H |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 9 | |
| 10 | #include <arch.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <lib/utils_def.h> |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 12 | |
| 13 | /******************************************************************************* |
| 14 | * Constants for the types of interrupts recognised by the IM framework |
| 15 | ******************************************************************************/ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 16 | #define INTR_TYPE_S_EL1 U(0) |
| 17 | #define INTR_TYPE_EL3 U(1) |
| 18 | #define INTR_TYPE_NS U(2) |
| 19 | #define MAX_INTR_TYPES U(3) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 20 | #define INTR_TYPE_INVAL MAX_INTR_TYPES |
Jeenu Viswambharan | fc529fe | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 21 | |
| 22 | /* Interrupt routing modes */ |
| 23 | #define INTR_ROUTING_MODE_PE 0 |
| 24 | #define INTR_ROUTING_MODE_ANY 1 |
| 25 | |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 26 | /* |
| 27 | * Constant passed to the interrupt handler in the 'id' field when the |
| 28 | * framework does not read the gic registers to determine the interrupt id. |
| 29 | */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 30 | #define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 31 | |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * Mask for _both_ the routing model bits in the 'flags' parameter and |
| 35 | * constants to define the valid routing models for each supported interrupt |
| 36 | * type |
| 37 | ******************************************************************************/ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 38 | #define INTR_RM_FLAGS_SHIFT U(0x0) |
| 39 | #define INTR_RM_FLAGS_MASK U(0x3) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 40 | /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 41 | #define INTR_SEL1_VALID_RM0 U(0x2) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 42 | /* Routed to EL3 from NS and Secure */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 43 | #define INTR_SEL1_VALID_RM1 U(0x3) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 44 | /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 45 | #define INTR_NS_VALID_RM0 U(0x0) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 46 | /* Routed to EL1/EL2 from NS and to EL3 from Secure */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 47 | #define INTR_NS_VALID_RM1 U(0x1) |
Soby Mathew | 4e0e0f4 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 48 | /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 49 | #define INTR_EL3_VALID_RM0 U(0x2) |
Soby Mathew | 4e0e0f4 | 2015-11-23 13:58:45 +0000 | [diff] [blame] | 50 | /* Routed to EL3 from NS and Secure */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 51 | #define INTR_EL3_VALID_RM1 U(0x3) |
Soby Mathew | f4f1ae7 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 52 | /* This is the default routing model */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 53 | #define INTR_DEFAULT_RM U(0x0) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 54 | |
| 55 | /******************************************************************************* |
| 56 | * Constants for the _individual_ routing model bits in the 'flags' field for |
| 57 | * each interrupt type and mask to validate the 'flags' parameter while |
| 58 | * registering an interrupt handler |
| 59 | ******************************************************************************/ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 60 | #define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 61 | |
| 62 | #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ |
| 63 | #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 64 | #define INTR_RM_FROM_FLAG_MASK U(1) |
Jeenu Viswambharan | 03b645e | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 65 | #define get_interrupt_rm_flag(flag, ss) \ |
| 66 | ((((flag) >> INTR_RM_FLAGS_SHIFT) >> (ss)) & INTR_RM_FROM_FLAG_MASK) |
| 67 | #define set_interrupt_rm_flag(flag, ss) ((flag) |= U(1) << (ss)) |
| 68 | #define clr_interrupt_rm_flag(flag, ss) ((flag) &= ~(U(1) << (ss))) |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 69 | |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 70 | /******************************************************************************* |
| 71 | * Macros to set the 'flags' parameter passed to an interrupt type handler. Only |
| 72 | * the flag to indicate the security state when the exception was generated is |
| 73 | * supported. |
| 74 | ******************************************************************************/ |
Varun Wadekar | 030567e | 2017-05-25 18:04:48 -0700 | [diff] [blame] | 75 | #define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ |
| 76 | #define INTR_SRC_SS_FLAG_MASK U(1) |
Jeenu Viswambharan | ba6e5ca | 2018-08-02 10:14:12 +0100 | [diff] [blame] | 77 | #define set_interrupt_src_ss(flag, val) ((flag) |= (val) << INTR_SRC_SS_FLAG_SHIFT) |
| 78 | #define clr_interrupt_src_ss(flag) ((flag) &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) |
| 79 | #define get_interrupt_src_ss(flag) (((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \ |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 80 | INTR_SRC_SS_FLAG_MASK) |
| 81 | |
| 82 | #ifndef __ASSEMBLY__ |
| 83 | |
Antonio Nino Diaz | c9512bc | 2018-08-24 16:30:29 +0100 | [diff] [blame] | 84 | #include <errno.h> |
Jeenu Viswambharan | c639e8e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 85 | #include <stdint.h> |
| 86 | |
Antonio Nino Diaz | c9512bc | 2018-08-24 16:30:29 +0100 | [diff] [blame] | 87 | /******************************************************************************* |
| 88 | * Helpers to validate the routing model bits in the 'flags' for a type |
| 89 | * of interrupt. If the model does not match one of the valid masks |
| 90 | * -EINVAL is returned. |
| 91 | ******************************************************************************/ |
| 92 | static inline int32_t validate_sel1_interrupt_rm(uint32_t x) |
| 93 | { |
| 94 | if ((x == INTR_SEL1_VALID_RM0) || (x == INTR_SEL1_VALID_RM1)) |
| 95 | return 0; |
| 96 | |
| 97 | return -EINVAL; |
| 98 | } |
| 99 | |
| 100 | static inline int32_t validate_ns_interrupt_rm(uint32_t x) |
| 101 | { |
| 102 | if ((x == INTR_NS_VALID_RM0) || (x == INTR_NS_VALID_RM1)) |
| 103 | return 0; |
| 104 | |
| 105 | return -EINVAL; |
| 106 | } |
| 107 | |
| 108 | static inline int32_t validate_el3_interrupt_rm(uint32_t x) |
| 109 | { |
| 110 | #if EL3_EXCEPTION_HANDLING |
| 111 | /* |
| 112 | * With EL3 exception handling, EL3 interrupts are always routed to EL3 |
| 113 | * from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is |
| 114 | * the only valid routing model. |
| 115 | */ |
| 116 | if (x == INTR_EL3_VALID_RM1) |
| 117 | return 0; |
| 118 | #else |
| 119 | if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1)) |
| 120 | return 0; |
| 121 | #endif |
| 122 | |
| 123 | return -EINVAL; |
| 124 | } |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * Prototype for defining a handler for an interrupt type |
| 128 | ******************************************************************************/ |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 129 | typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, |
| 130 | uint32_t flags, |
| 131 | void *handle, |
| 132 | void *cookie); |
| 133 | |
| 134 | /******************************************************************************* |
| 135 | * Function & variable prototypes |
| 136 | ******************************************************************************/ |
Dan Handley | c6bc071 | 2014-05-14 12:38:32 +0100 | [diff] [blame] | 137 | uint32_t get_scr_el3_from_routing_model(uint32_t security_state); |
| 138 | int32_t set_routing_model(uint32_t type, uint32_t flags); |
| 139 | int32_t register_interrupt_type_handler(uint32_t type, |
| 140 | interrupt_type_handler_t handler, |
| 141 | uint32_t flags); |
Roberto Vargas | 9fb8af3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 142 | interrupt_type_handler_t get_interrupt_type_handler(uint32_t type); |
Soby Mathew | f4f1ae7 | 2015-01-13 15:48:26 +0000 | [diff] [blame] | 143 | int disable_intr_rm_local(uint32_t type, uint32_t security_state); |
| 144 | int enable_intr_rm_local(uint32_t type, uint32_t security_state); |
Achin Gupta | e1333f7 | 2014-05-09 10:03:15 +0100 | [diff] [blame] | 145 | |
| 146 | #endif /*__ASSEMBLY__*/ |
Antonio Nino Diaz | c3cf06f | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 147 | #endif /* INTERRUPT_MGMT_H */ |