Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 31 | #include <asm_macros.S> |
Achin Gupta | 0a46e2c | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 32 | #include <assert_macros.S> |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 33 | #include <platform_def.h> |
Achin Gupta | 0a46e2c | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 34 | #include <psci.h> |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 35 | |
| 36 | .globl psci_do_pwrdown_cache_maintenance |
| 37 | .globl psci_do_pwrup_cache_maintenance |
| 38 | |
| 39 | /* ----------------------------------------------------------------------- |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame^] | 40 | * void psci_do_pwrdown_cache_maintenance(unsigned int power level); |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 41 | * |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 42 | * This function performs cache maintenance for the specified power |
| 43 | * level. The levels of cache affected are determined by the power |
| 44 | * level which is passed as the argument i.e. level 0 results |
| 45 | * in a flush of the L1 cache. Both the L1 and L2 caches are flushed |
| 46 | * for a higher power level. |
Achin Gupta | 0a46e2c | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 47 | * |
| 48 | * Additionally, this function also ensures that stack memory is correctly |
| 49 | * flushed out to avoid coherency issues due to a change in its memory |
| 50 | * attributes after the data cache is disabled. |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 51 | * ----------------------------------------------------------------------- |
| 52 | */ |
| 53 | func psci_do_pwrdown_cache_maintenance |
| 54 | stp x29, x30, [sp,#-16]! |
| 55 | stp x19, x20, [sp,#-16]! |
| 56 | |
| 57 | /* --------------------------------------------- |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 58 | * Determine to how many levels of cache will be |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 59 | * subject to cache maintenance. Power level |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 60 | * 0 implies that only the cpu is being powered |
| 61 | * down. Only the L1 data cache needs to be |
| 62 | * flushed to the PoU in this case. For a higher |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 63 | * power level we are assuming that a flush |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 64 | * of L1 data and L2 unified cache is enough. |
| 65 | * This information should be provided by the |
| 66 | * platform. |
| 67 | * --------------------------------------------- |
| 68 | */ |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame^] | 69 | cmp w0, #PSCI_CPU_PWR_LVL |
Soby Mathew | add4035 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 70 | b.eq do_core_pwr_dwn |
| 71 | bl prepare_cluster_pwr_dwn |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 72 | b do_stack_maintenance |
| 73 | |
Soby Mathew | add4035 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 74 | do_core_pwr_dwn: |
| 75 | bl prepare_core_pwr_dwn |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 76 | |
| 77 | /* --------------------------------------------- |
| 78 | * Do stack maintenance by flushing the used |
| 79 | * stack to the main memory and invalidating the |
| 80 | * remainder. |
| 81 | * --------------------------------------------- |
| 82 | */ |
| 83 | do_stack_maintenance: |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 84 | bl plat_get_my_stack |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 85 | |
| 86 | /* --------------------------------------------- |
| 87 | * Calculate and store the size of the used |
| 88 | * stack memory in x1. |
| 89 | * --------------------------------------------- |
| 90 | */ |
| 91 | mov x19, x0 |
| 92 | mov x1, sp |
| 93 | sub x1, x0, x1 |
| 94 | mov x0, sp |
| 95 | bl flush_dcache_range |
| 96 | |
| 97 | /* --------------------------------------------- |
| 98 | * Calculate and store the size of the unused |
| 99 | * stack memory in x1. Calculate and store the |
| 100 | * stack base address in x0. |
| 101 | * --------------------------------------------- |
| 102 | */ |
| 103 | sub x0, x19, #PLATFORM_STACK_SIZE |
| 104 | sub x1, sp, x0 |
| 105 | bl inv_dcache_range |
| 106 | |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 107 | ldp x19, x20, [sp], #16 |
| 108 | ldp x29, x30, [sp], #16 |
| 109 | ret |
Kévin Petit | 8b77962 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 110 | endfunc psci_do_pwrdown_cache_maintenance |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 111 | |
| 112 | |
| 113 | /* ----------------------------------------------------------------------- |
| 114 | * void psci_do_pwrup_cache_maintenance(void); |
| 115 | * |
| 116 | * This function performs cache maintenance after this cpu is powered up. |
| 117 | * Currently, this involves managing the used stack memory before turning |
| 118 | * on the data cache. |
| 119 | * ----------------------------------------------------------------------- |
| 120 | */ |
| 121 | func psci_do_pwrup_cache_maintenance |
| 122 | stp x29, x30, [sp,#-16]! |
| 123 | |
| 124 | /* --------------------------------------------- |
| 125 | * Ensure any inflight stack writes have made it |
| 126 | * to main memory. |
| 127 | * --------------------------------------------- |
| 128 | */ |
| 129 | dmb st |
| 130 | |
| 131 | /* --------------------------------------------- |
| 132 | * Calculate and store the size of the used |
| 133 | * stack memory in x1. Calculate and store the |
| 134 | * stack base address in x0. |
| 135 | * --------------------------------------------- |
| 136 | */ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 137 | bl plat_get_my_stack |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 138 | mov x1, sp |
| 139 | sub x1, x0, x1 |
| 140 | mov x0, sp |
| 141 | bl inv_dcache_range |
| 142 | |
| 143 | /* --------------------------------------------- |
| 144 | * Enable the data cache. |
| 145 | * --------------------------------------------- |
| 146 | */ |
| 147 | mrs x0, sctlr_el3 |
| 148 | orr x0, x0, #SCTLR_C_BIT |
| 149 | msr sctlr_el3, x0 |
| 150 | isb |
| 151 | |
| 152 | ldp x29, x30, [sp], #16 |
| 153 | ret |
Kévin Petit | 8b77962 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 154 | endfunc psci_do_pwrup_cache_maintenance |