Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
dp-arm | 04c1db1 | 2017-01-31 13:01:04 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PSCI_PRIVATE_H__ |
| 32 | #define __PSCI_PRIVATE_H__ |
| 33 | |
Achin Gupta | a59caa4 | 2013-12-05 14:21:04 +0000 | [diff] [blame] | 34 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | #include <bakery_lock.h> |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 36 | #include <bl_common.h> |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 37 | #include <cpu_data.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 38 | #include <psci.h> |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 39 | #include <spinlock.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
Jeenu Viswambharan | a10d363 | 2017-01-06 14:58:11 +0000 | [diff] [blame] | 41 | #if HW_ASSISTED_COHERENCY |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 42 | |
Jeenu Viswambharan | a10d363 | 2017-01-06 14:58:11 +0000 | [diff] [blame] | 43 | /* |
| 44 | * On systems with hardware-assisted coherency, make PSCI cache operations NOP, |
| 45 | * as PSCI participants are cache-coherent, and there's no need for explicit |
| 46 | * cache maintenance operations or barriers to coordinate their state. |
| 47 | */ |
| 48 | #define psci_flush_dcache_range(addr, size) |
| 49 | #define psci_flush_cpu_data(member) |
| 50 | #define psci_inv_cpu_data(member) |
| 51 | |
| 52 | #define psci_dsbish() |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 53 | |
| 54 | /* |
| 55 | * On systems where participant CPUs are cache-coherent, we can use spinlocks |
| 56 | * instead of bakery locks. |
| 57 | */ |
| 58 | #define DEFINE_PSCI_LOCK(_name) spinlock_t _name |
| 59 | #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) |
| 60 | |
| 61 | #define psci_lock_get(non_cpu_pd_node) \ |
| 62 | spin_lock(&psci_locks[(non_cpu_pd_node)->lock_index]) |
| 63 | #define psci_lock_release(non_cpu_pd_node) \ |
| 64 | spin_unlock(&psci_locks[(non_cpu_pd_node)->lock_index]) |
| 65 | |
Jeenu Viswambharan | a10d363 | 2017-01-06 14:58:11 +0000 | [diff] [blame] | 66 | #else |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 67 | |
Jeenu Viswambharan | a10d363 | 2017-01-06 14:58:11 +0000 | [diff] [blame] | 68 | /* |
| 69 | * If not all PSCI participants are cache-coherent, perform cache maintenance |
| 70 | * and issue barriers wherever required to coordinate state. |
| 71 | */ |
| 72 | #define psci_flush_dcache_range(addr, size) flush_dcache_range(addr, size) |
| 73 | #define psci_flush_cpu_data(member) flush_cpu_data(member) |
| 74 | #define psci_inv_cpu_data(member) inv_cpu_data(member) |
| 75 | |
| 76 | #define psci_dsbish() dsbish() |
Jeenu Viswambharan | a10d363 | 2017-01-06 14:58:11 +0000 | [diff] [blame] | 77 | |
Soby Mathew | 8c5fe0b | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 78 | /* |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 79 | * Use bakery locks for state coordination as not all PSCI participants are |
| 80 | * cache coherent. |
Soby Mathew | 8c5fe0b | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 81 | */ |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 82 | #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) |
| 83 | #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) |
| 84 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 85 | #define psci_lock_get(non_cpu_pd_node) \ |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 86 | bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index]) |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 87 | #define psci_lock_release(non_cpu_pd_node) \ |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 88 | bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index]) |
Andrew Thoelke | 6c0b45d | 2014-06-20 00:36:14 +0100 | [diff] [blame] | 89 | |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 90 | #endif |
| 91 | |
| 92 | #define psci_lock_init(non_cpu_pd_node, idx) \ |
| 93 | ((non_cpu_pd_node)[(idx)].lock_index = (idx)) |
| 94 | |
Soby Mathew | 90e8258 | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 95 | /* |
| 96 | * The PSCI capability which are provided by the generic code but does not |
| 97 | * depend on the platform or spd capabilities. |
| 98 | */ |
| 99 | #define PSCI_GENERIC_CAP \ |
| 100 | (define_psci_cap(PSCI_VERSION) | \ |
| 101 | define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ |
| 102 | define_psci_cap(PSCI_FEATURES)) |
| 103 | |
| 104 | /* |
| 105 | * The PSCI capabilities mask for 64 bit functions. |
| 106 | */ |
| 107 | #define PSCI_CAP_64BIT_MASK \ |
| 108 | (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ |
| 109 | define_psci_cap(PSCI_CPU_ON_AARCH64) | \ |
| 110 | define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ |
| 111 | define_psci_cap(PSCI_MIG_AARCH64) | \ |
Soby Mathew | c0aff0e | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 112 | define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ |
Jeenu Viswambharan | 28d3d61 | 2016-08-03 15:54:50 +0100 | [diff] [blame] | 113 | define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ |
Yatharth Kochar | 170fb93 | 2016-05-09 18:26:35 +0100 | [diff] [blame] | 114 | define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ |
| 115 | define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ |
| 116 | define_psci_cap(PSCI_STAT_COUNT_AARCH64)) |
Soby Mathew | 90e8258 | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 117 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 118 | /* |
| 119 | * Helper macros to get/set the fields of PSCI per-cpu data. |
| 120 | */ |
| 121 | #define psci_set_aff_info_state(aff_state) \ |
| 122 | set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state) |
| 123 | #define psci_get_aff_info_state() \ |
| 124 | get_cpu_data(psci_svc_cpu_data.aff_info_state) |
| 125 | #define psci_get_aff_info_state_by_idx(idx) \ |
| 126 | get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state) |
Soby Mathew | 203cdfe | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 127 | #define psci_set_aff_info_state_by_idx(idx, aff_state) \ |
| 128 | set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state,\ |
| 129 | aff_state) |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 130 | #define psci_get_suspend_pwrlvl() \ |
| 131 | get_cpu_data(psci_svc_cpu_data.target_pwrlvl) |
| 132 | #define psci_set_suspend_pwrlvl(target_lvl) \ |
| 133 | set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl) |
| 134 | #define psci_set_cpu_local_state(state) \ |
| 135 | set_cpu_data(psci_svc_cpu_data.local_state, state) |
| 136 | #define psci_get_cpu_local_state() \ |
| 137 | get_cpu_data(psci_svc_cpu_data.local_state) |
| 138 | #define psci_get_cpu_local_state_by_idx(idx) \ |
| 139 | get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state) |
| 140 | |
| 141 | /* |
| 142 | * Helper macros for the CPU level spinlocks |
| 143 | */ |
| 144 | #define psci_spin_lock_cpu(idx) spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock) |
| 145 | #define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock) |
| 146 | |
| 147 | /* Helper macro to identify a CPU standby request in PSCI Suspend call */ |
| 148 | #define is_cpu_standby_req(is_power_down_state, retn_lvl) \ |
| 149 | (((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0) |
Soby Mathew | 90e8258 | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 150 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 151 | /******************************************************************************* |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 152 | * The following two data structures implement the power domain tree. The tree |
| 153 | * is used to track the state of all the nodes i.e. power domain instances |
| 154 | * described by the platform. The tree consists of nodes that describe CPU power |
| 155 | * domains i.e. leaf nodes and all other power domains which are parents of a |
| 156 | * CPU power domain i.e. non-leaf nodes. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | ******************************************************************************/ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 158 | typedef struct non_cpu_pwr_domain_node { |
| 159 | /* |
| 160 | * Index of the first CPU power domain node level 0 which has this node |
| 161 | * as its parent. |
| 162 | */ |
| 163 | unsigned int cpu_start_idx; |
| 164 | |
| 165 | /* |
| 166 | * Number of CPU power domains which are siblings of the domain indexed |
| 167 | * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx |
| 168 | * -> cpu_start_idx + ncpus' have this node as their parent. |
| 169 | */ |
| 170 | unsigned int ncpus; |
| 171 | |
| 172 | /* |
| 173 | * Index of the parent power domain node. |
| 174 | * TODO: Figure out whether to whether using pointer is more efficient. |
| 175 | */ |
| 176 | unsigned int parent_node; |
| 177 | |
| 178 | plat_local_state_t local_state; |
| 179 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 180 | unsigned char level; |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 181 | |
| 182 | /* For indexing the psci_lock array*/ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 183 | unsigned char lock_index; |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 184 | } non_cpu_pd_node_t; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 186 | typedef struct cpu_pwr_domain_node { |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 187 | u_register_t mpidr; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 189 | /* |
| 190 | * Index of the parent power domain node. |
| 191 | * TODO: Figure out whether to whether using pointer is more efficient. |
| 192 | */ |
| 193 | unsigned int parent_node; |
| 194 | |
| 195 | /* |
| 196 | * A CPU power domain does not require state coordination like its |
| 197 | * parent power domains. Hence this node does not include a bakery |
| 198 | * lock. A spinlock is required by the CPU_ON handler to prevent a race |
| 199 | * when multiple CPUs try to turn ON the same target CPU. |
| 200 | */ |
| 201 | spinlock_t cpu_lock; |
| 202 | } cpu_pd_node_t; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | |
| 204 | /******************************************************************************* |
| 205 | * Data prototypes |
| 206 | ******************************************************************************/ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 207 | extern const plat_psci_ops_t *psci_plat_pm_ops; |
| 208 | extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; |
| 209 | extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 210 | extern unsigned int psci_caps; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 211 | |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 212 | /* One lock is required per non-CPU power domain node */ |
| 213 | DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 214 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 215 | /******************************************************************************* |
Jeenu Viswambharan | 7f36660 | 2014-02-20 17:11:00 +0000 | [diff] [blame] | 216 | * SPD's power management hooks registered with PSCI |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 217 | ******************************************************************************/ |
Dan Handley | fb037bf | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 218 | extern const spd_pm_ops_t *psci_spd_pm; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 219 | |
| 220 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | * Function prototypes |
| 222 | ******************************************************************************/ |
| 223 | /* Private exported functions from psci_common.c */ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 224 | int psci_validate_power_state(unsigned int power_state, |
| 225 | psci_power_state_t *state_info); |
| 226 | void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 227 | int psci_validate_mpidr(u_register_t mpidr); |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 228 | void psci_init_req_local_pwr_states(void); |
Achin Gupta | 61eae52 | 2016-06-28 16:46:15 +0100 | [diff] [blame] | 229 | void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, |
| 230 | psci_power_state_t *target_state); |
Soby Mathew | 617540d | 2015-07-15 12:13:26 +0100 | [diff] [blame] | 231 | int psci_validate_entry_point(entry_point_info_t *ep, |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 232 | uintptr_t entrypoint, u_register_t context_id); |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 233 | void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 234 | unsigned int end_lvl, |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 235 | unsigned int node_index[]); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 236 | void psci_do_state_coordination(unsigned int end_pwrlvl, |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 237 | psci_power_state_t *state_info); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 238 | void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 239 | unsigned int cpu_idx); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 240 | void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 241 | unsigned int cpu_idx); |
| 242 | int psci_validate_suspend_req(const psci_power_state_t *state_info, |
| 243 | unsigned int is_power_down_state_req); |
| 244 | unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); |
| 245 | unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 246 | void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 247 | void psci_print_power_domain_map(void); |
Soby Mathew | c0aff0e | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 248 | unsigned int psci_is_last_on_cpu(void); |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 249 | int psci_spd_migrate_info(u_register_t *mpidr); |
Jeenu Viswambharan | b0408e8 | 2017-01-05 11:01:02 +0000 | [diff] [blame^] | 250 | void psci_do_pwrdown_sequence(unsigned int power_level); |
| 251 | |
| 252 | /* |
| 253 | * CPU power down is directly called only when HW_ASSISTED_COHERENCY is |
| 254 | * available. Otherwise, this needs post-call stack maintenance, which is |
| 255 | * handled in assembly. |
| 256 | */ |
| 257 | void prepare_cpu_pwr_dwn(unsigned int power_level); |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 258 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 259 | /* Private exported functions from psci_on.c */ |
Soby Mathew | 4c0d039 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 260 | int psci_cpu_on_start(u_register_t target_cpu, |
Sandrine Bailleux | 22b09c1 | 2016-04-25 09:28:43 +0100 | [diff] [blame] | 261 | entry_point_info_t *ep); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 262 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 263 | void psci_cpu_on_finish(unsigned int cpu_idx, |
| 264 | psci_power_state_t *state_info); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 265 | |
Sandrine Bailleux | 1645d3e | 2015-12-17 13:58:58 +0000 | [diff] [blame] | 266 | /* Private exported functions from psci_off.c */ |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 267 | int psci_do_cpu_off(unsigned int end_pwrlvl); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 268 | |
Sandrine Bailleux | 1645d3e | 2015-12-17 13:58:58 +0000 | [diff] [blame] | 269 | /* Private exported functions from psci_suspend.c */ |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 270 | void psci_cpu_suspend_start(entry_point_info_t *ep, |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 271 | unsigned int end_pwrlvl, |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 272 | psci_power_state_t *state_info, |
| 273 | unsigned int is_power_down_state_req); |
Soby Mathew | 78879b9 | 2015-01-06 15:36:38 +0000 | [diff] [blame] | 274 | |
Soby Mathew | 6748784 | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 275 | void psci_cpu_suspend_finish(unsigned int cpu_idx, |
| 276 | psci_power_state_t *state_info); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 277 | |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 278 | /* Private exported functions from psci_helpers.S */ |
Soby Mathew | 9d070b9 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 279 | void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); |
Achin Gupta | b51da82 | 2014-06-26 09:58:52 +0100 | [diff] [blame] | 280 | void psci_do_pwrup_cache_maintenance(void); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 281 | |
Juan Castillo | d5f1309 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 282 | /* Private exported functions from psci_system_off.c */ |
| 283 | void __dead2 psci_system_off(void); |
| 284 | void __dead2 psci_system_reset(void); |
| 285 | |
Yatharth Kochar | 170fb93 | 2016-05-09 18:26:35 +0100 | [diff] [blame] | 286 | /* Private exported functions from psci_stat.c */ |
| 287 | void psci_stats_update_pwr_down(unsigned int end_pwrlvl, |
| 288 | const psci_power_state_t *state_info); |
| 289 | void psci_stats_update_pwr_up(unsigned int end_pwrlvl, |
dp-arm | 04c1db1 | 2017-01-31 13:01:04 +0000 | [diff] [blame] | 290 | const psci_power_state_t *state_info); |
Yatharth Kochar | 170fb93 | 2016-05-09 18:26:35 +0100 | [diff] [blame] | 291 | u_register_t psci_stat_residency(u_register_t target_cpu, |
| 292 | unsigned int power_state); |
| 293 | u_register_t psci_stat_count(u_register_t target_cpu, |
| 294 | unsigned int power_state); |
| 295 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 296 | #endif /* __PSCI_PRIVATE_H__ */ |