Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 1 | /* |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <drivers/console.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <errno.h> |
| 12 | #include <drivers/arm/gicv2.h> |
| 13 | #include <lib/mmio.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | #include <platform_def.h> |
| 16 | #include <lib/psci/psci.h> |
| 17 | |
Carlo Caione | e26864a | 2019-08-24 17:31:51 +0100 | [diff] [blame] | 18 | #include "aml_private.h" |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 19 | |
| 20 | #define SCPI_POWER_ON 0 |
| 21 | #define SCPI_POWER_RETENTION 1 |
| 22 | #define SCPI_POWER_OFF 3 |
| 23 | |
| 24 | #define SCPI_SYSTEM_SHUTDOWN 0 |
| 25 | #define SCPI_SYSTEM_REBOOT 1 |
| 26 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 27 | static uintptr_t gxl_sec_entrypoint; |
| 28 | static volatile uint32_t gxl_cpu0_go; |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 29 | |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 30 | static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 31 | { |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 32 | unsigned int core = plat_calc_core_pos(mpidr); |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 33 | uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 34 | |
| 35 | mmio_write_64(cpu_mailbox_addr, value); |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | static void gxl_pm_reset(u_register_t mpidr) |
| 39 | { |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 40 | unsigned int core = plat_calc_core_pos(mpidr); |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 41 | uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8; |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 42 | |
| 43 | mmio_write_32(cpu_mailbox_addr, 0); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 44 | } |
| 45 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 46 | static void __dead2 gxl_system_reset(void) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 47 | { |
| 48 | INFO("BL31: PSCI_SYSTEM_RESET\n"); |
| 49 | |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 50 | u_register_t mpidr = read_mpidr_el1(); |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 51 | uint32_t status = mmio_read_32(AML_AO_RTI_STATUS_REG3); |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 52 | int ret; |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 53 | |
| 54 | NOTICE("BL31: Reboot reason: 0x%x\n", status); |
| 55 | |
| 56 | status &= 0xFFFF0FF0; |
| 57 | |
| 58 | console_flush(); |
| 59 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 60 | mmio_write_32(AML_AO_RTI_STATUS_REG3, status); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 61 | |
Carlo Caione | 9a5616f | 2019-08-28 10:08:24 +0100 | [diff] [blame] | 62 | ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 63 | |
| 64 | if (ret != 0) { |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 65 | ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 66 | panic(); |
| 67 | } |
| 68 | |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 69 | gxl_pm_reset(mpidr); |
| 70 | |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 71 | wfi(); |
| 72 | |
| 73 | ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); |
| 74 | panic(); |
| 75 | } |
| 76 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 77 | static void __dead2 gxl_system_off(void) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 78 | { |
| 79 | INFO("BL31: PSCI_SYSTEM_OFF\n"); |
| 80 | |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 81 | u_register_t mpidr = read_mpidr_el1(); |
| 82 | int ret; |
| 83 | |
Carlo Caione | 9a5616f | 2019-08-28 10:08:24 +0100 | [diff] [blame] | 84 | ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 85 | |
| 86 | if (ret != 0) { |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 87 | ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 88 | panic(); |
| 89 | } |
| 90 | |
Remi Pommarel | 43d4a29 | 2019-04-04 23:12:56 +0200 | [diff] [blame] | 91 | gxl_pm_set_reset_addr(mpidr, 0); |
| 92 | gxl_pm_reset(mpidr); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 93 | |
| 94 | wfi(); |
| 95 | |
| 96 | ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); |
| 97 | panic(); |
| 98 | } |
| 99 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 100 | static int32_t gxl_pwr_domain_on(u_register_t mpidr) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 101 | { |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 102 | unsigned int core = plat_calc_core_pos(mpidr); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 103 | |
| 104 | /* CPU0 can't be turned OFF, emulate it with a WFE loop */ |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 105 | if (core == AML_PRIMARY_CPU) { |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 106 | VERBOSE("BL31: Releasing CPU0 from wait loop...\n"); |
| 107 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 108 | gxl_cpu0_go = 1; |
| 109 | flush_dcache_range((uintptr_t)&gxl_cpu0_go, |
| 110 | sizeof(gxl_cpu0_go)); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 111 | dsb(); |
| 112 | isb(); |
| 113 | |
| 114 | sev(); |
| 115 | |
| 116 | return PSCI_E_SUCCESS; |
| 117 | } |
| 118 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 119 | gxl_pm_set_reset_addr(mpidr, gxl_sec_entrypoint); |
Carlo Caione | 9a5616f | 2019-08-28 10:08:24 +0100 | [diff] [blame] | 120 | aml_scpi_set_css_power_state(mpidr, |
| 121 | SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 122 | dmbsy(); |
| 123 | sev(); |
| 124 | |
| 125 | return PSCI_E_SUCCESS; |
| 126 | } |
| 127 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 128 | static void gxl_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 129 | { |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 130 | unsigned int core = plat_calc_core_pos(read_mpidr_el1()); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 131 | |
| 132 | assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == |
| 133 | PLAT_LOCAL_STATE_OFF); |
| 134 | |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 135 | if (core == AML_PRIMARY_CPU) { |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 136 | gxl_cpu0_go = 0; |
| 137 | flush_dcache_range((uintptr_t)&gxl_cpu0_go, |
| 138 | sizeof(gxl_cpu0_go)); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 139 | dsb(); |
| 140 | isb(); |
| 141 | } |
| 142 | |
| 143 | gicv2_pcpu_distif_init(); |
| 144 | gicv2_cpuif_enable(); |
| 145 | } |
| 146 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 147 | static void gxl_pwr_domain_off(const psci_power_state_t *target_state) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 148 | { |
| 149 | u_register_t mpidr = read_mpidr_el1(); |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 150 | unsigned int core = plat_calc_core_pos(mpidr); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 151 | |
| 152 | gicv2_cpuif_disable(); |
| 153 | |
| 154 | /* CPU0 can't be turned OFF, emulate it with a WFE loop */ |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 155 | if (core == AML_PRIMARY_CPU) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 156 | return; |
| 157 | |
Carlo Caione | 9a5616f | 2019-08-28 10:08:24 +0100 | [diff] [blame] | 158 | aml_scpi_set_css_power_state(mpidr, |
| 159 | SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 160 | } |
| 161 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 162 | static void __dead2 gxl_pwr_domain_pwr_down_wfi(const psci_power_state_t |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 163 | *target_state) |
| 164 | { |
Remi Pommarel | b4694a8 | 2019-07-30 18:04:38 +0200 | [diff] [blame] | 165 | u_register_t mpidr = read_mpidr_el1(); |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 166 | unsigned int core = plat_calc_core_pos(mpidr); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 167 | |
| 168 | /* CPU0 can't be turned OFF, emulate it with a WFE loop */ |
Carlo Caione | f681c67 | 2019-08-24 18:47:06 +0100 | [diff] [blame] | 169 | if (core == AML_PRIMARY_CPU) { |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 170 | VERBOSE("BL31: CPU0 entering wait loop...\n"); |
| 171 | |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 172 | while (gxl_cpu0_go == 0) |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 173 | wfe(); |
| 174 | |
| 175 | VERBOSE("BL31: CPU0 resumed.\n"); |
| 176 | |
Remi Pommarel | b4694a8 | 2019-07-30 18:04:38 +0200 | [diff] [blame] | 177 | /* |
| 178 | * Because setting CPU0's warm reset entrypoint through PSCI |
| 179 | * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem |
| 180 | * to work, jump to it manually. |
| 181 | * In order to avoid an assert, mmu has to be disabled. |
| 182 | */ |
| 183 | disable_mmu_el3(); |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 184 | ((void(*)(void))gxl_sec_entrypoint)(); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | dsbsy(); |
Remi Pommarel | b4694a8 | 2019-07-30 18:04:38 +0200 | [diff] [blame] | 188 | gxl_pm_set_reset_addr(mpidr, 0); |
| 189 | gxl_pm_reset(mpidr); |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 190 | |
| 191 | for (;;) |
| 192 | wfi(); |
| 193 | } |
| 194 | |
| 195 | /******************************************************************************* |
| 196 | * Platform handlers and setup function. |
| 197 | ******************************************************************************/ |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 198 | static const plat_psci_ops_t gxl_ops = { |
| 199 | .pwr_domain_on = gxl_pwr_domain_on, |
| 200 | .pwr_domain_on_finish = gxl_pwr_domain_on_finish, |
| 201 | .pwr_domain_off = gxl_pwr_domain_off, |
| 202 | .pwr_domain_pwr_down_wfi = gxl_pwr_domain_pwr_down_wfi, |
| 203 | .system_off = gxl_system_off, |
| 204 | .system_reset = gxl_system_reset, |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 208 | const plat_psci_ops_t **psci_ops) |
| 209 | { |
Carlo Caione | 0e1d789 | 2019-08-28 15:19:56 +0100 | [diff] [blame] | 210 | gxl_sec_entrypoint = sec_entrypoint; |
| 211 | *psci_ops = &gxl_ops; |
| 212 | gxl_cpu0_go = 0; |
Antonio Nino Diaz | 95d0d13 | 2018-12-05 00:09:30 +0000 | [diff] [blame] | 213 | return 0; |
| 214 | } |