Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <platform.h> |
| 32 | |
| 33 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 34 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 9f98aa1 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 35 | ENTRY(bl31_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | |
| 37 | |
| 38 | MEMORY { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 39 | RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE |
| 40 | } |
| 41 | |
| 42 | |
| 43 | SECTIONS |
| 44 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 45 | . = BL31_BASE; |
| 46 | ASSERT(. == ALIGN(4096), |
| 47 | "BL31_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 49 | ro . : { |
| 50 | __RO_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 51 | *bl31_entrypoint.o(.text*) |
| 52 | *(.text*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 53 | *(.rodata*) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 54 | |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 55 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 56 | . = ALIGN(8); |
| 57 | __RT_SVC_DESCS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 58 | KEEP(*(rt_svc_descs)) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 59 | __RT_SVC_DESCS_END__ = .; |
| 60 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 61 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 62 | __RO_END_UNALIGNED__ = .; |
| 63 | /* |
| 64 | * Memory page(s) mapped to this section will be marked as read-only, |
| 65 | * executable. No RW data from the next section must creep in. |
| 66 | * Ensure the rest of the current memory page is unused. |
| 67 | */ |
| 68 | . = NEXT(4096); |
| 69 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 70 | } >RAM |
| 71 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 72 | .data . : { |
| 73 | __DATA_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 74 | *(.data*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 75 | __DATA_END__ = .; |
| 76 | } >RAM |
| 77 | |
| 78 | stacks (NOLOAD) : { |
| 79 | __STACKS_START__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 80 | *(tzfw_normal_stacks) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 81 | __STACKS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 82 | } >RAM |
| 83 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 84 | /* |
| 85 | * The .bss section gets initialised to 0 at runtime. |
| 86 | * Its base address must be 16-byte aligned. |
| 87 | */ |
| 88 | .bss : ALIGN(16) { |
| 89 | __BSS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 90 | *(.bss*) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 91 | *(COMMON) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 92 | __BSS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | } >RAM |
| 94 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 95 | /* |
Jeenu Viswambharan | e3fff15 | 2014-02-24 15:20:28 +0000 | [diff] [blame] | 96 | * The xlat_table section is for full, aligned page tables (4K). |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 97 | * Removing them from .bss avoids forcing 4K alignment on |
| 98 | * the .bss section and eliminates the unecessary zero init |
| 99 | */ |
| 100 | xlat_table (NOLOAD) : { |
| 101 | *(xlat_table) |
| 102 | } >RAM |
| 103 | |
| 104 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 105 | * The base address of the coherent memory section must be page-aligned (4K) |
| 106 | * to guarantee that the coherent data are stored on their own pages and |
| 107 | * are not mixed with normal data. This is required to set up the correct |
| 108 | * memory attributes for the coherent data page tables. |
| 109 | */ |
| 110 | coherent_ram (NOLOAD) : ALIGN(4096) { |
| 111 | __COHERENT_RAM_START__ = .; |
| 112 | *(tzfw_coherent_mem) |
| 113 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 114 | /* |
| 115 | * Memory page(s) mapped to this section will be marked |
| 116 | * as device memory. No other unexpected data must creep in. |
| 117 | * Ensure the rest of the current memory page is unused. |
| 118 | */ |
| 119 | . = NEXT(4096); |
| 120 | __COHERENT_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 121 | } >RAM |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 122 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 123 | __BL31_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 124 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 125 | __BSS_SIZE__ = SIZEOF(.bss); |
| 126 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 127 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 128 | |
Sandrine Bailleux | a37255a | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 129 | ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 130 | } |