Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | ca661a0 | 2019-12-23 14:49:52 -0600 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | ee21281 | 2018-06-20 13:43:43 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 4 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 8 | #include <assert.h> |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 9 | #include <errno.h> |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 10 | #include <stddef.h> |
Varun Wadekar | da3849e | 2016-05-23 15:56:14 -0700 | [diff] [blame] | 11 | #include <string.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <platform_def.h> |
| 14 | |
| 15 | #include <arch.h> |
| 16 | #include <arch_helpers.h> |
| 17 | #include <bl31/bl31.h> |
| 18 | #include <common/bl_common.h> |
| 19 | #include <common/debug.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 20 | #include <cortex_a57.h> |
| 21 | #include <denver.h> |
| 22 | #include <drivers/console.h> |
| 23 | #include <lib/mmio.h> |
| 24 | #include <lib/utils.h> |
| 25 | #include <lib/utils_def.h> |
| 26 | #include <plat/common/platform.h> |
| 27 | |
| 28 | #include <memctrl.h> |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 29 | #include <profiler.h> |
Varun Wadekar | 21ec61a | 2019-09-26 08:26:41 -0700 | [diff] [blame] | 30 | #include <smmu.h> |
Varun Wadekar | 06b19d5 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 31 | #include <tegra_def.h> |
Harvey Hsieh | 322e7c3 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 32 | #include <tegra_platform.h> |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 33 | #include <tegra_private.h> |
| 34 | |
Arve Hjønnevåg | 06ff251 | 2018-02-21 17:36:44 -0800 | [diff] [blame] | 35 | /* length of Trusty's input parameters (in bytes) */ |
| 36 | #define TRUSTY_PARAMS_LEN_BYTES (4096*2) |
| 37 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 38 | /******************************************************************************* |
| 39 | * Declarations of linker defined symbols which will help us find the layout |
| 40 | * of trusted SRAM |
| 41 | ******************************************************************************/ |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 42 | IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); |
Madhukar Pappireddy | ca661a0 | 2019-12-23 14:49:52 -0600 | [diff] [blame] | 43 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 44 | extern uint64_t tegra_bl31_phys_base; |
| 45 | |
Varun Wadekar | dc7fdad | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 46 | static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 47 | static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 48 | .tzdram_size = TZDRAM_SIZE |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 49 | }; |
Varun Wadekar | 2783205 | 2019-12-17 21:23:24 -0800 | [diff] [blame] | 50 | #ifdef SPD_trusty |
| 51 | static aapcs64_params_t bl32_args; |
| 52 | #endif |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 53 | |
| 54 | /******************************************************************************* |
| 55 | * This variable holds the non-secure image entry address |
| 56 | ******************************************************************************/ |
| 57 | extern uint64_t ns_image_entrypoint; |
| 58 | |
| 59 | /******************************************************************************* |
| 60 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 61 | * security state specified. BL33 corresponds to the non-secure image type |
| 62 | * while BL32 corresponds to the secure image type. |
| 63 | ******************************************************************************/ |
| 64 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 65 | { |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 66 | entry_point_info_t *ep = NULL; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 67 | |
Varun Wadekar | 4ce9a18 | 2016-06-06 10:46:28 -0700 | [diff] [blame] | 68 | /* return BL32 entry point info if it is valid */ |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 69 | if (type == NON_SECURE) { |
| 70 | ep = &bl33_image_ep_info; |
| 71 | } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { |
| 72 | ep = &bl32_image_ep_info; |
| 73 | } |
Varun Wadekar | dc7fdad | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 74 | |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 75 | return ep; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | /******************************************************************************* |
| 79 | * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image |
| 80 | * passes this platform specific information. |
| 81 | ******************************************************************************/ |
| 82 | plat_params_from_bl2_t *bl31_get_plat_params(void) |
| 83 | { |
| 84 | return &plat_bl31_params_from_bl2; |
| 85 | } |
| 86 | |
| 87 | /******************************************************************************* |
| 88 | * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image |
| 89 | * info. |
| 90 | ******************************************************************************/ |
Antonio Nino Diaz | fdcc112 | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 91 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 92 | u_register_t arg2, u_register_t arg3) |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 93 | { |
Antonio Nino Diaz | fdcc112 | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 94 | struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; |
| 95 | plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 96 | int32_t ret; |
Varun Wadekar | 08cefa9 | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 97 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 98 | /* |
Varun Wadekar | 8ab06d2 | 2016-05-23 11:41:07 -0700 | [diff] [blame] | 99 | * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so |
| 100 | * there's no argument to relay from a previous bootloader. Platforms |
Varun Wadekar | 39171cd | 2018-05-17 09:36:38 -0700 | [diff] [blame] | 101 | * might use custom ways to get arguments. |
Varun Wadekar | 8ab06d2 | 2016-05-23 11:41:07 -0700 | [diff] [blame] | 102 | */ |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 103 | if (arg_from_bl2 == NULL) { |
Antonio Nino Diaz | fdcc112 | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 104 | arg_from_bl2 = plat_get_bl31_params(); |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 105 | } |
| 106 | if (plat_params == NULL) { |
Varun Wadekar | 8ab06d2 | 2016-05-23 11:41:07 -0700 | [diff] [blame] | 107 | plat_params = plat_get_bl31_plat_params(); |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 108 | } |
Varun Wadekar | 8ab06d2 | 2016-05-23 11:41:07 -0700 | [diff] [blame] | 109 | |
| 110 | /* |
Varun Wadekar | dc7fdad | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 111 | * Copy BL3-3, BL3-2 entry point information. |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 112 | * They are stored in Secure RAM, in BL2's address space. |
| 113 | */ |
Anthony Zhou | 4c99400 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 114 | assert(arg_from_bl2 != NULL); |
| 115 | assert(arg_from_bl2->bl33_ep_info != NULL); |
Antonio Nino Diaz | fdcc112 | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 116 | bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; |
Varun Wadekar | 08cefa9 | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 117 | |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 118 | if (arg_from_bl2->bl32_ep_info != NULL) { |
Antonio Nino Diaz | fdcc112 | 2018-09-24 17:16:05 +0100 | [diff] [blame] | 119 | bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; |
Varun Wadekar | 2783205 | 2019-12-17 21:23:24 -0800 | [diff] [blame] | 120 | #ifdef SPD_trusty |
| 121 | /* save BL32 boot parameters */ |
| 122 | memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); |
| 123 | #endif |
Arve Hjønnevåg | 06ff251 | 2018-02-21 17:36:44 -0800 | [diff] [blame] | 124 | } |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 125 | |
| 126 | /* |
Varun Wadekar | 3ca3c27 | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 127 | * Parse platform specific parameters |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 128 | */ |
Anthony Zhou | 4c99400 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 129 | assert(plat_params != NULL); |
Varun Wadekar | e0d4158 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 130 | plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; |
| 131 | plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; |
Varun Wadekar | e108421 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 132 | plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; |
Harvey Hsieh | b495791 | 2016-11-23 19:13:08 +0800 | [diff] [blame] | 133 | plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; |
Varun Wadekar | 3ca3c27 | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 134 | plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; |
| 135 | plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; |
Varun Wadekar | e108421 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 136 | |
| 137 | /* |
Varun Wadekar | 939dcf2 | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 138 | * It is very important that we run either from TZDRAM or TZSRAM base. |
| 139 | * Add an explicit check here. |
| 140 | */ |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 141 | if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && |
| 142 | (TEGRA_TZRAM_BASE != BL31_BASE)) { |
Varun Wadekar | 939dcf2 | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 143 | panic(); |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 144 | } |
Varun Wadekar | 939dcf2 | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 145 | |
| 146 | /* |
Varun Wadekar | 117dbe6 | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 147 | * Enable console for the platform |
Harvey Hsieh | 322e7c3 | 2017-04-10 16:20:32 +0800 | [diff] [blame] | 148 | */ |
Varun Wadekar | 117dbe6 | 2019-08-21 14:01:31 -0700 | [diff] [blame] | 149 | plat_enable_console(plat_params->uart_id); |
Varun Wadekar | e108421 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 150 | |
Varun Wadekar | 08012f4 | 2016-06-04 22:08:50 -0700 | [diff] [blame] | 151 | /* |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 152 | * The previous bootloader passes the base address of the shared memory |
| 153 | * location to store the boot profiler logs. Sanity check the |
Andreas Färber | 9d74bc3 | 2019-06-17 00:06:43 +0200 | [diff] [blame] | 154 | * address and initialise the profiler library, if it looks ok. |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 155 | */ |
Varun Wadekar | ee21281 | 2018-06-20 13:43:43 -0700 | [diff] [blame] | 156 | ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, |
| 157 | PROFILER_SIZE_BYTES); |
| 158 | if (ret == (int32_t)0) { |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 159 | |
Varun Wadekar | ee21281 | 2018-06-20 13:43:43 -0700 | [diff] [blame] | 160 | /* store the membase for the profiler lib */ |
| 161 | plat_bl31_params_from_bl2.boot_profiler_shmem_base = |
| 162 | plat_params->boot_profiler_shmem_base; |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 163 | |
Varun Wadekar | ee21281 | 2018-06-20 13:43:43 -0700 | [diff] [blame] | 164 | /* initialise the profiler library */ |
| 165 | boot_profiler_init(plat_params->boot_profiler_shmem_base, |
| 166 | TEGRA_TMRUS_BASE); |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | /* |
| 170 | * Add timestamp for platform early setup entry. |
| 171 | */ |
| 172 | boot_profiler_add_record("[TF] early setup entry"); |
| 173 | |
| 174 | /* |
Steven Kao | d29d96f | 2016-10-21 14:16:59 +0800 | [diff] [blame] | 175 | * Initialize delay timer |
| 176 | */ |
| 177 | tegra_delay_timer_init(); |
| 178 | |
Varun Wadekar | 01da3bd | 2017-09-20 15:09:38 -0700 | [diff] [blame] | 179 | /* Early platform setup for Tegra SoCs */ |
| 180 | plat_early_platform_setup(); |
| 181 | |
Steven Kao | d29d96f | 2016-10-21 14:16:59 +0800 | [diff] [blame] | 182 | /* |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 183 | * Add timestamp for platform early setup exit. |
| 184 | */ |
| 185 | boot_profiler_add_record("[TF] early setup exit"); |
| 186 | |
Sandrine Bailleux | c426fd7 | 2018-06-21 11:41:43 +0200 | [diff] [blame] | 187 | INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", |
| 188 | (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) |
| 189 | == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 190 | } |
| 191 | |
Arve Hjønnevåg | 06ff251 | 2018-02-21 17:36:44 -0800 | [diff] [blame] | 192 | #ifdef SPD_trusty |
| 193 | void plat_trusty_set_boot_args(aapcs64_params_t *args) |
| 194 | { |
Varun Wadekar | 2783205 | 2019-12-17 21:23:24 -0800 | [diff] [blame] | 195 | /* |
| 196 | * arg0 = TZDRAM aperture available for BL32 |
| 197 | * arg1 = BL32 boot params |
| 198 | * arg2 = EKS Blob Length |
| 199 | * arg3 = Boot Profiler Carveout Base |
| 200 | */ |
| 201 | args->arg0 = bl32_args.arg0; |
| 202 | args->arg1 = bl32_args.arg2; |
Varun Wadekar | 47b83ad | 2018-12-28 13:50:20 -0800 | [diff] [blame] | 203 | |
| 204 | /* update EKS size */ |
Varun Wadekar | 2783205 | 2019-12-17 21:23:24 -0800 | [diff] [blame] | 205 | args->arg2 = bl32_args.arg4; |
Varun Wadekar | db82b61 | 2019-01-02 16:30:01 -0800 | [diff] [blame] | 206 | |
| 207 | /* Profiler Carveout Base */ |
Varun Wadekar | 2783205 | 2019-12-17 21:23:24 -0800 | [diff] [blame] | 208 | args->arg3 = bl32_args.arg5; |
Arve Hjønnevåg | 06ff251 | 2018-02-21 17:36:44 -0800 | [diff] [blame] | 209 | } |
| 210 | #endif |
| 211 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 212 | /******************************************************************************* |
| 213 | * Initialize the gic, configure the SCR. |
| 214 | ******************************************************************************/ |
| 215 | void bl31_platform_setup(void) |
| 216 | { |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 217 | /* |
| 218 | * Add timestamp for platform setup entry. |
| 219 | */ |
| 220 | boot_profiler_add_record("[TF] plat setup entry"); |
| 221 | |
Varun Wadekar | d336030 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 222 | /* Initialize the gic cpu and distributor interfaces */ |
| 223 | plat_gic_setup(); |
| 224 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 225 | /* |
| 226 | * Setup secondary CPU POR infrastructure. |
| 227 | */ |
| 228 | plat_secondary_setup(); |
| 229 | |
| 230 | /* |
| 231 | * Initial Memory Controller configuration. |
| 232 | */ |
| 233 | tegra_memctrl_setup(); |
| 234 | |
| 235 | /* |
Dilan Lee | 3e1923d | 2017-10-27 09:51:09 +0800 | [diff] [blame] | 236 | * Late setup handler to allow platforms to performs additional |
| 237 | * functionality. |
| 238 | * This handler gets called with MMU enabled. |
| 239 | */ |
| 240 | plat_late_platform_setup(); |
| 241 | |
| 242 | /* |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 243 | * Add timestamp for platform setup exit. |
| 244 | */ |
| 245 | boot_profiler_add_record("[TF] plat setup exit"); |
| 246 | |
Varun Wadekar | 08cefa9 | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 247 | INFO("BL3-1: Tegra platform setup complete\n"); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | /******************************************************************************* |
Varun Wadekar | 25caa16 | 2016-01-08 17:48:42 -0800 | [diff] [blame] | 251 | * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit |
| 252 | ******************************************************************************/ |
| 253 | void bl31_plat_runtime_setup(void) |
| 254 | { |
Varun Wadekar | 0c2276e | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 255 | /* |
Kalyani Chidambaram Vaidyanathan | 3ff448f | 2020-06-15 16:48:53 -0700 | [diff] [blame] | 256 | * Platform specific runtime setup |
Harvey Hsieh | 650d9c5 | 2017-08-21 15:01:53 +0800 | [diff] [blame] | 257 | */ |
Kalyani Chidambaram Vaidyanathan | 3ff448f | 2020-06-15 16:48:53 -0700 | [diff] [blame] | 258 | plat_runtime_setup(); |
Varun Wadekar | 21ec61a | 2019-09-26 08:26:41 -0700 | [diff] [blame] | 259 | |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 260 | /* |
| 261 | * Add final timestamp before exiting BL31. |
| 262 | */ |
| 263 | boot_profiler_add_record("[TF] bl31 exit"); |
| 264 | boot_profiler_deinit(); |
Varun Wadekar | 25caa16 | 2016-01-08 17:48:42 -0800 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | /******************************************************************************* |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 268 | * Perform the very early platform specific architectural setup here. At the |
| 269 | * moment this only intializes the mmu in a quick and dirty way. |
| 270 | ******************************************************************************/ |
| 271 | void bl31_plat_arch_setup(void) |
| 272 | { |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 273 | uint64_t rw_start = BL31_RW_START; |
Kalyani Chidambaram | 2bf1085 | 2018-12-19 11:06:14 -0800 | [diff] [blame] | 274 | uint64_t rw_size = BL_END - BL31_RW_START; |
| 275 | uint64_t rodata_start = BL_RO_DATA_BASE; |
| 276 | uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; |
| 277 | uint64_t code_base = BL_CODE_BASE; |
| 278 | uint64_t code_size = BL_CODE_END - BL_CODE_BASE; |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 279 | const mmap_region_t *plat_mmio_map = NULL; |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 280 | const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 281 | |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 282 | /* |
| 283 | * Add timestamp for arch setup entry. |
| 284 | */ |
| 285 | boot_profiler_add_record("[TF] arch setup entry"); |
| 286 | |
Varun Wadekar | 26cf084 | 2018-01-23 14:38:51 -0800 | [diff] [blame] | 287 | /* add MMIO space */ |
| 288 | plat_mmio_map = plat_get_mmio_map(); |
| 289 | if (plat_mmio_map != NULL) { |
| 290 | mmap_add(plat_mmio_map); |
| 291 | } else { |
| 292 | WARN("MMIO map not available\n"); |
| 293 | } |
| 294 | |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 295 | /* add memory regions */ |
Varun Wadekar | bc0a0be | 2017-02-28 08:23:59 -0800 | [diff] [blame] | 296 | mmap_add_region(rw_start, rw_start, |
| 297 | rw_size, |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 298 | MT_MEMORY | MT_RW | MT_SECURE); |
Varun Wadekar | bc0a0be | 2017-02-28 08:23:59 -0800 | [diff] [blame] | 299 | mmap_add_region(rodata_start, rodata_start, |
| 300 | rodata_size, |
| 301 | MT_RO_DATA | MT_SECURE); |
| 302 | mmap_add_region(code_base, code_base, |
| 303 | code_size, |
| 304 | MT_CODE | MT_SECURE); |
Varun Wadekar | 68e2a64 | 2015-07-08 12:57:50 +0530 | [diff] [blame] | 305 | |
Varun Wadekar | 26cf084 | 2018-01-23 14:38:51 -0800 | [diff] [blame] | 306 | /* map TZDRAM used by BL31 as coherent memory */ |
| 307 | if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { |
| 308 | mmap_add_region(params_from_bl2->tzdram_base, |
| 309 | params_from_bl2->tzdram_base, |
| 310 | BL31_SIZE, |
| 311 | MT_DEVICE | MT_RW | MT_SECURE); |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 312 | } |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 313 | |
| 314 | /* set up translation tables */ |
| 315 | init_xlat_tables(); |
| 316 | |
| 317 | /* enable the MMU */ |
| 318 | enable_mmu_el3(0); |
Varun Wadekar | 08cefa9 | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 319 | |
Varun Wadekar | 087cf68 | 2017-07-21 13:34:16 -0700 | [diff] [blame] | 320 | /* |
| 321 | * Add timestamp for arch setup exit. |
| 322 | */ |
| 323 | boot_profiler_add_record("[TF] arch setup exit"); |
| 324 | |
Varun Wadekar | 08cefa9 | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 325 | INFO("BL3-1: Tegra: MMU enabled\n"); |
Varun Wadekar | 08438e2 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 326 | } |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 327 | |
| 328 | /******************************************************************************* |
| 329 | * Check if the given NS DRAM range is valid |
| 330 | ******************************************************************************/ |
Varun Wadekar | fcf23a1 | 2019-01-02 10:48:18 -0800 | [diff] [blame] | 331 | int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 332 | { |
Varun Wadekar | 6460ed7 | 2017-07-20 09:43:28 -0700 | [diff] [blame] | 333 | uint64_t end = base + size_in_bytes - U(1); |
Varun Wadekar | 685e560 | 2020-06-02 21:16:00 -0700 | [diff] [blame] | 334 | |
| 335 | /* |
| 336 | * Sanity check the input values |
| 337 | */ |
| 338 | if ((base == 0U) || (size_in_bytes == 0U)) { |
| 339 | ERROR("NS address 0x%llx (%lld bytes) is invalid\n", |
| 340 | base, size_in_bytes); |
| 341 | return -EINVAL; |
| 342 | } |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 343 | |
| 344 | /* |
| 345 | * Check if the NS DRAM address is valid |
| 346 | */ |
Varun Wadekar | 6460ed7 | 2017-07-20 09:43:28 -0700 | [diff] [blame] | 347 | if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || |
| 348 | (end > TEGRA_DRAM_END)) { |
| 349 | |
Andreas Färber | 055b7e9 | 2019-06-16 23:32:20 +0200 | [diff] [blame] | 350 | ERROR("NS address 0x%llx is out-of-bounds!\n", base); |
Varun Wadekar | 685e560 | 2020-06-02 21:16:00 -0700 | [diff] [blame] | 351 | return -EFAULT; |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /* |
| 355 | * TZDRAM aperture contains the BL31 and BL32 images, so we need |
| 356 | * to check if the NS DRAM range overlaps the TZDRAM aperture. |
| 357 | */ |
Varun Wadekar | 6460ed7 | 2017-07-20 09:43:28 -0700 | [diff] [blame] | 358 | if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { |
Andreas Färber | 055b7e9 | 2019-06-16 23:32:20 +0200 | [diff] [blame] | 359 | ERROR("NS address 0x%llx overlaps TZDRAM!\n", base); |
Varun Wadekar | 685e560 | 2020-06-02 21:16:00 -0700 | [diff] [blame] | 360 | return -ENOTSUP; |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | /* valid NS address */ |
Varun Wadekar | 685e560 | 2020-06-02 21:16:00 -0700 | [diff] [blame] | 364 | return 0; |
Varun Wadekar | 9a96451 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 365 | } |