Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 7 | #include <platform_def.h> |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 8 | #include <xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 9f98aa1 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 12 | ENTRY(bl31_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 13 | |
| 14 | |
| 15 | MEMORY { |
Juan Castillo | d7fbf13 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 16 | RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 17 | } |
| 18 | |
Caesar Wang | ec69356 | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 19 | #ifdef PLAT_EXTRA_LD_SCRIPT |
| 20 | #include <plat.ld.S> |
| 21 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 22 | |
| 23 | SECTIONS |
| 24 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 25 | . = BL31_BASE; |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 26 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 27 | "BL31_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 28 | |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 29 | #if SEPARATE_CODE_AND_RODATA |
| 30 | .text . : { |
| 31 | __TEXT_START__ = .; |
| 32 | *bl31_entrypoint.o(.text*) |
| 33 | *(.text*) |
| 34 | *(.vectors) |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 35 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 36 | __TEXT_END__ = .; |
| 37 | } >RAM |
| 38 | |
| 39 | .rodata . : { |
| 40 | __RODATA_START__ = .; |
| 41 | *(.rodata*) |
| 42 | |
| 43 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 44 | . = ALIGN(8); |
| 45 | __RT_SVC_DESCS_START__ = .; |
| 46 | KEEP(*(rt_svc_descs)) |
| 47 | __RT_SVC_DESCS_END__ = .; |
| 48 | |
| 49 | #if ENABLE_PMF |
| 50 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 51 | . = ALIGN(8); |
| 52 | __PMF_SVC_DESCS_START__ = .; |
| 53 | KEEP(*(pmf_svc_descs)) |
| 54 | __PMF_SVC_DESCS_END__ = .; |
| 55 | #endif /* ENABLE_PMF */ |
| 56 | |
| 57 | /* |
| 58 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 59 | * aligned. Also ensure cpu_ops inclusion. |
| 60 | */ |
| 61 | . = ALIGN(8); |
| 62 | __CPU_OPS_START__ = .; |
| 63 | KEEP(*(cpu_ops)) |
| 64 | __CPU_OPS_END__ = .; |
| 65 | |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 66 | /* Place pubsub sections for events */ |
| 67 | . = ALIGN(8); |
| 68 | #include <pubsub_events.h> |
| 69 | |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 70 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 71 | __RODATA_END__ = .; |
| 72 | } >RAM |
| 73 | #else |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 74 | ro . : { |
| 75 | __RO_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 76 | *bl31_entrypoint.o(.text*) |
| 77 | *(.text*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 78 | *(.rodata*) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 79 | |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 80 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 81 | . = ALIGN(8); |
| 82 | __RT_SVC_DESCS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 83 | KEEP(*(rt_svc_descs)) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 84 | __RT_SVC_DESCS_END__ = .; |
| 85 | |
Yatharth Kochar | a31d898 | 2016-03-11 14:20:19 +0000 | [diff] [blame] | 86 | #if ENABLE_PMF |
| 87 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 88 | . = ALIGN(8); |
| 89 | __PMF_SVC_DESCS_START__ = .; |
| 90 | KEEP(*(pmf_svc_descs)) |
| 91 | __PMF_SVC_DESCS_END__ = .; |
| 92 | #endif /* ENABLE_PMF */ |
| 93 | |
Soby Mathew | 9b47684 | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 94 | /* |
| 95 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 96 | * aligned. Also ensure cpu_ops inclusion. |
| 97 | */ |
| 98 | . = ALIGN(8); |
| 99 | __CPU_OPS_START__ = .; |
| 100 | KEEP(*(cpu_ops)) |
| 101 | __CPU_OPS_END__ = .; |
| 102 | |
Jeenu Viswambharan | 8e743bc | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 103 | /* Place pubsub sections for events */ |
| 104 | . = ALIGN(8); |
| 105 | #include <pubsub_events.h> |
| 106 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 107 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 108 | __RO_END_UNALIGNED__ = .; |
| 109 | /* |
| 110 | * Memory page(s) mapped to this section will be marked as read-only, |
| 111 | * executable. No RW data from the next section must creep in. |
| 112 | * Ensure the rest of the current memory page is unused. |
| 113 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 114 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 115 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 116 | } >RAM |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 117 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 118 | |
Soby Mathew | 9b47684 | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 119 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 120 | "cpu_ops not defined for this platform.") |
| 121 | |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 122 | #if ENABLE_SPM |
| 123 | /* |
| 124 | * Exception vectors of the SPM shim layer. They must be aligned to a 2K |
| 125 | * address, but we need to place them in a separate page so that we can set |
| 126 | * individual permissions to them, so the actual alignment needed is 4K. |
| 127 | * |
| 128 | * There's no need to include this into the RO section of BL31 because it |
| 129 | * doesn't need to be accessed by BL31. |
| 130 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 131 | spm_shim_exceptions : ALIGN(PAGE_SIZE) { |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 132 | __SPM_SHIM_EXCEPTIONS_START__ = .; |
| 133 | *(.spm_shim_exceptions) |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 134 | . = NEXT(PAGE_SIZE); |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 135 | __SPM_SHIM_EXCEPTIONS_END__ = .; |
| 136 | } >RAM |
| 137 | #endif |
| 138 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 139 | /* |
| 140 | * Define a linker symbol to mark start of the RW memory area for this |
| 141 | * image. |
| 142 | */ |
| 143 | __RW_START__ = . ; |
| 144 | |
Douglas Raillard | 51faada | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 145 | /* |
| 146 | * .data must be placed at a lower address than the stacks if the stack |
| 147 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 148 | * section can be placed independently of the main .data section. |
| 149 | */ |
| 150 | .data . : { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 151 | __DATA_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 152 | *(.data*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 153 | __DATA_END__ = .; |
| 154 | } >RAM |
| 155 | |
Sandrine Bailleux | a1b6db6 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 156 | #ifdef BL31_PROGBITS_LIMIT |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 157 | ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") |
Sandrine Bailleux | a1b6db6 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 158 | #endif |
| 159 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 160 | stacks (NOLOAD) : { |
| 161 | __STACKS_START__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 162 | *(tzfw_normal_stacks) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 163 | __STACKS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 164 | } >RAM |
| 165 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 166 | /* |
| 167 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 308d359 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 168 | * Its base address should be 16-byte aligned for better performance of the |
| 169 | * zero-initialization code. |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 170 | */ |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 171 | .bss (NOLOAD) : ALIGN(16) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 172 | __BSS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 173 | *(.bss*) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 174 | *(COMMON) |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 175 | #if !USE_COHERENT_MEM |
| 176 | /* |
| 177 | * Bakery locks are stored in normal .bss memory |
| 178 | * |
| 179 | * Each lock's data is spread across multiple cache lines, one per CPU, |
| 180 | * but multiple locks can share the same cache line. |
| 181 | * The compiler will allocate enough memory for one CPU's bakery locks, |
| 182 | * the remaining cache lines are allocated by the linker script |
| 183 | */ |
| 184 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 185 | __BAKERY_LOCK_START__ = .; |
| 186 | *(bakery_lock) |
| 187 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
Vikram Kanigiri | 7173f5f | 2015-09-24 15:45:43 +0100 | [diff] [blame] | 188 | __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 189 | . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); |
| 190 | __BAKERY_LOCK_END__ = .; |
| 191 | #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE |
| 192 | ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, |
| 193 | "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); |
| 194 | #endif |
| 195 | #endif |
Yatharth Kochar | a31d898 | 2016-03-11 14:20:19 +0000 | [diff] [blame] | 196 | |
| 197 | #if ENABLE_PMF |
| 198 | /* |
| 199 | * Time-stamps are stored in normal .bss memory |
| 200 | * |
| 201 | * The compiler will allocate enough memory for one CPU's time-stamps, |
| 202 | * the remaining memory for other CPU's is allocated by the |
| 203 | * linker script |
| 204 | */ |
| 205 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 206 | __PMF_TIMESTAMP_START__ = .; |
| 207 | KEEP(*(pmf_timestamp_array)) |
| 208 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 209 | __PMF_PERCPU_TIMESTAMP_END__ = .; |
| 210 | __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); |
| 211 | . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); |
| 212 | __PMF_TIMESTAMP_END__ = .; |
| 213 | #endif /* ENABLE_PMF */ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 214 | __BSS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 215 | } >RAM |
| 216 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 217 | /* |
Jeenu Viswambharan | e3fff15 | 2014-02-24 15:20:28 +0000 | [diff] [blame] | 218 | * The xlat_table section is for full, aligned page tables (4K). |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 219 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 220 | * the .bss section. The tables are initialized to zero by the translation |
| 221 | * tables library. |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 222 | */ |
| 223 | xlat_table (NOLOAD) : { |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 224 | #if ENABLE_SPM |
| 225 | __SP_IMAGE_XLAT_TABLES_START__ = .; |
| 226 | *secure_partition*.o(xlat_table) |
| 227 | /* Make sure that the rest of the page is empty. */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 228 | . = NEXT(PAGE_SIZE); |
Antonio Nino Diaz | 2fccb22 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 229 | __SP_IMAGE_XLAT_TABLES_END__ = .; |
| 230 | #endif |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 231 | *(xlat_table) |
| 232 | } >RAM |
| 233 | |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 234 | #if USE_COHERENT_MEM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 235 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 236 | * The base address of the coherent memory section must be page-aligned (4K) |
| 237 | * to guarantee that the coherent data are stored on their own pages and |
| 238 | * are not mixed with normal data. This is required to set up the correct |
| 239 | * memory attributes for the coherent data page tables. |
| 240 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 241 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 242 | __COHERENT_RAM_START__ = .; |
Andrew Thoelke | ee7b35c | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 243 | /* |
| 244 | * Bakery locks are stored in coherent memory |
| 245 | * |
| 246 | * Each lock's data is contiguous and fully allocated by the compiler |
| 247 | */ |
| 248 | *(bakery_lock) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 249 | *(tzfw_coherent_mem) |
| 250 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 251 | /* |
| 252 | * Memory page(s) mapped to this section will be marked |
| 253 | * as device memory. No other unexpected data must creep in. |
| 254 | * Ensure the rest of the current memory page is unused. |
| 255 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 256 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 257 | __COHERENT_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 258 | } >RAM |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 259 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 260 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 261 | /* |
| 262 | * Define a linker symbol to mark end of the RW memory area for this |
| 263 | * image. |
| 264 | */ |
| 265 | __RW_END__ = .; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 266 | __BL31_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 267 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 268 | __BSS_SIZE__ = SIZEOF(.bss); |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 269 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 270 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 271 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 272 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 274 | ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 275 | } |