Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1 | ARM Trusted Firmware User Guide |
| 2 | =============================== |
| 3 | |
| 4 | |
| 5 | .. section-numbering:: |
| 6 | :suffix: . |
| 7 | |
| 8 | .. contents:: |
| 9 | |
| 10 | This document describes how to build ARM Trusted Firmware (TF) and run it with a |
| 11 | tested set of other software components using defined configurations on the Juno |
| 12 | ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is |
| 13 | possible to use other software components, configurations and platforms but that |
| 14 | is outside the scope of this document. |
| 15 | |
| 16 | This document assumes that the reader has previous experience running a fully |
| 17 | bootable Linux software stack on Juno or FVP using the prebuilt binaries and |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 18 | filesystems provided by `Linaro`_. Further information may be found in the |
| 19 | `Linaro instructions`_. It also assumes that the user understands the role of |
| 20 | the different software components required to boot a Linux system: |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 21 | |
| 22 | - Specific firmware images required by the platform (e.g. SCP firmware on Juno) |
| 23 | - Normal world bootloader (e.g. UEFI or U-Boot) |
| 24 | - Device tree |
| 25 | - Linux kernel image |
| 26 | - Root filesystem |
| 27 | |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 28 | This document also assumes that the user is familiar with the `FVP models`_ and |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 29 | the different command line options available to launch the model. |
| 30 | |
| 31 | This document should be used in conjunction with the `Firmware Design`_. |
| 32 | |
| 33 | Host machine requirements |
| 34 | ------------------------- |
| 35 | |
| 36 | The minimum recommended machine specification for building the software and |
| 37 | running the FVP models is a dual-core processor running at 2GHz with 12GB of |
| 38 | RAM. For best performance, use a machine with a quad-core processor running at |
| 39 | 2.6GHz with 16GB of RAM. |
| 40 | |
| 41 | The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for |
| 42 | building the software were installed from that distribution unless otherwise |
| 43 | specified. |
| 44 | |
| 45 | The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE, |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 46 | Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 47 | |
| 48 | Tools |
| 49 | ----- |
| 50 | |
| 51 | Install the required packages to build Trusted Firmware with the following |
| 52 | command: |
| 53 | |
| 54 | :: |
| 55 | |
| 56 | sudo apt-get install build-essential gcc make git libssl-dev |
| 57 | |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 58 | ARM TF has been tested with `Linaro Release 17.04`_. |
| 59 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 60 | Download and install the AArch32 or AArch64 little-endian GCC cross compiler. |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 61 | The `Linaro Release Notes`_ documents which version of the compiler to use for a |
| 62 | given Linaro Release. Also, these `Linaro instructions`_ provide further |
| 63 | guidance and a script, which can be used to download Linaro deliverables |
| 64 | automatically. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 65 | |
| 66 | Optionally, Trusted Firmware can be built using clang or ARM Compiler 6. |
| 67 | See instructions below on how to switch the default compiler. |
| 68 | |
| 69 | In addition, the following optional packages and tools may be needed: |
| 70 | |
| 71 | - ``device-tree-compiler`` package if you need to rebuild the Flattened Device |
| 72 | Tree (FDT) source files (``.dts`` files) provided with this software. |
| 73 | |
| 74 | - For debugging, ARM `Development Studio 5 (DS-5)`_. |
| 75 | |
Antonio Nino Diaz | 6feb9e8 | 2017-05-23 11:49:22 +0100 | [diff] [blame] | 76 | - To create and modify the diagram files included in the documentation, `Dia`_. |
| 77 | This tool can be found in most Linux distributions. Inkscape is needed to |
| 78 | generate the actual *.png files. |
| 79 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 80 | Getting the Trusted Firmware source code |
| 81 | ---------------------------------------- |
| 82 | |
| 83 | Download the Trusted Firmware source code from Github: |
| 84 | |
| 85 | :: |
| 86 | |
| 87 | git clone https://github.com/ARM-software/arm-trusted-firmware.git |
| 88 | |
| 89 | Building the Trusted Firmware |
| 90 | ----------------------------- |
| 91 | |
| 92 | - Before building Trusted Firmware, the environment variable ``CROSS_COMPILE`` |
| 93 | must point to the Linaro cross compiler. |
| 94 | |
| 95 | For AArch64: |
| 96 | |
| 97 | :: |
| 98 | |
| 99 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 100 | |
| 101 | For AArch32: |
| 102 | |
| 103 | :: |
| 104 | |
| 105 | export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf- |
| 106 | |
| 107 | It is possible to build Trusted Firmware using clang or ARM Compiler 6. |
| 108 | To do so ``CC`` needs to point to the clang or armclang binary. Only the |
| 109 | compiler is switched; the assembler and linker need to be provided by |
| 110 | the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above. |
| 111 | |
| 112 | ARM Compiler 6 will be selected when the base name of the path assigned |
| 113 | to ``CC`` matches the string 'armclang'. |
| 114 | |
| 115 | For AArch64 using ARM Compiler 6: |
| 116 | |
| 117 | :: |
| 118 | |
| 119 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 120 | make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all |
| 121 | |
| 122 | Clang will be selected when the base name of the path assigned to ``CC`` |
| 123 | contains the string 'clang'. This is to allow both clang and clang-X.Y |
| 124 | to work. |
| 125 | |
| 126 | For AArch64 using clang: |
| 127 | |
| 128 | :: |
| 129 | |
| 130 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 131 | make CC=<path-to-clang>/bin/clang PLAT=<platform> all |
| 132 | |
| 133 | - Change to the root directory of the Trusted Firmware source tree and build. |
| 134 | |
| 135 | For AArch64: |
| 136 | |
| 137 | :: |
| 138 | |
| 139 | make PLAT=<platform> all |
| 140 | |
| 141 | For AArch32: |
| 142 | |
| 143 | :: |
| 144 | |
| 145 | make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all |
| 146 | |
| 147 | Notes: |
| 148 | |
| 149 | - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the |
| 150 | `Summary of build options`_ for more information on available build |
| 151 | options. |
| 152 | |
| 153 | - (AArch32 only) Currently only ``PLAT=fvp`` is supported. |
| 154 | |
| 155 | - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it |
| 156 | corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is |
| 157 | provided by ARM Trusted Firmware to demonstrate how PSCI Library can |
| 158 | be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3 |
| 159 | Runtime Software may include other runtime services, for example |
| 160 | Trusted OS services. A guide to integrate PSCI library with AArch32 |
| 161 | EL3 Runtime Software can be found `here`_. |
| 162 | |
| 163 | - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 |
| 164 | image, is not compiled in by default. Refer to the |
| 165 | `Building the Test Secure Payload`_ section below. |
| 166 | |
| 167 | - By default this produces a release version of the build. To produce a |
| 168 | debug version instead, refer to the "Debugging options" section below. |
| 169 | |
| 170 | - The build process creates products in a ``build`` directory tree, building |
| 171 | the objects and binaries for each boot loader stage in separate |
| 172 | sub-directories. The following boot loader binary files are created |
| 173 | from the corresponding ELF files: |
| 174 | |
| 175 | - ``build/<platform>/<build-type>/bl1.bin`` |
| 176 | - ``build/<platform>/<build-type>/bl2.bin`` |
| 177 | - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only) |
| 178 | - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32) |
| 179 | |
| 180 | where ``<platform>`` is the name of the chosen platform and ``<build-type>`` |
| 181 | is either ``debug`` or ``release``. The actual number of images might differ |
| 182 | depending on the platform. |
| 183 | |
| 184 | - Build products for a specific build variant can be removed using: |
| 185 | |
| 186 | :: |
| 187 | |
| 188 | make DEBUG=<D> PLAT=<platform> clean |
| 189 | |
| 190 | ... where ``<D>`` is ``0`` or ``1``, as specified when building. |
| 191 | |
| 192 | The build tree can be removed completely using: |
| 193 | |
| 194 | :: |
| 195 | |
| 196 | make realclean |
| 197 | |
| 198 | Summary of build options |
| 199 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 200 | |
| 201 | ARM Trusted Firmware build system supports the following build options. Unless |
| 202 | mentioned otherwise, these options are expected to be specified at the build |
| 203 | command line and are not to be modified in any component makefiles. Note that |
| 204 | the build system doesn't track dependency for build options. Therefore, if any |
| 205 | of the build options are changed from a previous build, a clean build must be |
| 206 | performed. |
| 207 | |
| 208 | Common build options |
| 209 | ^^^^^^^^^^^^^^^^^^^^ |
| 210 | |
| 211 | - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as |
| 212 | as the BL32 image when ``ARCH=aarch32``. The value should be the path to the |
| 213 | directory containing the SP source, relative to the ``bl32/``; the directory |
| 214 | is expected to contain a makefile called ``<aarch32_sp-value>.mk``. |
| 215 | |
| 216 | - ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware. |
| 217 | It can take either ``aarch64`` or ``aarch32`` as values. By default, it is |
| 218 | defined to ``aarch64``. |
| 219 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 220 | - ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when |
| 221 | compiling ARM Trusted Firmware. Its value must be numeric, and defaults to |
| 222 | 8 . See also, *ARMv8 Architecture Extensions* in `Firmware Design`_. |
| 223 | |
| 224 | - ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when |
| 225 | compiling ARM Trusted Firmware. Its value must be a numeric, and defaults |
| 226 | to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_. |
| 227 | |
| 228 | - ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM |
| 229 | Legacy GIC driver for implementing the platform GIC API. This API is used |
| 230 | by the interrupt management framework. Default is 2 (that is, version 2.0). |
| 231 | This build option is deprecated. |
| 232 | |
| 233 | - ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to |
Jeenu Viswambharan | 11ad8f2 | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 234 | cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag |
| 235 | is set, the functions which deal with MPIDR assume that the ``MT`` bit in |
| 236 | MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of |
| 237 | this flag is 0. Note that this option is not used on FVP platforms. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 238 | |
| 239 | - ``BL2``: This is an optional build option which specifies the path to BL2 |
| 240 | image for the ``fip`` target. In this case, the BL2 in the ARM Trusted |
| 241 | Firmware will not be built. |
| 242 | |
| 243 | - ``BL2U``: This is an optional build option which specifies the path to |
| 244 | BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not |
| 245 | be built. |
| 246 | |
| 247 | - ``BL31``: This is an optional build option which specifies the path to |
| 248 | BL31 image for the ``fip`` target. In this case, the BL31 in the ARM |
| 249 | Trusted Firmware will not be built. |
| 250 | |
| 251 | - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 252 | file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, |
| 253 | this file name will be used to save the key. |
| 254 | |
| 255 | - ``BL32``: This is an optional build option which specifies the path to |
| 256 | BL32 image for the ``fip`` target. In this case, the BL32 in the ARM |
| 257 | Trusted Firmware will not be built. |
| 258 | |
Summer Qin | 71fb396 | 2017-04-20 16:28:39 +0100 | [diff] [blame] | 259 | - ``BL32_EXTRA1``: This is an optional build option which specifies the path to |
| 260 | Trusted OS Extra1 image for the ``fip`` target. |
| 261 | |
| 262 | - ``BL32_EXTRA2``: This is an optional build option which specifies the path to |
| 263 | Trusted OS Extra2 image for the ``fip`` target. |
| 264 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 265 | - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 266 | file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, |
| 267 | this file name will be used to save the key. |
| 268 | |
| 269 | - ``BL33``: Path to BL33 image in the host file system. This is mandatory for |
| 270 | ``fip`` target in case the BL2 from ARM Trusted Firmware is used. |
| 271 | |
| 272 | - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 273 | file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, |
| 274 | this file name will be used to save the key. |
| 275 | |
| 276 | - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the |
| 277 | compilation of each build. It must be set to a C string (including quotes |
| 278 | where applicable). Defaults to a string that contains the time and date of |
| 279 | the compilation. |
| 280 | |
| 281 | - ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build |
| 282 | to be uniquely identified. Defaults to the current git commit id. |
| 283 | |
| 284 | - ``CFLAGS``: Extra user options appended on the compiler's command line in |
| 285 | addition to the options set by the build system. |
| 286 | |
| 287 | - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may |
| 288 | release several CPUs out of reset. It can take either 0 (several CPUs may be |
| 289 | brought up) or 1 (only one CPU will ever be brought up during cold reset). |
| 290 | Default is 0. If the platform always brings up a single CPU, there is no |
| 291 | need to distinguish between primary and secondary CPUs and the boot path can |
| 292 | be optimised. The ``plat_is_my_cpu_primary()`` and |
| 293 | ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need |
| 294 | to be implemented in this case. |
| 295 | |
| 296 | - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor |
| 297 | register state when an unexpected exception occurs during execution of |
| 298 | BL31. This option defaults to the value of ``DEBUG`` - i.e. by default |
| 299 | this is only enabled for a debug build of the firmware. |
| 300 | |
| 301 | - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 302 | certificate generation tool to create new keys in case no valid keys are |
| 303 | present or specified. Allowed options are '0' or '1'. Default is '1'. |
| 304 | |
| 305 | - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause |
| 306 | the AArch32 system registers to be included when saving and restoring the |
| 307 | CPU context. The option must be set to 0 for AArch64-only platforms (that |
| 308 | is on hardware that does not implement AArch32, or at least not at EL1 and |
| 309 | higher ELs). Default value is 1. |
| 310 | |
| 311 | - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP |
| 312 | registers to be included when saving and restoring the CPU context. Default |
| 313 | is 0. |
| 314 | |
| 315 | - ``DEBUG``: Chooses between a debug and release build. It can take either 0 |
| 316 | (release) or 1 (debug) as values. 0 is the default. |
| 317 | |
| 318 | - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of |
| 319 | the normal boot flow. It must specify the entry point address of the EL3 |
| 320 | payload. Please refer to the "Booting an EL3 payload" section for more |
| 321 | details. |
| 322 | |
| 323 | - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` |
| 324 | are compiled out. For debug builds, this option defaults to 1, and calls to |
| 325 | ``assert()`` are left in place. For release builds, this option defaults to 0 |
| 326 | and calls to ``assert()`` function are compiled out. This option can be set |
| 327 | independently of ``DEBUG``. It can also be used to hide any auxiliary code |
| 328 | that is only required for the assertion and does not fit in the assertion |
| 329 | itself. |
| 330 | |
| 331 | - ``ENABLE_PMF``: Boolean option to enable support for optional Performance |
| 332 | Measurement Framework(PMF). Default is 0. |
| 333 | |
| 334 | - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI |
| 335 | functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. |
| 336 | In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must |
| 337 | be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in |
| 338 | software. |
| 339 | |
| 340 | - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime |
| 341 | instrumentation which injects timestamp collection points into |
| 342 | Trusted Firmware to allow runtime performance to be measured. |
| 343 | Currently, only PSCI is instrumented. Enabling this option enables |
| 344 | the ``ENABLE_PMF`` build option as well. Default is 0. |
| 345 | |
Jeenu Viswambharan | c1232c3 | 2017-07-19 13:52:12 +0100 | [diff] [blame] | 346 | - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling |
| 347 | extensions. This is an optional architectural feature available only for |
| 348 | AArch64 8.2 onwards. This option defaults to 1 but is automatically |
| 349 | disabled when the target architecture is AArch32 or AArch64 8.0/8.1. |
| 350 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 351 | - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection |
| 352 | checks in GCC. Allowed values are "all", "strong" and "0" (default). |
| 353 | "strong" is the recommended stack protection level if this feature is |
| 354 | desired. 0 disables the stack protection. For all values other than 0, the |
| 355 | ``plat_get_stack_protector_canary()`` platform hook needs to be implemented. |
| 356 | The value is passed as the last component of the option |
| 357 | ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. |
| 358 | |
| 359 | - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of |
| 360 | deprecated platform APIs, helper functions or drivers within Trusted |
| 361 | Firmware as error. It can take the value 1 (flag the use of deprecated |
| 362 | APIs as error) or 0. The default is 0. |
| 363 | |
| 364 | - ``FIP_NAME``: This is an optional build option which specifies the FIP |
| 365 | filename for the ``fip`` target. Default is ``fip.bin``. |
| 366 | |
| 367 | - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU |
| 368 | FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. |
| 369 | |
| 370 | - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` |
| 371 | tool to create certificates as per the Chain of Trust described in |
| 372 | `Trusted Board Boot`_. The build system then calls ``fiptool`` to |
| 373 | include the certificates in the FIP and FWU\_FIP. Default value is '0'. |
| 374 | |
| 375 | Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support |
| 376 | for the Trusted Board Boot feature in the BL1 and BL2 images, to generate |
| 377 | the corresponding certificates, and to include those certificates in the |
| 378 | FIP and FWU\_FIP. |
| 379 | |
| 380 | Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 |
| 381 | images will not include support for Trusted Board Boot. The FIP will still |
| 382 | include the corresponding certificates. This FIP can be used to verify the |
| 383 | Chain of Trust on the host machine through other mechanisms. |
| 384 | |
| 385 | Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 |
| 386 | images will include support for Trusted Board Boot, but the FIP and FWU\_FIP |
| 387 | will not include the corresponding certificates, causing a boot failure. |
| 388 | |
| 389 | - ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts |
| 390 | will be always trapped in EL3 i.e. in BL31 at runtime. |
| 391 | |
| 392 | - ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific |
| 393 | software operations are required for CPUs to enter and exit coherency. |
| 394 | However, there exists newer systems where CPUs' entry to and exit from |
| 395 | coherency is managed in hardware. Such systems require software to only |
| 396 | initiate the operations, and the rest is managed in hardware, minimizing |
| 397 | active software management. In such systems, this boolean option enables ARM |
| 398 | Trusted Firmware to carry out build and run-time optimizations during boot |
| 399 | and power management operations. This option defaults to 0 and if it is |
| 400 | enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. |
| 401 | |
| 402 | - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 |
| 403 | runtime software in AArch32 mode, which is required to run AArch32 on Juno. |
| 404 | By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in |
| 405 | AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable |
| 406 | images. |
| 407 | |
Soby Mathew | 2091755 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 408 | - ``KEY_ALG``: This build flag enables the user to select the algorithm to be |
| 409 | used for generating the PKCS keys and subsequent signing of the certificate. |
Soby Mathew | a8eb286 | 2017-08-31 11:50:29 +0100 | [diff] [blame] | 410 | It accepts 3 values viz ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is |
| 411 | the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is |
| 412 | retained only for compatibility. The default value of this flag is ``rsa`` |
| 413 | which is the TBBR compliant PKCS#1 RSA 2.1 scheme. |
Soby Mathew | 2091755 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 414 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 415 | - ``LDFLAGS``: Extra user options appended to the linkers' command line in |
| 416 | addition to the one set by the build system. |
| 417 | |
| 418 | - ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of |
| 419 | image loading, which provides more flexibility and scalability around what |
| 420 | images are loaded and executed during boot. Default is 0. |
| 421 | Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when |
| 422 | ``LOAD_IMAGE_V2`` is enabled. |
| 423 | |
| 424 | - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log |
| 425 | output compiled into the build. This should be one of the following: |
| 426 | |
| 427 | :: |
| 428 | |
| 429 | 0 (LOG_LEVEL_NONE) |
| 430 | 10 (LOG_LEVEL_NOTICE) |
| 431 | 20 (LOG_LEVEL_ERROR) |
| 432 | 30 (LOG_LEVEL_WARNING) |
| 433 | 40 (LOG_LEVEL_INFO) |
| 434 | 50 (LOG_LEVEL_VERBOSE) |
| 435 | |
| 436 | All log output up to and including the log level is compiled into the build. |
| 437 | The default value is 40 in debug builds and 20 in release builds. |
| 438 | |
| 439 | - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 440 | specifies the file that contains the Non-Trusted World private key in PEM |
| 441 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 442 | |
| 443 | - ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is |
| 444 | optional. It is only needed if the platform makefile specifies that it |
| 445 | is required in order to build the ``fwu_fip`` target. |
| 446 | |
| 447 | - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register |
| 448 | contents upon world switch. It can take either 0 (don't save and restore) or |
| 449 | 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it |
| 450 | wants the timer registers to be saved and restored. |
| 451 | |
| 452 | - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that |
| 453 | the underlying hardware is not a full PL011 UART but a minimally compliant |
| 454 | generic UART, which is a subset of the PL011. The driver will not access |
| 455 | any register that is not part of the SBSA generic UART specification. |
| 456 | Default value is 0 (a full PL011 compliant UART is present). |
| 457 | |
| 458 | - ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen |
| 459 | platform name must be subdirectory of any depth under ``plat/``, and must |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 460 | contain a platform makefile named ``platform.mk``. For example to build ARM |
| 461 | Trusted Firmware for ARM Juno board select PLAT=juno. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 462 | |
| 463 | - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image |
| 464 | instead of the normal boot flow. When defined, it must specify the entry |
| 465 | point address for the preloaded BL33 image. This option is incompatible with |
| 466 | ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority |
| 467 | over ``PRELOADED_BL33_BASE``. |
| 468 | |
| 469 | - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset |
| 470 | vector address can be programmed or is fixed on the platform. It can take |
| 471 | either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a |
| 472 | programmable reset address, it is expected that a CPU will start executing |
| 473 | code directly at the right address, both on a cold and warm reset. In this |
| 474 | case, there is no need to identify the entrypoint on boot and the boot path |
| 475 | can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface |
| 476 | does not need to be implemented in this case. |
| 477 | |
| 478 | - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats |
| 479 | possible for the PSCI power-state parameter viz original and extended |
| 480 | State-ID formats. This flag if set to 1, configures the generic PSCI layer |
| 481 | to use the extended format. The default value of this flag is 0, which |
| 482 | means by default the original power-state format is used by the PSCI |
| 483 | implementation. This flag should be specified by the platform makefile |
| 484 | and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND |
| 485 | smc function id. When this option is enabled on ARM platforms, the |
| 486 | option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well. |
| 487 | |
| 488 | - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead |
| 489 | of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 |
| 490 | entrypoint) or 1 (CPU reset to BL31 entrypoint). |
| 491 | The default value is 0. |
| 492 | |
| 493 | - ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in |
| 494 | ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU |
| 495 | reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU |
| 496 | reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default |
| 497 | value is 0. |
| 498 | |
| 499 | - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 500 | file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this |
| 501 | file name will be used to save the key. |
| 502 | |
| 503 | - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 504 | certificate generation tool to save the keys used to establish the Chain of |
| 505 | Trust. Allowed options are '0' or '1'. Default is '0' (do not save). |
| 506 | |
| 507 | - ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional. |
| 508 | If a SCP\_BL2 image is present then this option must be passed for the ``fip`` |
| 509 | target. |
| 510 | |
| 511 | - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 512 | file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``, |
| 513 | this file name will be used to save the key. |
| 514 | |
| 515 | - ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is |
| 516 | optional. It is only needed if the platform makefile specifies that it |
| 517 | is required in order to build the ``fwu_fip`` target. |
| 518 | |
| 519 | - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be |
| 520 | isolated on separate memory pages. This is a trade-off between security and |
| 521 | memory usage. See "Isolating code and read-only data on separate memory |
| 522 | pages" section in `Firmware Design`_. This flag is disabled by default and |
| 523 | affects all BL images. |
| 524 | |
| 525 | - ``SPD``: Choose a Secure Payload Dispatcher component to be built into the |
| 526 | Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The |
| 527 | value should be the path to the directory containing the SPD source, |
| 528 | relative to ``services/spd/``; the directory is expected to |
| 529 | contain a makefile called ``<spd-value>.mk``. |
| 530 | |
| 531 | - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can |
| 532 | take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops |
| 533 | execution in BL1 just before handing over to BL31. At this point, all |
| 534 | firmware images have been loaded in memory, and the MMU and caches are |
| 535 | turned off. Refer to the "Debugging options" section for more details. |
| 536 | |
Etienne Carriere | 7181609 | 2017-08-09 15:48:53 +0200 | [diff] [blame] | 537 | - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles |
| 538 | secure interrupts (caught through the FIQ line). Platforms can enable |
| 539 | this directive if they need to handle such interruption. When enabled, |
| 540 | the FIQ are handled in monitor mode and non secure world is not allowed |
| 541 | to mask these events. Platforms that enable FIQ handling in SP_MIN shall |
| 542 | implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. |
| 543 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 544 | - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board |
| 545 | Boot feature. When set to '1', BL1 and BL2 images include support to load |
| 546 | and verify the certificates and images in a FIP, and BL1 includes support |
| 547 | for the Firmware Update. The default value is '0'. Generation and inclusion |
| 548 | of certificates in the FIP and FWU\_FIP depends upon the value of the |
| 549 | ``GENERATE_COT`` option. |
| 550 | |
| 551 | Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys |
| 552 | already exist in disk, they will be overwritten without further notice. |
| 553 | |
| 554 | - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 555 | specifies the file that contains the Trusted World private key in PEM |
| 556 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 557 | |
| 558 | - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or |
| 559 | synchronous, (see "Initializing a BL32 Image" section in |
| 560 | `Firmware Design`_). It can take the value 0 (BL32 is initialized using |
| 561 | synchronous method) or 1 (BL32 is initialized using asynchronous method). |
| 562 | Default is 0. |
| 563 | |
| 564 | - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt |
| 565 | routing model which routes non-secure interrupts asynchronously from TSP |
| 566 | to EL3 causing immediate preemption of TSP. The EL3 is responsible |
| 567 | for saving and restoring the TSP context in this routing model. The |
| 568 | default routing model (when the value is 0) is to route non-secure |
| 569 | interrupts to TSP allowing it to save its context and hand over |
| 570 | synchronously to EL3 via an SMC. |
| 571 | |
| 572 | - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent |
| 573 | memory region in the BL memory map or not (see "Use of Coherent memory in |
| 574 | Trusted Firmware" section in `Firmware Design`_). It can take the value 1 |
| 575 | (Coherent memory region is included) or 0 (Coherent memory region is |
| 576 | excluded). Default is 1. |
| 577 | |
| 578 | - ``V``: Verbose build. If assigned anything other than 0, the build commands |
| 579 | are printed. Default is 0. |
| 580 | |
| 581 | - ``VERSION_STRING``: String used in the log output for each TF image. Defaults |
| 582 | to a string formed by concatenating the version number, build type and build |
| 583 | string. |
| 584 | |
| 585 | - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on |
| 586 | the CPU after warm boot. This is applicable for platforms which do not |
| 587 | require interconnect programming to enable cache coherency (eg: single |
| 588 | cluster platforms). If this option is enabled, then warm boot path |
| 589 | enables D-caches immediately after enabling MMU. This option defaults to 0. |
| 590 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 591 | ARM development platform specific build options |
| 592 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 593 | |
| 594 | - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured |
| 595 | DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load |
| 596 | BL31 in TZC secured DRAM. If TSP is present, then setting this option also |
| 597 | sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build |
| 598 | flag. |
| 599 | |
| 600 | - ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation |
| 601 | of the memory reserved for each image. This affects the maximum size of each |
| 602 | BL image as well as the number of allocated memory regions and translation |
| 603 | tables. By default this flag is 0, which means it uses the default |
| 604 | unoptimised values for these macros. ARM development platforms that wish to |
| 605 | optimise memory usage need to set this flag to 1 and must override the |
| 606 | related macros. |
| 607 | |
| 608 | - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` |
| 609 | frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The |
| 610 | frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should |
| 611 | match the frame used by the Non-Secure image (normally the Linux kernel). |
| 612 | Default is true (access to the frame is allowed). |
| 613 | |
| 614 | - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. |
| 615 | By default, ARM platforms use a watchdog to trigger a system reset in case |
| 616 | an error is encountered during the boot process (for example, when an image |
| 617 | could not be loaded or authenticated). The watchdog is enabled in the early |
| 618 | platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The |
| 619 | Trusted Watchdog may be disabled at build time for testing or development |
| 620 | purposes. |
| 621 | |
| 622 | - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding |
| 623 | for the construction of composite state-ID in the power-state parameter. |
| 624 | The existing PSCI clients currently do not support this encoding of |
| 625 | State-ID yet. Hence this flag is used to configure whether to use the |
| 626 | recommended State-ID encoding or not. The default value of this flag is 0, |
| 627 | in which case the platform is configured to expect NULL in the State-ID |
| 628 | field of power-state parameter. |
| 629 | |
| 630 | - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the |
| 631 | location of the ROTPK hash returned by the function ``plat_get_rotpk_info()`` |
| 632 | for ARM platforms. Depending on the selected option, the proper private key |
| 633 | must be specified using the ``ROT_KEY`` option when building the Trusted |
| 634 | Firmware. This private key will be used by the certificate generation tool |
| 635 | to sign the BL2 and Trusted Key certificates. Available options for |
| 636 | ``ARM_ROTPK_LOCATION`` are: |
| 637 | |
| 638 | - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage |
| 639 | registers. The private key corresponding to this ROTPK hash is not |
| 640 | currently available. |
| 641 | - ``devel_rsa`` : return a development public key hash embedded in the BL1 |
| 642 | and BL2 binaries. This hash has been obtained from the RSA public key |
| 643 | ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use |
| 644 | this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when |
| 645 | creating the certificates. |
| 646 | |
| 647 | - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: |
| 648 | |
| 649 | - ``tsram`` : Trusted SRAM (default option) |
| 650 | - ``tdram`` : Trusted DRAM (if available) |
| 651 | - ``dram`` : Secure region in DRAM (configured by the TrustZone controller) |
| 652 | |
| 653 | - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware |
| 654 | with version 1 of the translation tables library instead of version 2. It is |
| 655 | set to 0 by default, which selects version 2. |
| 656 | |
| 657 | - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke |
| 658 | ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable |
| 659 | ARM platforms. If this option is specified, then the path to the CryptoCell |
| 660 | SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. |
| 661 | |
| 662 | For a better understanding of these options, the ARM development platform memory |
| 663 | map is explained in the `Firmware Design`_. |
| 664 | |
| 665 | ARM CSS platform specific build options |
| 666 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 667 | |
| 668 | - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version |
| 669 | incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards |
| 670 | compatible change to the MTL protocol, used for AP/SCP communication. |
| 671 | Trusted Firmware no longer supports earlier SCP versions. If this option is |
| 672 | set to 1 then Trusted Firmware will detect if an earlier version is in use. |
| 673 | Default is 1. |
| 674 | |
| 675 | - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and |
| 676 | SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded |
| 677 | during boot. Default is 1. |
| 678 | |
Soby Mathew | 18e279e | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 679 | - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers |
| 680 | instead of SCPI/BOM driver for communicating with the SCP during power |
| 681 | management operations and for SCP RAM Firmware transfer. If this option |
| 682 | is set to 1, then SCMI/SDS drivers will be used. Default is 0. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 683 | |
| 684 | ARM FVP platform specific build options |
| 685 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 686 | |
| 687 | - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to |
| 688 | build the topology tree within Trusted Firmware. By default the |
| 689 | Trusted Firmware is configured for dual cluster topology and this option |
| 690 | can be used to override the default value. |
| 691 | |
| 692 | - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The |
| 693 | default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as |
| 694 | explained in the options below: |
| 695 | |
| 696 | - ``FVP_CCI`` : The CCI driver is selected. This is the default |
| 697 | if 0 < ``FVP_CLUSTER_COUNT`` <= 2. |
| 698 | - ``FVP_CCN`` : The CCN driver is selected. This is the default |
| 699 | if ``FVP_CLUSTER_COUNT`` > 2. |
| 700 | |
Jeenu Viswambharan | 11ad8f2 | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 701 | - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU |
| 702 | in the system. This option defaults to 1. Note that the build option |
| 703 | ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. |
| 704 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 705 | - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: |
| 706 | |
| 707 | - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected |
| 708 | - ``FVP_GICV2`` : The GICv2 only driver is selected |
| 709 | - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) |
| 710 | - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated) |
| 711 | Note: If Trusted Firmware is compiled with this option on FVPs with |
| 712 | GICv3 hardware, then it configures the hardware to run in GICv2 |
| 713 | emulation mode |
| 714 | |
| 715 | - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer |
| 716 | for functions that wait for an arbitrary time length (udelay and mdelay). |
| 717 | The default value is 0. |
| 718 | |
| 719 | Debugging options |
| 720 | ~~~~~~~~~~~~~~~~~ |
| 721 | |
| 722 | To compile a debug version and make the build more verbose use |
| 723 | |
| 724 | :: |
| 725 | |
| 726 | make PLAT=<platform> DEBUG=1 V=1 all |
| 727 | |
| 728 | AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for |
| 729 | example DS-5) might not support this and may need an older version of DWARF |
| 730 | symbols to be emitted by GCC. This can be achieved by using the |
| 731 | ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the |
| 732 | version to 2 is recommended for DS-5 versions older than 5.16. |
| 733 | |
| 734 | When debugging logic problems it might also be useful to disable all compiler |
| 735 | optimizations by using ``-O0``. |
| 736 | |
| 737 | NOTE: Using ``-O0`` could cause output images to be larger and base addresses |
| 738 | might need to be recalculated (see the **Memory layout on ARM development |
| 739 | platforms** section in the `Firmware Design`_). |
| 740 | |
| 741 | Extra debug options can be passed to the build system by setting ``CFLAGS`` or |
| 742 | ``LDFLAGS``: |
| 743 | |
| 744 | .. code:: makefile |
| 745 | |
| 746 | CFLAGS='-O0 -gdwarf-2' \ |
| 747 | make PLAT=<platform> DEBUG=1 V=1 all |
| 748 | |
| 749 | Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be |
| 750 | ignored as the linker is called directly. |
| 751 | |
| 752 | It is also possible to introduce an infinite loop to help in debugging the |
| 753 | post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with |
Douglas Raillard | 668c502 | 2017-06-28 16:14:55 +0100 | [diff] [blame] | 754 | the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 755 | section. In this case, the developer may take control of the target using a |
| 756 | debugger when indicated by the console output. When using DS-5, the following |
| 757 | commands can be used: |
| 758 | |
| 759 | :: |
| 760 | |
| 761 | # Stop target execution |
| 762 | interrupt |
| 763 | |
| 764 | # |
| 765 | # Prepare your debugging environment, e.g. set breakpoints |
| 766 | # |
| 767 | |
| 768 | # Jump over the debug loop |
| 769 | set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 |
| 770 | |
| 771 | # Resume execution |
| 772 | continue |
| 773 | |
| 774 | Building the Test Secure Payload |
| 775 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 776 | |
| 777 | The TSP is coupled with a companion runtime service in the BL31 firmware, |
| 778 | called the TSPD. Therefore, if you intend to use the TSP, the BL31 image |
| 779 | must be recompiled as well. For more information on SPs and SPDs, see the |
| 780 | `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_. |
| 781 | |
| 782 | First clean the Trusted Firmware build directory to get rid of any previous |
| 783 | BL31 binary. Then to build the TSP image use: |
| 784 | |
| 785 | :: |
| 786 | |
| 787 | make PLAT=<platform> SPD=tspd all |
| 788 | |
| 789 | An additional boot loader binary file is created in the ``build`` directory: |
| 790 | |
| 791 | :: |
| 792 | |
| 793 | build/<platform>/<build-type>/bl32.bin |
| 794 | |
| 795 | Checking source code style |
| 796 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 797 | |
| 798 | When making changes to the source for submission to the project, the source |
| 799 | must be in compliance with the Linux style guide, and to assist with this check |
| 800 | the project Makefile contains two targets, which both utilise the |
| 801 | ``checkpatch.pl`` script that ships with the Linux source tree. |
| 802 | |
| 803 | To check the entire source tree, you must first download a copy of |
| 804 | ``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment |
| 805 | variable to point to the script and build the target checkcodebase: |
| 806 | |
| 807 | :: |
| 808 | |
| 809 | make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase |
| 810 | |
| 811 | To just check the style on the files that differ between your local branch and |
| 812 | the remote master, use: |
| 813 | |
| 814 | :: |
| 815 | |
| 816 | make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch |
| 817 | |
| 818 | If you wish to check your patch against something other than the remote master, |
| 819 | set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT`` |
| 820 | is set to ``origin/master``. |
| 821 | |
| 822 | Building and using the FIP tool |
| 823 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 824 | |
| 825 | Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware |
| 826 | project to package firmware images in a single binary. The number and type of |
| 827 | images that should be packed in a FIP is platform specific and may include TF |
| 828 | images and other firmware images required by the platform. For example, most |
| 829 | platforms require a BL33 image which corresponds to the normal world bootloader |
| 830 | (e.g. UEFI or U-Boot). |
| 831 | |
| 832 | The TF build system provides the make target ``fip`` to create a FIP file for the |
| 833 | specified platform using the FIP creation tool included in the TF project. |
| 834 | Examples below show how to build a FIP file for FVP, packaging TF images and a |
| 835 | BL33 image. |
| 836 | |
| 837 | For AArch64: |
| 838 | |
| 839 | :: |
| 840 | |
| 841 | make PLAT=fvp BL33=<path/to/bl33.bin> fip |
| 842 | |
| 843 | For AArch32: |
| 844 | |
| 845 | :: |
| 846 | |
| 847 | make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip |
| 848 | |
| 849 | Note that AArch32 support for Normal world boot loader (BL33), like U-boot or |
| 850 | UEFI, on FVP is not available upstream. Hence custom solutions are required to |
| 851 | allow Linux boot on FVP. These instructions assume such a custom boot loader |
| 852 | (BL33) is available. |
| 853 | |
| 854 | The resulting FIP may be found in: |
| 855 | |
| 856 | :: |
| 857 | |
| 858 | build/fvp/<build-type>/fip.bin |
| 859 | |
| 860 | For advanced operations on FIP files, it is also possible to independently build |
| 861 | the tool and create or modify FIPs using this tool. To do this, follow these |
| 862 | steps: |
| 863 | |
| 864 | It is recommended to remove old artifacts before building the tool: |
| 865 | |
| 866 | :: |
| 867 | |
| 868 | make -C tools/fiptool clean |
| 869 | |
| 870 | Build the tool: |
| 871 | |
| 872 | :: |
| 873 | |
| 874 | make [DEBUG=1] [V=1] fiptool |
| 875 | |
| 876 | The tool binary can be located in: |
| 877 | |
| 878 | :: |
| 879 | |
| 880 | ./tools/fiptool/fiptool |
| 881 | |
| 882 | Invoking the tool with ``--help`` will print a help message with all available |
| 883 | options. |
| 884 | |
| 885 | Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31: |
| 886 | |
| 887 | :: |
| 888 | |
| 889 | ./tools/fiptool/fiptool create \ |
| 890 | --tb-fw build/<platform>/<build-type>/bl2.bin \ |
| 891 | --soc-fw build/<platform>/<build-type>/bl31.bin \ |
| 892 | fip.bin |
| 893 | |
| 894 | Example 2: view the contents of an existing Firmware package: |
| 895 | |
| 896 | :: |
| 897 | |
| 898 | ./tools/fiptool/fiptool info <path-to>/fip.bin |
| 899 | |
| 900 | Example 3: update the entries of an existing Firmware package: |
| 901 | |
| 902 | :: |
| 903 | |
| 904 | # Change the BL2 from Debug to Release version |
| 905 | ./tools/fiptool/fiptool update \ |
| 906 | --tb-fw build/<platform>/release/bl2.bin \ |
| 907 | build/<platform>/debug/fip.bin |
| 908 | |
| 909 | Example 4: unpack all entries from an existing Firmware package: |
| 910 | |
| 911 | :: |
| 912 | |
| 913 | # Images will be unpacked to the working directory |
| 914 | ./tools/fiptool/fiptool unpack <path-to>/fip.bin |
| 915 | |
| 916 | Example 5: remove an entry from an existing Firmware package: |
| 917 | |
| 918 | :: |
| 919 | |
| 920 | ./tools/fiptool/fiptool remove \ |
| 921 | --tb-fw build/<platform>/debug/fip.bin |
| 922 | |
| 923 | Note that if the destination FIP file exists, the create, update and |
| 924 | remove operations will automatically overwrite it. |
| 925 | |
| 926 | The unpack operation will fail if the images already exist at the |
| 927 | destination. In that case, use -f or --force to continue. |
| 928 | |
| 929 | More information about FIP can be found in the `Firmware Design`_ document. |
| 930 | |
| 931 | Migrating from fip\_create to fiptool |
| 932 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 933 | |
| 934 | The previous version of fiptool was called fip\_create. A compatibility script |
| 935 | that emulates the basic functionality of the previous fip\_create is provided. |
| 936 | However, users are strongly encouraged to migrate to fiptool. |
| 937 | |
| 938 | - To create a new FIP file, replace "fip\_create" with "fiptool create". |
| 939 | - To update a FIP file, replace "fip\_create" with "fiptool update". |
| 940 | - To dump the contents of a FIP file, replace "fip\_create --dump" |
| 941 | with "fiptool info". |
| 942 | |
| 943 | Building FIP images with support for Trusted Board Boot |
| 944 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 945 | |
| 946 | Trusted Board Boot primarily consists of the following two features: |
| 947 | |
| 948 | - Image Authentication, described in `Trusted Board Boot`_, and |
| 949 | - Firmware Update, described in `Firmware Update`_ |
| 950 | |
| 951 | The following steps should be followed to build FIP and (optionally) FWU\_FIP |
| 952 | images with support for these features: |
| 953 | |
| 954 | #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser |
| 955 | modules by checking out a recent version of the `mbed TLS Repository`_. It |
| 956 | is important to use a version that is compatible with TF and fixes any |
| 957 | known security vulnerabilities. See `mbed TLS Security Center`_ for more |
| 958 | information. The latest version of TF is tested with tag ``mbedtls-2.4.2``. |
| 959 | |
| 960 | The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS |
| 961 | source files the modules depend upon. |
| 962 | ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration |
| 963 | options required to build the mbed TLS sources. |
| 964 | |
| 965 | Note that the mbed TLS library is licensed under the Apache version 2.0 |
| 966 | license. Using mbed TLS source code will affect the licensing of |
| 967 | Trusted Firmware binaries that are built using this library. |
| 968 | |
| 969 | #. To build the FIP image, ensure the following command line variables are set |
| 970 | while invoking ``make`` to build Trusted Firmware: |
| 971 | |
| 972 | - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>`` |
| 973 | - ``TRUSTED_BOARD_BOOT=1`` |
| 974 | - ``GENERATE_COT=1`` |
| 975 | |
| 976 | In the case of ARM platforms, the location of the ROTPK hash must also be |
| 977 | specified at build time. Two locations are currently supported (see |
| 978 | ``ARM_ROTPK_LOCATION`` build option): |
| 979 | |
| 980 | - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted |
| 981 | root-key storage registers present in the platform. On Juno, this |
| 982 | registers are read-only. On FVP Base and Cortex models, the registers |
| 983 | are read-only, but the value can be specified using the command line |
| 984 | option ``bp.trusted_key_storage.public_key`` when launching the model. |
| 985 | On both Juno and FVP models, the default value corresponds to an |
| 986 | ECDSA-SECP256R1 public key hash, whose private part is not currently |
| 987 | available. |
| 988 | |
| 989 | - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded |
| 990 | in the ARM platform port. The private/public RSA key pair may be |
| 991 | found in ``plat/arm/board/common/rotpk``. |
| 992 | |
| 993 | Example of command line using RSA development keys: |
| 994 | |
| 995 | :: |
| 996 | |
| 997 | MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \ |
| 998 | make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ |
| 999 | ARM_ROTPK_LOCATION=devel_rsa \ |
| 1000 | ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ |
| 1001 | BL33=<path-to>/<bl33_image> \ |
| 1002 | all fip |
| 1003 | |
| 1004 | The result of this build will be the bl1.bin and the fip.bin binaries. This |
| 1005 | FIP will include the certificates corresponding to the Chain of Trust |
| 1006 | described in the TBBR-client document. These certificates can also be found |
| 1007 | in the output build directory. |
| 1008 | |
| 1009 | #. The optional FWU\_FIP contains any additional images to be loaded from |
| 1010 | Non-Volatile storage during the `Firmware Update`_ process. To build the |
| 1011 | FWU\_FIP, any FWU images required by the platform must be specified on the |
| 1012 | command line. On ARM development platforms like Juno, these are: |
| 1013 | |
| 1014 | - NS\_BL2U. The AP non-secure Firmware Updater image. |
| 1015 | - SCP\_BL2U. The SCP Firmware Update Configuration image. |
| 1016 | |
| 1017 | Example of Juno command line for generating both ``fwu`` and ``fwu_fip`` |
| 1018 | targets using RSA development: |
| 1019 | |
| 1020 | :: |
| 1021 | |
| 1022 | MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \ |
| 1023 | make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ |
| 1024 | ARM_ROTPK_LOCATION=devel_rsa \ |
| 1025 | ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ |
| 1026 | BL33=<path-to>/<bl33_image> \ |
| 1027 | SCP_BL2=<path-to>/<scp_bl2_image> \ |
| 1028 | SCP_BL2U=<path-to>/<scp_bl2u_image> \ |
| 1029 | NS_BL2U=<path-to>/<ns_bl2u_image> \ |
| 1030 | all fip fwu_fip |
| 1031 | |
| 1032 | Note: The BL2U image will be built by default and added to the FWU\_FIP. |
| 1033 | The user may override this by adding ``BL2U=<path-to>/<bl2u_image>`` |
| 1034 | to the command line above. |
| 1035 | |
| 1036 | Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U, |
| 1037 | NS\_BL2U and SCP\_BL2U) is outside the scope of this document. |
| 1038 | |
| 1039 | The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries. |
| 1040 | Both the FIP and FWU\_FIP will include the certificates corresponding to the |
| 1041 | Chain of Trust described in the TBBR-client document. These certificates |
| 1042 | can also be found in the output build directory. |
| 1043 | |
| 1044 | Building the Certificate Generation Tool |
| 1045 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1046 | |
| 1047 | The ``cert_create`` tool is built as part of the TF build process when the ``fip`` |
| 1048 | make target is specified and TBB is enabled (as described in the previous |
| 1049 | section), but it can also be built separately with the following command: |
| 1050 | |
| 1051 | :: |
| 1052 | |
| 1053 | make PLAT=<platform> [DEBUG=1] [V=1] certtool |
| 1054 | |
| 1055 | For platforms that do not require their own IDs in certificate files, |
| 1056 | the generic 'cert\_create' tool can be built with the following command: |
| 1057 | |
| 1058 | :: |
| 1059 | |
| 1060 | make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool |
| 1061 | |
| 1062 | ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more |
| 1063 | verbose. The following command should be used to obtain help about the tool: |
| 1064 | |
| 1065 | :: |
| 1066 | |
| 1067 | ./tools/cert_create/cert_create -h |
| 1068 | |
| 1069 | Building a FIP for Juno and FVP |
| 1070 | ------------------------------- |
| 1071 | |
| 1072 | This section provides Juno and FVP specific instructions to build Trusted |
| 1073 | Firmware, obtain the additional required firmware, and pack it all together in |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1074 | a single FIP binary. It assumes that a `Linaro Release`_ has been installed. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1075 | |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1076 | Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12 |
| 1077 | onwards. Before that release, pre-built binaries are only available for AArch64. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1078 | |
| 1079 | Note: follow the full instructions for one platform before switching to a |
| 1080 | different one. Mixing instructions for different platforms may result in |
| 1081 | corrupted binaries. |
| 1082 | |
| 1083 | #. Clean the working directory |
| 1084 | |
| 1085 | :: |
| 1086 | |
| 1087 | make realclean |
| 1088 | |
| 1089 | #. Obtain SCP\_BL2 (Juno) and BL33 (all platforms) |
| 1090 | |
| 1091 | Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP |
| 1092 | package included in the Linaro release: |
| 1093 | |
| 1094 | :: |
| 1095 | |
| 1096 | # Build the fiptool |
| 1097 | make [DEBUG=1] [V=1] fiptool |
| 1098 | |
| 1099 | # Unpack firmware images from Linaro FIP |
| 1100 | ./tools/fiptool/fiptool unpack \ |
| 1101 | <path/to/linaro/release>/fip.bin |
| 1102 | |
| 1103 | The unpack operation will result in a set of binary images extracted to the |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1104 | current working directory. The SCP\_BL2 image corresponds to |
| 1105 | ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1106 | |
| 1107 | Note: the fiptool will complain if the images to be unpacked already |
| 1108 | exist in the current directory. If that is the case, either delete those |
| 1109 | files or use the ``--force`` option to overwrite. |
| 1110 | |
| 1111 | Note for AArch32, the instructions below assume that nt-fw.bin is a custom |
| 1112 | Normal world boot loader that supports AArch32. |
| 1113 | |
| 1114 | #. Build TF images and create a new FIP for FVP |
| 1115 | |
| 1116 | :: |
| 1117 | |
| 1118 | # AArch64 |
| 1119 | make PLAT=fvp BL33=nt-fw.bin all fip |
| 1120 | |
| 1121 | # AArch32 |
| 1122 | make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip |
| 1123 | |
| 1124 | #. Build TF images and create a new FIP for Juno |
| 1125 | |
| 1126 | For AArch64: |
| 1127 | |
| 1128 | Building for AArch64 on Juno simply requires the addition of ``SCP_BL2`` |
| 1129 | as a build parameter. |
| 1130 | |
| 1131 | :: |
| 1132 | |
| 1133 | make PLAT=juno all fip \ |
| 1134 | BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \ |
| 1135 | SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin |
| 1136 | |
| 1137 | For AArch32: |
| 1138 | |
| 1139 | Hardware restrictions on Juno prevent cold reset into AArch32 execution mode, |
| 1140 | therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled |
| 1141 | separately for AArch32. |
| 1142 | |
| 1143 | - Before building BL32, the environment variable ``CROSS_COMPILE`` must point |
| 1144 | to the AArch32 Linaro cross compiler. |
| 1145 | |
| 1146 | :: |
| 1147 | |
| 1148 | export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf- |
| 1149 | |
| 1150 | - Build BL32 in AArch32. |
| 1151 | |
| 1152 | :: |
| 1153 | |
| 1154 | make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \ |
| 1155 | RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 |
| 1156 | |
| 1157 | - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE`` |
| 1158 | must point to the AArch64 Linaro cross compiler. |
| 1159 | |
| 1160 | :: |
| 1161 | |
| 1162 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 1163 | |
| 1164 | - The following parameters should be used to build BL1 and BL2 in AArch64 |
| 1165 | and point to the BL32 file. |
| 1166 | |
| 1167 | :: |
| 1168 | |
| 1169 | make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \ |
| 1170 | BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \ |
| 1171 | SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin SPD=tspd \ |
| 1172 | BL32=<path-to-bl32>/bl32.bin all fip |
| 1173 | |
| 1174 | The resulting BL1 and FIP images may be found in: |
| 1175 | |
| 1176 | :: |
| 1177 | |
| 1178 | # Juno |
| 1179 | ./build/juno/release/bl1.bin |
| 1180 | ./build/juno/release/fip.bin |
| 1181 | |
| 1182 | # FVP |
| 1183 | ./build/fvp/release/bl1.bin |
| 1184 | ./build/fvp/release/fip.bin |
| 1185 | |
| 1186 | EL3 payloads alternative boot flow |
| 1187 | ---------------------------------- |
| 1188 | |
| 1189 | On a pre-production system, the ability to execute arbitrary, bare-metal code at |
| 1190 | the highest exception level is required. It allows full, direct access to the |
| 1191 | hardware, for example to run silicon soak tests. |
| 1192 | |
| 1193 | Although it is possible to implement some baremetal secure firmware from |
| 1194 | scratch, this is a complex task on some platforms, depending on the level of |
| 1195 | configuration required to put the system in the expected state. |
| 1196 | |
| 1197 | Rather than booting a baremetal application, a possible compromise is to boot |
| 1198 | ``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an |
| 1199 | alternative boot flow, where a modified BL2 boots an EL3 payload, instead of |
| 1200 | loading the other BL images and passing control to BL31. It reduces the |
| 1201 | complexity of developing EL3 baremetal code by: |
| 1202 | |
| 1203 | - putting the system into a known architectural state; |
| 1204 | - taking care of platform secure world initialization; |
| 1205 | - loading the SCP\_BL2 image if required by the platform. |
| 1206 | |
| 1207 | When booting an EL3 payload on ARM standard platforms, the configuration of the |
| 1208 | TrustZone controller is simplified such that only region 0 is enabled and is |
| 1209 | configured to permit secure access only. This gives full access to the whole |
| 1210 | DRAM to the EL3 payload. |
| 1211 | |
| 1212 | The system is left in the same state as when entering BL31 in the default boot |
| 1213 | flow. In particular: |
| 1214 | |
| 1215 | - Running in EL3; |
| 1216 | - Current state is AArch64; |
| 1217 | - Little-endian data access; |
| 1218 | - All exceptions disabled; |
| 1219 | - MMU disabled; |
| 1220 | - Caches disabled. |
| 1221 | |
| 1222 | Booting an EL3 payload |
| 1223 | ~~~~~~~~~~~~~~~~~~~~~~ |
| 1224 | |
| 1225 | The EL3 payload image is a standalone image and is not part of the FIP. It is |
| 1226 | not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios: |
| 1227 | |
| 1228 | - The EL3 payload may reside in non-volatile memory (NVM) and execute in |
| 1229 | place. In this case, booting it is just a matter of specifying the right |
| 1230 | address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF. |
| 1231 | |
| 1232 | - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at |
| 1233 | run-time. |
| 1234 | |
| 1235 | To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be |
| 1236 | used. The infinite loop that it introduces in BL1 stops execution at the right |
| 1237 | moment for a debugger to take control of the target and load the payload (for |
| 1238 | example, over JTAG). |
| 1239 | |
| 1240 | It is expected that this loading method will work in most cases, as a debugger |
| 1241 | connection is usually available in a pre-production system. The user is free to |
| 1242 | use any other platform-specific mechanism to load the EL3 payload, though. |
| 1243 | |
| 1244 | Booting an EL3 payload on FVP |
| 1245 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1246 | |
| 1247 | The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for |
| 1248 | the secondary CPUs holding pen to work properly. Unfortunately, its reset value |
| 1249 | is undefined on the FVP platform and the FVP platform code doesn't clear it. |
| 1250 | Therefore, one must modify the way the model is normally invoked in order to |
| 1251 | clear the mailbox at start-up. |
| 1252 | |
| 1253 | One way to do that is to create an 8-byte file containing all zero bytes using |
| 1254 | the following command: |
| 1255 | |
| 1256 | :: |
| 1257 | |
| 1258 | dd if=/dev/zero of=mailbox.dat bs=1 count=8 |
| 1259 | |
| 1260 | and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) |
| 1261 | using the following model parameters: |
| 1262 | |
| 1263 | :: |
| 1264 | |
| 1265 | --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] |
| 1266 | --data=mailbox.dat@0x04000000 [Foundation FVP] |
| 1267 | |
| 1268 | To provide the model with the EL3 payload image, the following methods may be |
| 1269 | used: |
| 1270 | |
| 1271 | #. If the EL3 payload is able to execute in place, it may be programmed into |
| 1272 | flash memory. On Base Cortex and AEM FVPs, the following model parameter |
| 1273 | loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already |
| 1274 | used for the FIP): |
| 1275 | |
| 1276 | :: |
| 1277 | |
| 1278 | -C bp.flashloader1.fname="/path/to/el3-payload" |
| 1279 | |
| 1280 | On Foundation FVP, there is no flash loader component and the EL3 payload |
| 1281 | may be programmed anywhere in flash using method 3 below. |
| 1282 | |
| 1283 | #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 |
| 1284 | command may be used to load the EL3 payload ELF image over JTAG: |
| 1285 | |
| 1286 | :: |
| 1287 | |
| 1288 | load /path/to/el3-payload.elf |
| 1289 | |
| 1290 | #. The EL3 payload may be pre-loaded in volatile memory using the following |
| 1291 | model parameters: |
| 1292 | |
| 1293 | :: |
| 1294 | |
| 1295 | --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs] |
| 1296 | --data="/path/to/el3-payload"@address [Foundation FVP] |
| 1297 | |
| 1298 | The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address |
| 1299 | used when building the Trusted Firmware. |
| 1300 | |
| 1301 | Booting an EL3 payload on Juno |
| 1302 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1303 | |
| 1304 | If the EL3 payload is able to execute in place, it may be programmed in flash |
| 1305 | memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file |
| 1306 | on the Juno SD card (where ``x`` depends on the revision of the Juno board). |
| 1307 | Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory |
| 1308 | programming" for more information. |
| 1309 | |
| 1310 | Alternatively, the same DS-5 command mentioned in the FVP section above can |
| 1311 | be used to load the EL3 payload's ELF file over JTAG on Juno. |
| 1312 | |
| 1313 | Preloaded BL33 alternative boot flow |
| 1314 | ------------------------------------ |
| 1315 | |
| 1316 | Some platforms have the ability to preload BL33 into memory instead of relying |
| 1317 | on Trusted Firmware to load it. This may simplify packaging of the normal world |
| 1318 | code and improve performance in a development environment. When secure world |
| 1319 | cold boot is complete, Trusted Firmware simply jumps to a BL33 base address |
| 1320 | provided at build time. |
| 1321 | |
| 1322 | For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be |
| 1323 | used when compiling the Trusted Firmware. For example, the following command |
| 1324 | will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at |
| 1325 | address 0x80000000: |
| 1326 | |
| 1327 | :: |
| 1328 | |
| 1329 | make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip |
| 1330 | |
| 1331 | Boot of a preloaded bootwrapped kernel image on Base FVP |
| 1332 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1333 | |
| 1334 | The following example uses the AArch64 boot wrapper. This simplifies normal |
| 1335 | world booting while also making use of TF features. It can be obtained from its |
| 1336 | repository with: |
| 1337 | |
| 1338 | :: |
| 1339 | |
| 1340 | git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git |
| 1341 | |
| 1342 | After compiling it, an ELF file is generated. It can be loaded with the |
| 1343 | following command: |
| 1344 | |
| 1345 | :: |
| 1346 | |
| 1347 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1348 | -C bp.secureflashloader.fname=bl1.bin \ |
| 1349 | -C bp.flashloader0.fname=fip.bin \ |
| 1350 | -a cluster0.cpu0=<bootwrapped-kernel.elf> \ |
| 1351 | --start cluster0.cpu0=0x0 |
| 1352 | |
| 1353 | The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It |
| 1354 | also sets the PC register to the ELF entry point address, which is not the |
| 1355 | desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back |
| 1356 | to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define |
| 1357 | used when compiling the FIP must match the ELF entry point. |
| 1358 | |
| 1359 | Boot of a preloaded bootwrapped kernel image on Juno |
| 1360 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1361 | |
| 1362 | The procedure to obtain and compile the boot wrapper is very similar to the case |
| 1363 | of the FVP. The execution must be stopped at the end of bl2\_main(), and the |
| 1364 | loading method explained above in the EL3 payload boot flow section may be used |
| 1365 | to load the ELF file over JTAG on Juno. |
| 1366 | |
| 1367 | Running the software on FVP |
| 1368 | --------------------------- |
| 1369 | |
| 1370 | The latest version of the AArch64 build of ARM Trusted Firmware has been tested |
| 1371 | on the following ARM FVPs (64-bit host machine only). |
| 1372 | |
David Cunado | 64d50c7 | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1373 | NOTE: Unless otherwise stated, the model version is Version 11.0 Build 11.0.34. |
| 1374 | |
| 1375 | - ``Foundation_Platform`` |
| 1376 | - ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502) |
| 1377 | - ``FVP_Base_Cortex-A35x4`` |
| 1378 | - ``FVP_Base_Cortex-A53x4`` |
| 1379 | - ``FVP_Base_Cortex-A57x4-A53x4`` |
| 1380 | - ``FVP_Base_Cortex-A57x4`` |
| 1381 | - ``FVP_Base_Cortex-A72x4-A53x4`` |
| 1382 | - ``FVP_Base_Cortex-A72x4`` |
| 1383 | - ``FVP_Base_Cortex-A73x4-A53x4`` |
| 1384 | - ``FVP_Base_Cortex-A73x4`` |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1385 | |
| 1386 | The latest version of the AArch32 build of ARM Trusted Firmware has been tested |
| 1387 | on the following ARM FVPs (64-bit host machine only). |
| 1388 | |
David Cunado | 64d50c7 | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1389 | - ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.5, Build 0.8.8502) |
| 1390 | - ``FVP_Base_Cortex-A32x4`` |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1391 | |
| 1392 | NOTE: The build numbers quoted above are those reported by launching the FVP |
| 1393 | with the ``--version`` parameter. |
| 1394 | |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1395 | NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full |
| 1396 | file systems that can be downloaded separately. To run an FVP with a virtio |
| 1397 | file system image an additional FVP configuration option |
| 1398 | ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be |
| 1399 | used. |
| 1400 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1401 | NOTE: The software will not work on Version 1.0 of the Foundation FVP. |
| 1402 | The commands below would report an ``unhandled argument`` error in this case. |
| 1403 | |
| 1404 | NOTE: FVPs can be launched with ``--cadi-server`` option such that a |
| 1405 | CADI-compliant debugger (for example, ARM DS-5) can connect to and control its |
| 1406 | execution. |
| 1407 | |
David Cunado | 279fedc | 2017-07-31 12:24:51 +0100 | [diff] [blame] | 1408 | NOTE: With FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 |
| 1409 | the internal synchronisation timings changed compared to older versions of the |
| 1410 | models. The models can be launched with ``-Q 100`` option if they are required |
| 1411 | to match the run time characteristics of the older versions. |
| 1412 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1413 | The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be |
| 1414 | downloaded for free from `ARM's website`_. |
| 1415 | |
David Cunado | 64d50c7 | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1416 | The Cortex-A models listed above are also available to download from |
| 1417 | `ARM's website`_. |
| 1418 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1419 | Please refer to the FVP documentation for a detailed description of the model |
| 1420 | parameter options. A brief description of the important ones that affect the ARM |
| 1421 | Trusted Firmware and normal world software behavior is provided below. |
| 1422 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1423 | Obtaining the Flattened Device Trees |
| 1424 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1425 | |
| 1426 | Depending on the FVP configuration and Linux configuration used, different |
| 1427 | FDT files are required. FDTs for the Foundation and Base FVPs can be found in |
| 1428 | the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a |
| 1429 | subset of the Base FVP components. For example, the Foundation FVP lacks CLCD |
| 1430 | and MMC support, and has only one CPU cluster. |
| 1431 | |
| 1432 | Note: It is not recommended to use the FDTs built along the kernel because not |
| 1433 | all FDTs are available from there. |
| 1434 | |
| 1435 | - ``fvp-base-gicv2-psci.dtb`` |
| 1436 | |
| 1437 | For use with both AEMv8 and Cortex-A57-A53 Base FVPs with |
| 1438 | Base memory map configuration. |
| 1439 | |
| 1440 | - ``fvp-base-gicv2-psci-aarch32.dtb`` |
| 1441 | |
| 1442 | For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state |
| 1443 | with Base memory map configuration. |
| 1444 | |
| 1445 | - ``fvp-base-gicv3-psci.dtb`` |
| 1446 | |
| 1447 | (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base |
| 1448 | memory map configuration and Linux GICv3 support. |
| 1449 | |
| 1450 | - ``fvp-base-gicv3-psci-aarch32.dtb`` |
| 1451 | |
| 1452 | For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state |
| 1453 | with Base memory map configuration and Linux GICv3 support. |
| 1454 | |
| 1455 | - ``fvp-foundation-gicv2-psci.dtb`` |
| 1456 | |
| 1457 | For use with Foundation FVP with Base memory map configuration. |
| 1458 | |
| 1459 | - ``fvp-foundation-gicv3-psci.dtb`` |
| 1460 | |
| 1461 | (Default) For use with Foundation FVP with Base memory map configuration |
| 1462 | and Linux GICv3 support. |
| 1463 | |
| 1464 | Running on the Foundation FVP with reset to BL1 entrypoint |
| 1465 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1466 | |
| 1467 | The following ``Foundation_Platform`` parameters should be used to boot Linux with |
| 1468 | 4 CPUs using the AArch64 build of ARM Trusted Firmware. |
| 1469 | |
| 1470 | :: |
| 1471 | |
| 1472 | <path-to>/Foundation_Platform \ |
| 1473 | --cores=4 \ |
| 1474 | --secure-memory \ |
| 1475 | --visualization \ |
| 1476 | --gicv3 \ |
| 1477 | --data="<path-to>/<bl1-binary>"@0x0 \ |
| 1478 | --data="<path-to>/<FIP-binary>"@0x08000000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1479 | --data="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1480 | --data="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1481 | --data="<path-to>/<ramdisk-binary>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1482 | |
| 1483 | Notes: |
| 1484 | |
| 1485 | - BL1 is loaded at the start of the Trusted ROM. |
| 1486 | - The Firmware Image Package is loaded at the start of NOR FLASH0. |
| 1487 | - The Linux kernel image and device tree are loaded in DRAM. |
| 1488 | - The default use-case for the Foundation FVP is to use the ``--gicv3`` option |
| 1489 | and enable the GICv3 device in the model. Note that without this option, |
| 1490 | the Foundation FVP defaults to legacy (Versatile Express) memory map which |
| 1491 | is not supported by ARM Trusted Firmware. |
| 1492 | |
| 1493 | Running on the AEMv8 Base FVP with reset to BL1 entrypoint |
| 1494 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1495 | |
| 1496 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 1497 | with 8 CPUs using the AArch64 build of ARM Trusted Firmware. |
| 1498 | |
| 1499 | :: |
| 1500 | |
| 1501 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1502 | -C pctl.startup=0.0.0.0 \ |
| 1503 | -C bp.secure_memory=1 \ |
| 1504 | -C bp.tzc_400.diagnostics=1 \ |
| 1505 | -C cluster0.NUM_CORES=4 \ |
| 1506 | -C cluster1.NUM_CORES=4 \ |
| 1507 | -C cache_state_modelled=1 \ |
| 1508 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1509 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1510 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1511 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1512 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1513 | |
| 1514 | Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint |
| 1515 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1516 | |
| 1517 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 1518 | with 8 CPUs using the AArch32 build of ARM Trusted Firmware. |
| 1519 | |
| 1520 | :: |
| 1521 | |
| 1522 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1523 | -C pctl.startup=0.0.0.0 \ |
| 1524 | -C bp.secure_memory=1 \ |
| 1525 | -C bp.tzc_400.diagnostics=1 \ |
| 1526 | -C cluster0.NUM_CORES=4 \ |
| 1527 | -C cluster1.NUM_CORES=4 \ |
| 1528 | -C cache_state_modelled=1 \ |
| 1529 | -C cluster0.cpu0.CONFIG64=0 \ |
| 1530 | -C cluster0.cpu1.CONFIG64=0 \ |
| 1531 | -C cluster0.cpu2.CONFIG64=0 \ |
| 1532 | -C cluster0.cpu3.CONFIG64=0 \ |
| 1533 | -C cluster1.cpu0.CONFIG64=0 \ |
| 1534 | -C cluster1.cpu1.CONFIG64=0 \ |
| 1535 | -C cluster1.cpu2.CONFIG64=0 \ |
| 1536 | -C cluster1.cpu3.CONFIG64=0 \ |
| 1537 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1538 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1539 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1540 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1541 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1542 | |
| 1543 | Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint |
| 1544 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1545 | |
| 1546 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
| 1547 | boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. |
| 1548 | |
| 1549 | :: |
| 1550 | |
| 1551 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 1552 | -C pctl.startup=0.0.0.0 \ |
| 1553 | -C bp.secure_memory=1 \ |
| 1554 | -C bp.tzc_400.diagnostics=1 \ |
| 1555 | -C cache_state_modelled=1 \ |
| 1556 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1557 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1558 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1559 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1560 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1561 | |
| 1562 | Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint |
| 1563 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1564 | |
| 1565 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
| 1566 | boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. |
| 1567 | |
| 1568 | :: |
| 1569 | |
| 1570 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 1571 | -C pctl.startup=0.0.0.0 \ |
| 1572 | -C bp.secure_memory=1 \ |
| 1573 | -C bp.tzc_400.diagnostics=1 \ |
| 1574 | -C cache_state_modelled=1 \ |
| 1575 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1576 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1577 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1578 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1579 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1580 | |
| 1581 | Running on the AEMv8 Base FVP with reset to BL31 entrypoint |
| 1582 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1583 | |
| 1584 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 1585 | with 8 CPUs using the AArch64 build of ARM Trusted Firmware. |
| 1586 | |
| 1587 | :: |
| 1588 | |
| 1589 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1590 | -C pctl.startup=0.0.0.0 \ |
| 1591 | -C bp.secure_memory=1 \ |
| 1592 | -C bp.tzc_400.diagnostics=1 \ |
| 1593 | -C cluster0.NUM_CORES=4 \ |
| 1594 | -C cluster1.NUM_CORES=4 \ |
| 1595 | -C cache_state_modelled=1 \ |
Qixiang Xu | fd5763e | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 1596 | -C cluster0.cpu0.RVBAR=0x04020000 \ |
| 1597 | -C cluster0.cpu1.RVBAR=0x04020000 \ |
| 1598 | -C cluster0.cpu2.RVBAR=0x04020000 \ |
| 1599 | -C cluster0.cpu3.RVBAR=0x04020000 \ |
| 1600 | -C cluster1.cpu0.RVBAR=0x04020000 \ |
| 1601 | -C cluster1.cpu1.RVBAR=0x04020000 \ |
| 1602 | -C cluster1.cpu2.RVBAR=0x04020000 \ |
| 1603 | -C cluster1.cpu3.RVBAR=0x04020000 \ |
| 1604 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1605 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ |
| 1606 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1607 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1608 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1609 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1610 | |
| 1611 | Notes: |
| 1612 | |
| 1613 | - Since a FIP is not loaded when using BL31 as reset entrypoint, the |
| 1614 | ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` |
| 1615 | parameter is needed to load the individual bootloader images in memory. |
| 1616 | BL32 image is only needed if BL31 has been built to expect a Secure-EL1 |
| 1617 | Payload. |
| 1618 | |
| 1619 | - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where |
| 1620 | X and Y are the cluster and CPU numbers respectively, is used to set the |
| 1621 | reset vector for each core. |
| 1622 | |
| 1623 | - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require |
| 1624 | changing the value of |
| 1625 | ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of |
| 1626 | ``BL32_BASE``. |
| 1627 | |
| 1628 | Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint |
| 1629 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1630 | |
| 1631 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 1632 | with 8 CPUs using the AArch32 build of ARM Trusted Firmware. |
| 1633 | |
| 1634 | :: |
| 1635 | |
| 1636 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1637 | -C pctl.startup=0.0.0.0 \ |
| 1638 | -C bp.secure_memory=1 \ |
| 1639 | -C bp.tzc_400.diagnostics=1 \ |
| 1640 | -C cluster0.NUM_CORES=4 \ |
| 1641 | -C cluster1.NUM_CORES=4 \ |
| 1642 | -C cache_state_modelled=1 \ |
| 1643 | -C cluster0.cpu0.CONFIG64=0 \ |
| 1644 | -C cluster0.cpu1.CONFIG64=0 \ |
| 1645 | -C cluster0.cpu2.CONFIG64=0 \ |
| 1646 | -C cluster0.cpu3.CONFIG64=0 \ |
| 1647 | -C cluster1.cpu0.CONFIG64=0 \ |
| 1648 | -C cluster1.cpu1.CONFIG64=0 \ |
| 1649 | -C cluster1.cpu2.CONFIG64=0 \ |
| 1650 | -C cluster1.cpu3.CONFIG64=0 \ |
| 1651 | -C cluster0.cpu0.RVBAR=0x04001000 \ |
| 1652 | -C cluster0.cpu1.RVBAR=0x04001000 \ |
| 1653 | -C cluster0.cpu2.RVBAR=0x04001000 \ |
| 1654 | -C cluster0.cpu3.RVBAR=0x04001000 \ |
| 1655 | -C cluster1.cpu0.RVBAR=0x04001000 \ |
| 1656 | -C cluster1.cpu1.RVBAR=0x04001000 \ |
| 1657 | -C cluster1.cpu2.RVBAR=0x04001000 \ |
| 1658 | -C cluster1.cpu3.RVBAR=0x04001000 \ |
| 1659 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ |
| 1660 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1661 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1662 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1663 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1664 | |
| 1665 | Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. |
| 1666 | It should match the address programmed into the RVBAR register as well. |
| 1667 | |
| 1668 | Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint |
| 1669 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1670 | |
| 1671 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
| 1672 | boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. |
| 1673 | |
| 1674 | :: |
| 1675 | |
| 1676 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 1677 | -C pctl.startup=0.0.0.0 \ |
| 1678 | -C bp.secure_memory=1 \ |
| 1679 | -C bp.tzc_400.diagnostics=1 \ |
| 1680 | -C cache_state_modelled=1 \ |
Qixiang Xu | fd5763e | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 1681 | -C cluster0.cpu0.RVBARADDR=0x04020000 \ |
| 1682 | -C cluster0.cpu1.RVBARADDR=0x04020000 \ |
| 1683 | -C cluster0.cpu2.RVBARADDR=0x04020000 \ |
| 1684 | -C cluster0.cpu3.RVBARADDR=0x04020000 \ |
| 1685 | -C cluster1.cpu0.RVBARADDR=0x04020000 \ |
| 1686 | -C cluster1.cpu1.RVBARADDR=0x04020000 \ |
| 1687 | -C cluster1.cpu2.RVBARADDR=0x04020000 \ |
| 1688 | -C cluster1.cpu3.RVBARADDR=0x04020000 \ |
| 1689 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1690 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ |
| 1691 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1692 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1693 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1694 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1695 | |
| 1696 | Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint |
| 1697 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1698 | |
| 1699 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
| 1700 | boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. |
| 1701 | |
| 1702 | :: |
| 1703 | |
| 1704 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 1705 | -C pctl.startup=0.0.0.0 \ |
| 1706 | -C bp.secure_memory=1 \ |
| 1707 | -C bp.tzc_400.diagnostics=1 \ |
| 1708 | -C cache_state_modelled=1 \ |
| 1709 | -C cluster0.cpu0.RVBARADDR=0x04001000 \ |
| 1710 | -C cluster0.cpu1.RVBARADDR=0x04001000 \ |
| 1711 | -C cluster0.cpu2.RVBARADDR=0x04001000 \ |
| 1712 | -C cluster0.cpu3.RVBARADDR=0x04001000 \ |
| 1713 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \ |
| 1714 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1715 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1716 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1717 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1718 | |
| 1719 | Running the software on Juno |
| 1720 | ---------------------------- |
| 1721 | |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1722 | This version of the ARM Trusted Firmware has been tested on variants r0, r1 and |
| 1723 | r2 of Juno. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1724 | |
| 1725 | To execute the software stack on Juno, the version of the Juno board recovery |
| 1726 | image indicated in the `Linaro Release Notes`_ must be installed. If you have an |
| 1727 | earlier version installed or are unsure which version is installed, please |
| 1728 | re-install the recovery image by following the |
| 1729 | `Instructions for using Linaro's deliverables on Juno`_. |
| 1730 | |
| 1731 | Preparing Trusted Firmware images |
| 1732 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1733 | |
| 1734 | After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying |
| 1735 | to the ``SOFTWARE/`` directory of the Juno SD card. |
| 1736 | |
| 1737 | Other Juno software information |
| 1738 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1739 | |
| 1740 | Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno |
| 1741 | software information. Please also refer to the `Juno Getting Started Guide`_ to |
| 1742 | get more detailed information about the Juno ARM development platform and how to |
| 1743 | configure it. |
| 1744 | |
| 1745 | Testing SYSTEM SUSPEND on Juno |
| 1746 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1747 | |
| 1748 | The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend |
| 1749 | to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend |
| 1750 | on Juno, at the linux shell prompt, issue the following command: |
| 1751 | |
| 1752 | :: |
| 1753 | |
| 1754 | echo +10 > /sys/class/rtc/rtc0/wakealarm |
| 1755 | echo -n mem > /sys/power/state |
| 1756 | |
| 1757 | The Juno board should suspend to RAM and then wakeup after 10 seconds due to |
| 1758 | wakeup interrupt from RTC. |
| 1759 | |
| 1760 | -------------- |
| 1761 | |
| 1762 | *Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.* |
| 1763 | |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1764 | .. _Linaro: `Linaro Release Notes`_ |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1765 | .. _Linaro Release: `Linaro Release Notes`_ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1766 | .. _Linaro Release Notes: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1767 | .. _Linaro Release 17.04: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.04 |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1768 | .. _Linaro instructions: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1769 | .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/b/documents/posts/using-linaros-deliverables-on-juno |
| 1770 | .. _ARM Platforms Portal: https://community.arm.com/dev-platforms/ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1771 | .. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php |
Antonio Nino Diaz | 6feb9e8 | 2017-05-23 11:49:22 +0100 | [diff] [blame] | 1772 | .. _Dia: https://wiki.gnome.org/Apps/Dia/Download |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1773 | .. _here: psci-lib-integration-guide.rst |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1774 | .. _Trusted Board Boot: trusted-board-boot.rst |
| 1775 | .. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1776 | .. _Firmware Update: firmware-update.rst |
| 1777 | .. _Firmware Design: firmware-design.rst |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1778 | .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git |
| 1779 | .. _mbed TLS Security Center: https://tls.mbed.org/security |
Eleanor Bonnici | ec4a2bb | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1780 | .. _ARM's website: `FVP models`_ |
| 1781 | .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1782 | .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf |
David Cunado | 31f2f79 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1783 | .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf |