Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <common/debug.h> |
| 8 | #include <lib/mmio.h> |
| 9 | |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 10 | #include "rcar_def.h" |
| 11 | #include "cpg_registers.h" |
| 12 | #include "rcar_private.h" |
| 13 | |
| 14 | static void bl2_secure_cpg_init(void); |
| 15 | |
| 16 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) |
| 17 | static void bl2_realtime_cpg_init_h3(void); |
| 18 | static void bl2_system_cpg_init_h3(void); |
| 19 | #endif |
| 20 | |
| 21 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) |
| 22 | static void bl2_realtime_cpg_init_m3(void); |
| 23 | static void bl2_system_cpg_init_m3(void); |
| 24 | #endif |
| 25 | |
| 26 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) |
| 27 | static void bl2_realtime_cpg_init_m3n(void); |
| 28 | static void bl2_system_cpg_init_m3n(void); |
| 29 | #endif |
| 30 | |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 31 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) |
| 32 | static void bl2_realtime_cpg_init_v3m(void); |
| 33 | static void bl2_system_cpg_init_v3m(void); |
| 34 | #endif |
| 35 | |
Marek Vasut | 2ec3221 | 2019-01-05 13:57:16 +0100 | [diff] [blame] | 36 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 37 | static void bl2_realtime_cpg_init_e3(void); |
| 38 | static void bl2_system_cpg_init_e3(void); |
| 39 | #endif |
| 40 | |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 41 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) |
| 42 | static void bl2_realtime_cpg_init_d3(void); |
| 43 | static void bl2_system_cpg_init_d3(void); |
| 44 | #endif |
| 45 | |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 46 | typedef struct { |
| 47 | uintptr_t adr; |
| 48 | uint32_t val; |
| 49 | } reg_setting_t; |
| 50 | |
| 51 | static void bl2_secure_cpg_init(void) |
| 52 | { |
| 53 | uint32_t stop_cr2, reset_cr2; |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 54 | uint32_t stop_cr4, reset_cr4; |
| 55 | uint32_t stop_cr5, reset_cr5; |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 56 | |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 57 | #if (RCAR_LSI == RCAR_D3) |
| 58 | reset_cr2 = 0x00000000U; |
| 59 | stop_cr2 = 0xFFFFFFFFU; |
| 60 | #elif (RCAR_LSI == RCAR_E3) |
ldts | 04d1f8d | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 61 | reset_cr2 = 0x10000000U; |
| 62 | stop_cr2 = 0xEFFFFFFFU; |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 63 | #else |
| 64 | reset_cr2 = 0x14000000U; |
| 65 | stop_cr2 = 0xEBFFFFFFU; |
| 66 | #endif |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 67 | |
| 68 | #if (RCAR_LSI == RCAR_D3) |
| 69 | reset_cr4 = 0x00000000U; |
| 70 | stop_cr4 = 0xFFFFFFFFU; |
| 71 | reset_cr5 = 0x00000000U; |
| 72 | stop_cr5 = 0xFFFFFFFFU; |
| 73 | #else |
| 74 | reset_cr4 = 0x80000003U; |
| 75 | stop_cr4 = 0x7FFFFFFFU; |
| 76 | reset_cr5 = 0x40000000U; |
| 77 | stop_cr5 = 0xBFFFFFFFU; |
| 78 | #endif |
| 79 | |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 80 | /** Secure Module Stop Control Registers */ |
| 81 | cpg_write(SCMSTPCR0, 0xFFFFFFFFU); |
| 82 | cpg_write(SCMSTPCR1, 0xFFFFFFFFU); |
| 83 | cpg_write(SCMSTPCR2, stop_cr2); |
| 84 | cpg_write(SCMSTPCR3, 0xFFFFFFFFU); |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 85 | cpg_write(SCMSTPCR4, stop_cr4); |
| 86 | cpg_write(SCMSTPCR5, stop_cr5); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 87 | cpg_write(SCMSTPCR6, 0xFFFFFFFFU); |
| 88 | cpg_write(SCMSTPCR7, 0xFFFFFFFFU); |
| 89 | cpg_write(SCMSTPCR8, 0xFFFFFFFFU); |
| 90 | cpg_write(SCMSTPCR9, 0xFFFDFFFFU); |
| 91 | cpg_write(SCMSTPCR10, 0xFFFFFFFFU); |
| 92 | cpg_write(SCMSTPCR11, 0xFFFFFFFFU); |
| 93 | |
| 94 | /** Secure Software Reset Access Enable Control Registers */ |
| 95 | cpg_write(SCSRSTECR0, 0x00000000U); |
| 96 | cpg_write(SCSRSTECR1, 0x00000000U); |
| 97 | cpg_write(SCSRSTECR2, reset_cr2); |
| 98 | cpg_write(SCSRSTECR3, 0x00000000U); |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 99 | cpg_write(SCSRSTECR4, reset_cr4); |
| 100 | cpg_write(SCSRSTECR5, reset_cr5); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 101 | cpg_write(SCSRSTECR6, 0x00000000U); |
| 102 | cpg_write(SCSRSTECR7, 0x00000000U); |
| 103 | cpg_write(SCSRSTECR8, 0x00000000U); |
| 104 | cpg_write(SCSRSTECR9, 0x00020000U); |
| 105 | cpg_write(SCSRSTECR10, 0x00000000U); |
| 106 | cpg_write(SCSRSTECR11, 0x00000000U); |
| 107 | } |
| 108 | |
| 109 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) |
| 110 | static void bl2_realtime_cpg_init_h3(void) |
| 111 | { |
| 112 | uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; |
| 113 | uint32_t cr0, cr8; |
| 114 | |
| 115 | cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? |
| 116 | 0x00200000U : 0x00210000U; |
| 117 | cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? |
| 118 | 0x01F1FFF4U : 0x01F1FFF7U; |
| 119 | |
| 120 | cpg_write(RMSTPCR0, cr0); |
| 121 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 122 | cpg_write(RMSTPCR2, 0x040E0FDCU); |
| 123 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 124 | cpg_write(RMSTPCR4, 0x80000004U); |
| 125 | cpg_write(RMSTPCR5, 0xC3FFFFFFU); |
| 126 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 127 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 128 | cpg_write(RMSTPCR8, cr8); |
| 129 | cpg_write(RMSTPCR9, 0xFFFFFFFEU); |
| 130 | cpg_write(RMSTPCR10, 0xFFFEFFE0U); |
| 131 | cpg_write(RMSTPCR11, 0x000000B7U); |
| 132 | } |
| 133 | |
| 134 | static void bl2_system_cpg_init_h3(void) |
| 135 | { |
| 136 | /** System Module Stop Control Registers */ |
| 137 | cpg_write(SMSTPCR0, 0x00210000U); |
| 138 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 139 | cpg_write(SMSTPCR2, 0x040E2FDCU); |
| 140 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 141 | cpg_write(SMSTPCR4, 0x80000004U); |
| 142 | cpg_write(SMSTPCR5, 0xC3FFFFFFU); |
| 143 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 144 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 145 | cpg_write(SMSTPCR8, 0x01F1FFF5U); |
| 146 | cpg_write(SMSTPCR9, 0xFFFFFFFFU); |
| 147 | cpg_write(SMSTPCR10, 0xFFFEFFE0U); |
| 148 | cpg_write(SMSTPCR11, 0x000000B7U); |
| 149 | } |
| 150 | #endif |
| 151 | |
| 152 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) |
| 153 | static void bl2_realtime_cpg_init_m3(void) |
| 154 | { |
| 155 | /** Realtime Module Stop Control Registers */ |
| 156 | cpg_write(RMSTPCR0, 0x00200000U); |
| 157 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 158 | cpg_write(RMSTPCR2, 0x040E0FDCU); |
| 159 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 160 | cpg_write(RMSTPCR4, 0x80000004U); |
| 161 | cpg_write(RMSTPCR5, 0xC3FFFFFFU); |
| 162 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 163 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 164 | cpg_write(RMSTPCR8, 0x01F1FFF7U); |
| 165 | cpg_write(RMSTPCR9, 0xFFFFFFFEU); |
| 166 | cpg_write(RMSTPCR10, 0xFFFEFFE0U); |
| 167 | cpg_write(RMSTPCR11, 0x000000B7U); |
| 168 | } |
| 169 | |
| 170 | static void bl2_system_cpg_init_m3(void) |
| 171 | { |
| 172 | /** System Module Stop Control Registers */ |
| 173 | cpg_write(SMSTPCR0, 0x00200000U); |
| 174 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 175 | cpg_write(SMSTPCR2, 0x040E2FDCU); |
| 176 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 177 | cpg_write(SMSTPCR4, 0x80000004U); |
| 178 | cpg_write(SMSTPCR5, 0xC3FFFFFFU); |
| 179 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 180 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 181 | cpg_write(SMSTPCR8, 0x01F1FFF7U); |
| 182 | cpg_write(SMSTPCR9, 0xFFFFFFFFU); |
| 183 | cpg_write(SMSTPCR10, 0xFFFEFFE0U); |
| 184 | cpg_write(SMSTPCR11, 0x000000B7U); |
| 185 | } |
| 186 | #endif |
| 187 | |
| 188 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) |
| 189 | static void bl2_realtime_cpg_init_m3n(void) |
| 190 | { |
| 191 | /** Realtime Module Stop Control Registers */ |
| 192 | cpg_write(RMSTPCR0, 0x00210000U); |
| 193 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 194 | cpg_write(RMSTPCR2, 0x040E0FDCU); |
| 195 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 196 | cpg_write(RMSTPCR4, 0x80000004U); |
| 197 | cpg_write(RMSTPCR5, 0xC3FFFFFFU); |
| 198 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 199 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 200 | cpg_write(RMSTPCR8, 0x00F1FFF7U); |
| 201 | cpg_write(RMSTPCR9, 0xFFFFFFFFU); |
| 202 | cpg_write(RMSTPCR10, 0xFFFFFFE0U); |
| 203 | cpg_write(RMSTPCR11, 0x000000B7U); |
| 204 | } |
| 205 | |
| 206 | static void bl2_system_cpg_init_m3n(void) |
| 207 | { |
| 208 | /* System Module Stop Control Registers */ |
| 209 | cpg_write(SMSTPCR0, 0x00210000U); |
| 210 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 211 | cpg_write(SMSTPCR2, 0x040E2FDCU); |
| 212 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 213 | cpg_write(SMSTPCR4, 0x80000004U); |
| 214 | cpg_write(SMSTPCR5, 0xC3FFFFFFU); |
| 215 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 216 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 217 | cpg_write(SMSTPCR8, 0x00F1FFF7U); |
| 218 | cpg_write(SMSTPCR9, 0xFFFFFFFFU); |
| 219 | cpg_write(SMSTPCR10, 0xFFFFFFE0U); |
| 220 | cpg_write(SMSTPCR11, 0x000000B7U); |
| 221 | } |
| 222 | #endif |
| 223 | |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 224 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) |
| 225 | static void bl2_realtime_cpg_init_v3m(void) |
| 226 | { |
| 227 | /* Realtime Module Stop Control Registers */ |
| 228 | cpg_write(RMSTPCR0, 0x00230000U); |
| 229 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 230 | cpg_write(RMSTPCR2, 0x14062FD8U); |
| 231 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 232 | cpg_write(RMSTPCR4, 0x80000184U); |
| 233 | cpg_write(RMSTPCR5, 0x83FFFFFFU); |
| 234 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 235 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 236 | cpg_write(RMSTPCR8, 0x7FF3FFF4U); |
| 237 | cpg_write(RMSTPCR9, 0xFFFFFFFEU); |
| 238 | } |
| 239 | |
| 240 | static void bl2_system_cpg_init_v3m(void) |
| 241 | { |
| 242 | /* System Module Stop Control Registers */ |
| 243 | cpg_write(SMSTPCR0, 0x00210000U); |
| 244 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 245 | cpg_write(SMSTPCR2, 0x340E2FDCU); |
| 246 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 247 | cpg_write(SMSTPCR4, 0x80000004U); |
| 248 | cpg_write(SMSTPCR5, 0xC3FFFFFFU); |
| 249 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 250 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 251 | cpg_write(SMSTPCR8, 0x01F1FFF5U); |
| 252 | cpg_write(SMSTPCR9, 0xFFFFFFFEU); |
| 253 | } |
| 254 | #endif |
| 255 | |
Marek Vasut | 2ec3221 | 2019-01-05 13:57:16 +0100 | [diff] [blame] | 256 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 257 | static void bl2_realtime_cpg_init_e3(void) |
| 258 | { |
| 259 | /* Realtime Module Stop Control Registers */ |
| 260 | cpg_write(RMSTPCR0, 0x00210000U); |
| 261 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 262 | cpg_write(RMSTPCR2, 0x000E0FDCU); |
| 263 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 264 | cpg_write(RMSTPCR4, 0x80000004U); |
| 265 | cpg_write(RMSTPCR5, 0xC3FFFFFFU); |
| 266 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 267 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 268 | cpg_write(RMSTPCR8, 0x00F1FFF7U); |
| 269 | cpg_write(RMSTPCR9, 0xFFFFFFDFU); |
| 270 | cpg_write(RMSTPCR10, 0xFFFFFFE8U); |
| 271 | cpg_write(RMSTPCR11, 0x000000B7U); |
| 272 | } |
| 273 | |
| 274 | static void bl2_system_cpg_init_e3(void) |
| 275 | { |
| 276 | /* System Module Stop Control Registers */ |
| 277 | cpg_write(SMSTPCR0, 0x00210000U); |
| 278 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 279 | cpg_write(SMSTPCR2, 0x000E2FDCU); |
| 280 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 281 | cpg_write(SMSTPCR4, 0x80000004U); |
| 282 | cpg_write(SMSTPCR5, 0xC3FFFFFFU); |
| 283 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 284 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 285 | cpg_write(SMSTPCR8, 0x00F1FFF7U); |
| 286 | cpg_write(SMSTPCR9, 0xFFFFFFDFU); |
| 287 | cpg_write(SMSTPCR10, 0xFFFFFFE8U); |
| 288 | cpg_write(SMSTPCR11, 0x000000B7U); |
| 289 | } |
| 290 | #endif |
| 291 | |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 292 | #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3) |
| 293 | static void bl2_realtime_cpg_init_d3(void) |
| 294 | { |
| 295 | /* Realtime Module Stop Control Registers */ |
| 296 | cpg_write(RMSTPCR0, 0x00010000U); |
| 297 | cpg_write(RMSTPCR1, 0xFFFFFFFFU); |
| 298 | cpg_write(RMSTPCR2, 0x00060FDCU); |
| 299 | cpg_write(RMSTPCR3, 0xFFFFFFDFU); |
| 300 | cpg_write(RMSTPCR4, 0x80000184U); |
| 301 | cpg_write(RMSTPCR5, 0x83FFFFFFU); |
| 302 | cpg_write(RMSTPCR6, 0xFFFFFFFFU); |
| 303 | cpg_write(RMSTPCR7, 0xFFFFFFFFU); |
| 304 | cpg_write(RMSTPCR8, 0x00F1FFF7U); |
| 305 | cpg_write(RMSTPCR9, 0xF3F5E016U); |
| 306 | cpg_write(RMSTPCR10, 0xFFFEFFE0U); |
| 307 | cpg_write(RMSTPCR11, 0x000000B7U); |
| 308 | } |
| 309 | |
| 310 | static void bl2_system_cpg_init_d3(void) |
| 311 | { |
| 312 | /* System Module Stop Control Registers */ |
| 313 | cpg_write(SMSTPCR0, 0x00010000U); |
| 314 | cpg_write(SMSTPCR1, 0xFFFFFFFFU); |
| 315 | cpg_write(SMSTPCR2, 0x00060FDCU); |
| 316 | cpg_write(SMSTPCR3, 0xFFFFFBDFU); |
| 317 | cpg_write(SMSTPCR4, 0x00000084U); |
| 318 | cpg_write(SMSTPCR5, 0x83FFFFFFU); |
| 319 | cpg_write(SMSTPCR6, 0xFFFFFFFFU); |
| 320 | cpg_write(SMSTPCR7, 0xFFFFFFFFU); |
| 321 | cpg_write(SMSTPCR8, 0x00F1FFF7U); |
| 322 | cpg_write(SMSTPCR9, 0xF3F5E016U); |
| 323 | cpg_write(SMSTPCR10, 0xFFFEFFE0U); |
| 324 | cpg_write(SMSTPCR11, 0x000000B7U); |
| 325 | } |
| 326 | #endif |
| 327 | |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 328 | void bl2_cpg_init(void) |
| 329 | { |
| 330 | uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK; |
| 331 | #if RCAR_LSI == RCAR_AUTO |
| 332 | uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; |
| 333 | #endif |
| 334 | bl2_secure_cpg_init(); |
| 335 | |
| 336 | if (boot_cpu == MODEMR_BOOT_CPU_CA57 || |
| 337 | boot_cpu == MODEMR_BOOT_CPU_CA53) { |
| 338 | #if RCAR_LSI == RCAR_AUTO |
| 339 | |
| 340 | switch (product) { |
| 341 | case RCAR_PRODUCT_H3: |
| 342 | bl2_realtime_cpg_init_h3(); |
| 343 | break; |
| 344 | case RCAR_PRODUCT_M3: |
| 345 | bl2_realtime_cpg_init_m3(); |
| 346 | break; |
| 347 | case RCAR_PRODUCT_M3N: |
| 348 | bl2_realtime_cpg_init_m3n(); |
| 349 | break; |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 350 | case RCAR_PRODUCT_V3M: |
| 351 | bl2_realtime_cpg_init_v3m(); |
| 352 | break; |
Marek Vasut | 2ec3221 | 2019-01-05 13:57:16 +0100 | [diff] [blame] | 353 | case RCAR_PRODUCT_E3: |
| 354 | bl2_realtime_cpg_init_e3(); |
| 355 | break; |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 356 | case RCAR_PRODUCT_D3: |
| 357 | bl2_realtime_cpg_init_d3(); |
| 358 | break; |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 359 | default: |
| 360 | panic(); |
| 361 | break; |
| 362 | } |
| 363 | #elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) |
| 364 | bl2_realtime_cpg_init_h3(); |
| 365 | #elif RCAR_LSI == RCAR_M3 |
| 366 | bl2_realtime_cpg_init_m3(); |
| 367 | #elif RCAR_LSI == RCAR_M3N |
| 368 | bl2_realtime_cpg_init_m3n(); |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 369 | #elif RCAR_LSI == RCAR_V3M |
| 370 | bl2_realtime_cpg_init_v3m(); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 371 | #elif RCAR_LSI == RCAR_E3 |
| 372 | bl2_realtime_cpg_init_e3(); |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 373 | #elif RCAR_LSI == RCAR_D3 |
| 374 | bl2_realtime_cpg_init_d3(); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 375 | #else |
| 376 | #error "Don't have CPG initialize routine(unknown)." |
| 377 | #endif |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | void bl2_system_cpg_init(void) |
| 382 | { |
| 383 | #if RCAR_LSI == RCAR_AUTO |
| 384 | uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; |
| 385 | |
| 386 | switch (product) { |
| 387 | case RCAR_PRODUCT_H3: |
| 388 | bl2_system_cpg_init_h3(); |
| 389 | break; |
| 390 | case RCAR_PRODUCT_M3: |
| 391 | bl2_system_cpg_init_m3(); |
| 392 | break; |
| 393 | case RCAR_PRODUCT_M3N: |
| 394 | bl2_system_cpg_init_m3n(); |
| 395 | break; |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 396 | case RCAR_PRODUCT_V3M: |
| 397 | bl2_system_cpg_init_v3m(); |
| 398 | break; |
Marek Vasut | 2ec3221 | 2019-01-05 13:57:16 +0100 | [diff] [blame] | 399 | case RCAR_PRODUCT_E3: |
| 400 | bl2_system_cpg_init_e3(); |
| 401 | break; |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 402 | case RCAR_PRODUCT_D3: |
| 403 | bl2_system_cpg_init_d3(); |
| 404 | break; |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 405 | default: |
| 406 | panic(); |
| 407 | break; |
| 408 | } |
| 409 | #elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) |
| 410 | bl2_system_cpg_init_h3(); |
| 411 | #elif RCAR_LSI == RCAR_M3 |
| 412 | bl2_system_cpg_init_m3(); |
| 413 | #elif RCAR_LSI == RCAR_M3N |
| 414 | bl2_system_cpg_init_m3n(); |
Valentine Barshak | b709fe9 | 2018-10-30 02:06:17 +0300 | [diff] [blame] | 415 | #elif RCAR_LSI == RCAR_V3M |
| 416 | bl2_system_cpg_init_v3m(); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 417 | #elif RCAR_LSI == RCAR_E3 |
| 418 | bl2_system_cpg_init_e3(); |
Marek Vasut | bfbf5df | 2019-01-05 13:56:03 +0100 | [diff] [blame] | 419 | #elif RCAR_LSI == RCAR_D3 |
| 420 | bl2_system_cpg_init_d3(); |
Jorge Ramirez-Ortiz | 7e532c4 | 2018-09-23 09:36:13 +0200 | [diff] [blame] | 421 | #else |
| 422 | #error "Don't have CPG initialize routine(unknown)." |
| 423 | #endif |
| 424 | } |