Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | eb68ea9 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <assert.h> |
| 7 | #include <gic_common.h> |
| 8 | #include <gicv2.h> |
| 9 | #include <interrupt_mgmt.h> |
Jeenu Viswambharan | 8db978b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 10 | #include <platform.h> |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 11 | |
| 12 | /* |
| 13 | * The following platform GIC functions are weakly defined. They |
| 14 | * provide typical implementations that may be re-used by multiple |
| 15 | * platforms but may also be overridden by a platform if required. |
| 16 | */ |
| 17 | #pragma weak plat_ic_get_pending_interrupt_id |
| 18 | #pragma weak plat_ic_get_pending_interrupt_type |
| 19 | #pragma weak plat_ic_acknowledge_interrupt |
| 20 | #pragma weak plat_ic_get_interrupt_type |
| 21 | #pragma weak plat_ic_end_of_interrupt |
| 22 | #pragma weak plat_interrupt_type_to_line |
| 23 | |
Jeenu Viswambharan | eb68ea9 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 24 | #pragma weak plat_ic_get_running_priority |
Jeenu Viswambharan | ca43b55 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 25 | #pragma weak plat_ic_is_spi |
| 26 | #pragma weak plat_ic_is_ppi |
| 27 | #pragma weak plat_ic_is_sgi |
Jeenu Viswambharan | cbd3f37 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 28 | #pragma weak plat_ic_get_interrupt_active |
Jeenu Viswambharan | 979225f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 29 | #pragma weak plat_ic_enable_interrupt |
| 30 | #pragma weak plat_ic_disable_interrupt |
Jeenu Viswambharan | f3a8660 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 31 | #pragma weak plat_ic_set_interrupt_priority |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 32 | #pragma weak plat_ic_set_interrupt_type |
Jeenu Viswambharan | 8db978b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 33 | #pragma weak plat_ic_raise_el3_sgi |
Jeenu Viswambharan | fc529fe | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 34 | #pragma weak plat_ic_set_spi_routing |
Jeenu Viswambharan | eb68ea9 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 35 | |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 36 | /* |
| 37 | * This function returns the highest priority pending interrupt at |
| 38 | * the Interrupt controller |
| 39 | */ |
| 40 | uint32_t plat_ic_get_pending_interrupt_id(void) |
| 41 | { |
| 42 | unsigned int id; |
| 43 | |
| 44 | id = gicv2_get_pending_interrupt_id(); |
| 45 | if (id == GIC_SPURIOUS_INTERRUPT) |
| 46 | return INTR_ID_UNAVAILABLE; |
| 47 | |
| 48 | return id; |
| 49 | } |
| 50 | |
| 51 | /* |
| 52 | * This function returns the type of the highest priority pending interrupt |
| 53 | * at the Interrupt controller. In the case of GICv2, the Highest Priority |
| 54 | * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of |
| 55 | * the pending interrupt. The type of interrupt depends upon the id value |
| 56 | * as follows. |
| 57 | * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt |
| 58 | * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. |
| 59 | * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt |
| 60 | * type. |
| 61 | */ |
| 62 | uint32_t plat_ic_get_pending_interrupt_type(void) |
| 63 | { |
| 64 | unsigned int id; |
| 65 | |
| 66 | id = gicv2_get_pending_interrupt_type(); |
| 67 | |
| 68 | /* Assume that all secure interrupts are S-EL1 interrupts */ |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 69 | if (id < PENDING_G1_INTID) { |
| 70 | #if GICV2_G0_FOR_EL3 |
| 71 | return INTR_TYPE_EL3; |
| 72 | #else |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 73 | return INTR_TYPE_S_EL1; |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 74 | #endif |
| 75 | } |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 76 | |
| 77 | if (id == GIC_SPURIOUS_INTERRUPT) |
| 78 | return INTR_TYPE_INVAL; |
| 79 | |
| 80 | return INTR_TYPE_NS; |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * This function returns the highest priority pending interrupt at |
| 85 | * the Interrupt controller and indicates to the Interrupt controller |
| 86 | * that the interrupt processing has started. |
| 87 | */ |
| 88 | uint32_t plat_ic_acknowledge_interrupt(void) |
| 89 | { |
| 90 | return gicv2_acknowledge_interrupt(); |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * This function returns the type of the interrupt `id`, depending on how |
| 95 | * the interrupt has been configured in the interrupt controller |
| 96 | */ |
| 97 | uint32_t plat_ic_get_interrupt_type(uint32_t id) |
| 98 | { |
| 99 | unsigned int type; |
| 100 | |
| 101 | type = gicv2_get_interrupt_group(id); |
| 102 | |
| 103 | /* Assume that all secure interrupts are S-EL1 interrupts */ |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 104 | return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS : |
| 105 | #if GICV2_G0_FOR_EL3 |
| 106 | INTR_TYPE_EL3; |
| 107 | #else |
| 108 | INTR_TYPE_S_EL1; |
| 109 | #endif |
Soby Mathew | f14d188 | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | /* |
| 113 | * This functions is used to indicate to the interrupt controller that |
| 114 | * the processing of the interrupt corresponding to the `id` has |
| 115 | * finished. |
| 116 | */ |
| 117 | void plat_ic_end_of_interrupt(uint32_t id) |
| 118 | { |
| 119 | gicv2_end_of_interrupt(id); |
| 120 | } |
| 121 | |
| 122 | /* |
| 123 | * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. |
| 124 | * The interrupt controller knows which pin/line it uses to signal a type of |
| 125 | * interrupt. It lets the interrupt management framework determine |
| 126 | * for a type of interrupt and security state, which line should be used in the |
| 127 | * SCR_EL3 to control its routing to EL3. The interrupt line is represented |
| 128 | * as the bit position of the IRQ or FIQ bit in the SCR_EL3. |
| 129 | */ |
| 130 | uint32_t plat_interrupt_type_to_line(uint32_t type, |
| 131 | uint32_t security_state) |
| 132 | { |
| 133 | assert(type == INTR_TYPE_S_EL1 || |
| 134 | type == INTR_TYPE_EL3 || |
| 135 | type == INTR_TYPE_NS); |
| 136 | |
| 137 | /* Non-secure interrupts are signaled on the IRQ line always */ |
| 138 | if (type == INTR_TYPE_NS) |
| 139 | return __builtin_ctz(SCR_IRQ_BIT); |
| 140 | |
| 141 | /* |
| 142 | * Secure interrupts are signaled using the IRQ line if the FIQ is |
| 143 | * not enabled else they are signaled using the FIQ line. |
| 144 | */ |
| 145 | return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : |
| 146 | __builtin_ctz(SCR_IRQ_BIT)); |
| 147 | } |
Jeenu Viswambharan | eb68ea9 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 148 | |
| 149 | unsigned int plat_ic_get_running_priority(void) |
| 150 | { |
| 151 | return gicv2_get_running_priority(); |
| 152 | } |
Jeenu Viswambharan | ca43b55 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 153 | |
| 154 | int plat_ic_is_spi(unsigned int id) |
| 155 | { |
| 156 | return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); |
| 157 | } |
| 158 | |
| 159 | int plat_ic_is_ppi(unsigned int id) |
| 160 | { |
| 161 | return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); |
| 162 | } |
| 163 | |
| 164 | int plat_ic_is_sgi(unsigned int id) |
| 165 | { |
| 166 | return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); |
| 167 | } |
Jeenu Viswambharan | cbd3f37 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 168 | |
| 169 | unsigned int plat_ic_get_interrupt_active(unsigned int id) |
| 170 | { |
| 171 | return gicv2_get_interrupt_active(id); |
| 172 | } |
Jeenu Viswambharan | 979225f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 173 | |
| 174 | void plat_ic_enable_interrupt(unsigned int id) |
| 175 | { |
| 176 | gicv2_enable_interrupt(id); |
| 177 | } |
| 178 | |
| 179 | void plat_ic_disable_interrupt(unsigned int id) |
| 180 | { |
| 181 | gicv2_disable_interrupt(id); |
| 182 | } |
Jeenu Viswambharan | f3a8660 | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 183 | |
| 184 | void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) |
| 185 | { |
| 186 | gicv2_set_interrupt_priority(id, priority); |
| 187 | } |
Jeenu Viswambharan | 74dce7f | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 188 | |
| 189 | int plat_ic_has_interrupt_type(unsigned int type) |
| 190 | { |
| 191 | switch (type) { |
| 192 | #if GICV2_G0_FOR_EL3 |
| 193 | case INTR_TYPE_EL3: |
| 194 | #else |
| 195 | case INTR_TYPE_S_EL1: |
| 196 | #endif |
| 197 | case INTR_TYPE_NS: |
| 198 | return 1; |
| 199 | default: |
| 200 | return 0; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) |
| 205 | { |
| 206 | int gicv2_type = 0; |
| 207 | |
| 208 | /* Map canonical interrupt type to GICv2 type */ |
| 209 | switch (type) { |
| 210 | #if GICV2_G0_FOR_EL3 |
| 211 | case INTR_TYPE_EL3: |
| 212 | #else |
| 213 | case INTR_TYPE_S_EL1: |
| 214 | #endif |
| 215 | gicv2_type = GICV2_INTR_GROUP0; |
| 216 | break; |
| 217 | case INTR_TYPE_NS: |
| 218 | gicv2_type = GICV2_INTR_GROUP1; |
| 219 | break; |
| 220 | default: |
| 221 | assert(0); |
| 222 | } |
| 223 | |
| 224 | gicv2_set_interrupt_type(id, gicv2_type); |
| 225 | } |
Jeenu Viswambharan | 8db978b | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 226 | |
| 227 | void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) |
| 228 | { |
| 229 | #if GICV2_G0_FOR_EL3 |
| 230 | int id; |
| 231 | |
| 232 | /* Target must be a valid MPIDR in the system */ |
| 233 | id = plat_core_pos_by_mpidr(target); |
| 234 | assert(id >= 0); |
| 235 | |
| 236 | /* Verify that this is a secure SGI */ |
| 237 | assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); |
| 238 | |
| 239 | gicv2_raise_sgi(sgi_num, id); |
| 240 | #else |
| 241 | assert(0); |
| 242 | #endif |
| 243 | } |
Jeenu Viswambharan | fc529fe | 2017-09-22 08:32:09 +0100 | [diff] [blame^] | 244 | |
| 245 | void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, |
| 246 | u_register_t mpidr) |
| 247 | { |
| 248 | int proc_num = 0; |
| 249 | |
| 250 | switch (routing_mode) { |
| 251 | case INTR_ROUTING_MODE_PE: |
| 252 | proc_num = plat_core_pos_by_mpidr(mpidr); |
| 253 | assert(proc_num >= 0); |
| 254 | break; |
| 255 | case INTR_ROUTING_MODE_ANY: |
| 256 | /* Bit mask selecting all 8 CPUs as candidates */ |
| 257 | proc_num = -1; |
| 258 | break; |
| 259 | default: |
| 260 | assert(0); |
| 261 | } |
| 262 | |
| 263 | gicv2_set_spi_routing(id, proc_num); |
| 264 | } |