Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Masahiro Yamada | 11f001c | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 7 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 8 | #include <arch_helpers.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 9 | #include <assert.h> |
Juan Castillo | 1779ba6 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 10 | #include <auth_mod.h> |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 11 | #include <bl1.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 12 | #include <bl_common.h> |
Antonio Nino Diaz | 0b32628 | 2017-02-16 16:17:19 +0000 | [diff] [blame] | 13 | #include <console.h> |
Vikram Kanigiri | 4112bfa | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 14 | #include <debug.h> |
Jeenu Viswambharan | 10bcd76 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 15 | #include <errata_report.h> |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 16 | #include <platform.h> |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 17 | #include <platform_def.h> |
Antonio Nino Diaz | 085e80e | 2018-03-21 10:49:27 +0000 | [diff] [blame] | 18 | #include <smccc_helpers.h> |
Soby Mathew | c45f627 | 2016-07-20 14:38:36 +0100 | [diff] [blame] | 19 | #include <utils.h> |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 20 | #include <uuid.h> |
Isla Mitchell | 2a4b4b7 | 2017-07-11 14:54:08 +0100 | [diff] [blame] | 21 | #include "bl1_private.h" |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 22 | |
| 23 | /* BL1 Service UUID */ |
Roberto Vargas | 0336486 | 2018-04-26 13:36:53 +0100 | [diff] [blame] | 24 | DEFINE_SVC_UUID2(bl1_svc_uid, |
| 25 | 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 26 | 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 27 | |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 28 | static void bl1_load_bl2(void); |
Vikram Kanigiri | 29fb905 | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 29 | |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 30 | /******************************************************************************* |
Soby Mathew | 101d01e | 2018-01-10 12:51:34 +0000 | [diff] [blame] | 31 | * Helper utility to calculate the BL2 memory layout taking into consideration |
| 32 | * the BL1 RW data assuming that it is at the top of the memory layout. |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 33 | ******************************************************************************/ |
Soby Mathew | 101d01e | 2018-01-10 12:51:34 +0000 | [diff] [blame] | 34 | void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, |
| 35 | meminfo_t *bl2_mem_layout) |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 36 | { |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 37 | assert(bl1_mem_layout != NULL); |
| 38 | assert(bl2_mem_layout != NULL); |
| 39 | |
Yatharth Kochar | 42019bf | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 40 | #if LOAD_IMAGE_V2 |
| 41 | /* |
| 42 | * Remove BL1 RW data from the scope of memory visible to BL2. |
| 43 | * This is assuming BL1 RW data is at the top of bl1_mem_layout. |
| 44 | */ |
| 45 | assert(BL1_RW_BASE > bl1_mem_layout->total_base); |
| 46 | bl2_mem_layout->total_base = bl1_mem_layout->total_base; |
| 47 | bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; |
| 48 | #else |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 49 | /* Check that BL1's memory is lying outside of the free memory */ |
| 50 | assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 51 | (BL1_RAM_BASE >= bl1_mem_layout->free_base + |
| 52 | bl1_mem_layout->free_size)); |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 53 | |
| 54 | /* Remove BL1 RW data from the scope of memory visible to BL2 */ |
| 55 | *bl2_mem_layout = *bl1_mem_layout; |
| 56 | reserve_mem(&bl2_mem_layout->total_base, |
| 57 | &bl2_mem_layout->total_size, |
| 58 | BL1_RAM_BASE, |
Yatharth Kochar | 42019bf | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 59 | BL1_RAM_LIMIT - BL1_RAM_BASE); |
| 60 | #endif /* LOAD_IMAGE_V2 */ |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 61 | |
| 62 | flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); |
| 63 | } |
Vikram Kanigiri | 29fb905 | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 64 | |
Soby Mathew | 101d01e | 2018-01-10 12:51:34 +0000 | [diff] [blame] | 65 | #if !ERROR_DEPRECATED |
| 66 | /******************************************************************************* |
| 67 | * Compatibility default implementation for deprecated API. This has a weak |
| 68 | * definition. Platform specific code can override it if it wishes to. |
| 69 | ******************************************************************************/ |
| 70 | #pragma weak bl1_init_bl2_mem_layout |
| 71 | |
| 72 | /******************************************************************************* |
| 73 | * Function that takes a memory layout into which BL2 has been loaded and |
| 74 | * populates a new memory layout for BL2 that ensures that BL1's data sections |
| 75 | * resident in secure RAM are not visible to BL2. |
| 76 | ******************************************************************************/ |
| 77 | void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, |
| 78 | meminfo_t *bl2_mem_layout) |
| 79 | { |
| 80 | bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout); |
| 81 | } |
| 82 | #endif |
| 83 | |
Vikram Kanigiri | 29fb905 | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 84 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | * Function to perform late architectural and platform specific initialization. |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 86 | * It also queries the platform to load and run next BL image. Only called |
| 87 | * by the primary cpu after a cold boot. |
| 88 | ******************************************************************************/ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | void bl1_main(void) |
| 90 | { |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 91 | unsigned int image_id; |
| 92 | |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 93 | /* Announce our arrival */ |
| 94 | NOTICE(FIRMWARE_WELCOME_STR); |
| 95 | NOTICE("BL1: %s\n", version_string); |
| 96 | NOTICE("BL1: %s\n", build_message); |
| 97 | |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 98 | INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, |
| 99 | (void *)BL1_RAM_LIMIT); |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 100 | |
Jeenu Viswambharan | 10bcd76 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 101 | print_errata_status(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 102 | |
Antonio Nino Diaz | aa61368 | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 103 | #if ENABLE_ASSERTIONS |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 104 | u_register_t val; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 105 | /* |
| 106 | * Ensure that MMU/Caches and coherency are turned on |
| 107 | */ |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 108 | #ifdef AARCH32 |
| 109 | val = read_sctlr(); |
| 110 | #else |
Dan Handley | ce4c820 | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 111 | val = read_sctlr_el3(); |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 112 | #endif |
Andrew Thoelke | 354ab57 | 2015-06-11 14:12:14 +0100 | [diff] [blame] | 113 | assert(val & SCTLR_M_BIT); |
| 114 | assert(val & SCTLR_C_BIT); |
| 115 | assert(val & SCTLR_I_BIT); |
Dan Handley | ce4c820 | 2015-03-30 17:15:16 +0100 | [diff] [blame] | 116 | /* |
| 117 | * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the |
| 118 | * provided platform value |
| 119 | */ |
| 120 | val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; |
| 121 | /* |
| 122 | * If CWG is zero, then no CWG information is available but we can |
| 123 | * at least check the platform value is less than the architectural |
| 124 | * maximum. |
| 125 | */ |
| 126 | if (val != 0) |
| 127 | assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); |
| 128 | else |
| 129 | assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); |
Antonio Nino Diaz | aa61368 | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 130 | #endif /* ENABLE_ASSERTIONS */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 131 | |
| 132 | /* Perform remaining generic architectural setup from EL3 */ |
| 133 | bl1_arch_setup(); |
| 134 | |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 135 | #if TRUSTED_BOARD_BOOT |
| 136 | /* Initialize authentication module */ |
| 137 | auth_mod_init(); |
| 138 | #endif /* TRUSTED_BOARD_BOOT */ |
| 139 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 140 | /* Perform platform setup in BL1. */ |
| 141 | bl1_platform_setup(); |
| 142 | |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 143 | /* Get the image id of next image to load and run. */ |
| 144 | image_id = bl1_plat_get_next_image_id(); |
| 145 | |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 146 | /* |
| 147 | * We currently interpret any image id other than |
| 148 | * BL2_IMAGE_ID as the start of firmware update. |
| 149 | */ |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 150 | if (image_id == BL2_IMAGE_ID) |
| 151 | bl1_load_bl2(); |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 152 | else |
| 153 | NOTICE("BL1-FWU: *******FWU Process Started*******\n"); |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 154 | |
| 155 | bl1_prepare_next_image(image_id); |
Antonio Nino Diaz | 0b32628 | 2017-02-16 16:17:19 +0000 | [diff] [blame] | 156 | |
| 157 | console_flush(); |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | /******************************************************************************* |
| 161 | * This function locates and loads the BL2 raw binary image in the trusted SRAM. |
| 162 | * Called by the primary cpu after a cold boot. |
| 163 | * TODO: Add support for alternative image load mechanism e.g using virtio/elf |
| 164 | * loader etc. |
| 165 | ******************************************************************************/ |
Roberto Vargas | ce3f9a6 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 166 | static void bl1_load_bl2(void) |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 167 | { |
| 168 | image_desc_t *image_desc; |
| 169 | image_info_t *image_info; |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 170 | int err; |
| 171 | |
| 172 | /* Get the image descriptor */ |
| 173 | image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); |
| 174 | assert(image_desc); |
| 175 | |
| 176 | /* Get the image info */ |
| 177 | image_info = &image_desc->image_info; |
Juan Castillo | 16948ae | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 178 | INFO("BL1: Loading BL2\n"); |
| 179 | |
Soby Mathew | 566034f | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 180 | err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); |
Masahiro Yamada | 11f001c | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 181 | if (err) { |
| 182 | ERROR("Failure in pre image load handling of BL2 (%d)\n", err); |
| 183 | plat_error_handler(err); |
| 184 | } |
| 185 | |
Soby Mathew | 566034f | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 186 | #if LOAD_IMAGE_V2 |
Yatharth Kochar | 42019bf | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 187 | err = load_auth_image(BL2_IMAGE_ID, image_info); |
| 188 | #else |
Soby Mathew | 101d01e | 2018-01-10 12:51:34 +0000 | [diff] [blame] | 189 | entry_point_info_t *ep_info; |
| 190 | meminfo_t *bl1_tzram_layout; |
| 191 | |
| 192 | /* Get the entry point info */ |
| 193 | ep_info = &image_desc->ep_info; |
| 194 | |
| 195 | /* Find out how much free trusted ram remains after BL1 load */ |
| 196 | bl1_tzram_layout = bl1_plat_sec_mem_layout(); |
| 197 | |
Sandrine Bailleux | 8f55dfb | 2014-06-24 14:02:34 +0100 | [diff] [blame] | 198 | /* Load the BL2 image */ |
Juan Castillo | 1779ba6 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 199 | err = load_auth_image(bl1_tzram_layout, |
Juan Castillo | 16948ae | 2015-04-13 17:36:19 +0100 | [diff] [blame] | 200 | BL2_IMAGE_ID, |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 201 | image_info->image_base, |
| 202 | image_info, |
| 203 | ep_info); |
Juan Castillo | 1779ba6 | 2015-05-19 11:54:12 +0100 | [diff] [blame] | 204 | |
Yatharth Kochar | 42019bf | 2016-09-12 16:10:33 +0100 | [diff] [blame] | 205 | #endif /* LOAD_IMAGE_V2 */ |
| 206 | |
Vikram Kanigiri | 4112bfa | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 207 | if (err) { |
Dan Handley | 6ad2e46 | 2014-07-29 17:14:00 +0100 | [diff] [blame] | 208 | ERROR("Failed to load BL2 firmware.\n"); |
Juan Castillo | 40fc6cd | 2015-09-25 15:41:14 +0100 | [diff] [blame] | 209 | plat_error_handler(err); |
Vikram Kanigiri | 4112bfa | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 210 | } |
Juan Castillo | 01df3c1 | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 211 | |
Masahiro Yamada | 11f001c | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 212 | /* Allow platform to handle image information. */ |
Soby Mathew | 566034f | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 213 | err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); |
Masahiro Yamada | 11f001c | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 214 | if (err) { |
| 215 | ERROR("Failure in post image load handling of BL2 (%d)\n", err); |
| 216 | plat_error_handler(err); |
| 217 | } |
| 218 | |
Yatharth Kochar | 7baff11 | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 219 | NOTICE("BL1: Booting BL2\n"); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | /******************************************************************************* |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 223 | * Function called just before handing over to the next BL to inform the user |
| 224 | * about the boot progress. In debug mode, also print details about the BL |
| 225 | * image's execution context. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 226 | ******************************************************************************/ |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 227 | void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 228 | { |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 229 | #ifdef AARCH32 |
| 230 | NOTICE("BL1: Booting BL32\n"); |
| 231 | #else |
Juan Castillo | d178637 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 232 | NOTICE("BL1: Booting BL31\n"); |
Yatharth Kochar | f3b4914 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 233 | #endif /* AARCH32 */ |
| 234 | print_entry_point_info(bl_ep_info); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 235 | } |
Sandrine Bailleux | 35e8c76 | 2015-11-10 10:01:19 +0000 | [diff] [blame] | 236 | |
| 237 | #if SPIN_ON_BL1_EXIT |
| 238 | void print_debug_loop_message(void) |
| 239 | { |
| 240 | NOTICE("BL1: Debug loop, spinning forever\n"); |
| 241 | NOTICE("BL1: Please connect the debugger to continue\n"); |
| 242 | } |
| 243 | #endif |
Yatharth Kochar | 48bfb88 | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 244 | |
| 245 | /******************************************************************************* |
| 246 | * Top level handler for servicing BL1 SMCs. |
| 247 | ******************************************************************************/ |
| 248 | register_t bl1_smc_handler(unsigned int smc_fid, |
| 249 | register_t x1, |
| 250 | register_t x2, |
| 251 | register_t x3, |
| 252 | register_t x4, |
| 253 | void *cookie, |
| 254 | void *handle, |
| 255 | unsigned int flags) |
| 256 | { |
| 257 | |
| 258 | #if TRUSTED_BOARD_BOOT |
| 259 | /* |
| 260 | * Dispatch FWU calls to FWU SMC handler and return its return |
| 261 | * value |
| 262 | */ |
| 263 | if (is_fwu_fid(smc_fid)) { |
| 264 | return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, |
| 265 | handle, flags); |
| 266 | } |
| 267 | #endif |
| 268 | |
| 269 | switch (smc_fid) { |
| 270 | case BL1_SMC_CALL_COUNT: |
| 271 | SMC_RET1(handle, BL1_NUM_SMC_CALLS); |
| 272 | |
| 273 | case BL1_SMC_UID: |
| 274 | SMC_UUID_RET(handle, bl1_svc_uid); |
| 275 | |
| 276 | case BL1_SMC_VERSION: |
| 277 | SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); |
| 278 | |
| 279 | default: |
| 280 | break; |
| 281 | } |
| 282 | |
| 283 | WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); |
| 284 | SMC_RET1(handle, SMC_UNK); |
| 285 | } |
dp-arm | a440900 | 2017-02-15 11:07:55 +0000 | [diff] [blame] | 286 | |
| 287 | /******************************************************************************* |
| 288 | * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI |
| 289 | * compliance when invoking bl1_smc_handler. |
| 290 | ******************************************************************************/ |
| 291 | register_t bl1_smc_wrapper(uint32_t smc_fid, |
| 292 | void *cookie, |
| 293 | void *handle, |
| 294 | unsigned int flags) |
| 295 | { |
| 296 | register_t x1, x2, x3, x4; |
| 297 | |
| 298 | assert(handle); |
| 299 | |
| 300 | get_smc_params_from_ctx(handle, x1, x2, x3, x4); |
| 301 | return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); |
| 302 | } |