Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 5f0cdb0 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 7 | #include <platform_def.h> |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 8 | #include <xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 9f98aa1 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 12 | ENTRY(bl2_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 13 | |
| 14 | MEMORY { |
Juan Castillo | d7fbf13 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 15 | RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 16 | } |
| 17 | |
| 18 | |
| 19 | SECTIONS |
| 20 | { |
| 21 | . = BL2_BASE; |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 22 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 23 | "BL2_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 24 | |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 25 | #if SEPARATE_CODE_AND_RODATA |
| 26 | .text . : { |
| 27 | __TEXT_START__ = .; |
| 28 | *bl2_entrypoint.o(.text*) |
| 29 | *(.text*) |
| 30 | *(.vectors) |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 31 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 32 | __TEXT_END__ = .; |
| 33 | } >RAM |
| 34 | |
| 35 | .rodata . : { |
| 36 | __RODATA_START__ = .; |
| 37 | *(.rodata*) |
| 38 | |
| 39 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 40 | . = ALIGN(8); |
| 41 | __PARSER_LIB_DESCS_START__ = .; |
| 42 | KEEP(*(.img_parser_lib_descs)) |
| 43 | __PARSER_LIB_DESCS_END__ = .; |
| 44 | |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 45 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 46 | __RODATA_END__ = .; |
| 47 | } >RAM |
| 48 | #else |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 49 | ro . : { |
| 50 | __RO_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 51 | *bl2_entrypoint.o(.text*) |
| 52 | *(.text*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 53 | *(.rodata*) |
Juan Castillo | 05799ae | 2015-04-02 09:48:16 +0100 | [diff] [blame] | 54 | |
| 55 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 56 | . = ALIGN(8); |
| 57 | __PARSER_LIB_DESCS_START__ = .; |
| 58 | KEEP(*(.img_parser_lib_descs)) |
| 59 | __PARSER_LIB_DESCS_END__ = .; |
| 60 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 61 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 62 | __RO_END_UNALIGNED__ = .; |
| 63 | /* |
| 64 | * Memory page(s) mapped to this section will be marked as |
| 65 | * read-only, executable. No RW data from the next section must |
| 66 | * creep in. Ensure the rest of the current memory page is unused. |
| 67 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 68 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 69 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 70 | } >RAM |
Sandrine Bailleux | 5d1c104 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 71 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 72 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 73 | /* |
| 74 | * Define a linker symbol to mark start of the RW memory area for this |
| 75 | * image. |
| 76 | */ |
| 77 | __RW_START__ = . ; |
| 78 | |
Douglas Raillard | 51faada | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 79 | /* |
| 80 | * .data must be placed at a lower address than the stacks if the stack |
| 81 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 82 | * section can be placed independently of the main .data section. |
| 83 | */ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 84 | .data . : { |
| 85 | __DATA_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 86 | *(.data*) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 87 | __DATA_END__ = .; |
| 88 | } >RAM |
| 89 | |
| 90 | stacks (NOLOAD) : { |
| 91 | __STACKS_START__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 92 | *(tzfw_normal_stacks) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 93 | __STACKS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 94 | } >RAM |
| 95 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 96 | /* |
| 97 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 308d359 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 98 | * Its base address should be 16-byte aligned for better performance of the |
| 99 | * zero-initialization code. |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 100 | */ |
| 101 | .bss : ALIGN(16) { |
| 102 | __BSS_START__ = .; |
Andrew Thoelke | dccc537 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 103 | *(SORT_BY_ALIGNMENT(.bss*)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 104 | *(COMMON) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 105 | __BSS_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 106 | } >RAM |
| 107 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 108 | /* |
Jeenu Viswambharan | e3fff15 | 2014-02-24 15:20:28 +0000 | [diff] [blame] | 109 | * The xlat_table section is for full, aligned page tables (4K). |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 110 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 111 | * the .bss section. The tables are initialized to zero by the translation |
| 112 | * tables library. |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 113 | */ |
| 114 | xlat_table (NOLOAD) : { |
| 115 | *(xlat_table) |
| 116 | } >RAM |
| 117 | |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 118 | #if USE_COHERENT_MEM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 119 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 120 | * The base address of the coherent memory section must be page-aligned (4K) |
| 121 | * to guarantee that the coherent data are stored on their own pages and |
| 122 | * are not mixed with normal data. This is required to set up the correct |
| 123 | * memory attributes for the coherent data page tables. |
| 124 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 125 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 126 | __COHERENT_RAM_START__ = .; |
| 127 | *(tzfw_coherent_mem) |
| 128 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 129 | /* |
| 130 | * Memory page(s) mapped to this section will be marked |
| 131 | * as device memory. No other unexpected data must creep in. |
| 132 | * Ensure the rest of the current memory page is unused. |
| 133 | */ |
Antonio Nino Diaz | a2aedac | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 134 | . = NEXT(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 135 | __COHERENT_RAM_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | } >RAM |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 137 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 138 | |
Achin Gupta | 54dc71e | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 139 | /* |
| 140 | * Define a linker symbol to mark end of the RW memory area for this |
| 141 | * image. |
| 142 | */ |
| 143 | __RW_END__ = .; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 144 | __BL2_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 145 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 146 | __BSS_SIZE__ = SIZEOF(.bss); |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 147 | |
| 148 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 149 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 150 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
Soby Mathew | ab8707e | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 151 | #endif |
Sandrine Bailleux | a37255a | 2014-05-22 15:28:26 +0100 | [diff] [blame] | 152 | |
| 153 | ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | } |