Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <platform_def.h> |
| 8 | #include <xlat_tables_defs.h> |
| 9 | |
| 10 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 11 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
| 12 | ENTRY(bl2_entrypoint) |
| 13 | |
| 14 | MEMORY { |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 15 | #if BL2_IN_XIP_MEM |
| 16 | ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE |
| 17 | RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE |
| 18 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 19 | RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 20 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 21 | } |
| 22 | |
| 23 | |
| 24 | SECTIONS |
| 25 | { |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 26 | #if BL2_IN_XIP_MEM |
| 27 | . = BL2_RO_BASE; |
| 28 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 29 | "BL2_RO_BASE address is not aligned on a page boundary.") |
| 30 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 31 | . = BL2_BASE; |
| 32 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 33 | "BL2_BASE address is not aligned on a page boundary.") |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 34 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 35 | |
| 36 | #if SEPARATE_CODE_AND_RODATA |
| 37 | .text . : { |
| 38 | __TEXT_START__ = .; |
Roberto Vargas | 487d3bf | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 39 | __TEXT_RESIDENT_START__ = .; |
| 40 | *bl2_el3_entrypoint.o(.text*) |
| 41 | *(.text.asm.*) |
| 42 | __TEXT_RESIDENT_END__ = .; |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 43 | *(.text*) |
| 44 | *(.vectors) |
| 45 | . = NEXT(PAGE_SIZE); |
| 46 | __TEXT_END__ = .; |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 47 | #if BL2_IN_XIP_MEM |
| 48 | } >ROM |
| 49 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 50 | } >RAM |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 51 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 52 | |
| 53 | .rodata . : { |
| 54 | __RODATA_START__ = .; |
| 55 | *(.rodata*) |
| 56 | |
| 57 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 58 | . = ALIGN(8); |
| 59 | __PARSER_LIB_DESCS_START__ = .; |
| 60 | KEEP(*(.img_parser_lib_descs)) |
| 61 | __PARSER_LIB_DESCS_END__ = .; |
| 62 | |
| 63 | /* |
| 64 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 65 | * aligned. Also ensure cpu_ops inclusion. |
| 66 | */ |
| 67 | . = ALIGN(8); |
| 68 | __CPU_OPS_START__ = .; |
| 69 | KEEP(*(cpu_ops)) |
| 70 | __CPU_OPS_END__ = .; |
| 71 | |
| 72 | . = NEXT(PAGE_SIZE); |
| 73 | __RODATA_END__ = .; |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 74 | #if BL2_IN_XIP_MEM |
| 75 | } >ROM |
| 76 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 77 | } >RAM |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 78 | #endif |
Roberto Vargas | 487d3bf | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 79 | |
| 80 | ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE, |
| 81 | "Resident part of BL2 has exceeded its limit.") |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 82 | #else |
| 83 | ro . : { |
| 84 | __RO_START__ = .; |
Roberto Vargas | 487d3bf | 2017-11-17 10:51:54 +0000 | [diff] [blame] | 85 | __TEXT_RESIDENT_START__ = .; |
| 86 | *bl2_el3_entrypoint.o(.text*) |
| 87 | *(.text.asm.*) |
| 88 | __TEXT_RESIDENT_END__ = .; |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 89 | *(.text*) |
| 90 | *(.rodata*) |
| 91 | |
| 92 | /* |
| 93 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 94 | * aligned. Also ensure cpu_ops inclusion. |
| 95 | */ |
| 96 | . = ALIGN(8); |
| 97 | __CPU_OPS_START__ = .; |
| 98 | KEEP(*(cpu_ops)) |
| 99 | __CPU_OPS_END__ = .; |
| 100 | |
| 101 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 102 | . = ALIGN(8); |
| 103 | __PARSER_LIB_DESCS_START__ = .; |
| 104 | KEEP(*(.img_parser_lib_descs)) |
| 105 | __PARSER_LIB_DESCS_END__ = .; |
| 106 | |
| 107 | *(.vectors) |
| 108 | __RO_END_UNALIGNED__ = .; |
| 109 | /* |
| 110 | * Memory page(s) mapped to this section will be marked as |
| 111 | * read-only, executable. No RW data from the next section must |
| 112 | * creep in. Ensure the rest of the current memory page is unused. |
| 113 | */ |
| 114 | . = NEXT(PAGE_SIZE); |
| 115 | |
| 116 | __RO_END__ = .; |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 117 | #if BL2_IN_XIP_MEM |
| 118 | } >ROM |
| 119 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 120 | } >RAM |
| 121 | #endif |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 122 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 123 | |
| 124 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 125 | "cpu_ops not defined for this platform.") |
| 126 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 127 | #if BL2_IN_XIP_MEM |
| 128 | . = BL2_RW_BASE; |
| 129 | ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), |
| 130 | "BL2_RW_BASE address is not aligned on a page boundary.") |
| 131 | #endif |
| 132 | |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 133 | /* |
| 134 | * Define a linker symbol to mark start of the RW memory area for this |
| 135 | * image. |
| 136 | */ |
| 137 | __RW_START__ = . ; |
| 138 | |
| 139 | /* |
| 140 | * .data must be placed at a lower address than the stacks if the stack |
| 141 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 142 | * section can be placed independently of the main .data section. |
| 143 | */ |
| 144 | .data . : { |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 145 | __DATA_RAM_START__ = .; |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 146 | *(.data*) |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 147 | __DATA_RAM_END__ = .; |
| 148 | #if BL2_IN_XIP_MEM |
| 149 | } >RAM AT>ROM |
| 150 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 151 | } >RAM |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 152 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 153 | |
| 154 | stacks (NOLOAD) : { |
| 155 | __STACKS_START__ = .; |
| 156 | *(tzfw_normal_stacks) |
| 157 | __STACKS_END__ = .; |
| 158 | } >RAM |
| 159 | |
| 160 | /* |
| 161 | * The .bss section gets initialised to 0 at runtime. |
| 162 | * Its base address should be 16-byte aligned for better performance of the |
| 163 | * zero-initialization code. |
| 164 | */ |
| 165 | .bss : ALIGN(16) { |
| 166 | __BSS_START__ = .; |
| 167 | *(SORT_BY_ALIGNMENT(.bss*)) |
| 168 | *(COMMON) |
| 169 | __BSS_END__ = .; |
| 170 | } >RAM |
| 171 | |
| 172 | /* |
| 173 | * The xlat_table section is for full, aligned page tables (4K). |
| 174 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 883d1b5 | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 175 | * the .bss section. The tables are initialized to zero by the translation |
| 176 | * tables library. |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 177 | */ |
| 178 | xlat_table (NOLOAD) : { |
| 179 | *(xlat_table) |
| 180 | } >RAM |
| 181 | |
| 182 | #if USE_COHERENT_MEM |
| 183 | /* |
| 184 | * The base address of the coherent memory section must be page-aligned (4K) |
| 185 | * to guarantee that the coherent data are stored on their own pages and |
| 186 | * are not mixed with normal data. This is required to set up the correct |
| 187 | * memory attributes for the coherent data page tables. |
| 188 | */ |
| 189 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
| 190 | __COHERENT_RAM_START__ = .; |
| 191 | *(tzfw_coherent_mem) |
| 192 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 193 | /* |
| 194 | * Memory page(s) mapped to this section will be marked |
| 195 | * as device memory. No other unexpected data must creep in. |
| 196 | * Ensure the rest of the current memory page is unused. |
| 197 | */ |
| 198 | . = NEXT(PAGE_SIZE); |
| 199 | __COHERENT_RAM_END__ = .; |
| 200 | } >RAM |
| 201 | #endif |
| 202 | |
| 203 | /* |
| 204 | * Define a linker symbol to mark end of the RW memory area for this |
| 205 | * image. |
| 206 | */ |
| 207 | __RW_END__ = .; |
| 208 | __BL2_END__ = .; |
| 209 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 210 | #if BL2_IN_XIP_MEM |
| 211 | __BL2_RAM_START__ = ADDR(.data); |
| 212 | __BL2_RAM_END__ = .; |
| 213 | |
| 214 | __DATA_ROM_START__ = LOADADDR(.data); |
| 215 | __DATA_SIZE__ = SIZEOF(.data); |
| 216 | |
| 217 | /* |
| 218 | * The .data section is the last PROGBITS section so its end marks the end |
| 219 | * of BL2's RO content in XIP memory.. |
| 220 | */ |
| 221 | __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; |
| 222 | ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT, |
| 223 | "BL2's RO content has exceeded its limit.") |
| 224 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 225 | __BSS_SIZE__ = SIZEOF(.bss); |
| 226 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 227 | |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 228 | #if USE_COHERENT_MEM |
| 229 | __COHERENT_RAM_UNALIGNED_SIZE__ = |
| 230 | __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; |
| 231 | #endif |
| 232 | |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 233 | #if BL2_IN_XIP_MEM |
| 234 | ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") |
| 235 | #else |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 236 | ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") |
Jiafei Pan | 7d173fc | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 237 | #endif |
Roberto Vargas | b1d27b4 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 238 | } |