Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1 | Arm CPU Specific Build Macros |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2 | ============================= |
| 3 | |
| 4 | |
| 5 | .. section-numbering:: |
| 6 | :suffix: . |
| 7 | |
| 8 | .. contents:: |
| 9 | |
| 10 | This document describes the various build options present in the CPU specific |
| 11 | operations framework to enable errata workarounds and to enable optimizations |
| 12 | for a specific CPU on a platform. |
| 13 | |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 14 | Security Vulnerability Workarounds |
| 15 | ---------------------------------- |
| 16 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 17 | TF-A exports a series of build flags which control which security |
| 18 | vulnerability workarounds should be applied at runtime. |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 19 | |
| 20 | - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for |
Dimitris Papastamos | 59dc4ef | 2018-03-28 12:06:40 +0100 | [diff] [blame] | 21 | `CVE-2017-5715`_. This flag can be set to 0 by the platform if none |
| 22 | of the PEs in the system need the workaround. Setting this flag to 0 provides |
| 23 | no performance benefit for non-affected platforms, it just helps to comply |
| 24 | with the recommendation in the spec regarding workaround discovery. |
| 25 | Defaults to 1. |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 26 | |
Dimitris Papastamos | b8a25bb | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 27 | - ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for |
| 28 | `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep |
| 29 | the default value of 1 even on platforms that are unaffected by |
| 30 | CVE-2018-3639, in order to comply with the recommendation in the spec |
| 31 | regarding workaround discovery. |
| 32 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 33 | CPU Errata Workarounds |
| 34 | ---------------------- |
| 35 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 36 | TF-A exports a series of build flags which control the errata workarounds that |
| 37 | are applied to each CPU by the reset handler. The errata details can be found |
| 38 | in the CPU specific errata documents published by Arm: |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 39 | |
| 40 | - `Cortex-A53 MPCore Software Developers Errata Notice`_ |
| 41 | - `Cortex-A57 MPCore Software Developers Errata Notice`_ |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 42 | - `Cortex-A72 MPCore Software Developers Errata Notice`_ |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 43 | |
| 44 | The errata workarounds are implemented for a particular revision or a set of |
| 45 | processor revisions. This is checked by the reset handler at runtime. Each |
| 46 | errata workaround is identified by its ``ID`` as specified in the processor's |
| 47 | errata notice document. The format of the define used to enable/disable the |
| 48 | errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` |
| 49 | is for example ``A57`` for the ``Cortex_A57`` CPU. |
| 50 | |
| 51 | Refer to the section *CPU errata status reporting* in |
Eleanor Bonnici | 45b52c2 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 52 | `Firmware Design guide`_ for information on how to write errata workaround |
| 53 | functions. |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 54 | |
| 55 | All workarounds are disabled by default. The platform is responsible for |
| 56 | enabling these workarounds according to its requirement by defining the |
| 57 | errata workaround build flags in the platform specific makefile. In case |
| 58 | these workarounds are enabled for the wrong CPU revision then the errata |
| 59 | workaround is not applied. In the DEBUG build, this is indicated by |
| 60 | printing a warning to the crash console. |
| 61 | |
| 62 | In the current implementation, a platform which has more than 1 variant |
| 63 | with different revisions of a processor has no runtime mechanism available |
| 64 | for it to specify which errata workarounds should be enabled or not. |
| 65 | |
| 66 | The value of the build flags are 0 by default, that is, disabled. Any other |
| 67 | value will enable it. |
| 68 | |
| 69 | For Cortex-A53, following errata build flags are defined : |
| 70 | |
| 71 | - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 |
| 72 | CPU. This needs to be enabled only for revision <= r0p2 of the CPU. |
| 73 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 74 | - ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and |
| 75 | link time to Cortex-A53 CPU. This needs to be enabled for some variants of |
| 76 | revision <= r0p4. This workaround can lead the linker to create ``*.stub`` |
| 77 | sections. |
| 78 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 79 | - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 |
| 80 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From |
| 81 | r0p4 and onwards, this errata is enabled by default in hardware. |
| 82 | |
Douglas Raillard | ca6b1cb | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 83 | - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time |
| 84 | to Cortex-A53 CPU. This needs to be enabled for some variants of revision |
| 85 | <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections |
| 86 | which are 4kB aligned. |
| 87 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 88 | - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 |
| 89 | CPUs. Though the erratum is present in every revision of the CPU, |
| 90 | this workaround is only applied to CPUs from r0p3 onwards, which feature |
| 91 | a chicken bit in CPUACTLR\_EL1 to enable a hardware workaround. |
| 92 | Earlier revisions of the CPU have other errata which require the same |
| 93 | workaround in software, so they should be covered anyway. |
| 94 | |
| 95 | For Cortex-A57, following errata build flags are defined : |
| 96 | |
| 97 | - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 |
| 98 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 99 | |
| 100 | - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 |
| 101 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 102 | |
| 103 | - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 |
| 104 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 105 | |
| 106 | - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 |
| 107 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 108 | |
| 109 | - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 |
| 110 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 111 | |
| 112 | - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 |
| 113 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 114 | |
| 115 | - ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 |
| 116 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 117 | |
| 118 | - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 |
| 119 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 120 | |
Eleanor Bonnici | 45b52c2 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 121 | - ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 |
| 122 | CPU. This needs to be enabled only for revision <= r1p3 of the CPU. |
| 123 | |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 124 | |
| 125 | For Cortex-A72, following errata build flags are defined : |
| 126 | |
| 127 | - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 |
| 128 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. |
| 129 | |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 130 | CPU Specific optimizations |
| 131 | -------------------------- |
| 132 | |
| 133 | This section describes some of the optimizations allowed by the CPU micro |
| 134 | architecture that can be enabled by the platform as desired. |
| 135 | |
| 136 | - ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the |
| 137 | Cortex-A57 cluster power down sequence by not flushing the Level 1 data |
| 138 | cache. The L1 data cache and the L2 unified cache are inclusive. A flush |
| 139 | of the L2 by set/way flushes any dirty lines from the L1 as well. This |
| 140 | is a known safe deviation from the Cortex-A57 TRM defined power down |
| 141 | sequence. Each Cortex-A57 based platform must make its own decision on |
| 142 | whether to use the optimization. |
| 143 | |
| 144 | - ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal |
| 145 | hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave |
| 146 | in a way most programmers expect, and will most probably result in a |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 147 | significant speed degradation to any code that employs them. The Armv8-A |
| 148 | architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 149 | the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this |
| 150 | flag enforces this behaviour. This needs to be enabled only for revisions |
| 151 | <= r0p3 of the CPU and is enabled by default. |
| 152 | |
| 153 | - ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as |
| 154 | ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be |
| 155 | enabled only for revisions <= r1p2 of the CPU and is enabled by default, |
| 156 | as recommended in section "4.7 Non-Temporal Loads/Stores" of the |
| 157 | `Cortex-A57 Software Optimization Guide`_. |
| 158 | |
| 159 | -------------- |
| 160 | |
Dan Handley | 4def07d | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 161 | *Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 162 | |
Dimitris Papastamos | f62ad32 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 163 | .. _CVE-2017-5715: http://www.cve.mitre.org/cgi-bin/cvename.cgi?name=2017-5715 |
Eleanor Bonnici | 45b52c2 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 164 | .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 165 | .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf |
Eleanor Bonnici | 6de9b33 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 166 | .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html |
Douglas Raillard | 6f62574 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 167 | .. _Firmware Design guide: firmware-design.rst |
| 168 | .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf |