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gerrit-public.fairphone.software / platform / external / arm-trusted-firmware / b49b3221900e4bc1d223227273815492da599f20 / services
  1. 42cae5a PSCI: Set ON_PENDING state early during CPU_ON by Soby Mathew · 9 years ago
  2. 709a3c4 Pass arguments/results between EL3/S-EL1 via CPU registers (x0-x7) by Varun Wadekar · 9 years ago
  3. 8b77962 Add support to indicate size and end of assembly functions by Kévin Petit · 9 years ago
  4. 874cd37 Merge pull request #280 from vwadekar/tlkd-fixed-v3 by danh-arm · 9 years ago
  5. 6693962 Open/Close TA sessions, send commands/events to TAs by Varun Wadekar · 9 years ago
  6. f9d2505 Preempt/Resume standard function ID calls by Varun Wadekar · 9 years ago
  7. 6e159e7 Translate secure/non-secure virtual addresses by Varun Wadekar · 9 years ago
  8. 77199df Register NS shared memory for SP's activity logs and TA sessions by Varun Wadekar · 9 years ago
  9. 2203831 Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd) by Varun Wadekar · 9 years ago
  10. 12e7c4a Initialise cpu ops after enabling data cache by Vikram Kanigiri · 9 years ago
  11. ba592e2 Fix violations to the coding style by Sandrine Bailleux · 9 years ago
  12. 8c32bc2 Export maximum affinity using PLATFORM_MAX_AFFLVL macro by Soby Mathew · 9 years ago
  13. 79a97b2 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 10 years ago
  14. f4f1ae7 Demonstrate model for routing IRQs to EL3 by Soby Mathew · 9 years ago
  15. b234b2c Verify capabilities before handling PSCI calls by Soby Mathew · 9 years ago
  16. 90e8258 Implement PSCI_FEATURES API by Soby Mathew · 10 years ago
  17. 8991eed Rework the PSCI migrate APIs by Soby Mathew · 10 years ago
  18. 22f0897 Return success if an interrupt is seen during PSCI CPU_SUSPEND by Soby Mathew · 10 years ago
  19. 539dced Validate power_state and entrypoint when executing PSCI calls by Soby Mathew · 10 years ago
  20. 31244d7 Save 'power_state' early in PSCI CPU_SUSPEND call by Soby Mathew · 10 years ago
  21. 78879b9 Rework internal API to save non-secure entry point info by Soby Mathew · 10 years ago
  22. 2f5aade PSCI: Check early for invalid CPU state during CPU ON by Soby Mathew · 10 years ago
  23. e146f4c Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops by Soby Mathew · 10 years ago
  24. ab8707e Remove coherent memory from the BL memory maps by Soby Mathew · 10 years ago
  25. 8c5fe0b Move bakery algorithm implementation out of coherent memory by Soby Mathew · 10 years ago
  26. 0999734 Invalidate the dcache after initializing cpu-ops by Soby Mathew · 10 years ago
  27. 264999f Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl() by Soby Mathew · 10 years ago
  28. 235585b Fix the array size of mpidr_aff_map_nodes_t. by Soby Mathew · 10 years ago
  29. aa5da46 Add opteed based on tspd by Jens Wiklander · 10 years ago
  30. add4035 Add CPU specific power management operations by Soby Mathew · 10 years ago
  31. a4a8eae Miscellaneous PSCI code cleanups by Achin Gupta · 10 years ago
  32. 0a46e2c Add APIs to preserve highest affinity level in OFF state by Achin Gupta · 10 years ago
  33. 84c9f10 Rework state management in the PSCI implementation by Achin Gupta · 10 years ago
  34. 776b68a Add PSCI service specific per-CPU data by Achin Gupta · 10 years ago
  35. d5f1309 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · 10 years ago
  36. a1d8044 Merge pull request #189 from achingupta/ag/tf-issues#153 by Dan Handley · 10 years ago
  37. 5a06bb7 Clarify platform porting interface to TSP by Dan Handley · 10 years ago
  38. 0c8d4fe Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · 10 years ago
  39. 319609a Merge pull request #178 from soby-mathew/sm/optmize_el3_context by danh-arm · 10 years ago
  40. faaa2e7 Support asynchronous method for BL3-2 initialization by Vikram Kanigiri · 10 years ago
  41. 50e27da Rework the TSPD setup code by Vikram Kanigiri · 10 years ago
  42. fdfabec Optimize EL3 register state stored in cpu_context structure by Soby Mathew · 10 years ago
  43. dd2bdee Merge pull request #177 from jcastillo-arm/jc/tf-issues/096 by danh-arm · 10 years ago
  44. d3280be Rework incorrect use of assert() and panic() in codebase by Juan Castillo · 10 years ago
  45. ec3c100 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · 10 years ago
  46. 539a7b3 Remove the concept of coherent stacks by Achin Gupta · 10 years ago
  47. b51da82 Remove coherent stack usage from the warm boot path by Achin Gupta · 10 years ago
  48. afff8cb Make enablement of the MMU more flexible by Achin Gupta · 10 years ago
  49. 56378aa Remove current CPU mpidr from PSCI common code by Andrew Thoelke · 10 years ago
  50. e73af8a Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2 by danh-arm · 10 years ago
  51. 7eea135 Merge pull request #147 from athoelke/at/remove-bakery-mpidr by danh-arm · 10 years ago
  52. 4f2104f Remove all checkpatch errors from codebase by Juan Castillo · 10 years ago
  53. 634ec6c Remove calling CPU mpidr from bakery lock API by Andrew Thoelke · 10 years ago
  54. 41cf7bd Merge pull request #145 from athoelke/at/psci-memory-optimization-v2 by danh-arm · 10 years ago
  55. 47fe640 Merge pull request #144 from athoelke/at/init-context-v2 by danh-arm · 10 years ago
  56. 6c0b45d Correctly dimension the PSCI aff_map_node array by Andrew Thoelke · 10 years ago
  57. 13ac44a Eliminate psci_suspend_context array by Andrew Thoelke · 10 years ago
  58. 167a935 Initialise CPU contexts from entry_point_info by Andrew Thoelke · 10 years ago
  59. 5219862 Merge pull request #140 from athoelke/at/psci_smc_handler by danh-arm · 10 years ago
  60. ee94cc6 Remove early_exceptions from BL3-1 by Andrew Thoelke · 10 years ago
  61. 5e91007 Per-cpu data cache restructuring by Andrew Thoelke · 10 years ago
  62. 08ab89d Provide cm_get/set_context() for current CPU by Andrew Thoelke · 10 years ago
  63. 5003eca PSCI SMC handler improvements by Andrew Thoelke · 10 years ago
  64. a378108 Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · 10 years ago
  65. 05b6edf Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 into for-v0.4 by Dan Handley · 10 years ago
  66. 9865ac1 Further renames of platform porting functions by Dan Handley · 10 years ago
  67. 10b65ec Fixup Standard SMC Resume Handling by Soby Mathew · 10 years ago
  68. dff8e47 Add enable mmu platform porting interfaces by Dan Handley · 10 years ago
  69. 5f0cdb0 Split platform.h into separate headers by Dan Handley · 10 years ago
  70. 7a9a5f2 Remove unused data declarations by Dan Handley · 10 years ago
  71. c6bc071 Remove extern keyword from function declarations by Dan Handley · 10 years ago
  72. 8957fc7 Merge pull request #104 from athoelke:at/tsp-entrypoints-v2 by Andrew Thoelke · 10 years ago
  73. 65335d4 Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2 by Andrew Thoelke · 10 years ago
  74. 8545a87 Merge pull request #102 from achingupta:ag/tf-issues#104-v2 by Andrew Thoelke · 10 years ago
  75. db0de0e Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3 by Andrew Thoelke · 10 years ago
  76. 3ea8540 Merge pull request #67 from achingupta:ag/psci_standby_bug_fix by Andrew Thoelke · 10 years ago
  77. 399fb08 Use a vector table for TSP entrypoints by Andrew Thoelke · 10 years ago
  78. 239b04f Non-Secure Interrupt support during Standard SMC processing in TSP by Soby Mathew · 10 years ago
  79. b44a443 Add S-EL1 interrupt handling support in the TSPD by Achin Gupta · 10 years ago
  80. fa9c08b Use secure timer to generate S-EL1 interrupts by Achin Gupta · 10 years ago
  81. dce74b8 Introduce interrupt handling framework in BL3-1 by Achin Gupta · 10 years ago
  82. c429b5e Add context library API to change a bit in SCR_EL3 by Achin Gupta · 10 years ago
  83. 3ee8a16 Rework 'state' field usage in per-cpu TSP context by Achin Gupta · 10 years ago
  84. 6871c5d Rework memory information passing to BL3-x images by Vikram Kanigiri · 10 years ago
  85. 4112bfa Populate BL31 input parameters as per new spec by Vikram Kanigiri · 10 years ago
  86. 23ff9ba Introduce macros to manipulate the SPSR by Vikram Kanigiri · 10 years ago
  87. a43d431 Rework BL3-1 unhandled exception handling and reporting by Soby Mathew · 10 years ago
  88. 317ba09 Fix broken standby state implementation in PSCI by Achin Gupta · 10 years ago
  89. b793e43 fvp: Provide per-EL MMU setup functions by Sandrine Bailleux · 10 years ago
  90. 401607c Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1 by danh-arm · 10 years ago
  91. c3260f9 Preserve x19-x29 across world switch for exception handling by Soby Mathew · 10 years ago
  92. 7935d0a Access system registers directly in assembler by Andrew Thoelke · 10 years ago
  93. 8cec598 Correct usage of data and instruction barriers by Andrew Thoelke · 10 years ago
  94. 625de1d Remove variables from .data section by Dan Handley · 10 years ago
  95. 97043ac Reduce deep nesting of header files by Dan Handley · 10 years ago
  96. fb037bf Always use named structs in header files by Dan Handley · 10 years ago
  97. c594573 Move PSCI global functions out of private header by Dan Handley · 10 years ago
  98. 5b827a8 Separate BL functions out of arch.h by Dan Handley · 10 years ago
  99. bdbfc3c Separate out CASSERT macro into own header by Dan Handley · 10 years ago
  100. bee8241 Remove vpath usage in makefiles by Dan Handley · 10 years ago