autotest: update Intel microarchitecture CPUID mapping and power metric support
This is to update IA uarch table for modern SoCs along with there MSR power
metric support which is associating with the uarch query, include:
- Adding keys for Comet Lake (CML), Ice Lake (ICL), and Tiger Lake (TGL)
- Adding Package C-state residency support for CML, ICL, and TGL
- Adding RAPL MSR access for CML, ICL, and TGL
Note that the uarch code names respect the documentation.
CPUID/MSR information comes from Intel SDM vol. #4 [1], Linux kernel source [2],
and the External Design Specification (EDS) of CML/ICL/TGL respectively [3].
[1] https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-4-model-specific-registers
[2] https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h
[3] https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
BUG=none
TEST=Test power_LoadTest.fast only, examine the modification doesn't break anything.
Change-Id: I75baf394cdf6966c69a7c8dd3f74a9acad89a27b
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/autotest/+/1857985
Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Eric Caruso <ejcaruso@chromium.org>
diff --git a/client/bin/utils.py b/client/bin/utils.py
index 1600d63..b43619f 100644
--- a/client/bin/utils.py
+++ b/client/bin/utils.py
@@ -326,6 +326,8 @@
'06_47': 'Broadwell',
'06_4F': 'Broadwell',
'06_56': 'Broadwell',
+ '06_A5': 'Comet Lake',
+ '06_A6': 'Comet Lake',
'06_0D': 'Dothan',
'06_5C': 'Goldmont',
'06_7A': 'Goldmont',
@@ -333,6 +335,8 @@
'06_45': 'Haswell',
'06_46': 'Haswell',
'06_3F': 'Haswell-E',
+ '06_7D': 'Ice Lake',
+ '06_7E': 'Ice Lake',
'06_3A': 'Ivy Bridge',
'06_3E': 'Ivy Bridge-E',
'06_8E': 'Kaby Lake',
@@ -358,6 +362,8 @@
'06_4E': 'Skylake',
'06_5E': 'Skylake',
'06_55': 'Skylake',
+ '06_8C': 'Tiger Lake',
+ '06_8D': 'Tiger Lake',
'06_25': 'Westmere',
'06_2C': 'Westmere',
'06_2F': 'Westmere',
diff --git a/client/cros/power/power_status.py b/client/cros/power/power_status.py
index 4a64d7b..583376c 100644
--- a/client/cros/power/power_status.py
+++ b/client/cros/power/power_status.py
@@ -983,8 +983,10 @@
'Airmont': self.SILVERMONT,
'Atom': self.ATOM,
'Broadwell': self.BROADWELL,
+ 'Comet Lake': self.BROADWELL,
'Goldmont': self.GOLDMONT,
'Haswell': self.SANDY_BRIDGE,
+ 'Ice Lake': self.BROADWELL,
'Ivy Bridge': self.SANDY_BRIDGE,
'Ivy Bridge-E': self.SANDY_BRIDGE,
'Kaby Lake': self.BROADWELL,
@@ -992,6 +994,7 @@
'Sandy Bridge': self.SANDY_BRIDGE,
'Silvermont': self.SILVERMONT,
'Skylake': self.BROADWELL,
+ 'Tiger Lake': self.BROADWELL,
'Westmere': self.NEHALEM,
}.get(cpu_uarch, None)
diff --git a/client/cros/power/power_utils.py b/client/cros/power/power_utils.py
index 0df2f86..f7cb76e 100644
--- a/client/cros/power/power_utils.py
+++ b/client/cros/power/power_utils.py
@@ -76,7 +76,7 @@
Boolean, True if RAPL supported, False otherwise.
"""
rapl_set = set(["Haswell", "Haswell-E", "Broadwell", "Skylake", "Goldmont",
- "Kaby Lake"])
+ "Kaby Lake", "Comet Lake", "Ice Lake", "Tiger Lake"])
cpu_uarch = utils.get_intel_cpu_uarch()
if (cpu_uarch in rapl_set):
return True