| commit | 5cbb5c8e9904cdd70a9336405c9c561a6b745a8a | [log] [tgz] |
|---|---|---|
| author | Robert Sloan <varomodt@google.com> | Tue Apr 24 11:35:46 2018 -0700 |
| committer | Robert Sloan <varomodt@google.com> | Tue Apr 24 11:35:52 2018 -0700 |
| tree | 87c407a05e18d9442cd85ef2cd5337cbb58de218 | |
| parent | 15c0b3594be4cd3bd18a44be8eef0429a0cb072f [diff] [blame] |
external/boringssl: Sync to a63d0ad40dd621d5b9472dc9f1756692f969451e. This includes the following changes: https://boringssl.googlesource.com/boringssl/+log/9f0e7cb314ae64234b928fd379381ae9760a9a5f..a63d0ad40dd621d5b9472dc9f1756692f969451e Test: BoringSSL CTS Presubmits. Change-Id: I283b7d8f01ceef3becb152708b65894c717e3680
diff --git a/src/include/openssl/cpu.h b/src/include/openssl/cpu.h index dd95ddc..bb847f9 100644 --- a/src/include/openssl/cpu.h +++ b/src/include/openssl/cpu.h
@@ -86,7 +86,8 @@ // Bit 11 is used to indicate AMD XOP support, not SDBG // Index 2: // EBX for CPUID where EAX = 7 -// Index 3 is set to zero. +// Index 3: +// ECX for CPUID where EAX = 7 // // Note: the CPUID bits are pre-adjusted for the OSXSAVE bit and the YMM and XMM // bits in XCR0, so it is not necessary to check those.