Added support for the TMS320C64x architecture.
diff --git a/cs.c b/cs.c
index b4e2dd1..e5266dc 100644
--- a/cs.c
+++ b/cs.c
@@ -60,6 +60,7 @@
extern void Sparc_enable(void);
extern void SystemZ_enable(void);
extern void XCore_enable(void);
+extern void TMS320C64x_enable(void);
static void archs_enable(void)
{
@@ -95,6 +96,9 @@
#ifdef CAPSTONE_HAS_XCORE
XCore_enable();
#endif
+#ifdef CAPSTONE_HAS_TMS320C64X
+ TMS320C64x_enable();
+#endif
initialized = true;
@@ -173,7 +177,8 @@
return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) |
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
- (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE));
+ (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) |
+ (1 << CS_ARCH_TMS320C64X));
if ((unsigned int)query < CS_ARCH_MAX)
return all_arch & (1 << query);
@@ -427,6 +432,9 @@
case CS_ARCH_M68K:
// M68K has 2 bytes instruction alignment but contain multibyte instruction so we skip 2 bytes
return 2;
+ case CS_ARCH_TMS320C64X:
+ // TMS320C64x alignment is 4.
+ return 4;
}
}
@@ -1106,6 +1114,11 @@
if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type)
count++;
break;
+ case CS_ARCH_TMS320C64X:
+ for (i = 0; i < insn->detail->tms320c64x.op_count; i++)
+ if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type)
+ count++;
+ break;
}
return count;
@@ -1207,6 +1220,14 @@
return i;
}
break;
+ case CS_ARCH_TMS320C64X:
+ for (i = 0; i < insn->detail->tms320c64x.op_count; i++) {
+ if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type)
+ count++;
+ if (count == post)
+ return i;
+ }
+ break;
}
return -1;