commit 1a66fecdbc0d0ca441b60213bcae767f18bbeb10
author Nguyen Anh Quynh <aquynh@gmail.com> Thu Jun 26 12:09:15 2014 +0800
committer Nguyen Anh Quynh <aquynh@gmail.com> Thu Jun 26 12:09:15 2014 +0800
tree 8797da4ce6ad86ce51bf4639ebca31b3a469a7a3
parent 7de200afeef34423ec870f4df8b87e7fe8ec57ae

x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change

arch/X86/X86GenAsmWriter1.inc

diff --git a/arch/X86/X86GenAsmWriter1.inc b/arch/X86/X86GenAsmWriter1.inc
index eccbfb9..6eab0e6 100644
--- a/arch/X86/X86GenAsmWriter1.inc
+++ b/arch/X86/X86GenAsmWriter1.inc
@@ -12823,6 +12823,7 @@
   case 5:
     // VCMPPDZrrib, VCMPPSZrrib, VRCP28PDZrb, VRCP28PSZrb, VRSQRT28PDZrb, VRS...
     SStream_concat0(O, ", {sae}"); 
+	op_addAvxSae(MI);
     return;
     break;
   case 6:
@@ -12838,7 +12839,7 @@
   case 8:
     // VMOVDQU32rrkz, VMOVDQU64rrkz, VPBROADCASTDZkrm, VPBROADCASTDZkrr, VPBR...
     SStream_concat0(O, "} {z}, "); 
-	op_addZeroOpmask(MI);
+	op_addAvxZeroOpmask(MI);
     break;
   case 9:
     // VPCONFLICTDrmb
@@ -13012,6 +13013,7 @@
   case 4:
     // VRCP28SDrrb, VRCP28SSrrb, VRSQRT28SDrrb, VRSQRT28SSrrb
     SStream_concat0(O, ", {sae}"); 
+	op_addAvxSae(MI);
     return;
     break;
   }