Merge branch 'next' of https://github.com/aquynh/capstone into next
diff --git a/arch/AArch64/AArch64Module.c b/arch/AArch64/AArch64Module.c
index 2e745b8..9ea4c2a 100644
--- a/arch/AArch64/AArch64Module.c
+++ b/arch/AArch64/AArch64Module.c
@@ -7,8 +7,6 @@
#include "AArch64InstPrinter.h"
#include "AArch64Mapping.h"
-void enable_arm64() {}
-
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index 8de834c..f8b460c 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -443,6 +443,7 @@
ud->ITBlock.size = 0;
if (code_len < 4)
+ // not enough data
return MCDisassembler_Fail;
memcpy(bytes, code, 4);
@@ -675,6 +676,7 @@
// We want to read exactly 2 bytes of data.
if (code_len < 2)
+ // not enough data
return MCDisassembler_Fail;
memcpy(bytes, code, 2);
@@ -728,10 +730,9 @@
}
// We want to read exactly 4 bytes of data.
- //if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
- // *Size = 0;
- // return MCDisassembler_Fail;
- //}
+ if (code_len < 4)
+ // not enough data
+ return MCDisassembler_Fail;
memcpy(bytes, code, 4);
diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c
index ea7d726..02ddb2e 100644
--- a/arch/Mips/MipsModule.c
+++ b/arch/Mips/MipsModule.c
@@ -7,8 +7,6 @@
#include "MipsInstPrinter.h"
#include "MipsMapping.h"
-void enable_mips() {};
-
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index 5f3702f..ee6aeb9 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#include <stdio.h>
#include <stdlib.h>
@@ -27,8 +27,6 @@
#include "../../MathExtras.h"
#include "PPCMapping.h"
-//#include "PPCMapping.h"
-
static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
@@ -127,18 +125,6 @@
}
}
- // For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
- // used when converting a 32-bit float to a 64-bit float as part of
- // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
- // as otherwise we have problems with incorrect register classes
- // in machine instruction verification. For now, just avoid trying
- // to print it as such an instruction has no effect (a 32-bit float
- // in a register is already in 64-bit form, just with lower
- // precision). FIXME: Is there a better solution?
-
- //if (MCInst_getOpcode(MI) == TargetOpcode_COPY_TO_REGCLASS)
- // return;
-
printInstruction(MI, O, NULL);
}
@@ -152,6 +138,7 @@
if (!strcmp(Modifier, "cc")) {
switch ((ppc_predicate)Code) {
+ default: // unreachable
case PPC_PRED_LT_MINUS:
case PPC_PRED_LT_PLUS:
case PPC_PRED_LT:
@@ -193,7 +180,6 @@
SStream_concat(O, "nu");
return;
}
- // llvm_unreachable("Invalid predicate code");
}
if (!strcmp(Modifier, "pm")) {
@@ -227,6 +213,8 @@
case PPC_PRED_NU_PLUS:
SStream_concat(O, "+");
return;
+ default: // unreachable
+ return;
}
// llvm_unreachable("Invalid predicate code");
}
diff --git a/arch/PowerPC/PPCModule.c b/arch/PowerPC/PPCModule.c
index 89845b1..f547bcc 100644
--- a/arch/PowerPC/PPCModule.c
+++ b/arch/PowerPC/PPCModule.c
@@ -7,8 +7,6 @@
#include "PPCInstPrinter.h"
#include "PPCMapping.h"
-void enable_powerpc() {};
-
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
diff --git a/arch/X86/X86Module.c b/arch/X86/X86Module.c
index 77a549b..02f3c97 100644
--- a/arch/X86/X86Module.c
+++ b/arch/X86/X86Module.c
@@ -7,8 +7,6 @@
#include "X86InstPrinter.h"
#include "X86Mapping.h"
-void enable_x86() {};
-
static cs_err init(cs_struct *ud)
{
// verify if requested mode is valid