initial import
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
new file mode 100644
index 0000000..b63094d
--- /dev/null
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -0,0 +1,984 @@
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include "../../asprintf.h"
+#include "../../utils.h"
+
+#include <stdlib.h>
+
+#include "AArch64BaseInfo.h"
+
+char *NamedImmMapper_toString(NamedImmMapper *N, uint32_t Value, bool *Valid)
+{
+ unsigned i;
+ for (i = 0; i < N->NumPairs; ++i) {
+ if (N->Pairs[i].Value == Value) {
+ *Valid = true;
+ return N->Pairs[i].Name;
+ }
+ }
+
+ *Valid = false;
+ return 0;
+}
+
+// compare s1 with lower(s2)
+// return true if s1 == lower(f2), and false otherwise
+static bool compare_lower_str(char *s1, char *s2)
+{
+ char *lower = strdup(s2), *c;
+ for (c = lower; *c; c++)
+ *c = tolower(*c);
+
+ bool res = (strcmp(s1, lower) == 0);
+ free(lower);
+
+ return res;
+}
+
+uint32_t NamedImmMapper_fromString(NamedImmMapper *N, char *Name, bool *Valid)
+{
+ unsigned i;
+ for (i = 0; i < N->NumPairs; ++i) {
+ if (compare_lower_str(N->Pairs[i].Name, Name)) {
+ *Valid = true;
+ return N->Pairs[i].Value;
+ }
+ }
+
+ *Valid = false;
+ return -1;
+}
+
+bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value)
+{
+ return Value < N->TooBigImm;
+}
+
+// return a string representing the number X
+// NOTE: caller must free() the result itself to avoid memory leak
+static char *utostr(uint64_t X, bool isNeg)
+{
+ char Buffer[22];
+ char *BufPtr = Buffer+21;
+
+ Buffer[21] = '\0';
+ if (X == 0) *--BufPtr = '0'; // Handle special case...
+
+ while (X) {
+ *--BufPtr = X % 10 + '0';
+ X /= 10;
+ }
+
+ if (isNeg) *--BufPtr = '-'; // Add negative sign...
+
+ char *result = strdup(BufPtr);
+ return result;
+}
+
+static NamedImmMapper_Mapping SysRegPairs[] = {
+ {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
+ {"osdtrtx_el1", A64SysReg_OSDTRTX_EL1},
+ {"teecr32_el1", A64SysReg_TEECR32_EL1},
+ {"mdccint_el1", A64SysReg_MDCCINT_EL1},
+ {"mdscr_el1", A64SysReg_MDSCR_EL1},
+ {"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
+ {"oseccr_el1", A64SysReg_OSECCR_EL1},
+ {"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
+ {"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
+ {"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
+ {"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
+ {"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
+ {"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
+ {"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
+ {"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
+ {"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
+ {"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
+ {"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
+ {"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
+ {"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
+ {"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
+ {"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
+ {"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
+ {"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
+ {"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
+ {"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
+ {"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
+ {"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
+ {"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
+ {"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
+ {"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
+ {"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
+ {"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
+ {"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
+ {"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
+ {"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
+ {"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
+ {"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
+ {"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
+ {"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
+ {"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
+ {"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
+ {"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
+ {"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
+ {"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
+ {"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
+ {"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
+ {"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
+ {"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
+ {"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
+ {"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
+ {"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
+ {"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
+ {"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
+ {"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
+ {"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
+ {"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
+ {"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
+ {"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
+ {"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
+ {"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
+ {"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
+ {"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
+ {"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
+ {"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
+ {"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
+ {"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
+ {"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
+ {"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
+ {"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
+ {"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
+ {"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
+ {"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
+ {"osdlr_el1", A64SysReg_OSDLR_EL1},
+ {"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
+ {"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
+ {"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
+ {"csselr_el1", A64SysReg_CSSELR_EL1},
+ {"vpidr_el2", A64SysReg_VPIDR_EL2},
+ {"vmpidr_el2", A64SysReg_VMPIDR_EL2},
+ {"sctlr_el1", A64SysReg_SCTLR_EL1},
+ {"sctlr_el2", A64SysReg_SCTLR_EL2},
+ {"sctlr_el3", A64SysReg_SCTLR_EL3},
+ {"actlr_el1", A64SysReg_ACTLR_EL1},
+ {"actlr_el2", A64SysReg_ACTLR_EL2},
+ {"actlr_el3", A64SysReg_ACTLR_EL3},
+ {"cpacr_el1", A64SysReg_CPACR_EL1},
+ {"hcr_el2", A64SysReg_HCR_EL2},
+ {"scr_el3", A64SysReg_SCR_EL3},
+ {"mdcr_el2", A64SysReg_MDCR_EL2},
+ {"sder32_el3", A64SysReg_SDER32_EL3},
+ {"cptr_el2", A64SysReg_CPTR_EL2},
+ {"cptr_el3", A64SysReg_CPTR_EL3},
+ {"hstr_el2", A64SysReg_HSTR_EL2},
+ {"hacr_el2", A64SysReg_HACR_EL2},
+ {"mdcr_el3", A64SysReg_MDCR_EL3},
+ {"ttbr0_el1", A64SysReg_TTBR0_EL1},
+ {"ttbr0_el2", A64SysReg_TTBR0_EL2},
+ {"ttbr0_el3", A64SysReg_TTBR0_EL3},
+ {"ttbr1_el1", A64SysReg_TTBR1_EL1},
+ {"tcr_el1", A64SysReg_TCR_EL1},
+ {"tcr_el2", A64SysReg_TCR_EL2},
+ {"tcr_el3", A64SysReg_TCR_EL3},
+ {"vttbr_el2", A64SysReg_VTTBR_EL2},
+ {"vtcr_el2", A64SysReg_VTCR_EL2},
+ {"dacr32_el2", A64SysReg_DACR32_EL2},
+ {"spsr_el1", A64SysReg_SPSR_EL1},
+ {"spsr_el2", A64SysReg_SPSR_EL2},
+ {"spsr_el3", A64SysReg_SPSR_EL3},
+ {"elr_el1", A64SysReg_ELR_EL1},
+ {"elr_el2", A64SysReg_ELR_EL2},
+ {"elr_el3", A64SysReg_ELR_EL3},
+ {"sp_el0", A64SysReg_SP_EL0},
+ {"sp_el1", A64SysReg_SP_EL1},
+ {"sp_el2", A64SysReg_SP_EL2},
+ {"spsel", A64SysReg_SPSel},
+ {"nzcv", A64SysReg_NZCV},
+ {"daif", A64SysReg_DAIF},
+ {"currentel", A64SysReg_CurrentEL},
+ {"spsr_irq", A64SysReg_SPSR_irq},
+ {"spsr_abt", A64SysReg_SPSR_abt},
+ {"spsr_und", A64SysReg_SPSR_und},
+ {"spsr_fiq", A64SysReg_SPSR_fiq},
+ {"fpcr", A64SysReg_FPCR},
+ {"fpsr", A64SysReg_FPSR},
+ {"dspsr_el0", A64SysReg_DSPSR_EL0},
+ {"dlr_el0", A64SysReg_DLR_EL0},
+ {"ifsr32_el2", A64SysReg_IFSR32_EL2},
+ {"afsr0_el1", A64SysReg_AFSR0_EL1},
+ {"afsr0_el2", A64SysReg_AFSR0_EL2},
+ {"afsr0_el3", A64SysReg_AFSR0_EL3},
+ {"afsr1_el1", A64SysReg_AFSR1_EL1},
+ {"afsr1_el2", A64SysReg_AFSR1_EL2},
+ {"afsr1_el3", A64SysReg_AFSR1_EL3},
+ {"esr_el1", A64SysReg_ESR_EL1},
+ {"esr_el2", A64SysReg_ESR_EL2},
+ {"esr_el3", A64SysReg_ESR_EL3},
+ {"fpexc32_el2", A64SysReg_FPEXC32_EL2},
+ {"far_el1", A64SysReg_FAR_EL1},
+ {"far_el2", A64SysReg_FAR_EL2},
+ {"far_el3", A64SysReg_FAR_EL3},
+ {"hpfar_el2", A64SysReg_HPFAR_EL2},
+ {"par_el1", A64SysReg_PAR_EL1},
+ {"pmcr_el0", A64SysReg_PMCR_EL0},
+ {"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
+ {"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
+ {"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
+ {"pmselr_el0", A64SysReg_PMSELR_EL0},
+ {"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
+ {"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
+ {"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
+ {"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
+ {"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
+ {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
+ {"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
+ {"mair_el1", A64SysReg_MAIR_EL1},
+ {"mair_el2", A64SysReg_MAIR_EL2},
+ {"mair_el3", A64SysReg_MAIR_EL3},
+ {"amair_el1", A64SysReg_AMAIR_EL1},
+ {"amair_el2", A64SysReg_AMAIR_EL2},
+ {"amair_el3", A64SysReg_AMAIR_EL3},
+ {"vbar_el1", A64SysReg_VBAR_EL1},
+ {"vbar_el2", A64SysReg_VBAR_EL2},
+ {"vbar_el3", A64SysReg_VBAR_EL3},
+ {"rmr_el1", A64SysReg_RMR_EL1},
+ {"rmr_el2", A64SysReg_RMR_EL2},
+ {"rmr_el3", A64SysReg_RMR_EL3},
+ {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+ {"tpidr_el0", A64SysReg_TPIDR_EL0},
+ {"tpidr_el2", A64SysReg_TPIDR_EL2},
+ {"tpidr_el3", A64SysReg_TPIDR_EL3},
+ {"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
+ {"tpidr_el1", A64SysReg_TPIDR_EL1},
+ {"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
+ {"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
+ {"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+ {"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
+ {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+ {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
+ {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
+ {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
+ {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+ {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
+ {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+ {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
+ {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
+ {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+ {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+ {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+ {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
+ {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
+ {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
+ {"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
+ {"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
+ {"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
+ {"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
+ {"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
+ {"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
+ {"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
+ {"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
+ {"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
+ {"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
+ {"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
+ {"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
+ {"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
+ {"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
+ {"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
+ {"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
+ {"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
+ {"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
+ {"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
+ {"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
+ {"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
+ {"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
+ {"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
+ {"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
+ {"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
+ {"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
+ {"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
+ {"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
+ {"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
+ {"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
+ {"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
+ {"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
+ {"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
+ {"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
+ {"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
+ {"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
+ {"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
+ {"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
+ {"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
+ {"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
+ {"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
+ {"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
+ {"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
+ {"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
+ {"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
+ {"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
+ {"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
+ {"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
+ {"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
+ {"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
+ {"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
+ {"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
+ {"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
+ {"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
+ {"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
+ {"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
+ {"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
+ {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
+ {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
+ {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+
+ // Trace registers
+ {"trcprgctlr", A64SysReg_TRCPRGCTLR},
+ {"trcprocselr", A64SysReg_TRCPROCSELR},
+ {"trcconfigr", A64SysReg_TRCCONFIGR},
+ {"trcauxctlr", A64SysReg_TRCAUXCTLR},
+ {"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
+ {"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
+ {"trcstallctlr", A64SysReg_TRCSTALLCTLR},
+ {"trctsctlr", A64SysReg_TRCTSCTLR},
+ {"trcsyncpr", A64SysReg_TRCSYNCPR},
+ {"trcccctlr", A64SysReg_TRCCCCTLR},
+ {"trcbbctlr", A64SysReg_TRCBBCTLR},
+ {"trctraceidr", A64SysReg_TRCTRACEIDR},
+ {"trcqctlr", A64SysReg_TRCQCTLR},
+ {"trcvictlr", A64SysReg_TRCVICTLR},
+ {"trcviiectlr", A64SysReg_TRCVIIECTLR},
+ {"trcvissctlr", A64SysReg_TRCVISSCTLR},
+ {"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
+ {"trcvdctlr", A64SysReg_TRCVDCTLR},
+ {"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
+ {"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
+ {"trcseqevr0", A64SysReg_TRCSEQEVR0},
+ {"trcseqevr1", A64SysReg_TRCSEQEVR1},
+ {"trcseqevr2", A64SysReg_TRCSEQEVR2},
+ {"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
+ {"trcseqstr", A64SysReg_TRCSEQSTR},
+ {"trcextinselr", A64SysReg_TRCEXTINSELR},
+ {"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
+ {"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
+ {"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
+ {"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
+ {"trccntctlr0", A64SysReg_TRCCNTCTLR0},
+ {"trccntctlr1", A64SysReg_TRCCNTCTLR1},
+ {"trccntctlr2", A64SysReg_TRCCNTCTLR2},
+ {"trccntctlr3", A64SysReg_TRCCNTCTLR3},
+ {"trccntvr0", A64SysReg_TRCCNTVR0},
+ {"trccntvr1", A64SysReg_TRCCNTVR1},
+ {"trccntvr2", A64SysReg_TRCCNTVR2},
+ {"trccntvr3", A64SysReg_TRCCNTVR3},
+ {"trcimspec0", A64SysReg_TRCIMSPEC0},
+ {"trcimspec1", A64SysReg_TRCIMSPEC1},
+ {"trcimspec2", A64SysReg_TRCIMSPEC2},
+ {"trcimspec3", A64SysReg_TRCIMSPEC3},
+ {"trcimspec4", A64SysReg_TRCIMSPEC4},
+ {"trcimspec5", A64SysReg_TRCIMSPEC5},
+ {"trcimspec6", A64SysReg_TRCIMSPEC6},
+ {"trcimspec7", A64SysReg_TRCIMSPEC7},
+ {"trcrsctlr2", A64SysReg_TRCRSCTLR2},
+ {"trcrsctlr3", A64SysReg_TRCRSCTLR3},
+ {"trcrsctlr4", A64SysReg_TRCRSCTLR4},
+ {"trcrsctlr5", A64SysReg_TRCRSCTLR5},
+ {"trcrsctlr6", A64SysReg_TRCRSCTLR6},
+ {"trcrsctlr7", A64SysReg_TRCRSCTLR7},
+ {"trcrsctlr8", A64SysReg_TRCRSCTLR8},
+ {"trcrsctlr9", A64SysReg_TRCRSCTLR9},
+ {"trcrsctlr10", A64SysReg_TRCRSCTLR10},
+ {"trcrsctlr11", A64SysReg_TRCRSCTLR11},
+ {"trcrsctlr12", A64SysReg_TRCRSCTLR12},
+ {"trcrsctlr13", A64SysReg_TRCRSCTLR13},
+ {"trcrsctlr14", A64SysReg_TRCRSCTLR14},
+ {"trcrsctlr15", A64SysReg_TRCRSCTLR15},
+ {"trcrsctlr16", A64SysReg_TRCRSCTLR16},
+ {"trcrsctlr17", A64SysReg_TRCRSCTLR17},
+ {"trcrsctlr18", A64SysReg_TRCRSCTLR18},
+ {"trcrsctlr19", A64SysReg_TRCRSCTLR19},
+ {"trcrsctlr20", A64SysReg_TRCRSCTLR20},
+ {"trcrsctlr21", A64SysReg_TRCRSCTLR21},
+ {"trcrsctlr22", A64SysReg_TRCRSCTLR22},
+ {"trcrsctlr23", A64SysReg_TRCRSCTLR23},
+ {"trcrsctlr24", A64SysReg_TRCRSCTLR24},
+ {"trcrsctlr25", A64SysReg_TRCRSCTLR25},
+ {"trcrsctlr26", A64SysReg_TRCRSCTLR26},
+ {"trcrsctlr27", A64SysReg_TRCRSCTLR27},
+ {"trcrsctlr28", A64SysReg_TRCRSCTLR28},
+ {"trcrsctlr29", A64SysReg_TRCRSCTLR29},
+ {"trcrsctlr30", A64SysReg_TRCRSCTLR30},
+ {"trcrsctlr31", A64SysReg_TRCRSCTLR31},
+ {"trcssccr0", A64SysReg_TRCSSCCR0},
+ {"trcssccr1", A64SysReg_TRCSSCCR1},
+ {"trcssccr2", A64SysReg_TRCSSCCR2},
+ {"trcssccr3", A64SysReg_TRCSSCCR3},
+ {"trcssccr4", A64SysReg_TRCSSCCR4},
+ {"trcssccr5", A64SysReg_TRCSSCCR5},
+ {"trcssccr6", A64SysReg_TRCSSCCR6},
+ {"trcssccr7", A64SysReg_TRCSSCCR7},
+ {"trcsscsr0", A64SysReg_TRCSSCSR0},
+ {"trcsscsr1", A64SysReg_TRCSSCSR1},
+ {"trcsscsr2", A64SysReg_TRCSSCSR2},
+ {"trcsscsr3", A64SysReg_TRCSSCSR3},
+ {"trcsscsr4", A64SysReg_TRCSSCSR4},
+ {"trcsscsr5", A64SysReg_TRCSSCSR5},
+ {"trcsscsr6", A64SysReg_TRCSSCSR6},
+ {"trcsscsr7", A64SysReg_TRCSSCSR7},
+ {"trcsspcicr0", A64SysReg_TRCSSPCICR0},
+ {"trcsspcicr1", A64SysReg_TRCSSPCICR1},
+ {"trcsspcicr2", A64SysReg_TRCSSPCICR2},
+ {"trcsspcicr3", A64SysReg_TRCSSPCICR3},
+ {"trcsspcicr4", A64SysReg_TRCSSPCICR4},
+ {"trcsspcicr5", A64SysReg_TRCSSPCICR5},
+ {"trcsspcicr6", A64SysReg_TRCSSPCICR6},
+ {"trcsspcicr7", A64SysReg_TRCSSPCICR7},
+ {"trcpdcr", A64SysReg_TRCPDCR},
+ {"trcacvr0", A64SysReg_TRCACVR0},
+ {"trcacvr1", A64SysReg_TRCACVR1},
+ {"trcacvr2", A64SysReg_TRCACVR2},
+ {"trcacvr3", A64SysReg_TRCACVR3},
+ {"trcacvr4", A64SysReg_TRCACVR4},
+ {"trcacvr5", A64SysReg_TRCACVR5},
+ {"trcacvr6", A64SysReg_TRCACVR6},
+ {"trcacvr7", A64SysReg_TRCACVR7},
+ {"trcacvr8", A64SysReg_TRCACVR8},
+ {"trcacvr9", A64SysReg_TRCACVR9},
+ {"trcacvr10", A64SysReg_TRCACVR10},
+ {"trcacvr11", A64SysReg_TRCACVR11},
+ {"trcacvr12", A64SysReg_TRCACVR12},
+ {"trcacvr13", A64SysReg_TRCACVR13},
+ {"trcacvr14", A64SysReg_TRCACVR14},
+ {"trcacvr15", A64SysReg_TRCACVR15},
+ {"trcacatr0", A64SysReg_TRCACATR0},
+ {"trcacatr1", A64SysReg_TRCACATR1},
+ {"trcacatr2", A64SysReg_TRCACATR2},
+ {"trcacatr3", A64SysReg_TRCACATR3},
+ {"trcacatr4", A64SysReg_TRCACATR4},
+ {"trcacatr5", A64SysReg_TRCACATR5},
+ {"trcacatr6", A64SysReg_TRCACATR6},
+ {"trcacatr7", A64SysReg_TRCACATR7},
+ {"trcacatr8", A64SysReg_TRCACATR8},
+ {"trcacatr9", A64SysReg_TRCACATR9},
+ {"trcacatr10", A64SysReg_TRCACATR10},
+ {"trcacatr11", A64SysReg_TRCACATR11},
+ {"trcacatr12", A64SysReg_TRCACATR12},
+ {"trcacatr13", A64SysReg_TRCACATR13},
+ {"trcacatr14", A64SysReg_TRCACATR14},
+ {"trcacatr15", A64SysReg_TRCACATR15},
+ {"trcdvcvr0", A64SysReg_TRCDVCVR0},
+ {"trcdvcvr1", A64SysReg_TRCDVCVR1},
+ {"trcdvcvr2", A64SysReg_TRCDVCVR2},
+ {"trcdvcvr3", A64SysReg_TRCDVCVR3},
+ {"trcdvcvr4", A64SysReg_TRCDVCVR4},
+ {"trcdvcvr5", A64SysReg_TRCDVCVR5},
+ {"trcdvcvr6", A64SysReg_TRCDVCVR6},
+ {"trcdvcvr7", A64SysReg_TRCDVCVR7},
+ {"trcdvcmr0", A64SysReg_TRCDVCMR0},
+ {"trcdvcmr1", A64SysReg_TRCDVCMR1},
+ {"trcdvcmr2", A64SysReg_TRCDVCMR2},
+ {"trcdvcmr3", A64SysReg_TRCDVCMR3},
+ {"trcdvcmr4", A64SysReg_TRCDVCMR4},
+ {"trcdvcmr5", A64SysReg_TRCDVCMR5},
+ {"trcdvcmr6", A64SysReg_TRCDVCMR6},
+ {"trcdvcmr7", A64SysReg_TRCDVCMR7},
+ {"trccidcvr0", A64SysReg_TRCCIDCVR0},
+ {"trccidcvr1", A64SysReg_TRCCIDCVR1},
+ {"trccidcvr2", A64SysReg_TRCCIDCVR2},
+ {"trccidcvr3", A64SysReg_TRCCIDCVR3},
+ {"trccidcvr4", A64SysReg_TRCCIDCVR4},
+ {"trccidcvr5", A64SysReg_TRCCIDCVR5},
+ {"trccidcvr6", A64SysReg_TRCCIDCVR6},
+ {"trccidcvr7", A64SysReg_TRCCIDCVR7},
+ {"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
+ {"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
+ {"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
+ {"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
+ {"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
+ {"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
+ {"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
+ {"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
+ {"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
+ {"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
+ {"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
+ {"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
+ {"trcitctrl", A64SysReg_TRCITCTRL},
+ {"trcclaimset", A64SysReg_TRCCLAIMSET},
+ {"trcclaimclr", A64SysReg_TRCCLAIMCLR},
+
+ // GICv3 registers
+ {"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
+ {"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
+ {"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
+ {"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
+ {"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
+ {"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
+ {"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
+ {"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
+ {"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
+ {"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
+ {"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
+ {"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
+ {"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
+ {"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
+ {"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
+ {"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
+ {"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
+ {"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
+ {"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
+ {"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
+ {"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
+ {"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
+ {"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
+ {"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
+ {"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
+ {"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
+ {"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
+ {"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
+ {"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
+ {"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
+ {"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
+ {"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
+ {"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
+ {"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
+ {"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
+ {"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
+ {"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
+ {"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
+ {"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
+ {"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
+ {"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
+ {"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
+ {"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
+ {"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
+ {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
+ {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
+ {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
+ {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}
+};
+
+// NOTE: caller must free() the result itself
+char *SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid)
+{
+ unsigned i;
+ for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
+ if (SysRegPairs[i].Value == Bits) {
+ *Valid = true;
+ return strdup(SysRegPairs[i].Name);
+ }
+ }
+
+ for (i = 0; i < S->NumInstPairs; ++i) {
+ if (S->InstPairs[i].Value == Bits) {
+ *Valid = true;
+ return strdup(S->InstPairs[i].Name);
+ }
+ }
+
+ uint32_t Op0 = (Bits >> 14) & 0x3;
+ uint32_t Op1 = (Bits >> 11) & 0x7;
+ uint32_t CRn = (Bits >> 7) & 0xf;
+ uint32_t CRm = (Bits >> 3) & 0xf;
+ uint32_t Op2 = Bits & 0x7;
+
+ // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
+ // name.
+ if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
+ *Valid = false;
+ return NULL;
+ }
+
+ //assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
+
+ *Valid = true;
+
+ //return "s3_" + utostr(Op1) + "_c" + utostr(CRn) + "_c" + utostr(CRm) + "_" + utostr(Op2);
+
+ char *Op1S, *CRnS, *CRmS, *Op2S;
+ Op1S = utostr(Op1, false);
+ CRnS = utostr(CRn, false);
+ CRmS = utostr(CRm, false);
+ Op2S = utostr(Op2, false);
+
+ char *result;
+ int dummy = asprintf(&result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+ (void)dummy;
+
+ free(Op1S);
+ free(CRnS);
+ free(CRmS);
+ free(Op2S);
+
+ return result;
+}
+
+static NamedImmMapper_Mapping TLBIPairs[] = {
+ {"ipas2e1is", A64TLBI_IPAS2E1IS},
+ {"ipas2le1is", A64TLBI_IPAS2LE1IS},
+ {"vmalle1is", A64TLBI_VMALLE1IS},
+ {"alle2is", A64TLBI_ALLE2IS},
+ {"alle3is", A64TLBI_ALLE3IS},
+ {"vae1is", A64TLBI_VAE1IS},
+ {"vae2is", A64TLBI_VAE2IS},
+ {"vae3is", A64TLBI_VAE3IS},
+ {"aside1is", A64TLBI_ASIDE1IS},
+ {"vaae1is", A64TLBI_VAAE1IS},
+ {"alle1is", A64TLBI_ALLE1IS},
+ {"vale1is", A64TLBI_VALE1IS},
+ {"vale2is", A64TLBI_VALE2IS},
+ {"vale3is", A64TLBI_VALE3IS},
+ {"vmalls12e1is", A64TLBI_VMALLS12E1IS},
+ {"vaale1is", A64TLBI_VAALE1IS},
+ {"ipas2e1", A64TLBI_IPAS2E1},
+ {"ipas2le1", A64TLBI_IPAS2LE1},
+ {"vmalle1", A64TLBI_VMALLE1},
+ {"alle2", A64TLBI_ALLE2},
+ {"alle3", A64TLBI_ALLE3},
+ {"vae1", A64TLBI_VAE1},
+ {"vae2", A64TLBI_VAE2},
+ {"vae3", A64TLBI_VAE3},
+ {"aside1", A64TLBI_ASIDE1},
+ {"vaae1", A64TLBI_VAAE1},
+ {"alle1", A64TLBI_ALLE1},
+ {"vale1", A64TLBI_VALE1},
+ {"vale2", A64TLBI_VALE2},
+ {"vale3", A64TLBI_VALE3},
+ {"vmalls12e1", A64TLBI_VMALLS12E1},
+ {"vaale1", A64TLBI_VAALE1}
+};
+
+NamedImmMapper AArch64_TLBIMapper = {
+ .Pairs = TLBIPairs,
+ .NumPairs = ARR_SIZE(TLBIPairs),
+ .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ATPairs[] = {
+ {"s1e1r", A64AT_S1E1R},
+ {"s1e2r", A64AT_S1E2R},
+ {"s1e3r", A64AT_S1E3R},
+ {"s1e1w", A64AT_S1E1W},
+ {"s1e2w", A64AT_S1E2W},
+ {"s1e3w", A64AT_S1E3W},
+ {"s1e0r", A64AT_S1E0R},
+ {"s1e0w", A64AT_S1E0W},
+ {"s12e1r", A64AT_S12E1R},
+ {"s12e1w", A64AT_S12E1W},
+ {"s12e0r", A64AT_S12E0R},
+ {"s12e0w", A64AT_S12E0W},
+};
+
+NamedImmMapper AArch64_ATMapper = {
+ .Pairs = ATPairs,
+ .NumPairs = ARR_SIZE(ATPairs),
+ .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping DBarrierPairs[] = {
+ {"oshld", A64DB_OSHLD},
+ {"oshst", A64DB_OSHST},
+ {"osh", A64DB_OSH},
+ {"nshld", A64DB_NSHLD},
+ {"nshst", A64DB_NSHST},
+ {"nsh", A64DB_NSH},
+ {"ishld", A64DB_ISHLD},
+ {"ishst", A64DB_ISHST},
+ {"ish", A64DB_ISH},
+ {"ld", A64DB_LD},
+ {"st", A64DB_ST},
+ {"sy", A64DB_SY}
+};
+
+NamedImmMapper AArch64_DBarrierMapper = {
+ .Pairs = DBarrierPairs,
+ .NumPairs = ARR_SIZE(DBarrierPairs),
+ .TooBigImm = 16,
+};
+
+static NamedImmMapper_Mapping DCPairs[] = {
+ {"zva", A64DC_ZVA},
+ {"ivac", A64DC_IVAC},
+ {"isw", A64DC_ISW},
+ {"cvac", A64DC_CVAC},
+ {"csw", A64DC_CSW},
+ {"cvau", A64DC_CVAU},
+ {"civac", A64DC_CIVAC},
+ {"cisw", A64DC_CISW}
+};
+
+NamedImmMapper AArch64_DCMapper = {
+ .Pairs = DCPairs,
+ .NumPairs = ARR_SIZE(DCPairs),
+ .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ICPairs[] = {
+ {"ialluis", A64IC_IALLUIS},
+ {"iallu", A64IC_IALLU},
+ {"ivau", A64IC_IVAU}
+};
+
+NamedImmMapper AArch64_ICMapper = {
+ .Pairs = ICPairs,
+ .NumPairs = ARR_SIZE(ICPairs),
+ .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping ISBPairs[] = {
+ {"sy", A64DB_SY},
+};
+
+NamedImmMapper AArch64_ISBMapper = {
+ .Pairs = ISBPairs,
+ .NumPairs = ARR_SIZE(ISBPairs),
+ .TooBigImm = 16,
+};
+
+static NamedImmMapper_Mapping PRFMPairs[] = {
+ {"pldl1keep", A64PRFM_PLDL1KEEP},
+ {"pldl1strm", A64PRFM_PLDL1STRM},
+ {"pldl2keep", A64PRFM_PLDL2KEEP},
+ {"pldl2strm", A64PRFM_PLDL2STRM},
+ {"pldl3keep", A64PRFM_PLDL3KEEP},
+ {"pldl3strm", A64PRFM_PLDL3STRM},
+ {"plil1keep", A64PRFM_PLIL1KEEP},
+ {"plil1strm", A64PRFM_PLIL1STRM},
+ {"plil2keep", A64PRFM_PLIL2KEEP},
+ {"plil2strm", A64PRFM_PLIL2STRM},
+ {"plil3keep", A64PRFM_PLIL3KEEP},
+ {"plil3strm", A64PRFM_PLIL3STRM},
+ {"pstl1keep", A64PRFM_PSTL1KEEP},
+ {"pstl1strm", A64PRFM_PSTL1STRM},
+ {"pstl2keep", A64PRFM_PSTL2KEEP},
+ {"pstl2strm", A64PRFM_PSTL2STRM},
+ {"pstl3keep", A64PRFM_PSTL3KEEP},
+ {"pstl3strm", A64PRFM_PSTL3STRM}
+};
+
+NamedImmMapper AArch64_PRFMMapper = {
+ .Pairs = PRFMPairs,
+ .NumPairs = ARR_SIZE(PRFMPairs),
+ .TooBigImm = 32,
+};
+
+static NamedImmMapper_Mapping PStatePairs[] = {
+ {"spsel", A64PState_SPSel},
+ {"daifset", A64PState_DAIFSet},
+ {"daifclr", A64PState_DAIFClr}
+};
+
+NamedImmMapper AArch64_PStateMapper = {
+ .Pairs = PStatePairs,
+ .NumPairs = ARR_SIZE(PStatePairs),
+ .TooBigImm = 0,
+};
+
+static NamedImmMapper_Mapping MRSPairs[] = {
+ {"mdccsr_el0", A64SysReg_MDCCSR_EL0},
+ {"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
+ {"mdrar_el1", A64SysReg_MDRAR_EL1},
+ {"oslsr_el1", A64SysReg_OSLSR_EL1},
+ {"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
+ {"pmceid0_el0", A64SysReg_PMCEID0_EL0},
+ {"pmceid1_el0", A64SysReg_PMCEID1_EL0},
+ {"midr_el1", A64SysReg_MIDR_EL1},
+ {"ccsidr_el1", A64SysReg_CCSIDR_EL1},
+ {"clidr_el1", A64SysReg_CLIDR_EL1},
+ {"ctr_el0", A64SysReg_CTR_EL0},
+ {"mpidr_el1", A64SysReg_MPIDR_EL1},
+ {"revidr_el1", A64SysReg_REVIDR_EL1},
+ {"aidr_el1", A64SysReg_AIDR_EL1},
+ {"dczid_el0", A64SysReg_DCZID_EL0},
+ {"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
+ {"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
+ {"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
+ {"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
+ {"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
+ {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
+ {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
+ {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+ {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
+ {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
+ {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
+ {"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
+ {"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
+ {"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
+ {"id_aa64pfr0_el1", A64SysReg_ID_AA64PFR0_EL1},
+ {"id_aa64pfr1_el1", A64SysReg_ID_AA64PFR1_EL1},
+ {"id_aa64dfr0_el1", A64SysReg_ID_AA64DFR0_EL1},
+ {"id_aa64dfr1_el1", A64SysReg_ID_AA64DFR1_EL1},
+ {"id_aa64afr0_el1", A64SysReg_ID_AA64AFR0_EL1},
+ {"id_aa64afr1_el1", A64SysReg_ID_AA64AFR1_EL1},
+ {"id_aa64isar0_el1", A64SysReg_ID_AA64ISAR0_EL1},
+ {"id_aa64isar1_el1", A64SysReg_ID_AA64ISAR1_EL1},
+ {"id_aa64mmfr0_el1", A64SysReg_ID_AA64MMFR0_EL1},
+ {"id_aa64mmfr1_el1", A64SysReg_ID_AA64MMFR1_EL1},
+ {"mvfr0_el1", A64SysReg_MVFR0_EL1},
+ {"mvfr1_el1", A64SysReg_MVFR1_EL1},
+ {"mvfr2_el1", A64SysReg_MVFR2_EL1},
+ {"rvbar_el1", A64SysReg_RVBAR_EL1},
+ {"rvbar_el2", A64SysReg_RVBAR_EL2},
+ {"rvbar_el3", A64SysReg_RVBAR_EL3},
+ {"isr_el1", A64SysReg_ISR_EL1},
+ {"cntpct_el0", A64SysReg_CNTPCT_EL0},
+ {"cntvct_el0", A64SysReg_CNTVCT_EL0},
+
+ // Trace registers
+ {"trcstatr", A64SysReg_TRCSTATR},
+ {"trcidr8", A64SysReg_TRCIDR8},
+ {"trcidr9", A64SysReg_TRCIDR9},
+ {"trcidr10", A64SysReg_TRCIDR10},
+ {"trcidr11", A64SysReg_TRCIDR11},
+ {"trcidr12", A64SysReg_TRCIDR12},
+ {"trcidr13", A64SysReg_TRCIDR13},
+ {"trcidr0", A64SysReg_TRCIDR0},
+ {"trcidr1", A64SysReg_TRCIDR1},
+ {"trcidr2", A64SysReg_TRCIDR2},
+ {"trcidr3", A64SysReg_TRCIDR3},
+ {"trcidr4", A64SysReg_TRCIDR4},
+ {"trcidr5", A64SysReg_TRCIDR5},
+ {"trcidr6", A64SysReg_TRCIDR6},
+ {"trcidr7", A64SysReg_TRCIDR7},
+ {"trcoslsr", A64SysReg_TRCOSLSR},
+ {"trcpdsr", A64SysReg_TRCPDSR},
+ {"trcdevaff0", A64SysReg_TRCDEVAFF0},
+ {"trcdevaff1", A64SysReg_TRCDEVAFF1},
+ {"trclsr", A64SysReg_TRCLSR},
+ {"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
+ {"trcdevarch", A64SysReg_TRCDEVARCH},
+ {"trcdevid", A64SysReg_TRCDEVID},
+ {"trcdevtype", A64SysReg_TRCDEVTYPE},
+ {"trcpidr4", A64SysReg_TRCPIDR4},
+ {"trcpidr5", A64SysReg_TRCPIDR5},
+ {"trcpidr6", A64SysReg_TRCPIDR6},
+ {"trcpidr7", A64SysReg_TRCPIDR7},
+ {"trcpidr0", A64SysReg_TRCPIDR0},
+ {"trcpidr1", A64SysReg_TRCPIDR1},
+ {"trcpidr2", A64SysReg_TRCPIDR2},
+ {"trcpidr3", A64SysReg_TRCPIDR3},
+ {"trccidr0", A64SysReg_TRCCIDR0},
+ {"trccidr1", A64SysReg_TRCCIDR1},
+ {"trccidr2", A64SysReg_TRCCIDR2},
+ {"trccidr3", A64SysReg_TRCCIDR3},
+
+ // GICv3 registers
+ {"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
+ {"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
+ {"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
+ {"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
+ {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
+ {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
+ {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
+ {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}
+};
+
+SysRegMapper AArch64_MRSMapper = {
+ .InstPairs = MRSPairs,
+ .NumInstPairs = ARR_SIZE(MRSPairs),
+};
+
+static NamedImmMapper_Mapping MSRPairs[] = {
+ {"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
+ {"oslar_el1", A64SysReg_OSLAR_EL1},
+ {"pmswinc_el0", A64SysReg_PMSWINC_EL0},
+
+ // Trace registers
+ {"trcoslar", A64SysReg_TRCOSLAR},
+ {"trclar", A64SysReg_TRCLAR},
+
+ // GICv3 registers
+ {"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
+ {"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
+ {"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
+ {"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
+ {"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
+ {"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
+};
+
+SysRegMapper AArch64_MSRMapper = {
+ .InstPairs = MSRPairs,
+ .NumInstPairs = ARR_SIZE(MSRPairs),
+};
+
+// Encoding of the immediate for logical (immediate) instructions:
+//
+// | N | imms | immr | size | R | S |
+// |---+--------+--------+------+--------------+--------------|
+// | 1 | ssssss | rrrrrr | 64 | UInt(rrrrrr) | UInt(ssssss) |
+// | 0 | 0sssss | xrrrrr | 32 | UInt(rrrrr) | UInt(sssss) |
+// | 0 | 10ssss | xxrrrr | 16 | UInt(rrrr) | UInt(ssss) |
+// | 0 | 110sss | xxxrrr | 8 | UInt(rrr) | UInt(sss) |
+// | 0 | 1110ss | xxxxrr | 4 | UInt(rr) | UInt(ss) |
+// | 0 | 11110s | xxxxxr | 2 | UInt(r) | UInt(s) |
+// | 0 | 11111x | - | | UNALLOCATED | |
+//
+// Columns 'R', 'S' and 'size' specify a "bitmask immediate" of size bits in
+// which the lower S+1 bits are ones and the remaining bits are zero, then
+// rotated right by R bits, which is then replicated across the datapath.
+//
+// + Values of 'N', 'imms' and 'immr' which do not match the above table are
+// RESERVED.
+// + If all 's' bits in the imms field are set then the instruction is
+// RESERVED.
+// + The 'x' bits in the 'immr' field are IGNORED.
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
+{
+ uint32_t N = Bits >> 12;
+ uint32_t ImmR = (Bits >> 6) & 0x3f;
+ uint32_t ImmS = Bits & 0x3f;
+
+ // N=1 encodes a 64-bit replication and is invalid for the 32-bit
+ // instructions.
+ if (RegWidth == 32 && N != 0) return false;
+
+ int Width = 0;
+ if (N == 1)
+ Width = 64;
+ else if ((ImmS & 0x20) == 0)
+ Width = 32;
+ else if ((ImmS & 0x10) == 0)
+ Width = 16;
+ else if ((ImmS & 0x08) == 0)
+ Width = 8;
+ else if ((ImmS & 0x04) == 0)
+ Width = 4;
+ else if ((ImmS & 0x02) == 0)
+ Width = 2;
+ else {
+ // ImmS is 0b11111x: UNALLOCATED
+ return false;
+ }
+
+ int Num1s = (ImmS & (Width - 1)) + 1;
+
+ // All encodings which would map to -1 (signed) are RESERVED.
+ if (Num1s == Width) return false;
+
+ int Rotation = (ImmR & (Width - 1));
+ uint64_t Mask = (1ULL << Num1s) - 1;
+ uint64_t WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1;
+ if (Rotation != 0 && Rotation != 64)
+ Mask = (Mask >> Rotation)
+ | ((Mask << (Width - Rotation)) & WidthMask);
+
+ *Imm = Mask;
+ unsigned i;
+ for (i = 1; i < RegWidth / Width; ++i) {
+ Mask <<= Width;
+ *Imm |= Mask;
+ }
+
+ return true;
+}
+
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
new file mode 100644
index 0000000..d7a4504
--- /dev/null
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -0,0 +1,863 @@
+//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the AArch64 target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_AARCH64_BASEINFO_H
+#define CS_LLVM_AARCH64_BASEINFO_H
+
+#include <ctype.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+/// Instances of this class can perform bidirectional mapping from random
+/// identifier strings to operand encodings. For example "MSR" takes a named
+/// system-register which must be encoded somehow and decoded for printing. This
+/// central location means that the information for those transformations is not
+/// duplicated and remains in sync.
+///
+/// FIXME: currently the algorithm is a completely unoptimised linear
+/// search. Obviously this could be improved, but we would probably want to work
+/// out just how often these instructions are emitted before working on it. It
+/// might even be optimal to just reorder the tables for the common instructions
+/// rather than changing the algorithm.
+typedef struct NamedImmMapper_Mapping {
+ char *Name;
+ uint32_t Value;
+} NamedImmMapper_Mapping;
+
+typedef struct NamedImmMapper {
+ NamedImmMapper_Mapping *Pairs;
+ size_t NumPairs;
+ uint32_t TooBigImm;
+} NamedImmMapper;
+
+typedef struct SysRegMapper {
+ NamedImmMapper_Mapping *SysRegPairs;
+ NamedImmMapper_Mapping *InstPairs;
+ size_t NumInstPairs;
+} SysRegMapper;
+
+extern SysRegMapper AArch64_MSRMapper;
+extern SysRegMapper AArch64_MRSMapper;
+
+extern NamedImmMapper AArch64_DBarrierMapper;
+extern NamedImmMapper AArch64_ATMapper;
+extern NamedImmMapper AArch64_DCMapper;
+extern NamedImmMapper AArch64_ICMapper;
+extern NamedImmMapper AArch64_ISBMapper;
+extern NamedImmMapper AArch64_PRFMMapper;
+extern NamedImmMapper AArch64_PStateMapper;
+extern NamedImmMapper AArch64_TLBIMapper;
+
+// // Enums corresponding to AArch64 condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum A64CC_CondCodes { // Meaning (integer) Meaning (floating-point)
+ A64CC_EQ = 0, // Equal Equal
+ A64CC_NE, // Not equal Not equal, or unordered
+ A64CC_HS, // Unsigned higher or same >, ==, or unordered
+ A64CC_LO, // Unsigned lower or same Less than
+ A64CC_MI, // Minus, negative Less than
+ A64CC_PL, // Plus, positive or zero >, ==, or unordered
+ A64CC_VS, // Overflow Unordered
+ A64CC_VC, // No overflow Ordered
+ A64CC_HI, // Unsigned higher Greater than, or unordered
+ A64CC_LS, // Unsigned lower or same Less than or equal
+ A64CC_GE, // Greater than or equal Greater than or equal
+ A64CC_LT, // Less than Less than, or unordered
+ A64CC_GT, // Signed greater than Greater than
+ A64CC_LE, // Signed less than or equal <, ==, or unordered
+ A64CC_AL, // Always (unconditional) Always (unconditional)
+ A64CC_NV, // Always (unconditional) Always (unconditional)
+ // Note the NV exists purely to disassemble 0b1111. Execution
+ // is "always".
+ A64CC_Invalid
+} A64CC_CondCodes;
+
+inline static const char *A64CondCodeToString(A64CC_CondCodes CC)
+{
+ switch (CC) {
+ default: return 0; // never reach
+ case A64CC_EQ: return "eq";
+ case A64CC_NE: return "ne";
+ case A64CC_HS: return "hs";
+ case A64CC_LO: return "lo";
+ case A64CC_MI: return "mi";
+ case A64CC_PL: return "pl";
+ case A64CC_VS: return "vs";
+ case A64CC_VC: return "vc";
+ case A64CC_HI: return "hi";
+ case A64CC_LS: return "ls";
+ case A64CC_GE: return "ge";
+ case A64CC_LT: return "lt";
+ case A64CC_GT: return "gt";
+ case A64CC_LE: return "le";
+ case A64CC_AL: return "al";
+ case A64CC_NV: return "nv";
+ }
+}
+
+enum {
+ A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2
+ A64AT_S1E1R = 0x43c0, // 01 000 0111 1000 000
+ A64AT_S1E2R = 0x63c0, // 01 100 0111 1000 000
+ A64AT_S1E3R = 0x73c0, // 01 110 0111 1000 000
+ A64AT_S1E1W = 0x43c1, // 01 000 0111 1000 001
+ A64AT_S1E2W = 0x63c1, // 01 100 0111 1000 001
+ A64AT_S1E3W = 0x73c1, // 01 110 0111 1000 001
+ A64AT_S1E0R = 0x43c2, // 01 000 0111 1000 010
+ A64AT_S1E0W = 0x43c3, // 01 000 0111 1000 011
+ A64AT_S12E1R = 0x63c4, // 01 100 0111 1000 100
+ A64AT_S12E1W = 0x63c5, // 01 100 0111 1000 101
+ A64AT_S12E0R = 0x63c6, // 01 100 0111 1000 110
+ A64AT_S12E0W = 0x63c7 // 01 100 0111 1000 111
+};
+
+enum DBValues {
+ A64DB_Invalid = -1,
+ A64DB_OSHLD = 0x1,
+ A64DB_OSHST = 0x2,
+ A64DB_OSH = 0x3,
+ A64DB_NSHLD = 0x5,
+ A64DB_NSHST = 0x6,
+ A64DB_NSH = 0x7,
+ A64DB_ISHLD = 0x9,
+ A64DB_ISHST = 0xa,
+ A64DB_ISH = 0xb,
+ A64DB_LD = 0xd,
+ A64DB_ST = 0xe,
+ A64DB_SY = 0xf
+};
+
+enum DCValues {
+ A64DC_Invalid = -1, // Op1 CRn CRm Op2
+ A64DC_ZVA = 0x5ba1, // 01 011 0111 0100 001
+ A64DC_IVAC = 0x43b1, // 01 000 0111 0110 001
+ A64DC_ISW = 0x43b2, // 01 000 0111 0110 010
+ A64DC_CVAC = 0x5bd1, // 01 011 0111 1010 001
+ A64DC_CSW = 0x43d2, // 01 000 0111 1010 010
+ A64DC_CVAU = 0x5bd9, // 01 011 0111 1011 001
+ A64DC_CIVAC = 0x5bf1, // 01 011 0111 1110 001
+ A64DC_CISW = 0x43f2 // 01 000 0111 1110 010
+};
+
+enum ICValues {
+ A64IC_Invalid = -1, // Op1 CRn CRm Op2
+ A64IC_IALLUIS = 0x0388, // 000 0111 0001 000
+ A64IC_IALLU = 0x03a8, // 000 0111 0101 000
+ A64IC_IVAU = 0x1ba9 // 011 0111 0101 001
+};
+
+enum ISBValues {
+ A64ISB_Invalid = -1,
+ A64ISB_SY = 0xf
+};
+
+enum PRFMValues {
+ A64PRFM_Invalid = -1,
+ A64PRFM_PLDL1KEEP = 0x00,
+ A64PRFM_PLDL1STRM = 0x01,
+ A64PRFM_PLDL2KEEP = 0x02,
+ A64PRFM_PLDL2STRM = 0x03,
+ A64PRFM_PLDL3KEEP = 0x04,
+ A64PRFM_PLDL3STRM = 0x05,
+ A64PRFM_PLIL1KEEP = 0x08,
+ A64PRFM_PLIL1STRM = 0x09,
+ A64PRFM_PLIL2KEEP = 0x0a,
+ A64PRFM_PLIL2STRM = 0x0b,
+ A64PRFM_PLIL3KEEP = 0x0c,
+ A64PRFM_PLIL3STRM = 0x0d,
+ A64PRFM_PSTL1KEEP = 0x10,
+ A64PRFM_PSTL1STRM = 0x11,
+ A64PRFM_PSTL2KEEP = 0x12,
+ A64PRFM_PSTL2STRM = 0x13,
+ A64PRFM_PSTL3KEEP = 0x14,
+ A64PRFM_PSTL3STRM = 0x15
+};
+
+enum PStateValues {
+ A64PState_Invalid = -1,
+ A64PState_SPSel = 0x05,
+ A64PState_DAIFSet = 0x1e,
+ A64PState_DAIFClr = 0x1f
+};
+
+typedef enum A64SE_ShiftExtSpecifiers {
+ A64SE_Invalid = -1,
+ A64SE_LSL,
+ A64SE_MSL,
+ A64SE_LSR,
+ A64SE_ASR,
+ A64SE_ROR,
+
+ A64SE_UXTB,
+ A64SE_UXTH,
+ A64SE_UXTW,
+ A64SE_UXTX,
+
+ A64SE_SXTB,
+ A64SE_SXTH,
+ A64SE_SXTW,
+ A64SE_SXTX
+} A64SE_ShiftExtSpecifiers;
+
+enum SysRegROValues {
+ A64SysReg_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
+ A64SysReg_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
+ A64SysReg_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
+ A64SysReg_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
+ A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
+ A64SysReg_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
+ A64SysReg_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
+ A64SysReg_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
+ A64SysReg_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
+ A64SysReg_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
+ A64SysReg_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
+ A64SysReg_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
+ A64SysReg_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
+ A64SysReg_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
+ A64SysReg_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
+ A64SysReg_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
+ A64SysReg_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
+ A64SysReg_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
+ A64SysReg_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
+ A64SysReg_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
+ A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
+ A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
+ A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
+ A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
+ A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
+ A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
+ A64SysReg_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
+ A64SysReg_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
+ A64SysReg_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
+ A64SysReg_ID_AA64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
+ A64SysReg_ID_AA64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
+ A64SysReg_ID_AA64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
+ A64SysReg_ID_AA64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
+ A64SysReg_ID_AA64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
+ A64SysReg_ID_AA64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
+ A64SysReg_ID_AA64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
+ A64SysReg_ID_AA64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
+ A64SysReg_ID_AA64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
+ A64SysReg_ID_AA64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
+ A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
+ A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
+ A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
+ A64SysReg_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
+ A64SysReg_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
+ A64SysReg_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
+ A64SysReg_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
+ A64SysReg_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
+ A64SysReg_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
+
+ // Trace registers
+ A64SysReg_TRCSTATR = 0x8818, // 10 001 0000 0011 000
+ A64SysReg_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
+ A64SysReg_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
+ A64SysReg_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
+ A64SysReg_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
+ A64SysReg_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
+ A64SysReg_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
+ A64SysReg_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
+ A64SysReg_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
+ A64SysReg_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
+ A64SysReg_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
+ A64SysReg_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
+ A64SysReg_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
+ A64SysReg_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
+ A64SysReg_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
+ A64SysReg_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
+ A64SysReg_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
+ A64SysReg_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
+ A64SysReg_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
+ A64SysReg_TRCLSR = 0x8bee, // 10 001 0111 1101 110
+ A64SysReg_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
+ A64SysReg_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
+ A64SysReg_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
+ A64SysReg_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
+ A64SysReg_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
+ A64SysReg_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
+ A64SysReg_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
+ A64SysReg_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
+ A64SysReg_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
+ A64SysReg_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
+ A64SysReg_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
+ A64SysReg_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
+ A64SysReg_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
+ A64SysReg_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
+ A64SysReg_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
+ A64SysReg_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
+
+ // GICv3 registers
+ A64SysReg_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
+ A64SysReg_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
+ A64SysReg_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
+ A64SysReg_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
+ A64SysReg_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
+ A64SysReg_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
+ A64SysReg_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
+ A64SysReg_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
+};
+
+enum SysRegWOValues {
+ A64SysReg_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
+ A64SysReg_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
+ A64SysReg_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
+
+ // Trace Registers
+ A64SysReg_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
+ A64SysReg_TRCLAR = 0x8be6, // 10 001 0111 1100 110
+
+ // GICv3 registers
+ A64SysReg_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
+ A64SysReg_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
+ A64SysReg_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
+ A64SysReg_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
+ A64SysReg_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
+ A64SysReg_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
+};
+
+enum SysRegValues {
+ A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2
+ A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
+ A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
+ A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
+ A64SysReg_MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
+ A64SysReg_MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
+ A64SysReg_DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
+ A64SysReg_OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
+ A64SysReg_DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
+ A64SysReg_DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
+ A64SysReg_DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
+ A64SysReg_DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
+ A64SysReg_DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
+ A64SysReg_DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
+ A64SysReg_DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
+ A64SysReg_DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
+ A64SysReg_DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
+ A64SysReg_DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
+ A64SysReg_DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
+ A64SysReg_DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
+ A64SysReg_DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
+ A64SysReg_DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
+ A64SysReg_DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
+ A64SysReg_DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
+ A64SysReg_DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
+ A64SysReg_DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
+ A64SysReg_DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
+ A64SysReg_DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
+ A64SysReg_DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
+ A64SysReg_DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
+ A64SysReg_DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
+ A64SysReg_DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
+ A64SysReg_DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
+ A64SysReg_DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
+ A64SysReg_DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
+ A64SysReg_DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
+ A64SysReg_DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
+ A64SysReg_DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
+ A64SysReg_DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
+ A64SysReg_DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
+ A64SysReg_DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
+ A64SysReg_DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
+ A64SysReg_DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
+ A64SysReg_DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
+ A64SysReg_DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
+ A64SysReg_DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
+ A64SysReg_DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
+ A64SysReg_DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
+ A64SysReg_DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
+ A64SysReg_DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
+ A64SysReg_DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
+ A64SysReg_DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
+ A64SysReg_DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
+ A64SysReg_DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
+ A64SysReg_DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
+ A64SysReg_DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
+ A64SysReg_DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
+ A64SysReg_DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
+ A64SysReg_DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
+ A64SysReg_DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
+ A64SysReg_DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
+ A64SysReg_DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
+ A64SysReg_DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
+ A64SysReg_DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
+ A64SysReg_DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
+ A64SysReg_DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
+ A64SysReg_DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
+ A64SysReg_DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
+ A64SysReg_DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
+ A64SysReg_DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
+ A64SysReg_DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
+ A64SysReg_DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
+ A64SysReg_DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
+ A64SysReg_TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
+ A64SysReg_OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
+ A64SysReg_DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
+ A64SysReg_DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
+ A64SysReg_DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
+ A64SysReg_CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
+ A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
+ A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
+ A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
+ A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
+ A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
+ A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
+ A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
+ A64SysReg_ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
+ A64SysReg_ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
+ A64SysReg_HCR_EL2 = 0xe088, // 11 100 0001 0001 000
+ A64SysReg_SCR_EL3 = 0xf088, // 11 110 0001 0001 000
+ A64SysReg_MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
+ A64SysReg_SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
+ A64SysReg_CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
+ A64SysReg_CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
+ A64SysReg_HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
+ A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
+ A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
+ A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
+ A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
+ A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
+ A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
+ A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010
+ A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010
+ A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010
+ A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
+ A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
+ A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
+ A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
+ A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
+ A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
+ A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001
+ A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001
+ A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001
+ A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000
+ A64SysReg_SP_EL1 = 0xe208, // 11 100 0100 0001 000
+ A64SysReg_SP_EL2 = 0xf208, // 11 110 0100 0001 000
+ A64SysReg_SPSel = 0xc210, // 11 000 0100 0010 000
+ A64SysReg_NZCV = 0xda10, // 11 011 0100 0010 000
+ A64SysReg_DAIF = 0xda11, // 11 011 0100 0010 001
+ A64SysReg_CurrentEL = 0xc212, // 11 000 0100 0010 010
+ A64SysReg_SPSR_irq = 0xe218, // 11 100 0100 0011 000
+ A64SysReg_SPSR_abt = 0xe219, // 11 100 0100 0011 001
+ A64SysReg_SPSR_und = 0xe21a, // 11 100 0100 0011 010
+ A64SysReg_SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
+ A64SysReg_FPCR = 0xda20, // 11 011 0100 0100 000
+ A64SysReg_FPSR = 0xda21, // 11 011 0100 0100 001
+ A64SysReg_DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
+ A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001
+ A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
+ A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
+ A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
+ A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
+ A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
+ A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
+ A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
+ A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000
+ A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000
+ A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000
+ A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
+ A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000
+ A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000
+ A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000
+ A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
+ A64SysReg_PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
+ A64SysReg_PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
+ A64SysReg_PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
+ A64SysReg_PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
+ A64SysReg_PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
+ A64SysReg_PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
+ A64SysReg_PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
+ A64SysReg_PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
+ A64SysReg_PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
+ A64SysReg_PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
+ A64SysReg_PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
+ A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
+ A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
+ A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
+ A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
+ A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
+ A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
+ A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
+ A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
+ A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
+ A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
+ A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
+ A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010
+ A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010
+ A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010
+ A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
+ A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
+ A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
+ A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
+ A64SysReg_TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
+ A64SysReg_TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
+ A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
+ A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
+ A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
+ A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
+ A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
+ A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
+ A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
+ A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
+ A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
+ A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
+ A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
+ A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
+ A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
+ A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
+ A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
+ A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
+ A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
+ A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
+ A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
+ A64SysReg_PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
+ A64SysReg_PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
+ A64SysReg_PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
+ A64SysReg_PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
+ A64SysReg_PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
+ A64SysReg_PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
+ A64SysReg_PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
+ A64SysReg_PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
+ A64SysReg_PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
+ A64SysReg_PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
+ A64SysReg_PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
+ A64SysReg_PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
+ A64SysReg_PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
+ A64SysReg_PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
+ A64SysReg_PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
+ A64SysReg_PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
+ A64SysReg_PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
+ A64SysReg_PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
+ A64SysReg_PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
+ A64SysReg_PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
+ A64SysReg_PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
+ A64SysReg_PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
+ A64SysReg_PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
+ A64SysReg_PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
+ A64SysReg_PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
+ A64SysReg_PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
+ A64SysReg_PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
+ A64SysReg_PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
+ A64SysReg_PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
+ A64SysReg_PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
+ A64SysReg_PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
+ A64SysReg_PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
+ A64SysReg_PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
+ A64SysReg_PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
+ A64SysReg_PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
+ A64SysReg_PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
+ A64SysReg_PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
+ A64SysReg_PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
+ A64SysReg_PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
+ A64SysReg_PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
+ A64SysReg_PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
+ A64SysReg_PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
+ A64SysReg_PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
+ A64SysReg_PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
+ A64SysReg_PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
+ A64SysReg_PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
+ A64SysReg_PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
+ A64SysReg_PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
+ A64SysReg_PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
+ A64SysReg_PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
+ A64SysReg_PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
+ A64SysReg_PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
+ A64SysReg_PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
+ A64SysReg_PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
+ A64SysReg_PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
+ A64SysReg_PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
+ A64SysReg_PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
+ A64SysReg_PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
+ A64SysReg_PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
+ A64SysReg_PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
+
+ // Trace registers
+ A64SysReg_TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
+ A64SysReg_TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
+ A64SysReg_TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
+ A64SysReg_TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
+ A64SysReg_TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
+ A64SysReg_TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
+ A64SysReg_TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
+ A64SysReg_TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
+ A64SysReg_TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
+ A64SysReg_TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
+ A64SysReg_TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
+ A64SysReg_TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
+ A64SysReg_TRCQCTLR = 0x8809, // 10 001 0000 0001 001
+ A64SysReg_TRCVICTLR = 0x8802, // 10 001 0000 0000 010
+ A64SysReg_TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
+ A64SysReg_TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
+ A64SysReg_TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
+ A64SysReg_TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
+ A64SysReg_TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
+ A64SysReg_TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
+ A64SysReg_TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
+ A64SysReg_TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
+ A64SysReg_TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
+ A64SysReg_TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
+ A64SysReg_TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
+ A64SysReg_TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
+ A64SysReg_TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
+ A64SysReg_TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
+ A64SysReg_TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
+ A64SysReg_TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
+ A64SysReg_TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
+ A64SysReg_TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
+ A64SysReg_TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
+ A64SysReg_TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
+ A64SysReg_TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
+ A64SysReg_TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
+ A64SysReg_TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
+ A64SysReg_TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
+ A64SysReg_TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
+ A64SysReg_TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
+ A64SysReg_TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
+ A64SysReg_TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
+ A64SysReg_TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
+ A64SysReg_TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
+ A64SysReg_TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
+ A64SysReg_TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
+ A64SysReg_TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
+ A64SysReg_TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
+ A64SysReg_TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
+ A64SysReg_TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
+ A64SysReg_TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
+ A64SysReg_TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
+ A64SysReg_TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
+ A64SysReg_TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
+ A64SysReg_TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
+ A64SysReg_TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
+ A64SysReg_TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
+ A64SysReg_TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
+ A64SysReg_TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
+ A64SysReg_TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
+ A64SysReg_TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
+ A64SysReg_TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
+ A64SysReg_TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
+ A64SysReg_TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
+ A64SysReg_TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
+ A64SysReg_TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
+ A64SysReg_TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
+ A64SysReg_TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
+ A64SysReg_TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
+ A64SysReg_TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
+ A64SysReg_TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
+ A64SysReg_TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
+ A64SysReg_TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
+ A64SysReg_TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
+ A64SysReg_TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
+ A64SysReg_TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
+ A64SysReg_TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
+ A64SysReg_TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
+ A64SysReg_TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
+ A64SysReg_TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
+ A64SysReg_TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
+ A64SysReg_TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
+ A64SysReg_TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
+ A64SysReg_TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
+ A64SysReg_TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
+ A64SysReg_TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
+ A64SysReg_TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
+ A64SysReg_TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
+ A64SysReg_TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
+ A64SysReg_TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
+ A64SysReg_TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
+ A64SysReg_TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
+ A64SysReg_TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
+ A64SysReg_TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
+ A64SysReg_TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
+ A64SysReg_TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
+ A64SysReg_TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
+ A64SysReg_TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
+ A64SysReg_TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
+ A64SysReg_TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
+ A64SysReg_TRCPDCR = 0x88a4, // 10 001 0001 0100 100
+ A64SysReg_TRCACVR0 = 0x8900, // 10 001 0010 0000 000
+ A64SysReg_TRCACVR1 = 0x8910, // 10 001 0010 0010 000
+ A64SysReg_TRCACVR2 = 0x8920, // 10 001 0010 0100 000
+ A64SysReg_TRCACVR3 = 0x8930, // 10 001 0010 0110 000
+ A64SysReg_TRCACVR4 = 0x8940, // 10 001 0010 1000 000
+ A64SysReg_TRCACVR5 = 0x8950, // 10 001 0010 1010 000
+ A64SysReg_TRCACVR6 = 0x8960, // 10 001 0010 1100 000
+ A64SysReg_TRCACVR7 = 0x8970, // 10 001 0010 1110 000
+ A64SysReg_TRCACVR8 = 0x8901, // 10 001 0010 0000 001
+ A64SysReg_TRCACVR9 = 0x8911, // 10 001 0010 0010 001
+ A64SysReg_TRCACVR10 = 0x8921, // 10 001 0010 0100 001
+ A64SysReg_TRCACVR11 = 0x8931, // 10 001 0010 0110 001
+ A64SysReg_TRCACVR12 = 0x8941, // 10 001 0010 1000 001
+ A64SysReg_TRCACVR13 = 0x8951, // 10 001 0010 1010 001
+ A64SysReg_TRCACVR14 = 0x8961, // 10 001 0010 1100 001
+ A64SysReg_TRCACVR15 = 0x8971, // 10 001 0010 1110 001
+ A64SysReg_TRCACATR0 = 0x8902, // 10 001 0010 0000 010
+ A64SysReg_TRCACATR1 = 0x8912, // 10 001 0010 0010 010
+ A64SysReg_TRCACATR2 = 0x8922, // 10 001 0010 0100 010
+ A64SysReg_TRCACATR3 = 0x8932, // 10 001 0010 0110 010
+ A64SysReg_TRCACATR4 = 0x8942, // 10 001 0010 1000 010
+ A64SysReg_TRCACATR5 = 0x8952, // 10 001 0010 1010 010
+ A64SysReg_TRCACATR6 = 0x8962, // 10 001 0010 1100 010
+ A64SysReg_TRCACATR7 = 0x8972, // 10 001 0010 1110 010
+ A64SysReg_TRCACATR8 = 0x8903, // 10 001 0010 0000 011
+ A64SysReg_TRCACATR9 = 0x8913, // 10 001 0010 0010 011
+ A64SysReg_TRCACATR10 = 0x8923, // 10 001 0010 0100 011
+ A64SysReg_TRCACATR11 = 0x8933, // 10 001 0010 0110 011
+ A64SysReg_TRCACATR12 = 0x8943, // 10 001 0010 1000 011
+ A64SysReg_TRCACATR13 = 0x8953, // 10 001 0010 1010 011
+ A64SysReg_TRCACATR14 = 0x8963, // 10 001 0010 1100 011
+ A64SysReg_TRCACATR15 = 0x8973, // 10 001 0010 1110 011
+ A64SysReg_TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
+ A64SysReg_TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
+ A64SysReg_TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
+ A64SysReg_TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
+ A64SysReg_TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
+ A64SysReg_TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
+ A64SysReg_TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
+ A64SysReg_TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
+ A64SysReg_TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
+ A64SysReg_TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
+ A64SysReg_TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
+ A64SysReg_TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
+ A64SysReg_TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
+ A64SysReg_TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
+ A64SysReg_TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
+ A64SysReg_TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
+ A64SysReg_TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
+ A64SysReg_TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
+ A64SysReg_TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
+ A64SysReg_TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
+ A64SysReg_TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
+ A64SysReg_TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
+ A64SysReg_TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
+ A64SysReg_TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
+ A64SysReg_TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
+ A64SysReg_TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
+ A64SysReg_TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
+ A64SysReg_TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
+ A64SysReg_TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
+ A64SysReg_TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
+ A64SysReg_TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
+ A64SysReg_TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
+ A64SysReg_TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
+ A64SysReg_TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
+ A64SysReg_TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
+ A64SysReg_TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
+ A64SysReg_TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
+ A64SysReg_TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
+ A64SysReg_TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
+
+ // GICv3 registers
+ A64SysReg_ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
+ A64SysReg_ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
+ A64SysReg_ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
+ A64SysReg_ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
+ A64SysReg_ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
+ A64SysReg_ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
+ A64SysReg_ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
+ A64SysReg_ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
+ A64SysReg_ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
+ A64SysReg_ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
+ A64SysReg_ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
+ A64SysReg_ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
+ A64SysReg_ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
+ A64SysReg_ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
+ A64SysReg_ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
+ A64SysReg_ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
+ A64SysReg_ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
+ A64SysReg_ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
+ A64SysReg_ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
+ A64SysReg_ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
+ A64SysReg_ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
+ A64SysReg_ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
+ A64SysReg_ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
+ A64SysReg_ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
+ A64SysReg_ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
+ A64SysReg_ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
+ A64SysReg_ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
+ A64SysReg_ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
+ A64SysReg_ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
+ A64SysReg_ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
+ A64SysReg_ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
+ A64SysReg_ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
+ A64SysReg_ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
+ A64SysReg_ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
+ A64SysReg_ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
+ A64SysReg_ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
+ A64SysReg_ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
+ A64SysReg_ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
+ A64SysReg_ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
+ A64SysReg_ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
+ A64SysReg_ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
+ A64SysReg_ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
+ A64SysReg_ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
+ A64SysReg_ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
+ A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
+ A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
+ A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
+ A64SysReg_ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111
+};
+
+enum TLBIValues {
+ A64TLBI_Invalid = -1, // Op0 Op1 CRn CRm Op2
+ A64TLBI_IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
+ A64TLBI_IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
+ A64TLBI_VMALLE1IS = 0x4418, // 01 000 1000 0011 000
+ A64TLBI_ALLE2IS = 0x6418, // 01 100 1000 0011 000
+ A64TLBI_ALLE3IS = 0x7418, // 01 110 1000 0011 000
+ A64TLBI_VAE1IS = 0x4419, // 01 000 1000 0011 001
+ A64TLBI_VAE2IS = 0x6419, // 01 100 1000 0011 001
+ A64TLBI_VAE3IS = 0x7419, // 01 110 1000 0011 001
+ A64TLBI_ASIDE1IS = 0x441a, // 01 000 1000 0011 010
+ A64TLBI_VAAE1IS = 0x441b, // 01 000 1000 0011 011
+ A64TLBI_ALLE1IS = 0x641c, // 01 100 1000 0011 100
+ A64TLBI_VALE1IS = 0x441d, // 01 000 1000 0011 101
+ A64TLBI_VALE2IS = 0x641d, // 01 100 1000 0011 101
+ A64TLBI_VALE3IS = 0x741d, // 01 110 1000 0011 101
+ A64TLBI_VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
+ A64TLBI_VAALE1IS = 0x441f, // 01 000 1000 0011 111
+ A64TLBI_IPAS2E1 = 0x6421, // 01 100 1000 0100 001
+ A64TLBI_IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
+ A64TLBI_VMALLE1 = 0x4438, // 01 000 1000 0111 000
+ A64TLBI_ALLE2 = 0x6438, // 01 100 1000 0111 000
+ A64TLBI_ALLE3 = 0x7438, // 01 110 1000 0111 000
+ A64TLBI_VAE1 = 0x4439, // 01 000 1000 0111 001
+ A64TLBI_VAE2 = 0x6439, // 01 100 1000 0111 001
+ A64TLBI_VAE3 = 0x7439, // 01 110 1000 0111 001
+ A64TLBI_ASIDE1 = 0x443a, // 01 000 1000 0111 010
+ A64TLBI_VAAE1 = 0x443b, // 01 000 1000 0111 011
+ A64TLBI_ALLE1 = 0x643c, // 01 100 1000 0111 100
+ A64TLBI_VALE1 = 0x443d, // 01 000 1000 0111 101
+ A64TLBI_VALE2 = 0x643d, // 01 100 1000 0111 101
+ A64TLBI_VALE3 = 0x743d, // 01 110 1000 0111 101
+ A64TLBI_VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
+ A64TLBI_VAALE1 = 0x443f // 01 000 1000 0111 111
+};
+
+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
+
+char *NamedImmMapper_toString(NamedImmMapper *N, uint32_t Value, bool *Valid);
+
+uint32_t NamedImmMapper_fromString(NamedImmMapper *N, char *Name, bool *Valid);
+
+bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value);
+
+char *SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid);
+
+#endif
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
new file mode 100644
index 0000000..97a2479
--- /dev/null
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -0,0 +1,879 @@
+//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the functions necessary to decode AArch64 instruction
+// bitpatterns into MCInsts (with the help of TableGenerated information from
+// the instruction definitions).
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h> // DEBUG
+#include <stdlib.h>
+
+#include "../../cs_priv.h"
+
+#include "../../SubtargetFeature.h"
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+
+#include "AArch64BaseInfo.h"
+
+// Forward-declarations used in the auto-generated files.
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus
+DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus
+DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address,
+ void *Decoder);
+static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
+ unsigned OptionHiS,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeBitfield32ImmOperand(MCInst *Inst,
+ unsigned Imm6Bits,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeCVT32FixedPosOperand(MCInst *Inst,
+ unsigned Imm6Bits,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeFPZeroOperand(MCInst *Inst,
+ unsigned RmBits,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeShiftRightImm8(MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder);
+static DecodeStatus DecodeShiftRightImm16(MCInst *Inst, unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+static DecodeStatus DecodeShiftRightImm32(MCInst *Inst, unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+static DecodeStatus DecodeShiftRightImm64(MCInst *Inst, unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
+ unsigned FullImm,
+ uint64_t Address,
+ void *Decoder, int RegWidth);
+
+static DecodeStatus DecodeLogicalImmOperand(MCInst *Inst,
+ unsigned Bits,
+ uint64_t Address,
+ void *Decoder, int RegWidth);
+
+static DecodeStatus DecodeRegExtendOperand(MCInst *Inst,
+ unsigned ShiftAmount,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus
+DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
+ uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf);
+
+static DecodeStatus Decode32BitShiftOperand(MCInst *Inst,
+ unsigned ShiftAmount,
+ uint64_t Address,
+ void *Decoder);
+static DecodeStatus DecodeBitfieldInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeLDSTPairInstruction(MCInst *Inst,
+ unsigned Insn,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeLoadPairExclusiveInstruction(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeNamedImmOperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder, NamedImmMapper *N);
+
+static DecodeStatus
+DecodeSysRegOperand(SysRegMapper *InstMapper,
+ MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMRSOperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+
+static DecodeStatus DecodeMSROperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+
+
+static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder);
+
+
+static bool Check(DecodeStatus *Out, DecodeStatus In);
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AArch64GenSubtargetInfo.inc"
+
+#define GET_SUBTARGETINFO_MC_DESC
+#include "AArch64GenSubtargetInfo.inc"
+
+// Hacky: enable all features for disassembler
+static uint64_t AArch64_getFeatureBits(void)
+{
+ int i;
+ uint64_t Bits = 0;
+ for (i = 0; i < sizeof(AArch64FeatureKV)/sizeof(AArch64FeatureKV[0]); i++) {
+ Bits |= AArch64FeatureKV[i].Value;
+ }
+
+ return Bits;
+}
+
+#include "AArch64GenDisassemblerTables.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+#define GET_REGINFO_ENUM
+#include "AArch64GenRegisterInfo.inc"
+
+static bool Check(DecodeStatus *Out, DecodeStatus In)
+{
+ switch (In) {
+ case MCDisassembler_Success:
+ // Out stays the same.
+ return true;
+ case MCDisassembler_SoftFail:
+ *Out = In;
+ return true;
+ case MCDisassembler_Fail:
+ *Out = In;
+ return false;
+ default:
+ return false; // never reach
+ }
+}
+
+#define GET_REGINFO_MC_DESC
+#include "AArch64GenRegisterInfo.inc"
+void AArch64_init(MCRegisterInfo *MRI)
+{
+ /*
+ RI->InitMCRegisterInfo(AArch64RegDesc, 228,
+ RA, PC,
+ AArch64MCRegisterClasses, 15,
+ AArch64RegUnitRoots, 66,
+ AArch64RegDiffLists,
+ AArch64RegStrings,
+ AArch64SubRegIdxLists, 6,
+ AArch64SubRegIdxRanges, AArch64RegEncodingTable);
+ */
+
+ MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 228,
+ 0, 0,
+ AArch64MCRegisterClasses, 15,
+ 0, 0,
+ AArch64RegDiffLists,
+ 0,
+ AArch64SubRegIdxLists, 6,
+ 0);
+}
+
+
+static DecodeStatus _getInstruction(MCInst *MI,
+ unsigned char *code, uint64_t code_len,
+ uint16_t *Size,
+ uint64_t Address, MCRegisterInfo *MRI)
+{
+ if (code_len < 4) {
+ // not enough data
+ *Size = 0;
+ return MCDisassembler_Fail;
+ }
+
+ // Encoded as a small-endian 32-bit word in the stream.
+ uint32_t insn = (code[3] << 24) | (code[2] << 16) |
+ (code[1] << 8) | (code[0] << 0);
+
+ //printf("insn: %u\n", insn);
+ // Calling the auto-generated decoder function.
+ DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, MRI);
+ //printf("result: %u\n", result);
+ if (result != MCDisassembler_Fail) {
+ *Size = 4;
+ return result;
+ }
+
+ MCInst_clear(MI);
+ *Size = 0;
+ return MCDisassembler_Fail;
+}
+
+bool AArch64_getInstruction(csh ud, char *code, uint64_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info)
+{
+ DecodeStatus status = _getInstruction(instr,
+ (unsigned char *)code, code_len,
+ size,
+ address, (MCRegisterInfo *)info);
+
+ return status == MCDisassembler_Success;
+}
+
+static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+ MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+ return rc->RegsBegin[RegNo];
+}
+
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address,
+ void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+
+static DecodeStatus
+DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ uint16_t Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
+ unsigned OptionHiS,
+ uint64_t Address,
+ void *Decoder)
+{
+ // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
+ // S}. Hence we want to check bit 1.
+ if (!(OptionHiS & 2))
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(OptionHiS));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitfield32ImmOperand(MCInst *Inst,
+ unsigned Imm6Bits,
+ uint64_t Address,
+ void *Decoder)
+{
+ // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
+ // between 0 and 31.
+ if (Imm6Bits > 31)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Imm6Bits));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCVT32FixedPosOperand(MCInst *Inst,
+ unsigned Imm6Bits,
+ uint64_t Address,
+ void *Decoder)
+{
+ // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
+ if (Imm6Bits < 32)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Imm6Bits));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFPZeroOperand(MCInst *Inst,
+ unsigned RmBits, uint64_t Address, void *Decoder)
+{
+ // Any bits are valid in the instruction (they're architecturally ignored),
+ // but a code generator should insert 0.
+ MCInst_addOperand(Inst, MCOperand_CreateImm(0));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm8(MCInst *Inst,
+ unsigned Val, uint64_t Address, void *Decoder)
+{
+ MCInst_addOperand(Inst, MCOperand_CreateImm(8 - Val));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm16(MCInst *Inst,
+ unsigned Val, uint64_t Address, void *Decoder)
+{
+ MCInst_addOperand(Inst, MCOperand_CreateImm(16 - Val));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm32(MCInst *Inst,
+ unsigned Val, uint64_t Address, void *Decoder)
+{
+ MCInst_addOperand(Inst, MCOperand_CreateImm(32 - Val));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeShiftRightImm64(MCInst *Inst,
+ unsigned Val, uint64_t Address, void *Decoder)
+{
+ MCInst_addOperand(Inst, MCOperand_CreateImm(64 - Val));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
+ unsigned FullImm,
+ uint64_t Address,
+ void *Decoder, int RegWidth)
+{
+ unsigned Imm16 = FullImm & 0xffff;
+ unsigned Shift = FullImm >> 16;
+
+ if (RegWidth == 32 && Shift > 1) return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Imm16));
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Shift));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLogicalImmOperand(MCInst *Inst,
+ unsigned Bits,
+ uint64_t Address,
+ void *Decoder, int RegWidth)
+{
+ uint64_t Imm;
+ if (!A64Imms_isLogicalImmBits(RegWidth, Bits, &Imm))
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Bits));
+ return MCDisassembler_Success;
+}
+
+
+static DecodeStatus DecodeRegExtendOperand(MCInst *Inst,
+ unsigned ShiftAmount,
+ uint64_t Address,
+ void *Decoder)
+{
+ // Only values 0-4 are valid for this 3-bit field
+ if (ShiftAmount > 4)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode32BitShiftOperand(MCInst *Inst,
+ unsigned ShiftAmount,
+ uint64_t Address,
+ void *Decoder)
+{
+ // Only values below 32 are valid for a 32-bit register
+ if (ShiftAmount > 31)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitfieldInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address,
+ void *Decoder)
+{
+ unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+ unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+ unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
+ unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
+ unsigned SF = fieldFromInstruction(Insn, 31, 1);
+
+ // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
+ // out assertions that it thinks should never be hit.
+ enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
+ Opc = (enum OpcTypes)fieldFromInstruction(Insn, 29, 2);
+
+ if (!SF) {
+ // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
+ if (ImmR > 31 || ImmS > 31)
+ return MCDisassembler_Fail;
+ }
+
+ if (SF) {
+ DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+ // BFM MCInsts use Rd as a source too.
+ if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
+ } else {
+ DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
+ // BFM MCInsts use Rd as a source too.
+ if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
+ DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+ // ASR and LSR have more specific patterns so they won't get here:
+ //assert(!(ImmS == 31 && !SF && Opc != BFM)
+ // && "shift should have used auto decode");
+ //assert(!(ImmS == 63 && SF && Opc != BFM)
+ // && "shift should have used auto decode");
+
+ // Extension instructions similarly:
+ if (Opc == SBFM && ImmR == 0) {
+ //assert((ImmS != 7 && ImmS != 15) && "extension got here");
+ //assert((ImmS != 31 || SF == 0) && "extension got here");
+ } else if (Opc == UBFM && ImmR == 0) {
+ //assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
+ }
+
+ if (Opc == UBFM) {
+ // It might be a LSL instruction, which actually takes the shift amount
+ // itself as an MCInst operand.
+ if (SF && (ImmS + 1) % 64 == ImmR) {
+ MCInst_setOpcode(Inst, AArch64_LSLxxi);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(63 - ImmS));
+ return MCDisassembler_Success;
+ } else if (!SF && (ImmS + 1) % 32 == ImmR) {
+ MCInst_setOpcode(Inst, AArch64_LSLwwi);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(31 - ImmS));
+ return MCDisassembler_Success;
+ }
+ }
+
+ // Otherwise it's definitely either an extract or an insert depending on which
+ // of ImmR or ImmS is larger.
+ unsigned ExtractOp = 0, InsertOp = 0;
+ switch (Opc) {
+ default: break; // never reach
+ case SBFM:
+ ExtractOp = SF ? AArch64_SBFXxxii : AArch64_SBFXwwii;
+ InsertOp = SF ? AArch64_SBFIZxxii : AArch64_SBFIZwwii;
+ break;
+ case BFM:
+ ExtractOp = SF ? AArch64_BFXILxxii : AArch64_BFXILwwii;
+ InsertOp = SF ? AArch64_BFIxxii : AArch64_BFIwwii;
+ break;
+ case UBFM:
+ ExtractOp = SF ? AArch64_UBFXxxii : AArch64_UBFXwwii;
+ InsertOp = SF ? AArch64_UBFIZxxii : AArch64_UBFIZwwii;
+ break;
+ }
+
+ // Otherwise it's a boring insert or extract
+ MCInst_addOperand(Inst, MCOperand_CreateImm(ImmR));
+ MCInst_addOperand(Inst, MCOperand_CreateImm(ImmS));
+
+
+ if (ImmS < ImmR)
+ MCInst_setOpcode(Inst, InsertOp);
+ else
+ MCInst_setOpcode(Inst, ExtractOp);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address,
+ void *Decoder)
+{
+ // This decoder exists to add the dummy Lane operand to the MCInst, which must
+ // be 1 in assembly but has no other real manifestation.
+ unsigned Rd = fieldFromInstruction(Insn, 0, 5);
+ unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+ unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
+
+ if (IsToVec) {
+ DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
+ } else {
+ DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
+ DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+ // Add the lane
+ MCInst_addOperand(Inst, MCOperand_CreateImm(1));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLDSTPairInstruction(MCInst *Inst,
+ unsigned Insn,
+ uint64_t Address,
+ void *Decoder)
+{
+ DecodeStatus Result = MCDisassembler_Success;
+ unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+ unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+ unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
+ unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
+ unsigned L = fieldFromInstruction(Insn, 22, 1);
+ unsigned V = fieldFromInstruction(Insn, 26, 1);
+ unsigned Opc = fieldFromInstruction(Insn, 30, 2);
+
+ // Not an official name, but it turns out that bit 23 distinguishes indexed
+ // from non-indexed operations.
+ unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
+
+ if (Indexed && L == 0) {
+ // The MCInst for an indexed store has an out operand and 4 ins:
+ // Rn_wb, Rt, Rt2, Rn, Imm
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+ // You shouldn't load to the same register twice in an instruction...
+ if (L && Rt == Rt2)
+ Result = MCDisassembler_SoftFail;
+
+ // ... or do any operation that writes-back to a transfer register. But note
+ // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
+ if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
+ Result = MCDisassembler_SoftFail;
+
+ // Exactly how we decode the MCInst's registers depends on the Opc and V
+ // fields of the instruction. These also obviously determine the size of the
+ // operation so we can fill in that information while we're at it.
+ if (V) {
+ // The instruction operates on the FP/SIMD registers
+ switch (Opc) {
+ default: return MCDisassembler_Fail;
+ case 0:
+ DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ case 1:
+ DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ case 2:
+ DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ }
+ } else {
+ switch (Opc) {
+ default: return MCDisassembler_Fail;
+ case 0:
+ DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ case 1:
+ //assert(L && "unexpected \"store signed\" attempt");
+ DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ case 2:
+ DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
+ break;
+ }
+ }
+
+ if (Indexed && L == 1) {
+ // The MCInst for an indexed load has 3 out operands and an 3 ins:
+ // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(SImm7));
+
+ return Result;
+}
+
+static DecodeStatus DecodeLoadPairExclusiveInstruction(MCInst *Inst,
+ uint32_t Val,
+ uint64_t Address,
+ void *Decoder)
+{
+ unsigned Rt = fieldFromInstruction(Val, 0, 5);
+ unsigned Rn = fieldFromInstruction(Val, 5, 5);
+ unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
+ unsigned MemSize = fieldFromInstruction(Val, 30, 2);
+
+ DecodeStatus S = MCDisassembler_Success;
+ if (Rt == Rt2) S = MCDisassembler_SoftFail;
+
+ switch (MemSize) {
+ case 2:
+ if (!Check(&S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler_Fail;
+ if (!Check(&S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler_Fail;
+ break;
+ case 3:
+ if (!Check(&S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
+ return MCDisassembler_Fail;
+ if (!Check(&S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
+ return MCDisassembler_Fail;
+ break;
+ default:
+ break; // never reach
+ }
+
+ if (!Check(&S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
+ return MCDisassembler_Fail;
+
+ return S;
+}
+
+static DecodeStatus DecodeNamedImmOperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder, NamedImmMapper *N)
+{
+ bool ValidNamed;
+
+ NamedImmMapper_toString(N, Val, &ValidNamed);
+ if (ValidNamed || NamedImmMapper_validImm(N, Val)) {
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+ return MCDisassembler_Success;
+ }
+
+ return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeSysRegOperand(SysRegMapper *Mapper,
+ MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder)
+{
+ bool ValidNamed;
+ char *str = SysRegMapper_toString(Mapper, Val, &ValidNamed);
+ free(str);
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
+
+ return ValidNamed ? MCDisassembler_Success : MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeMRSOperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder)
+{
+ return DecodeSysRegOperand(&AArch64_MRSMapper, Inst, Val, Address, Decoder);
+}
+
+static DecodeStatus DecodeMSROperand(MCInst *Inst,
+ unsigned Val,
+ uint64_t Address,
+ void *Decoder)
+{
+ return DecodeSysRegOperand(&AArch64_MSRMapper, Inst, Val, Address, Decoder);
+}
+
+static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
+ unsigned Insn,
+ uint64_t Address,
+ void *Decoder)
+{
+ unsigned Rt = fieldFromInstruction(Insn, 0, 5);
+ unsigned Rn = fieldFromInstruction(Insn, 5, 5);
+ unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
+
+ unsigned Opc = fieldFromInstruction(Insn, 22, 2);
+ unsigned V = fieldFromInstruction(Insn, 26, 1);
+ unsigned Size = fieldFromInstruction(Insn, 30, 2);
+
+ if (Opc == 0 || (V == 1 && Opc == 2)) {
+ // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+ if (V == 0 && (Opc == 2 || Size == 3)) {
+ DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
+ } else if (V == 0) {
+ DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
+ } else if (V == 1 && (Opc & 2)) {
+ DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
+ } else {
+ switch (Size) {
+ case 0:
+ DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
+ break;
+ case 1:
+ DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
+ break;
+ case 2:
+ DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
+ break;
+ case 3:
+ DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
+ break;
+ }
+ }
+
+ if (Opc != 0 && (V != 1 || Opc != 2)) {
+ // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+ }
+
+ DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Imm9));
+
+ // N.b. The official documentation says undpredictable if Rt == Rn, but this
+ // takes place at the architectural rather than encoding level:
+ //
+ // "STR xzr, [sp], #4" is perfectly valid.
+ if (V == 0 && Rt == Rn && Rn != 31)
+ return MCDisassembler_SoftFail;
+ else
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus
+DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
+ uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf)
+{
+ bool IsLSL = false;
+ if (Ext == A64SE_LSL)
+ IsLSL = true;
+ else if (Ext != A64SE_MSL)
+ return MCDisassembler_Fail;
+
+ // MSL and LSLH accepts encoded shift amount 0 or 1.
+ if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
+ return MCDisassembler_Fail;
+
+ // LSL accepts encoded shift amount 0, 1, 2 or 3.
+ if (IsLSL && ShiftAmount > 3)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
+ return MCDisassembler_Success;
+}
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
new file mode 100644
index 0000000..b1e0767
--- /dev/null
+++ b/arch/AArch64/AArch64Disassembler.h
@@ -0,0 +1,19 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef __SB_AARCH64DISASSEMBLER_H
+#define __SB_AARCH64DISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void AArch64_init(MCRegisterInfo *MRI);
+
+bool AArch64_getInstruction(csh ud, char *code, uint64_t code_len,
+ MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
new file mode 100644
index 0000000..8987188
--- /dev/null
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -0,0 +1,7821 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void AArch64InstPrinter_printInstruction(MCInst *MI, SStream *O)
+{
+ static uint32_t OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // PROLOG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 2407U, // DBG_VALUE
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 2400U, // BUNDLE
+ 2417U, // LIFETIME_START
+ 2387U, // LIFETIME_END
+ 5845U, // ADCSwww
+ 5845U, // ADCSxxx
+ 4664U, // ADCwww
+ 4664U, // ADCxxx
+ 1108418751U, // ADDHN2vvv_16b8h
+ 1142038719U, // ADDHN2vvv_4s2d
+ 1175658687U, // ADDHN2vvv_8h4s
+ 2216961313U, // ADDHNvvv_2s2d
+ 2250581281U, // ADDHNvvv_4h4s
+ 2183537953U, // ADDHNvvv_8b8h
+ 2283873683U, // ADDP_16B
+ 2217158035U, // ADDP_2D
+ 2317624723U, // ADDP_2S
+ 2351244691U, // ADDP_4H
+ 2250384787U, // ADDP_4S
+ 2384864659U, // ADDP_8B
+ 2183341459U, // ADDP_8H
+ 270539040U, // ADDPvv_D_2D
+ 5857U, // ADDSwww_asr
+ 5857U, // ADDSwww_lsl
+ 5857U, // ADDSwww_lsr
+ 5857U, // ADDSwww_sxtb
+ 5857U, // ADDSwww_sxth
+ 5857U, // ADDSwww_sxtw
+ 5857U, // ADDSwww_sxtx
+ 5857U, // ADDSwww_uxtb
+ 5857U, // ADDSwww_uxth
+ 5857U, // ADDSwww_uxtw
+ 5857U, // ADDSwww_uxtx
+ 5857U, // ADDSxxw_sxtb
+ 5857U, // ADDSxxw_sxth
+ 5857U, // ADDSxxw_sxtw
+ 5857U, // ADDSxxw_uxtb
+ 5857U, // ADDSxxw_uxth
+ 5857U, // ADDSxxw_uxtw
+ 5857U, // ADDSxxx_asr
+ 5857U, // ADDSxxx_lsl
+ 5857U, // ADDSxxx_lsr
+ 5857U, // ADDSxxx_sxtx
+ 5857U, // ADDSxxx_uxtx
+ 6346U, // ADDddd
+ 2283872875U, // ADDvvv_16B
+ 2217157227U, // ADDvvv_2D
+ 2317623915U, // ADDvvv_2S
+ 2351243883U, // ADDvvv_4H
+ 2250383979U, // ADDvvv_4S
+ 2384863851U, // ADDvvv_8B
+ 2183340651U, // ADDvvv_8H
+ 3221231329U, // ADDwwi_lsl0_S
+ 3152154U, // ADDwwi_lsl0_cmp
+ 3221230187U, // ADDwwi_lsl0_s
+ 5857U, // ADDwwi_lsl12_S
+ 4200730U, // ADDwwi_lsl12_cmp
+ 4715U, // ADDwwi_lsl12_s
+ 4715U, // ADDwww_asr
+ 4715U, // ADDwww_lsl
+ 4715U, // ADDwww_lsr
+ 4715U, // ADDwww_sxtb
+ 4715U, // ADDwww_sxth
+ 4715U, // ADDwww_sxtw
+ 4715U, // ADDwww_sxtx
+ 4715U, // ADDwww_uxtb
+ 4715U, // ADDwww_uxth
+ 4715U, // ADDwww_uxtw
+ 4715U, // ADDwww_uxtx
+ 3221231329U, // ADDxxi_lsl0_S
+ 3152154U, // ADDxxi_lsl0_cmp
+ 3221230187U, // ADDxxi_lsl0_s
+ 5857U, // ADDxxi_lsl12_S
+ 4200730U, // ADDxxi_lsl12_cmp
+ 4715U, // ADDxxi_lsl12_s
+ 4715U, // ADDxxw_sxtb
+ 4715U, // ADDxxw_sxth
+ 4715U, // ADDxxw_sxtw
+ 4715U, // ADDxxw_uxtb
+ 4715U, // ADDxxw_uxth
+ 4715U, // ADDxxw_uxtw
+ 4715U, // ADDxxx_asr
+ 4715U, // ADDxxx_lsl
+ 4715U, // ADDxxx_lsr
+ 4715U, // ADDxxx_sxtx
+ 4715U, // ADDxxx_uxtx
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 5248478U, // ADRPxi
+ 6297137U, // ADRxi
+ 1073747687U, // ANDSwwi
+ 5863U, // ANDSwww_asr
+ 5863U, // ANDSwww_lsl
+ 5863U, // ANDSwww_lsr
+ 5863U, // ANDSwww_ror
+ 2147489511U, // ANDSxxi
+ 5863U, // ANDSxxx_asr
+ 5863U, // ANDSxxx_lsl
+ 5863U, // ANDSxxx_lsr
+ 5863U, // ANDSxxx_ror
+ 2283872939U, // ANDvvv_16B
+ 2384863915U, // ANDvvv_8B
+ 1073746603U, // ANDwwi
+ 4779U, // ANDwww_asr
+ 4779U, // ANDwww_lsl
+ 4779U, // ANDwww_lsr
+ 4779U, // ANDwww_ror
+ 2147488427U, // ANDxxi
+ 4779U, // ANDxxx_asr
+ 4779U, // ANDxxx_lsl
+ 4779U, // ANDxxx_lsr
+ 4779U, // ANDxxx_ror
+ 5743U, // ASRVwww
+ 5743U, // ASRVxxx
+ 5743U, // ASRwwi
+ 5743U, // ASRxxi
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_MAX_I16
+ 0U, // ATOMIC_LOAD_MAX_I32
+ 0U, // ATOMIC_LOAD_MAX_I64
+ 0U, // ATOMIC_LOAD_MAX_I8
+ 0U, // ATOMIC_LOAD_MIN_I16
+ 0U, // ATOMIC_LOAD_MIN_I32
+ 0U, // ATOMIC_LOAD_MIN_I64
+ 0U, // ATOMIC_LOAD_MIN_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_UMAX_I16
+ 0U, // ATOMIC_LOAD_UMAX_I32
+ 0U, // ATOMIC_LOAD_UMAX_I64
+ 0U, // ATOMIC_LOAD_UMAX_I8
+ 0U, // ATOMIC_LOAD_UMIN_I16
+ 0U, // ATOMIC_LOAD_UMIN_I32
+ 0U, // ATOMIC_LOAD_UMIN_I64
+ 0U, // ATOMIC_LOAD_UMIN_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I8
+ 14142U, // ATix
+ 3228570531U, // BFIwwii
+ 7345059U, // BFIxxii
+ 1081087208U, // BFMwwii
+ 1081087208U, // BFMxxii
+ 1081087103U, // BFXILwwii
+ 1081087103U, // BFXILxxii
+ 5851U, // BICSwww_asr
+ 5851U, // BICSwww_lsl
+ 5851U, // BICSwww_lsr
+ 5851U, // BICSwww_ror
+ 5851U, // BICSxxx_asr
+ 5851U, // BICSxxx_lsl
+ 5851U, // BICSxxx_lsr
+ 5851U, // BICSxxx_ror
+ 310651075U, // BICvi_lsl_2S
+ 344271043U, // BICvi_lsl_4H
+ 310520003U, // BICvi_lsl_4S
+ 344139971U, // BICvi_lsl_8H
+ 2283872829U, // BICvvv_16B
+ 2384863805U, // BICvvv_8B
+ 4669U, // BICwww_asr
+ 4669U, // BICwww_lsl
+ 4669U, // BICwww_lsr
+ 4669U, // BICwww_ror
+ 4669U, // BICxxx_asr
+ 4669U, // BICxxx_lsl
+ 4669U, // BICxxx_lsr
+ 4669U, // BICxxx_ror
+ 1209082580U, // BIFvvv_16B
+ 1310073556U, // BIFvvv_8B
+ 1209083734U, // BITvvv_16B
+ 1310074710U, // BITvvv_8B
+ 530005U, // BLRx
+ 17402U, // BLimm
+ 529350U, // BRKi
+ 529965U, // BRx
+ 1209083058U, // BSLvvv_16B
+ 1310074034U, // BSLvvv_8B
+ 22864U, // Bcc
+ 16752U, // Bimm
+ 9443476U, // CBNZw
+ 9443476U, // CBNZx
+ 9443447U, // CBZw
+ 9443447U, // CBZx
+ 5434U, // CCMNwi
+ 5434U, // CCMNww
+ 5434U, // CCMNxi
+ 5434U, // CCMNxx
+ 5535U, // CCMPwi
+ 5535U, // CCMPww
+ 5535U, // CCMPxi
+ 5535U, // CCMPxx
+ 530517U, // CLREXi
+ 369104627U, // CLSww
+ 369104627U, // CLSxx
+ 369105039U, // CLZww
+ 369105039U, // CLZxx
+ 2283873825U, // CMEQvvi_16B
+ 2217158177U, // CMEQvvi_2D
+ 2317624865U, // CMEQvvi_2S
+ 2351244833U, // CMEQvvi_4H
+ 2250384929U, // CMEQvvi_4S
+ 2384864801U, // CMEQvvi_8B
+ 2183341601U, // CMEQvvi_8H
+ 2283873825U, // CMEQvvv_16B
+ 2217158177U, // CMEQvvv_2D
+ 2317624865U, // CMEQvvv_2S
+ 2351244833U, // CMEQvvv_4H
+ 2250384929U, // CMEQvvv_4S
+ 2384864801U, // CMEQvvv_8B
+ 2183341601U, // CMEQvvv_8H
+ 2283872952U, // CMGEvvi_16B
+ 2217157304U, // CMGEvvi_2D
+ 2317623992U, // CMGEvvi_2S
+ 2351243960U, // CMGEvvi_4H
+ 2250384056U, // CMGEvvi_4S
+ 2384863928U, // CMGEvvi_8B
+ 2183340728U, // CMGEvvi_8H
+ 2283872952U, // CMGEvvv_16B
+ 2217157304U, // CMGEvvv_2D
+ 2317623992U, // CMGEvvv_2S
+ 2351243960U, // CMGEvvv_4H
+ 2250384056U, // CMGEvvv_4S
+ 2384863928U, // CMGEvvv_8B
+ 2183340728U, // CMGEvvv_8H
+ 2283874127U, // CMGTvvi_16B
+ 2217158479U, // CMGTvvi_2D
+ 2317625167U, // CMGTvvi_2S
+ 2351245135U, // CMGTvvi_4H
+ 2250385231U, // CMGTvvi_4S
+ 2384865103U, // CMGTvvi_8B
+ 2183341903U, // CMGTvvi_8H
+ 2283874127U, // CMGTvvv_16B
+ 2217158479U, // CMGTvvv_2D
+ 2317625167U, // CMGTvvv_2S
+ 2351245135U, // CMGTvvv_4H
+ 2250385231U, // CMGTvvv_4S
+ 2384865103U, // CMGTvvv_8B
+ 2183341903U, // CMGTvvv_8H
+ 2283873192U, // CMHIvvv_16B
+ 2217157544U, // CMHIvvv_2D
+ 2317624232U, // CMHIvvv_2S
+ 2351244200U, // CMHIvvv_4H
+ 2250384296U, // CMHIvvv_4S
+ 2384864168U, // CMHIvvv_8B
+ 2183340968U, // CMHIvvv_8H
+ 2283874029U, // CMHSvvv_16B
+ 2217158381U, // CMHSvvv_2D
+ 2317625069U, // CMHSvvv_2S
+ 2351245037U, // CMHSvvv_4H
+ 2250385133U, // CMHSvvv_4S
+ 2384865005U, // CMHSvvv_8B
+ 2183341805U, // CMHSvvv_8H
+ 2283872959U, // CMLEvvi_16B
+ 2217157311U, // CMLEvvi_2D
+ 2317623999U, // CMLEvvi_2S
+ 2351243967U, // CMLEvvi_4H
+ 2250384063U, // CMLEvvi_4S
+ 2384863935U, // CMLEvvi_8B
+ 2183340735U, // CMLEvvi_8H
+ 2283874145U, // CMLTvvi_16B
+ 2217158497U, // CMLTvvi_2D
+ 2317625185U, // CMLTvvi_2S
+ 2351245153U, // CMLTvvi_4H
+ 2250385249U, // CMLTvvi_4S
+ 2384865121U, // CMLTvvi_8B
+ 2183341921U, // CMLTvvi_8H
+ 3221230907U, // CMNww_asr
+ 5435U, // CMNww_lsl
+ 1073747259U, // CMNww_lsr
+ 2147489083U, // CMNww_sxtb
+ 3221230907U, // CMNww_sxth
+ 5435U, // CMNww_sxtw
+ 1073747259U, // CMNww_sxtx
+ 2147489083U, // CMNww_uxtb
+ 3221230907U, // CMNww_uxth
+ 5435U, // CMNww_uxtw
+ 1073747259U, // CMNww_uxtx
+ 2147489083U, // CMNxw_sxtb
+ 3221230907U, // CMNxw_sxth
+ 5435U, // CMNxw_sxtw
+ 2147489083U, // CMNxw_uxtb
+ 3221230907U, // CMNxw_uxth
+ 5435U, // CMNxw_uxtw
+ 3221230907U, // CMNxx_asr
+ 5435U, // CMNxx_lsl
+ 1073747259U, // CMNxx_lsr
+ 1073747259U, // CMNxx_sxtx
+ 1073747259U, // CMNxx_uxtx
+ 3221231008U, // CMPww_asr
+ 5536U, // CMPww_lsl
+ 1073747360U, // CMPww_lsr
+ 2147489184U, // CMPww_sxtb
+ 3221231008U, // CMPww_sxth
+ 5536U, // CMPww_sxtw
+ 1073747360U, // CMPww_sxtx
+ 2147489184U, // CMPww_uxtb
+ 3221231008U, // CMPww_uxth
+ 5536U, // CMPww_uxtw
+ 1073747360U, // CMPww_uxtx
+ 2147489184U, // CMPxw_sxtb
+ 3221231008U, // CMPxw_sxth
+ 5536U, // CMPxw_sxtw
+ 2147489184U, // CMPxw_uxtb
+ 3221231008U, // CMPxw_uxth
+ 5536U, // CMPxw_uxtw
+ 3221231008U, // CMPxx_asr
+ 5536U, // CMPxx_lsl
+ 1073747360U, // CMPxx_lsr
+ 1073747360U, // CMPxx_sxtx
+ 1073747360U, // CMPxx_uxtx
+ 2283874164U, // CMTSTvvv_16B
+ 2217158516U, // CMTSTvvv_2D
+ 2317625204U, // CMTSTvvv_2S
+ 2351245172U, // CMTSTvvv_4H
+ 2250385268U, // CMTSTvvv_4S
+ 2384865140U, // CMTSTvvv_8B
+ 2183341940U, // CMTSTvvv_8H
+ 4459U, // CRC32B_www
+ 4467U, // CRC32CB_www
+ 4860U, // CRC32CH_www
+ 6135U, // CRC32CW_www
+ 6220U, // CRC32CX_wwx
+ 4852U, // CRC32H_www
+ 6113U, // CRC32W_www
+ 6194U, // CRC32X_wwx
+ 5185U, // CSELwwwc
+ 5185U, // CSELxxxc
+ 4679U, // CSINCwwwc
+ 4679U, // CSINCxxxc
+ 6088U, // CSINVwwwc
+ 6088U, // CSINVxxxc
+ 4845U, // CSNEGwwwc
+ 4845U, // CSNEGxxxc
+ 528385U, // DCPS1i
+ 528642U, // DCPS2i
+ 528681U, // DCPS3i
+ 25145U, // DCix
+ 29052U, // DMBi
+ 2432U, // DRPS
+ 29141U, // DSBi
+ 5440U, // EONwww_asr
+ 5440U, // EONwww_lsl
+ 5440U, // EONwww_lsr
+ 5440U, // EONwww_ror
+ 5440U, // EONxxx_asr
+ 5440U, // EONxxx_lsl
+ 5440U, // EONxxx_lsr
+ 5440U, // EONxxx_ror
+ 2283873888U, // EORvvv_16B
+ 2384864864U, // EORvvv_8B
+ 1073747552U, // EORwwi
+ 5728U, // EORwww_asr
+ 5728U, // EORwww_lsl
+ 5728U, // EORwww_lsr
+ 5728U, // EORwww_ror
+ 2147489376U, // EORxxi
+ 5728U, // EORxxx_asr
+ 5728U, // EORxxx_lsl
+ 5728U, // EORxxx_lsr
+ 5728U, // EORxxx_ror
+ 2437U, // ERET
+ 5775U, // EXTRwwwi
+ 5775U, // EXTRxxxi
+ 0U, // F128CSEL
+ 2217157208U, // FABDvvv_2D
+ 2317623896U, // FABDvvv_2S
+ 2250383960U, // FABDvvv_4S
+ 369104579U, // FABSdd
+ 369104579U, // FABSss
+ 2217157296U, // FACGEvvv_2D
+ 2317623984U, // FACGEvvv_2S
+ 2250384048U, // FACGEvvv_4S
+ 2217158471U, // FACGTvvv_2D
+ 2317625159U, // FACGTvvv_2S
+ 2250385223U, // FACGTvvv_4S
+ 2217158034U, // FADDP_2D
+ 2317624722U, // FADDP_2S
+ 2250384786U, // FADDP_4S
+ 270539039U, // FADDPvv_D_2D
+ 404756767U, // FADDPvv_S_2S
+ 4714U, // FADDddd
+ 4714U, // FADDsss
+ 2217157226U, // FADDvvv_2D
+ 2317623914U, // FADDvvv_2S
+ 2250383978U, // FADDvvv_4S
+ 4805U, // FCCMPEdd
+ 4805U, // FCCMPEss
+ 5534U, // FCCMPdd
+ 5534U, // FCCMPss
+ 2217158176U, // FCMEQvvi_2D
+ 2317624864U, // FCMEQvvi_2S
+ 2250384928U, // FCMEQvvi_4S
+ 2217158176U, // FCMEQvvv_2D
+ 2317624864U, // FCMEQvvv_2S
+ 2250384928U, // FCMEQvvv_4S
+ 2217157303U, // FCMGEvvi_2D
+ 2317623991U, // FCMGEvvi_2S
+ 2250384055U, // FCMGEvvi_4S
+ 2217157303U, // FCMGEvvv_2D
+ 2317623991U, // FCMGEvvv_2S
+ 2250384055U, // FCMGEvvv_4S
+ 2217158478U, // FCMGTvvi_2D
+ 2317625166U, // FCMGTvvi_2S
+ 2250385230U, // FCMGTvvi_4S
+ 2217158478U, // FCMGTvvv_2D
+ 2317625166U, // FCMGTvvv_2S
+ 2250385230U, // FCMGTvvv_4S
+ 2217157310U, // FCMLEvvi_2D
+ 2317623998U, // FCMLEvvi_2S
+ 2250384062U, // FCMLEvvi_4S
+ 2217158496U, // FCMLTvvi_2D
+ 2317625184U, // FCMLTvvi_2S
+ 2250385248U, // FCMLTvvi_4S
+ 369104293U, // FCMPdd_quiet
+ 369103565U, // FCMPdd_sig
+ 10491301U, // FCMPdi_quiet
+ 10490573U, // FCMPdi_sig
+ 10491301U, // FCMPsi_quiet
+ 10490573U, // FCMPsi_sig
+ 369104293U, // FCMPss_quiet
+ 369103565U, // FCMPss_sig
+ 5184U, // FCSELdddc
+ 5184U, // FCSELsssc
+ 369104571U, // FCVTASwd
+ 369104571U, // FCVTASws
+ 369104571U, // FCVTASxd
+ 369104571U, // FCVTASxs
+ 369104769U, // FCVTAUwd
+ 369104769U, // FCVTAUws
+ 369104769U, // FCVTAUxd
+ 369104769U, // FCVTAUxs
+ 369104638U, // FCVTMSwd
+ 369104638U, // FCVTMSws
+ 369104638U, // FCVTMSxd
+ 369104638U, // FCVTMSxs
+ 369104785U, // FCVTMUwd
+ 369104785U, // FCVTMUws
+ 369104785U, // FCVTMUxd
+ 369104785U, // FCVTMUxs
+ 369104651U, // FCVTNSwd
+ 369104651U, // FCVTNSws
+ 369104651U, // FCVTNSxd
+ 369104651U, // FCVTNSxs
+ 369104793U, // FCVTNUwd
+ 369104793U, // FCVTNUws
+ 369104793U, // FCVTNUxd
+ 369104793U, // FCVTNUxs
+ 369104667U, // FCVTPSwd
+ 369104667U, // FCVTPSws
+ 369104667U, // FCVTPSxd
+ 369104667U, // FCVTPSxs
+ 369104801U, // FCVTPUwd
+ 369104801U, // FCVTPUws
+ 369104801U, // FCVTPUxd
+ 369104801U, // FCVTPUxs
+ 369104694U, // FCVTZSwd
+ 3221231414U, // FCVTZSwdi
+ 369104694U, // FCVTZSws
+ 3221231414U, // FCVTZSwsi
+ 369104694U, // FCVTZSxd
+ 3221231414U, // FCVTZSxdi
+ 369104694U, // FCVTZSxs
+ 3221231414U, // FCVTZSxsi
+ 369104809U, // FCVTZUwd
+ 3221231529U, // FCVTZUwdi
+ 369104809U, // FCVTZUws
+ 3221231529U, // FCVTZUwsi
+ 369104809U, // FCVTZUxd
+ 3221231529U, // FCVTZUxdi
+ 369104809U, // FCVTZUxs
+ 3221231529U, // FCVTZUxsi
+ 369104763U, // FCVTdh
+ 369104763U, // FCVTds
+ 369104763U, // FCVThd
+ 369104763U, // FCVThs
+ 369104763U, // FCVTsd
+ 369104763U, // FCVTsh
+ 6070U, // FDIVddd
+ 6070U, // FDIVsss
+ 2217158582U, // FDIVvvv_2D
+ 2317625270U, // FDIVvvv_2S
+ 2250385334U, // FDIVvvv_4S
+ 4750U, // FMADDdddd
+ 4750U, // FMADDssss
+ 270539060U, // FMAXNMPvv_D_2D
+ 404756788U, // FMAXNMPvv_S_2S
+ 2217158068U, // FMAXNMPvvv_2D
+ 2317624756U, // FMAXNMPvvv_2S
+ 2250384820U, // FMAXNMPvvv_4S
+ 5377U, // FMAXNMddd
+ 5377U, // FMAXNMsss
+ 2217157889U, // FMAXNMvvv_2D
+ 2317624577U, // FMAXNMvvv_2S
+ 2250384641U, // FMAXNMvvv_4S
+ 270539076U, // FMAXPvv_D_2D
+ 404756804U, // FMAXPvv_S_2S
+ 2217158136U, // FMAXPvvv_2D
+ 2317624824U, // FMAXPvvv_2S
+ 2250384888U, // FMAXPvvv_4S
+ 6202U, // FMAXddd
+ 6202U, // FMAXsss
+ 2217158714U, // FMAXvvv_2D
+ 2317625402U, // FMAXvvv_2S
+ 2250385466U, // FMAXvvv_4S
+ 270539051U, // FMINNMPvv_D_2D
+ 404756779U, // FMINNMPvv_S_2S
+ 2217158059U, // FMINNMPvvv_2D
+ 2317624747U, // FMINNMPvvv_2S
+ 2250384811U, // FMINNMPvvv_4S
+ 5369U, // FMINNMddd
+ 5369U, // FMINNMsss
+ 2217157881U, // FMINNMvvv_2D
+ 2317624569U, // FMINNMvvv_2S
+ 2250384633U, // FMINNMvvv_4S
+ 270539069U, // FMINPvv_D_2D
+ 404756797U, // FMINPvv_S_2S
+ 2217158083U, // FMINPvvv_2D
+ 2317624771U, // FMINPvvv_2S
+ 2250384835U, // FMINPvvv_4S
+ 5416U, // FMINddd
+ 5416U, // FMINsss
+ 2217157928U, // FMINvvv_2D
+ 2317624616U, // FMINvvv_2S
+ 2250384680U, // FMINvvv_4S
+ 1142366531U, // FMLAvvv_2D
+ 1242833219U, // FMLAvvv_2S
+ 1175593283U, // FMLAvvv_4S
+ 1142367992U, // FMLSvvv_2D
+ 1242834680U, // FMLSvvv_2S
+ 1175594744U, // FMLSvvv_4S
+ 369104847U, // FMOVdd
+ 11540431U, // FMOVdi
+ 369104847U, // FMOVdx
+ 11540431U, // FMOVsi
+ 369104847U, // FMOVss
+ 369104847U, // FMOVsw
+ 12003279U, // FMOVvi_2D
+ 11806671U, // FMOVvi_2S
+ 11675599U, // FMOVvi_4S
+ 13182927U, // FMOVvx
+ 369104847U, // FMOVws
+ 369104847U, // FMOVxd
+ 438310863U, // FMOVxv
+ 4630U, // FMSUBdddd
+ 4630U, // FMSUBssss
+ 2217158760U, // FMULXvvv_2D
+ 2317625448U, // FMULXvvv_2S
+ 2250385512U, // FMULXvvv_4S
+ 5332U, // FMULddd
+ 5332U, // FMULsss
+ 2217157844U, // FMULvvv_2D
+ 2317624532U, // FMULvvv_2S
+ 2250384596U, // FMULvvv_4S
+ 369103591U, // FNEGdd
+ 369103591U, // FNEGss
+ 4757U, // FNMADDdddd
+ 4757U, // FNMADDssss
+ 4637U, // FNMSUBdddd
+ 4637U, // FNMSUBssss
+ 5338U, // FNMULddd
+ 5338U, // FNMULsss
+ 2217158419U, // FRECPSvvv_2D
+ 2317625107U, // FRECPSvvv_2S
+ 2250385171U, // FRECPSvvv_4S
+ 369103203U, // FRINTAdd
+ 369103203U, // FRINTAss
+ 369103800U, // FRINTIdd
+ 369103800U, // FRINTIss
+ 369104137U, // FRINTMdd
+ 369104137U, // FRINTMss
+ 369104236U, // FRINTNdd
+ 369104236U, // FRINTNss
+ 369104356U, // FRINTPdd
+ 369104356U, // FRINTPss
+ 369105007U, // FRINTXdd
+ 369105007U, // FRINTXss
+ 369105056U, // FRINTZdd
+ 369105056U, // FRINTZss
+ 2217158440U, // FRSQRTSvvv_2D
+ 2317625128U, // FRSQRTSvvv_2S
+ 2250385192U, // FRSQRTSvvv_4S
+ 369104749U, // FSQRTdd
+ 369104749U, // FSQRTss
+ 4610U, // FSUBddd
+ 4610U, // FSUBsss
+ 2217157122U, // FSUBvvv_2D
+ 2317623810U, // FSUBvvv_2S
+ 2250383874U, // FSUBvvv_4S
+ 530279U, // HINTi
+ 530267U, // HLTi
+ 528974U, // HVCi
+ 557630U, // ICi
+ 369132094U, // ICix
+ 1545217798U, // INSELb
+ 517547782U, // INSELd
+ 1612392198U, // INSELh
+ 1646012166U, // INSELs
+ 377104134U, // INSbw
+ 618211078U, // INSdx
+ 377169670U, // INShw
+ 377235206U, // INSsw
+ 37338U, // ISBi
+ 638390657U, // LDAR_byte
+ 638391847U, // LDAR_dword
+ 638391078U, // LDAR_hword
+ 638391847U, // LDAR_word
+ 671094257U, // LDAXP_dword
+ 671094257U, // LDAXP_word
+ 638390711U, // LDAXR_byte
+ 638391969U, // LDAXR_dword
+ 638391132U, // LDAXR_hword
+ 638391969U, // LDAXR_word
+ 671094798U, // LDPSWx
+ 1744836622U, // LDPSWx_PostInd
+ 1744836622U, // LDPSWx_PreInd
+ 2148340191U, // LDRSBw
+ 712839647U, // LDRSBw_PostInd
+ 3229422047U, // LDRSBw_PreInd
+ 856558U, // LDRSBw_U
+ 856543U, // LDRSBw_Wm_RegOffset
+ 856543U, // LDRSBw_Xm_RegOffset
+ 2148340191U, // LDRSBx
+ 712839647U, // LDRSBx_PostInd
+ 3229422047U, // LDRSBx_PreInd
+ 856558U, // LDRSBx_U
+ 856543U, // LDRSBx_Wm_RegOffset
+ 856543U, // LDRSBx_Xm_RegOffset
+ 1074598778U, // LDRSHw
+ 712840058U, // LDRSHw_PostInd
+ 3229422458U, // LDRSHw_PreInd
+ 856969U, // LDRSHw_U
+ 856954U, // LDRSHw_Wm_RegOffset
+ 856954U, // LDRSHw_Xm_RegOffset
+ 1074598778U, // LDRSHx
+ 712840058U, // LDRSHx_PostInd
+ 3229422458U, // LDRSHx_PreInd
+ 856969U, // LDRSHx_U
+ 856954U, // LDRSHx_Wm_RegOffset
+ 856954U, // LDRSHx_Xm_RegOffset
+ 2148341781U, // LDRSWx
+ 712841237U, // LDRSWx_PostInd
+ 3229423637U, // LDRSWx_PreInd
+ 858133U, // LDRSWx_Wm_RegOffset
+ 858133U, // LDRSWx_Xm_RegOffset
+ 9443349U, // LDRSWx_lit
+ 9442870U, // LDRd_lit
+ 9442870U, // LDRq_lit
+ 9442870U, // LDRs_lit
+ 9442870U, // LDRw_lit
+ 9442870U, // LDRx_lit
+ 856550U, // LDTRSBw
+ 856550U, // LDTRSBx
+ 856961U, // LDTRSHw
+ 856961U, // LDTRSHx
+ 858140U, // LDTRSWx
+ 858148U, // LDURSWx
+ 671094285U, // LDXP_dword
+ 671094285U, // LDXP_word
+ 638390719U, // LDXR_byte
+ 638391976U, // LDXR_dword
+ 638391140U, // LDXR_hword
+ 638391976U, // LDXR_word
+ 1074598701U, // LS16_LDR
+ 856910U, // LS16_LDUR
+ 712839981U, // LS16_PostInd_LDR
+ 712876865U, // LS16_PostInd_STR
+ 3229422381U, // LS16_PreInd_LDR
+ 3229459265U, // LS16_PreInd_STR
+ 1074598721U, // LS16_STR
+ 856917U, // LS16_STUR
+ 856890U, // LS16_UnPriv_LDR
+ 856903U, // LS16_UnPriv_STR
+ 856877U, // LS16_Wm_RegOffset_LDR
+ 856897U, // LS16_Wm_RegOffset_STR
+ 856877U, // LS16_Xm_RegOffset_LDR
+ 856897U, // LS16_Xm_RegOffset_STR
+ 2148341302U, // LS32_LDR
+ 857749U, // LS32_LDUR
+ 712840758U, // LS32_PostInd_LDR
+ 712877700U, // LS32_PostInd_STR
+ 3229423158U, // LS32_PreInd_LDR
+ 3229460100U, // LS32_PreInd_STR
+ 2148341380U, // LS32_STR
+ 857755U, // LS32_STUR
+ 857726U, // LS32_UnPriv_LDR
+ 857737U, // LS32_UnPriv_STR
+ 857654U, // LS32_Wm_RegOffset_LDR
+ 857732U, // LS32_Wm_RegOffset_STR
+ 857654U, // LS32_Xm_RegOffset_LDR
+ 857732U, // LS32_Xm_RegOffset_STR
+ 3222083126U, // LS64_LDR
+ 857749U, // LS64_LDUR
+ 712840758U, // LS64_PostInd_LDR
+ 712877700U, // LS64_PostInd_STR
+ 3229423158U, // LS64_PreInd_LDR
+ 3229460100U, // LS64_PreInd_STR
+ 3222083204U, // LS64_STR
+ 857755U, // LS64_STUR
+ 857726U, // LS64_UnPriv_LDR
+ 857737U, // LS64_UnPriv_STR
+ 857654U, // LS64_Wm_RegOffset_LDR
+ 857732U, // LS64_Wm_RegOffset_STR
+ 857654U, // LS64_Xm_RegOffset_LDR
+ 857732U, // LS64_Xm_RegOffset_STR
+ 2148340104U, // LS8_LDR
+ 856489U, // LS8_LDUR
+ 712839560U, // LS8_PostInd_LDR
+ 712876444U, // LS8_PostInd_STR
+ 3229421960U, // LS8_PreInd_LDR
+ 3229458844U, // LS8_PreInd_STR
+ 2148340124U, // LS8_STR
+ 856496U, // LS8_STUR
+ 856469U, // LS8_UnPriv_LDR
+ 856482U, // LS8_UnPriv_STR
+ 856456U, // LS8_Wm_RegOffset_LDR
+ 856476U, // LS8_Wm_RegOffset_STR
+ 856456U, // LS8_Xm_RegOffset_LDR
+ 856476U, // LS8_Xm_RegOffset_STR
+ 857654U, // LSFP128_LDR
+ 857749U, // LSFP128_LDUR
+ 712840758U, // LSFP128_PostInd_LDR
+ 712877700U, // LSFP128_PostInd_STR
+ 3229423158U, // LSFP128_PreInd_LDR
+ 3229460100U, // LSFP128_PreInd_STR
+ 857732U, // LSFP128_STR
+ 857755U, // LSFP128_STUR
+ 857654U, // LSFP128_Wm_RegOffset_LDR
+ 857732U, // LSFP128_Wm_RegOffset_STR
+ 857654U, // LSFP128_Xm_RegOffset_LDR
+ 857732U, // LSFP128_Xm_RegOffset_STR
+ 1074599478U, // LSFP16_LDR
+ 857749U, // LSFP16_LDUR
+ 712840758U, // LSFP16_PostInd_LDR
+ 712877700U, // LSFP16_PostInd_STR
+ 3229423158U, // LSFP16_PreInd_LDR
+ 3229460100U, // LSFP16_PreInd_STR
+ 1074599556U, // LSFP16_STR
+ 857755U, // LSFP16_STUR
+ 857654U, // LSFP16_Wm_RegOffset_LDR
+ 857732U, // LSFP16_Wm_RegOffset_STR
+ 857654U, // LSFP16_Xm_RegOffset_LDR
+ 857732U, // LSFP16_Xm_RegOffset_STR
+ 2148341302U, // LSFP32_LDR
+ 857749U, // LSFP32_LDUR
+ 712840758U, // LSFP32_PostInd_LDR
+ 712877700U, // LSFP32_PostInd_STR
+ 3229423158U, // LSFP32_PreInd_LDR
+ 3229460100U, // LSFP32_PreInd_STR
+ 2148341380U, // LSFP32_STR
+ 857755U, // LSFP32_STUR
+ 857654U, // LSFP32_Wm_RegOffset_LDR
+ 857732U, // LSFP32_Wm_RegOffset_STR
+ 857654U, // LSFP32_Xm_RegOffset_LDR
+ 857732U, // LSFP32_Xm_RegOffset_STR
+ 3222083126U, // LSFP64_LDR
+ 857749U, // LSFP64_LDUR
+ 712840758U, // LSFP64_PostInd_LDR
+ 712877700U, // LSFP64_PostInd_STR
+ 3229423158U, // LSFP64_PreInd_LDR
+ 3229460100U, // LSFP64_PreInd_STR
+ 3222083204U, // LSFP64_STR
+ 857755U, // LSFP64_STUR
+ 857654U, // LSFP64_Wm_RegOffset_LDR
+ 857732U, // LSFP64_Wm_RegOffset_STR
+ 857654U, // LSFP64_Xm_RegOffset_LDR
+ 857732U, // LSFP64_Xm_RegOffset_STR
+ 2148341302U, // LSFP8_LDR
+ 857749U, // LSFP8_LDUR
+ 712840758U, // LSFP8_PostInd_LDR
+ 712877700U, // LSFP8_PostInd_STR
+ 3229423158U, // LSFP8_PreInd_LDR
+ 3229460100U, // LSFP8_PreInd_STR
+ 2148341380U, // LSFP8_STR
+ 857755U, // LSFP8_STUR
+ 857654U, // LSFP8_Wm_RegOffset_LDR
+ 857732U, // LSFP8_Wm_RegOffset_STR
+ 857654U, // LSFP8_Xm_RegOffset_LDR
+ 857732U, // LSFP8_Xm_RegOffset_STR
+ 671094169U, // LSFPPair128_LDR
+ 671094205U, // LSFPPair128_NonTemp_LDR
+ 671094232U, // LSFPPair128_NonTemp_STR
+ 1744835993U, // LSFPPair128_PostInd_LDR
+ 1752212972U, // LSFPPair128_PostInd_STR
+ 1744835993U, // LSFPPair128_PreInd_LDR
+ 1752212972U, // LSFPPair128_PreInd_STR
+ 671094252U, // LSFPPair128_STR
+ 671094169U, // LSFPPair32_LDR
+ 671094205U, // LSFPPair32_NonTemp_LDR
+ 671094232U, // LSFPPair32_NonTemp_STR
+ 1744835993U, // LSFPPair32_PostInd_LDR
+ 1752212972U, // LSFPPair32_PostInd_STR
+ 1744835993U, // LSFPPair32_PreInd_LDR
+ 1752212972U, // LSFPPair32_PreInd_STR
+ 671094252U, // LSFPPair32_STR
+ 671094169U, // LSFPPair64_LDR
+ 671094205U, // LSFPPair64_NonTemp_LDR
+ 671094232U, // LSFPPair64_NonTemp_STR
+ 1744835993U, // LSFPPair64_PostInd_LDR
+ 1752212972U, // LSFPPair64_PostInd_STR
+ 1744835993U, // LSFPPair64_PreInd_LDR
+ 1752212972U, // LSFPPair64_PreInd_STR
+ 671094252U, // LSFPPair64_STR
+ 5307U, // LSLVwww
+ 5307U, // LSLVxxx
+ 5307U, // LSLwwi
+ 5307U, // LSLxxi
+ 671094169U, // LSPair32_LDR
+ 671094205U, // LSPair32_NonTemp_LDR
+ 671094232U, // LSPair32_NonTemp_STR
+ 1744835993U, // LSPair32_PostInd_LDR
+ 1752212972U, // LSPair32_PostInd_STR
+ 1744835993U, // LSPair32_PreInd_LDR
+ 1752212972U, // LSPair32_PreInd_STR
+ 671094252U, // LSPair32_STR
+ 671094169U, // LSPair64_LDR
+ 671094205U, // LSPair64_NonTemp_LDR
+ 671094232U, // LSPair64_NonTemp_STR
+ 1744835993U, // LSPair64_PostInd_LDR
+ 1752212972U, // LSPair64_PostInd_STR
+ 1744835993U, // LSPair64_PreInd_LDR
+ 1752212972U, // LSPair64_PreInd_STR
+ 671094252U, // LSPair64_STR
+ 5748U, // LSRVwww
+ 5748U, // LSRVxxx
+ 5748U, // LSRwwi
+ 5748U, // LSRxxi
+ 4751U, // MADDwwww
+ 4751U, // MADDxxxx
+ 1209082180U, // MLAvvv_16B
+ 1242833220U, // MLAvvv_2S
+ 1276453188U, // MLAvvv_4H
+ 1175593284U, // MLAvvv_4S
+ 1310073156U, // MLAvvv_8B
+ 1108549956U, // MLAvvv_8H
+ 1209083641U, // MLSvvv_16B
+ 1242834681U, // MLSvvv_2S
+ 1276454649U, // MLSvvv_4H
+ 1175594745U, // MLSvvv_4S
+ 1310074617U, // MLSvvv_8B
+ 1108551417U, // MLSvvv_8H
+ 14686382U, // MOVIdi
+ 384902080U, // MOVIvi_16B
+ 15149230U, // MOVIvi_2D
+ 385229760U, // MOVIvi_8B
+ 754198748U, // MOVIvi_lsl_2S
+ 787818716U, // MOVIvi_lsl_4H
+ 754067676U, // MOVIvi_lsl_4S
+ 787687644U, // MOVIvi_lsl_8H
+ 821307612U, // MOVIvi_msl_2S
+ 821176540U, // MOVIvi_msl_4S
+ 16782283U, // MOVKwii
+ 16782283U, // MOVKxii
+ 17831308U, // MOVNwii
+ 17831308U, // MOVNxii
+ 17832104U, // MOVZwii
+ 17832104U, // MOVZxii
+ 18880291U, // MRSxi
+ 46713U, // MSRii
+ 50809U, // MSRix
+ 4631U, // MSUBwwww
+ 4631U, // MSUBxxxx
+ 2283873493U, // MULvvv_16B
+ 2317624533U, // MULvvv_2S
+ 2351244501U, // MULvvv_4H
+ 2250384597U, // MULvvv_4S
+ 2384864469U, // MULvvv_8B
+ 2183341269U, // MULvvv_8H
+ 754198742U, // MVNIvi_lsl_2S
+ 787818710U, // MVNIvi_lsl_4H
+ 754067670U, // MVNIvi_lsl_4S
+ 787687638U, // MVNIvi_lsl_8H
+ 821307606U, // MVNIvi_msl_2S
+ 821176534U, // MVNIvi_msl_4S
+ 3221230983U, // MVNww_asr
+ 5511U, // MVNww_lsl
+ 1073747335U, // MVNww_lsr
+ 1073747335U, // MVNww_ror
+ 3221230983U, // MVNxx_asr
+ 5511U, // MVNxx_lsl
+ 1073747335U, // MVNxx_lsr
+ 1073747335U, // MVNxx_ror
+ 2283873639U, // ORNvvv_16B
+ 2384864615U, // ORNvvv_8B
+ 5479U, // ORNwww_asr
+ 5479U, // ORNwww_lsl
+ 5479U, // ORNwww_lsr
+ 5479U, // ORNwww_ror
+ 5479U, // ORNxxx_asr
+ 5479U, // ORNxxx_lsl
+ 5479U, // ORNxxx_lsr
+ 5479U, // ORNxxx_ror
+ 310651211U, // ORRvi_lsl_2S
+ 344271179U, // ORRvi_lsl_4H
+ 310520139U, // ORRvi_lsl_4S
+ 344140107U, // ORRvi_lsl_8H
+ 2283873898U, // ORRvvv_16B
+ 2384864874U, // ORRvvv_8B
+ 1073747562U, // ORRwwi
+ 5738U, // ORRwww_asr
+ 5738U, // ORRwww_lsl
+ 5738U, // ORRwww_lsr
+ 5738U, // ORRwww_ror
+ 2147489386U, // ORRxxi
+ 5738U, // ORRxxx_asr
+ 5738U, // ORRxxx_lsl
+ 5738U, // ORRxxx_lsr
+ 5738U, // ORRxxx_ror
+ 2284003459U, // PMULL2vvv_8h16b
+ 2384667805U, // PMULLvvv_8h8b
+ 2283873505U, // PMULvvv_16B
+ 2384864481U, // PMULvvv_8B
+ 3222131955U, // PRFM
+ 906483U, // PRFM_Wm_RegOffset
+ 906483U, // PRFM_Xm_RegOffset
+ 9491699U, // PRFM_lit
+ 906513U, // PRFUM
+ 1108418807U, // QRSHRUNvvi_16B
+ 69477757U, // QRSHRUNvvi_2S
+ 103097725U, // QRSHRUNvvi_4H
+ 1142038775U, // QRSHRUNvvi_4S
+ 36054397U, // QRSHRUNvvi_8B
+ 1175658743U, // QRSHRUNvvi_8H
+ 1108418797U, // QSHRUNvvi_16B
+ 69477748U, // QSHRUNvvi_2S
+ 103097716U, // QSHRUNvvi_4H
+ 1142038765U, // QSHRUNvvi_4S
+ 36054388U, // QSHRUNvvi_8B
+ 1175658733U, // QSHRUNvvi_8H
+ 1108418750U, // RADDHN2vvv_16b8h
+ 1142038718U, // RADDHN2vvv_4s2d
+ 1175658686U, // RADDHN2vvv_8h4s
+ 2216961312U, // RADDHNvvv_2s2d
+ 2250581280U, // RADDHNvvv_4h4s
+ 2183537952U, // RADDHNvvv_8b8h
+ 369104725U, // RBITww
+ 369104725U, // RBITxx
+ 0U, // RET
+ 530242U, // RETx
+ 369103152U, // REV16ww
+ 369103152U, // REV16xx
+ 369102856U, // REV32xx
+ 369104817U, // REVww
+ 369104817U, // REVxx
+ 5733U, // RORVwww
+ 5733U, // RORVxxx
+ 1108418779U, // RSHRNvvi_16B
+ 69477719U, // RSHRNvvi_2S
+ 103097687U, // RSHRNvvi_4H
+ 1142038747U, // RSHRNvvi_4S
+ 36054359U, // RSHRNvvi_8B
+ 1175658715U, // RSHRNvvi_8H
+ 1108418741U, // RSUBHN2vvv_16b8h
+ 1142038709U, // RSUBHN2vvv_4s2d
+ 1175658677U, // RSUBHN2vvv_8h4s
+ 2216961304U, // RSUBHNvvv_2s2d
+ 2250581272U, // RSUBHNvvv_4h4s
+ 2183537944U, // RSUBHNvvv_8b8h
+ 1175920655U, // SABAL2vvv_2d2s
+ 1108484111U, // SABAL2vvv_4s4h
+ 1209212943U, // SABAL2vvv_8h8b
+ 1243030481U, // SABALvvv_2d2s
+ 1276257233U, // SABALvvv_4s4h
+ 1309877201U, // SABALvvv_8h8b
+ 1209082167U, // SABAvvv_16B
+ 1242833207U, // SABAvvv_2S
+ 1276453175U, // SABAvvv_4H
+ 1175593271U, // SABAvvv_4S
+ 1310073143U, // SABAvvv_8B
+ 1108549943U, // SABAvvv_8H
+ 2250711113U, // SABDL2vvv_2d2s
+ 2183274569U, // SABDL2vvv_4s4h
+ 2284003401U, // SABDL2vvv_8h8b
+ 2317820948U, // SABDLvvv_2d2s
+ 2351047700U, // SABDLvvv_4s4h
+ 2384667668U, // SABDLvvv_8h8b
+ 2283872862U, // SABDvvv_16B
+ 2317623902U, // SABDvvv_2S
+ 2351243870U, // SABDvvv_4H
+ 2250383966U, // SABDvvv_4S
+ 2384863838U, // SABDvvv_8B
+ 2183340638U, // SABDvvv_8H
+ 2250711129U, // SADDL2vvv_2d4s
+ 2183274585U, // SADDL2vvv_4s8h
+ 2284003417U, // SADDL2vvv_8h16b
+ 2317820978U, // SADDLvvv_2d2s
+ 2351047730U, // SADDLvvv_4s4h
+ 2384667698U, // SADDLvvv_8h8b
+ 2217156889U, // SADDW2vvv_2d4s
+ 2250383641U, // SADDW2vvv_4s8h
+ 2183340313U, // SADDW2vvv_8h16b
+ 2217158656U, // SADDWvvv_2d2s
+ 2250385408U, // SADDWvvv_4s4h
+ 2183342080U, // SADDWvvv_8h8b
+ 5839U, // SBCSwww
+ 5839U, // SBCSxxx
+ 4659U, // SBCwww
+ 4659U, // SBCxxx
+ 2147489921U, // SBFIZwwii
+ 3221231745U, // SBFIZxxii
+ 5351U, // SBFMwwii
+ 5351U, // SBFMxxii
+ 6236U, // SBFXwwii
+ 6236U, // SBFXxxii
+ 369103577U, // SCVTFdw
+ 3221230297U, // SCVTFdwi
+ 369103577U, // SCVTFdx
+ 3221230297U, // SCVTFdxi
+ 369103577U, // SCVTFsw
+ 3221230297U, // SCVTFswi
+ 369103577U, // SCVTFsx
+ 3221230297U, // SCVTFsxi
+ 6076U, // SDIVwww
+ 6076U, // SDIVxxx
+ 2283872896U, // SHADDvvv_16B
+ 2317623936U, // SHADDvvv_2S
+ 2351243904U, // SHADDvvv_4H
+ 2250384000U, // SHADDvvv_4S
+ 2384863872U, // SHADDvvv_8B
+ 2183340672U, // SHADDvvv_8H
+ 136389705U, // SHLvvi_16B
+ 69674057U, // SHLvvi_2D
+ 170140745U, // SHLvvi_2S
+ 203760713U, // SHLvvi_4H
+ 102900809U, // SHLvvi_4S
+ 237380681U, // SHLvvi_8B
+ 35857481U, // SHLvvi_8H
+ 1108418761U, // SHRNvvi_16B
+ 69477703U, // SHRNvvi_2S
+ 103097671U, // SHRNvvi_4H
+ 1142038729U, // SHRNvvi_4S
+ 36054343U, // SHRNvvi_8B
+ 1175658697U, // SHRNvvi_8H
+ 2283872776U, // SHSUBvvv_16B
+ 2317623816U, // SHSUBvvv_2S
+ 2351243784U, // SHSUBvvv_4H
+ 2250383880U, // SHSUBvvv_4S
+ 2384863752U, // SHSUBvvv_8B
+ 2183340552U, // SHSUBvvv_8H
+ 1209082798U, // SLIvvi_16B
+ 1142367150U, // SLIvvi_2D
+ 1242833838U, // SLIvvi_2S
+ 1276453806U, // SLIvvi_4H
+ 1175593902U, // SLIvvi_4S
+ 1310073774U, // SLIvvi_8B
+ 1108550574U, // SLIvvi_8H
+ 5154U, // SMADDLxwwx
+ 2283873791U, // SMAXPvvv_16B
+ 2317624831U, // SMAXPvvv_2S
+ 2351244799U, // SMAXPvvv_4H
+ 2250384895U, // SMAXPvvv_4S
+ 2384864767U, // SMAXPvvv_8B
+ 2183341567U, // SMAXPvvv_8H
+ 2283874368U, // SMAXvvv_16B
+ 2317625408U, // SMAXvvv_2S
+ 2351245376U, // SMAXvvv_4H
+ 2250385472U, // SMAXvvv_4S
+ 2384865344U, // SMAXvvv_8B
+ 2183342144U, // SMAXvvv_8H
+ 528962U, // SMCi
+ 2283873738U, // SMINPvvv_16B
+ 2317624778U, // SMINPvvv_2S
+ 2351244746U, // SMINPvvv_4H
+ 2250384842U, // SMINPvvv_4S
+ 2384864714U, // SMINPvvv_8B
+ 2183341514U, // SMINPvvv_8H
+ 2283873582U, // SMINvvv_16B
+ 2317624622U, // SMINvvv_2S
+ 2351244590U, // SMINvvv_4H
+ 2250384686U, // SMINvvv_4S
+ 2384864558U, // SMINvvv_8B
+ 2183341358U, // SMINvvv_8H
+ 1175920681U, // SMLAL2vvv_2d4s
+ 1108484137U, // SMLAL2vvv_4s8h
+ 1209212969U, // SMLAL2vvv_8h16b
+ 1243030504U, // SMLALvvv_2d2s
+ 1276257256U, // SMLALvvv_4s4h
+ 1309877224U, // SMLALvvv_8h8b
+ 1175920805U, // SMLSL2vvv_2d4s
+ 1108484261U, // SMLSL2vvv_4s8h
+ 1209213093U, // SMLSL2vvv_8h16b
+ 1243030720U, // SMLSLvvv_2d2s
+ 1276257472U, // SMLSLvvv_4s4h
+ 1309877440U, // SMLSLvvv_8h8b
+ 471865301U, // SMOVwb
+ 538974165U, // SMOVwh
+ 471865301U, // SMOVxb
+ 538974165U, // SMOVxh
+ 572528597U, // SMOVxs
+ 5110U, // SMSUBLxwwx
+ 4888U, // SMULHxxx
+ 2250711179U, // SMULL2vvv_2d4s
+ 2183274635U, // SMULL2vvv_4s8h
+ 2284003467U, // SMULL2vvv_8h16b
+ 2317821092U, // SMULLvvv_2d2s
+ 2351047844U, // SMULLvvv_4s4h
+ 2384667812U, // SMULLvvv_8h8b
+ 6344U, // SQADDbbb
+ 6344U, // SQADDddd
+ 6344U, // SQADDhhh
+ 6344U, // SQADDsss
+ 2283872925U, // SQADDvvv_16B
+ 2217157277U, // SQADDvvv_2D
+ 2317623965U, // SQADDvvv_2S
+ 2351243933U, // SQADDvvv_4H
+ 2250384029U, // SQADDvvv_4S
+ 2384863901U, // SQADDvvv_8B
+ 2183340701U, // SQADDvvv_8H
+ 1175920671U, // SQDMLAL2vvv_2d4s
+ 1108484127U, // SQDMLAL2vvv_4s8h
+ 1243030495U, // SQDMLALvvv_2d2s
+ 1276257247U, // SQDMLALvvv_4s4h
+ 1175920795U, // SQDMLSL2vvv_2d4s
+ 1108484251U, // SQDMLSL2vvv_4s8h
+ 1243030711U, // SQDMLSLvvv_2d2s
+ 1276257463U, // SQDMLSLvvv_4s4h
+ 2317624069U, // SQDMULHvvv_2S
+ 2351244037U, // SQDMULHvvv_4H
+ 2250384133U, // SQDMULHvvv_4S
+ 2183340805U, // SQDMULHvvv_8H
+ 2250711161U, // SQDMULL2vvv_2d4s
+ 2183274617U, // SQDMULL2vvv_4s8h
+ 2317821076U, // SQDMULLvvv_2d2s
+ 2351047828U, // SQDMULLvvv_4s4h
+ 2317624078U, // SQRDMULHvvv_2S
+ 2351244046U, // SQRDMULHvvv_4H
+ 2250384142U, // SQRDMULHvvv_4S
+ 2183340814U, // SQRDMULHvvv_8H
+ 6384U, // SQRSHLbbb
+ 6384U, // SQRSHLddd
+ 6384U, // SQRSHLhhh
+ 6384U, // SQRSHLsss
+ 2283873365U, // SQRSHLvvv_16B
+ 2217157717U, // SQRSHLvvv_2D
+ 2317624405U, // SQRSHLvvv_2S
+ 2351244373U, // SQRSHLvvv_4H
+ 2250384469U, // SQRSHLvvv_4S
+ 2384864341U, // SQRSHLvvv_8B
+ 2183341141U, // SQRSHLvvv_8H
+ 1108418777U, // SQRSHRNvvi_16B
+ 69477717U, // SQRSHRNvvi_2S
+ 103097685U, // SQRSHRNvvi_4H
+ 1142038745U, // SQRSHRNvvi_4S
+ 36054357U, // SQRSHRNvvi_8B
+ 1175658713U, // SQRSHRNvvi_8H
+ 136390537U, // SQSHLUvvi_16B
+ 69674889U, // SQSHLUvvi_2D
+ 170141577U, // SQSHLUvvi_2S
+ 203761545U, // SQSHLUvvi_4H
+ 102901641U, // SQSHLUvvi_4S
+ 237381513U, // SQSHLUvvi_8B
+ 35858313U, // SQSHLUvvi_8H
+ 6370U, // SQSHLbbb
+ 6370U, // SQSHLddd
+ 6370U, // SQSHLhhh
+ 6370U, // SQSHLsss
+ 136389703U, // SQSHLvvi_16B
+ 69674055U, // SQSHLvvi_2D
+ 170140743U, // SQSHLvvi_2S
+ 203760711U, // SQSHLvvi_4H
+ 102900807U, // SQSHLvvi_4S
+ 237380679U, // SQSHLvvi_8B
+ 35857479U, // SQSHLvvi_8H
+ 2283873351U, // SQSHLvvv_16B
+ 2217157703U, // SQSHLvvv_2D
+ 2317624391U, // SQSHLvvv_2S
+ 2351244359U, // SQSHLvvv_4H
+ 2250384455U, // SQSHLvvv_4S
+ 2384864327U, // SQSHLvvv_8B
+ 2183341127U, // SQSHLvvv_8H
+ 1108418759U, // SQSHRNvvi_16B
+ 69477701U, // SQSHRNvvi_2S
+ 103097669U, // SQSHRNvvi_4H
+ 1142038727U, // SQSHRNvvi_4S
+ 36054341U, // SQSHRNvvi_8B
+ 1175658695U, // SQSHRNvvi_8H
+ 6325U, // SQSUBbbb
+ 6325U, // SQSUBddd
+ 6325U, // SQSUBhhh
+ 6325U, // SQSUBsss
+ 2283872805U, // SQSUBvvv_16B
+ 2217157157U, // SQSUBvvv_2D
+ 2317623845U, // SQSUBvvv_2S
+ 2351243813U, // SQSUBvvv_4H
+ 2250383909U, // SQSUBvvv_4S
+ 2384863781U, // SQSUBvvv_8B
+ 2183340581U, // SQSUBvvv_8H
+ 2283872880U, // SRHADDvvv_16B
+ 2317623920U, // SRHADDvvv_2S
+ 2351243888U, // SRHADDvvv_4H
+ 2250383984U, // SRHADDvvv_4S
+ 2384863856U, // SRHADDvvv_8B
+ 2183340656U, // SRHADDvvv_8H
+ 1209082803U, // SRIvvi_16B
+ 1142367155U, // SRIvvi_2D
+ 1242833843U, // SRIvvi_2S
+ 1276453811U, // SRIvvi_4H
+ 1175593907U, // SRIvvi_4S
+ 1310073779U, // SRIvvi_8B
+ 1108550579U, // SRIvvi_8H
+ 6400U, // SRSHLddd
+ 2283873381U, // SRSHLvvv_16B
+ 2217157733U, // SRSHLvvv_2D
+ 2317624421U, // SRSHLvvv_2S
+ 2351244389U, // SRSHLvvv_4H
+ 2250384485U, // SRSHLvvv_4S
+ 2384864357U, // SRSHLvvv_8B
+ 2183341157U, // SRSHLvvv_8H
+ 136390203U, // SRSHRvvi_16B
+ 69674555U, // SRSHRvvi_2D
+ 170141243U, // SRSHRvvi_2S
+ 203761211U, // SRSHRvvi_4H
+ 102901307U, // SRSHRvvi_4S
+ 237381179U, // SRSHRvvi_8B
+ 35857979U, // SRSHRvvi_8H
+ 1209082185U, // SRSRAvvi_16B
+ 1142366537U, // SRSRAvvi_2D
+ 1242833225U, // SRSRAvvi_2S
+ 1276453193U, // SRSRAvvi_4H
+ 1175593289U, // SRSRAvvi_4S
+ 1310073161U, // SRSRAvvi_8B
+ 1108549961U, // SRSRAvvi_8H
+ 136519785U, // SSHLLvvi_16B
+ 170337414U, // SSHLLvvi_2S
+ 203564166U, // SSHLLvvi_4H
+ 103227497U, // SSHLLvvi_4S
+ 237184134U, // SSHLLvvi_8B
+ 35790953U, // SSHLLvvi_8H
+ 6414U, // SSHLddd
+ 2283873395U, // SSHLvvv_16B
+ 2217157747U, // SSHLvvv_2D
+ 2317624435U, // SSHLvvv_2S
+ 2351244403U, // SSHLvvv_4H
+ 2250384499U, // SSHLvvv_4S
+ 2384864371U, // SSHLvvv_8B
+ 2183341171U, // SSHLvvv_8H
+ 136390217U, // SSHRvvi_16B
+ 69674569U, // SSHRvvi_2D
+ 170141257U, // SSHRvvi_2S
+ 203761225U, // SSHRvvi_4H
+ 102901321U, // SSHRvvi_4S
+ 237381193U, // SSHRvvi_8B
+ 35857993U, // SSHRvvi_8H
+ 1209082199U, // SSRAvvi_16B
+ 1142366551U, // SSRAvvi_2D
+ 1242833239U, // SSRAvvi_2S
+ 1276453207U, // SSRAvvi_4H
+ 1175593303U, // SSRAvvi_4S
+ 1310073175U, // SSRAvvi_8B
+ 1108549975U, // SSRAvvi_8H
+ 2250711097U, // SSUBL2vvv_2d4s
+ 2183274553U, // SSUBL2vvv_4s8h
+ 2284003385U, // SSUBL2vvv_8h16b
+ 2317820934U, // SSUBLvvv_2d2s
+ 2351047686U, // SSUBLvvv_4s4h
+ 2384667654U, // SSUBLvvv_8h8b
+ 2217156873U, // SSUBW2vvv_2d4s
+ 2250383625U, // SSUBW2vvv_4s8h
+ 2183340297U, // SSUBW2vvv_8h16b
+ 2217158633U, // SSUBWvvv_2d2s
+ 2250385385U, // SSUBWvvv_4s4h
+ 2183342057U, // SSUBWvvv_8h8b
+ 638390670U, // STLR_byte
+ 638391898U, // STLR_dword
+ 638391091U, // STLR_hword
+ 638391898U, // STLR_word
+ 5651U, // STLXP_dword
+ 5651U, // STLXP_word
+ 671093190U, // STLXR_byte
+ 671094446U, // STLXR_dword
+ 671093611U, // STLXR_hword
+ 671094446U, // STLXR_word
+ 5658U, // STXP_dword
+ 5658U, // STXP_word
+ 671093198U, // STXR_byte
+ 671094453U, // STXR_dword
+ 671093619U, // STXR_hword
+ 671094453U, // STXR_word
+ 1108418742U, // SUBHN2vvv_16b8h
+ 1142038710U, // SUBHN2vvv_4s2d
+ 1175658678U, // SUBHN2vvv_8h4s
+ 2216961305U, // SUBHNvvv_2s2d
+ 2250581273U, // SUBHNvvv_4h4s
+ 2183537945U, // SUBHNvvv_8b8h
+ 5833U, // SUBSwww_asr
+ 5833U, // SUBSwww_lsl
+ 5833U, // SUBSwww_lsr
+ 5833U, // SUBSwww_sxtb
+ 5833U, // SUBSwww_sxth
+ 5833U, // SUBSwww_sxtw
+ 5833U, // SUBSwww_sxtx
+ 5833U, // SUBSwww_uxtb
+ 5833U, // SUBSwww_uxth
+ 5833U, // SUBSwww_uxtw
+ 5833U, // SUBSwww_uxtx
+ 5833U, // SUBSxxw_sxtb
+ 5833U, // SUBSxxw_sxth
+ 5833U, // SUBSxxw_sxtw
+ 5833U, // SUBSxxw_uxtb
+ 5833U, // SUBSxxw_uxth
+ 5833U, // SUBSxxw_uxtw
+ 5833U, // SUBSxxx_asr
+ 5833U, // SUBSxxx_lsl
+ 5833U, // SUBSxxx_lsr
+ 5833U, // SUBSxxx_sxtx
+ 5833U, // SUBSxxx_uxtx
+ 6327U, // SUBddd
+ 2283872771U, // SUBvvv_16B
+ 2217157123U, // SUBvvv_2D
+ 2317623811U, // SUBvvv_2S
+ 2351243779U, // SUBvvv_4H
+ 2250383875U, // SUBvvv_4S
+ 2384863747U, // SUBvvv_8B
+ 2183340547U, // SUBvvv_8H
+ 3221231305U, // SUBwwi_lsl0_S
+ 3152166U, // SUBwwi_lsl0_cmp
+ 3221230083U, // SUBwwi_lsl0_s
+ 5833U, // SUBwwi_lsl12_S
+ 4200742U, // SUBwwi_lsl12_cmp
+ 4611U, // SUBwwi_lsl12_s
+ 4611U, // SUBwww_asr
+ 4611U, // SUBwww_lsl
+ 4611U, // SUBwww_lsr
+ 4611U, // SUBwww_sxtb
+ 4611U, // SUBwww_sxth
+ 4611U, // SUBwww_sxtw
+ 4611U, // SUBwww_sxtx
+ 4611U, // SUBwww_uxtb
+ 4611U, // SUBwww_uxth
+ 4611U, // SUBwww_uxtw
+ 4611U, // SUBwww_uxtx
+ 3221231305U, // SUBxxi_lsl0_S
+ 3152166U, // SUBxxi_lsl0_cmp
+ 3221230083U, // SUBxxi_lsl0_s
+ 5833U, // SUBxxi_lsl12_S
+ 4200742U, // SUBxxi_lsl12_cmp
+ 4611U, // SUBxxi_lsl12_s
+ 4611U, // SUBxxw_sxtb
+ 4611U, // SUBxxw_sxth
+ 4611U, // SUBxxw_sxtw
+ 4611U, // SUBxxw_uxtb
+ 4611U, // SUBxxw_uxth
+ 4611U, // SUBxxw_uxtw
+ 4611U, // SUBxxx_asr
+ 4611U, // SUBxxx_lsl
+ 4611U, // SUBxxx_lsr
+ 4611U, // SUBxxx_sxtx
+ 4611U, // SUBxxx_uxtx
+ 528979U, // SVCi
+ 369103350U, // SXTBww
+ 369103350U, // SXTBxw
+ 369103761U, // SXTHww
+ 369103761U, // SXTHxw
+ 369104940U, // SXTWxw
+ 1073747150U, // SYSLxicci
+ 19928881U, // SYSiccix
+ 0U, // TAIL_BRx
+ 0U, // TAIL_Bimm
+ 2147489946U, // TBNZwii
+ 2147489946U, // TBNZxii
+ 2147489916U, // TBZwii
+ 2147489916U, // TBZxii
+ 0U, // TC_RETURNdi
+ 0U, // TC_RETURNxi
+ 582557U, // TLBIi
+ 369157021U, // TLBIix
+ 0U, // TLSDESCCALL
+ 0U, // TLSDESC_BLRx
+ 3221231478U, // TSTww_asr
+ 6006U, // TSTww_lsl
+ 1073747830U, // TSTww_lsr
+ 1073747830U, // TSTww_ror
+ 3221231478U, // TSTxx_asr
+ 6006U, // TSTxx_lsl
+ 1073747830U, // TSTxx_lsr
+ 1073747830U, // TSTxx_ror
+ 1175920663U, // UABAL2vvv_2d2s
+ 1108484119U, // UABAL2vvv_4s4h
+ 1209212951U, // UABAL2vvv_8h8b
+ 1243030488U, // UABALvvv_2d2s
+ 1276257240U, // UABALvvv_4s4h
+ 1309877208U, // UABALvvv_8h8b
+ 1209082173U, // UABAvvv_16B
+ 1242833213U, // UABAvvv_2S
+ 1276453181U, // UABAvvv_4H
+ 1175593277U, // UABAvvv_4S
+ 1310073149U, // UABAvvv_8B
+ 1108549949U, // UABAvvv_8H
+ 2250711121U, // UABDL2vvv_2d2s
+ 2183274577U, // UABDL2vvv_4s4h
+ 2284003409U, // UABDL2vvv_8h8b
+ 2317820955U, // UABDLvvv_2d2s
+ 2351047707U, // UABDLvvv_4s4h
+ 2384667675U, // UABDLvvv_8h8b
+ 2283872868U, // UABDvvv_16B
+ 2317623908U, // UABDvvv_2S
+ 2351243876U, // UABDvvv_4H
+ 2250383972U, // UABDvvv_4S
+ 2384863844U, // UABDvvv_8B
+ 2183340644U, // UABDvvv_8H
+ 2250711137U, // UADDL2vvv_2d4s
+ 2183274593U, // UADDL2vvv_4s8h
+ 2284003425U, // UADDL2vvv_8h16b
+ 2317820985U, // UADDLvvv_2d2s
+ 2351047737U, // UADDLvvv_4s4h
+ 2384667705U, // UADDLvvv_8h8b
+ 2217156897U, // UADDW2vvv_2d4s
+ 2250383649U, // UADDW2vvv_4s8h
+ 2183340321U, // UADDW2vvv_8h16b
+ 2217158663U, // UADDWvvv_2d2s
+ 2250385415U, // UADDWvvv_4s4h
+ 2183342087U, // UADDWvvv_8h8b
+ 2147489928U, // UBFIZwwii
+ 3221231752U, // UBFIZxxii
+ 5357U, // UBFMwwii
+ 5357U, // UBFMxxii
+ 6242U, // UBFXwwii
+ 6242U, // UBFXxxii
+ 369103584U, // UCVTFdw
+ 3221230304U, // UCVTFdwi
+ 369103584U, // UCVTFdx
+ 3221230304U, // UCVTFdxi
+ 369103584U, // UCVTFsw
+ 3221230304U, // UCVTFswi
+ 369103584U, // UCVTFsx
+ 3221230304U, // UCVTFsxi
+ 6082U, // UDIVwww
+ 6082U, // UDIVxxx
+ 2283872903U, // UHADDvvv_16B
+ 2317623943U, // UHADDvvv_2S
+ 2351243911U, // UHADDvvv_4H
+ 2250384007U, // UHADDvvv_4S
+ 2384863879U, // UHADDvvv_8B
+ 2183340679U, // UHADDvvv_8H
+ 2283872783U, // UHSUBvvv_16B
+ 2317623823U, // UHSUBvvv_2S
+ 2351243791U, // UHSUBvvv_4H
+ 2250383887U, // UHSUBvvv_4S
+ 2384863759U, // UHSUBvvv_8B
+ 2183340559U, // UHSUBvvv_8H
+ 5162U, // UMADDLxwwx
+ 2283873798U, // UMAXPvvv_16B
+ 2317624838U, // UMAXPvvv_2S
+ 2351244806U, // UMAXPvvv_4H
+ 2250384902U, // UMAXPvvv_4S
+ 2384864774U, // UMAXPvvv_8B
+ 2183341574U, // UMAXPvvv_8H
+ 2283874374U, // UMAXvvv_16B
+ 2317625414U, // UMAXvvv_2S
+ 2351245382U, // UMAXvvv_4H
+ 2250385478U, // UMAXvvv_4S
+ 2384865350U, // UMAXvvv_8B
+ 2183342150U, // UMAXvvv_8H
+ 2283873745U, // UMINPvvv_16B
+ 2317624785U, // UMINPvvv_2S
+ 2351244753U, // UMINPvvv_4H
+ 2250384849U, // UMINPvvv_4S
+ 2384864721U, // UMINPvvv_8B
+ 2183341521U, // UMINPvvv_8H
+ 2283873588U, // UMINvvv_16B
+ 2317624628U, // UMINvvv_2S
+ 2351244596U, // UMINvvv_4H
+ 2250384692U, // UMINvvv_4S
+ 2384864564U, // UMINvvv_8B
+ 2183341364U, // UMINvvv_8H
+ 1175920689U, // UMLAL2vvv_2d4s
+ 1108484145U, // UMLAL2vvv_4s8h
+ 1209212977U, // UMLAL2vvv_8h16b
+ 1243030511U, // UMLALvvv_2d2s
+ 1276257263U, // UMLALvvv_4s4h
+ 1309877231U, // UMLALvvv_8h8b
+ 1175920813U, // UMLSL2vvv_2d4s
+ 1108484269U, // UMLSL2vvv_4s8h
+ 1209213101U, // UMLSL2vvv_8h16b
+ 1243030727U, // UMLSLvvv_2d2s
+ 1276257479U, // UMLSLvvv_4s4h
+ 1309877447U, // UMLSLvvv_8h8b
+ 471865307U, // UMOVwb
+ 538974171U, // UMOVwh
+ 572528603U, // UMOVws
+ 438310875U, // UMOVxd
+ 5118U, // UMSUBLxwwx
+ 4895U, // UMULHxxx
+ 2250711187U, // UMULL2vvv_2d4s
+ 2183274643U, // UMULL2vvv_4s8h
+ 2284003475U, // UMULL2vvv_8h16b
+ 2317821099U, // UMULLvvv_2d2s
+ 2351047851U, // UMULLvvv_4s4h
+ 2384667819U, // UMULLvvv_8h8b
+ 6351U, // UQADDbbb
+ 6351U, // UQADDddd
+ 6351U, // UQADDhhh
+ 6351U, // UQADDsss
+ 2283872932U, // UQADDvvv_16B
+ 2217157284U, // UQADDvvv_2D
+ 2317623972U, // UQADDvvv_2S
+ 2351243940U, // UQADDvvv_4H
+ 2250384036U, // UQADDvvv_4S
+ 2384863908U, // UQADDvvv_8B
+ 2183340708U, // UQADDvvv_8H
+ 6392U, // UQRSHLbbb
+ 6392U, // UQRSHLddd
+ 6392U, // UQRSHLhhh
+ 6392U, // UQRSHLsss
+ 2283873373U, // UQRSHLvvv_16B
+ 2217157725U, // UQRSHLvvv_2D
+ 2317624413U, // UQRSHLvvv_2S
+ 2351244381U, // UQRSHLvvv_4H
+ 2250384477U, // UQRSHLvvv_4S
+ 2384864349U, // UQRSHLvvv_8B
+ 2183341149U, // UQRSHLvvv_8H
+ 1108418787U, // UQRSHRNvvi_16B
+ 69477726U, // UQRSHRNvvi_2S
+ 103097694U, // UQRSHRNvvi_4H
+ 1142038755U, // UQRSHRNvvi_4S
+ 36054366U, // UQRSHRNvvi_8B
+ 1175658723U, // UQRSHRNvvi_8H
+ 6377U, // UQSHLbbb
+ 6377U, // UQSHLddd
+ 6377U, // UQSHLhhh
+ 6377U, // UQSHLsss
+ 136389710U, // UQSHLvvi_16B
+ 69674062U, // UQSHLvvi_2D
+ 170140750U, // UQSHLvvi_2S
+ 203760718U, // UQSHLvvi_4H
+ 102900814U, // UQSHLvvi_4S
+ 237380686U, // UQSHLvvi_8B
+ 35857486U, // UQSHLvvi_8H
+ 2283873358U, // UQSHLvvv_16B
+ 2217157710U, // UQSHLvvv_2D
+ 2317624398U, // UQSHLvvv_2S
+ 2351244366U, // UQSHLvvv_4H
+ 2250384462U, // UQSHLvvv_4S
+ 2384864334U, // UQSHLvvv_8B
+ 2183341134U, // UQSHLvvv_8H
+ 1108418768U, // UQSHRNvvi_16B
+ 69477709U, // UQSHRNvvi_2S
+ 103097677U, // UQSHRNvvi_4H
+ 1142038736U, // UQSHRNvvi_4S
+ 36054349U, // UQSHRNvvi_8B
+ 1175658704U, // UQSHRNvvi_8H
+ 6332U, // UQSUBbbb
+ 6332U, // UQSUBddd
+ 6332U, // UQSUBhhh
+ 6332U, // UQSUBsss
+ 2283872812U, // UQSUBvvv_16B
+ 2217157164U, // UQSUBvvv_2D
+ 2317623852U, // UQSUBvvv_2S
+ 2351243820U, // UQSUBvvv_4H
+ 2250383916U, // UQSUBvvv_4S
+ 2384863788U, // UQSUBvvv_8B
+ 2183340588U, // UQSUBvvv_8H
+ 2283872888U, // URHADDvvv_16B
+ 2317623928U, // URHADDvvv_2S
+ 2351243896U, // URHADDvvv_4H
+ 2250383992U, // URHADDvvv_4S
+ 2384863864U, // URHADDvvv_8B
+ 2183340664U, // URHADDvvv_8H
+ 6407U, // URSHLddd
+ 2283873388U, // URSHLvvv_16B
+ 2217157740U, // URSHLvvv_2D
+ 2317624428U, // URSHLvvv_2S
+ 2351244396U, // URSHLvvv_4H
+ 2250384492U, // URSHLvvv_4S
+ 2384864364U, // URSHLvvv_8B
+ 2183341164U, // URSHLvvv_8H
+ 136390210U, // URSHRvvi_16B
+ 69674562U, // URSHRvvi_2D
+ 170141250U, // URSHRvvi_2S
+ 203761218U, // URSHRvvi_4H
+ 102901314U, // URSHRvvi_4S
+ 237381186U, // URSHRvvi_8B
+ 35857986U, // URSHRvvi_8H
+ 1209082192U, // URSRAvvi_16B
+ 1142366544U, // URSRAvvi_2D
+ 1242833232U, // URSRAvvi_2S
+ 1276453200U, // URSRAvvi_4H
+ 1175593296U, // URSRAvvi_4S
+ 1310073168U, // URSRAvvi_8B
+ 1108549968U, // URSRAvvi_8H
+ 136519793U, // USHLLvvi_16B
+ 170337421U, // USHLLvvi_2S
+ 203564173U, // USHLLvvi_4H
+ 103227505U, // USHLLvvi_4S
+ 237184141U, // USHLLvvi_8B
+ 35790961U, // USHLLvvi_8H
+ 6420U, // USHLddd
+ 2283873401U, // USHLvvv_16B
+ 2217157753U, // USHLvvv_2D
+ 2317624441U, // USHLvvv_2S
+ 2351244409U, // USHLvvv_4H
+ 2250384505U, // USHLvvv_4S
+ 2384864377U, // USHLvvv_8B
+ 2183341177U, // USHLvvv_8H
+ 136390223U, // USHRvvi_16B
+ 69674575U, // USHRvvi_2D
+ 170141263U, // USHRvvi_2S
+ 203761231U, // USHRvvi_4H
+ 102901327U, // USHRvvi_4S
+ 237381199U, // USHRvvi_8B
+ 35857999U, // USHRvvi_8H
+ 1209082205U, // USRAvvi_16B
+ 1142366557U, // USRAvvi_2D
+ 1242833245U, // USRAvvi_2S
+ 1276453213U, // USRAvvi_4H
+ 1175593309U, // USRAvvi_4S
+ 1310073181U, // USRAvvi_8B
+ 1108549981U, // USRAvvi_8H
+ 2250711105U, // USUBL2vvv_2d4s
+ 2183274561U, // USUBL2vvv_4s8h
+ 2284003393U, // USUBL2vvv_8h16b
+ 2317820941U, // USUBLvvv_2d2s
+ 2351047693U, // USUBLvvv_4s4h
+ 2384667661U, // USUBLvvv_8h8b
+ 2217156881U, // USUBW2vvv_2d4s
+ 2250383633U, // USUBW2vvv_4s8h
+ 2183340305U, // USUBW2vvv_8h16b
+ 2217158640U, // USUBWvvv_2d2s
+ 2250385392U, // USUBWvvv_4s4h
+ 2183342064U, // USUBWvvv_8h8b
+ 369103356U, // UXTBww
+ 369103356U, // UXTBxw
+ 369103767U, // UXTHww
+ 369103767U, // UXTHxw
+ 69674806U, // VCVTf2xs_2D
+ 170141494U, // VCVTf2xs_2S
+ 102901558U, // VCVTf2xs_4S
+ 69674921U, // VCVTf2xu_2D
+ 170141609U, // VCVTf2xu_2S
+ 102901673U, // VCVTf2xu_4S
+ 69673689U, // VCVTxs2f_2D
+ 170140377U, // VCVTxs2f_2S
+ 102900441U, // VCVTxs2f_4S
+ 69673696U, // VCVTxu2f_2D
+ 170140384U, // VCVTxu2f_2S
+ 102900448U, // VCVTxu2f_4S
+ 0U
+ };
+
+ static uint16_t OpInfo2[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // PROLOG_LABEL
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 0U, // DBG_VALUE
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 0U, // BUNDLE
+ 0U, // LIFETIME_START
+ 0U, // LIFETIME_END
+ 0U, // ADCSwww
+ 0U, // ADCSxxx
+ 0U, // ADCwww
+ 0U, // ADCxxx
+ 16U, // ADDHN2vvv_16b8h
+ 32U, // ADDHN2vvv_4s2d
+ 48U, // ADDHN2vvv_8h4s
+ 32U, // ADDHNvvv_2s2d
+ 48U, // ADDHNvvv_4h4s
+ 16U, // ADDHNvvv_8b8h
+ 64U, // ADDP_16B
+ 32U, // ADDP_2D
+ 80U, // ADDP_2S
+ 96U, // ADDP_4H
+ 48U, // ADDP_4S
+ 112U, // ADDP_8B
+ 16U, // ADDP_8H
+ 0U, // ADDPvv_D_2D
+ 128U, // ADDSwww_asr
+ 384U, // ADDSwww_lsl
+ 640U, // ADDSwww_lsr
+ 896U, // ADDSwww_sxtb
+ 1152U, // ADDSwww_sxth
+ 1408U, // ADDSwww_sxtw
+ 1664U, // ADDSwww_sxtx
+ 1920U, // ADDSwww_uxtb
+ 2176U, // ADDSwww_uxth
+ 2432U, // ADDSwww_uxtw
+ 2688U, // ADDSwww_uxtx
+ 896U, // ADDSxxw_sxtb
+ 1152U, // ADDSxxw_sxth
+ 1408U, // ADDSxxw_sxtw
+ 1920U, // ADDSxxw_uxtb
+ 2176U, // ADDSxxw_uxth
+ 2432U, // ADDSxxw_uxtw
+ 128U, // ADDSxxx_asr
+ 384U, // ADDSxxx_lsl
+ 640U, // ADDSxxx_lsr
+ 1664U, // ADDSxxx_sxtx
+ 2688U, // ADDSxxx_uxtx
+ 0U, // ADDddd
+ 64U, // ADDvvv_16B
+ 32U, // ADDvvv_2D
+ 80U, // ADDvvv_2S
+ 96U, // ADDvvv_4H
+ 48U, // ADDvvv_4S
+ 112U, // ADDvvv_8B
+ 16U, // ADDvvv_8H
+ 0U, // ADDwwi_lsl0_S
+ 0U, // ADDwwi_lsl0_cmp
+ 0U, // ADDwwi_lsl0_s
+ 1U, // ADDwwi_lsl12_S
+ 0U, // ADDwwi_lsl12_cmp
+ 1U, // ADDwwi_lsl12_s
+ 128U, // ADDwww_asr
+ 384U, // ADDwww_lsl
+ 640U, // ADDwww_lsr
+ 896U, // ADDwww_sxtb
+ 1152U, // ADDwww_sxth
+ 1408U, // ADDwww_sxtw
+ 1664U, // ADDwww_sxtx
+ 1920U, // ADDwww_uxtb
+ 2176U, // ADDwww_uxth
+ 2432U, // ADDwww_uxtw
+ 2688U, // ADDwww_uxtx
+ 0U, // ADDxxi_lsl0_S
+ 0U, // ADDxxi_lsl0_cmp
+ 0U, // ADDxxi_lsl0_s
+ 1U, // ADDxxi_lsl12_S
+ 0U, // ADDxxi_lsl12_cmp
+ 1U, // ADDxxi_lsl12_s
+ 896U, // ADDxxw_sxtb
+ 1152U, // ADDxxw_sxth
+ 1408U, // ADDxxw_sxtw
+ 1920U, // ADDxxw_uxtb
+ 2176U, // ADDxxw_uxth
+ 2432U, // ADDxxw_uxtw
+ 128U, // ADDxxx_asr
+ 384U, // ADDxxx_lsl
+ 640U, // ADDxxx_lsr
+ 1664U, // ADDxxx_sxtx
+ 2688U, // ADDxxx_uxtx
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 0U, // ADRPxi
+ 0U, // ADRxi
+ 1U, // ANDSwwi
+ 128U, // ANDSwww_asr
+ 384U, // ANDSwww_lsl
+ 640U, // ANDSwww_lsr
+ 2944U, // ANDSwww_ror
+ 1U, // ANDSxxi
+ 128U, // ANDSxxx_asr
+ 384U, // ANDSxxx_lsl
+ 640U, // ANDSxxx_lsr
+ 2944U, // ANDSxxx_ror
+ 64U, // ANDvvv_16B
+ 112U, // ANDvvv_8B
+ 1U, // ANDwwi
+ 128U, // ANDwww_asr
+ 384U, // ANDwww_lsl
+ 640U, // ANDwww_lsr
+ 2944U, // ANDwww_ror
+ 1U, // ANDxxi
+ 128U, // ANDxxx_asr
+ 384U, // ANDxxx_lsl
+ 640U, // ANDxxx_lsr
+ 2944U, // ANDxxx_ror
+ 0U, // ASRVwww
+ 0U, // ASRVxxx
+ 0U, // ASRwwi
+ 0U, // ASRxxi
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_MAX_I16
+ 0U, // ATOMIC_LOAD_MAX_I32
+ 0U, // ATOMIC_LOAD_MAX_I64
+ 0U, // ATOMIC_LOAD_MAX_I8
+ 0U, // ATOMIC_LOAD_MIN_I16
+ 0U, // ATOMIC_LOAD_MIN_I32
+ 0U, // ATOMIC_LOAD_MIN_I64
+ 0U, // ATOMIC_LOAD_MIN_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_UMAX_I16
+ 0U, // ATOMIC_LOAD_UMAX_I32
+ 0U, // ATOMIC_LOAD_UMAX_I64
+ 0U, // ATOMIC_LOAD_UMAX_I8
+ 0U, // ATOMIC_LOAD_UMIN_I16
+ 0U, // ATOMIC_LOAD_UMIN_I32
+ 0U, // ATOMIC_LOAD_UMIN_I64
+ 0U, // ATOMIC_LOAD_UMIN_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I8
+ 0U, // ATix
+ 1U, // BFIwwii
+ 2U, // BFIxxii
+ 3202U, // BFMwwii
+ 3202U, // BFMxxii
+ 3458U, // BFXILwwii
+ 3458U, // BFXILxxii
+ 128U, // BICSwww_asr
+ 384U, // BICSwww_lsl
+ 640U, // BICSwww_lsr
+ 2944U, // BICSwww_ror
+ 128U, // BICSxxx_asr
+ 384U, // BICSxxx_lsl
+ 640U, // BICSxxx_lsr
+ 2944U, // BICSxxx_ror
+ 0U, // BICvi_lsl_2S
+ 0U, // BICvi_lsl_4H
+ 0U, // BICvi_lsl_4S
+ 0U, // BICvi_lsl_8H
+ 64U, // BICvvv_16B
+ 112U, // BICvvv_8B
+ 128U, // BICwww_asr
+ 384U, // BICwww_lsl
+ 640U, // BICwww_lsr
+ 2944U, // BICwww_ror
+ 128U, // BICxxx_asr
+ 384U, // BICxxx_lsl
+ 640U, // BICxxx_lsr
+ 2944U, // BICxxx_ror
+ 64U, // BIFvvv_16B
+ 112U, // BIFvvv_8B
+ 64U, // BITvvv_16B
+ 112U, // BITvvv_8B
+ 0U, // BLRx
+ 0U, // BLimm
+ 0U, // BRKi
+ 0U, // BRx
+ 64U, // BSLvvv_16B
+ 112U, // BSLvvv_8B
+ 0U, // Bcc
+ 0U, // Bimm
+ 0U, // CBNZw
+ 0U, // CBNZx
+ 0U, // CBZw
+ 0U, // CBZx
+ 3712U, // CCMNwi
+ 3712U, // CCMNww
+ 3712U, // CCMNxi
+ 3712U, // CCMNxx
+ 3712U, // CCMPwi
+ 3712U, // CCMPww
+ 3712U, // CCMPxi
+ 3712U, // CCMPxx
+ 0U, // CLREXi
+ 0U, // CLSww
+ 0U, // CLSxx
+ 0U, // CLZww
+ 0U, // CLZxx
+ 2U, // CMEQvvi_16B
+ 2U, // CMEQvvi_2D
+ 2U, // CMEQvvi_2S
+ 2U, // CMEQvvi_4H
+ 2U, // CMEQvvi_4S
+ 2U, // CMEQvvi_8B
+ 2U, // CMEQvvi_8H
+ 64U, // CMEQvvv_16B
+ 32U, // CMEQvvv_2D
+ 80U, // CMEQvvv_2S
+ 96U, // CMEQvvv_4H
+ 48U, // CMEQvvv_4S
+ 112U, // CMEQvvv_8B
+ 16U, // CMEQvvv_8H
+ 2U, // CMGEvvi_16B
+ 2U, // CMGEvvi_2D
+ 2U, // CMGEvvi_2S
+ 2U, // CMGEvvi_4H
+ 2U, // CMGEvvi_4S
+ 2U, // CMGEvvi_8B
+ 2U, // CMGEvvi_8H
+ 64U, // CMGEvvv_16B
+ 32U, // CMGEvvv_2D
+ 80U, // CMGEvvv_2S
+ 96U, // CMGEvvv_4H
+ 48U, // CMGEvvv_4S
+ 112U, // CMGEvvv_8B
+ 16U, // CMGEvvv_8H
+ 2U, // CMGTvvi_16B
+ 2U, // CMGTvvi_2D
+ 2U, // CMGTvvi_2S
+ 2U, // CMGTvvi_4H
+ 2U, // CMGTvvi_4S
+ 2U, // CMGTvvi_8B
+ 2U, // CMGTvvi_8H
+ 64U, // CMGTvvv_16B
+ 32U, // CMGTvvv_2D
+ 80U, // CMGTvvv_2S
+ 96U, // CMGTvvv_4H
+ 48U, // CMGTvvv_4S
+ 112U, // CMGTvvv_8B
+ 16U, // CMGTvvv_8H
+ 64U, // CMHIvvv_16B
+ 32U, // CMHIvvv_2D
+ 80U, // CMHIvvv_2S
+ 96U, // CMHIvvv_4H
+ 48U, // CMHIvvv_4S
+ 112U, // CMHIvvv_8B
+ 16U, // CMHIvvv_8H
+ 64U, // CMHSvvv_16B
+ 32U, // CMHSvvv_2D
+ 80U, // CMHSvvv_2S
+ 96U, // CMHSvvv_4H
+ 48U, // CMHSvvv_4S
+ 112U, // CMHSvvv_8B
+ 16U, // CMHSvvv_8H
+ 2U, // CMLEvvi_16B
+ 2U, // CMLEvvi_2D
+ 2U, // CMLEvvi_2S
+ 2U, // CMLEvvi_4H
+ 2U, // CMLEvvi_4S
+ 2U, // CMLEvvi_8B
+ 2U, // CMLEvvi_8H
+ 2U, // CMLTvvi_16B
+ 2U, // CMLTvvi_2D
+ 2U, // CMLTvvi_2S
+ 2U, // CMLTvvi_4H
+ 2U, // CMLTvvi_4S
+ 2U, // CMLTvvi_8B
+ 2U, // CMLTvvi_8H
+ 2U, // CMNww_asr
+ 3U, // CMNww_lsl
+ 3U, // CMNww_lsr
+ 3U, // CMNww_sxtb
+ 3U, // CMNww_sxth
+ 4U, // CMNww_sxtw
+ 4U, // CMNww_sxtx
+ 4U, // CMNww_uxtb
+ 4U, // CMNww_uxth
+ 5U, // CMNww_uxtw
+ 5U, // CMNww_uxtx
+ 3U, // CMNxw_sxtb
+ 3U, // CMNxw_sxth
+ 4U, // CMNxw_sxtw
+ 4U, // CMNxw_uxtb
+ 4U, // CMNxw_uxth
+ 5U, // CMNxw_uxtw
+ 2U, // CMNxx_asr
+ 3U, // CMNxx_lsl
+ 3U, // CMNxx_lsr
+ 4U, // CMNxx_sxtx
+ 5U, // CMNxx_uxtx
+ 2U, // CMPww_asr
+ 3U, // CMPww_lsl
+ 3U, // CMPww_lsr
+ 3U, // CMPww_sxtb
+ 3U, // CMPww_sxth
+ 4U, // CMPww_sxtw
+ 4U, // CMPww_sxtx
+ 4U, // CMPww_uxtb
+ 4U, // CMPww_uxth
+ 5U, // CMPww_uxtw
+ 5U, // CMPww_uxtx
+ 3U, // CMPxw_sxtb
+ 3U, // CMPxw_sxth
+ 4U, // CMPxw_sxtw
+ 4U, // CMPxw_uxtb
+ 4U, // CMPxw_uxth
+ 5U, // CMPxw_uxtw
+ 2U, // CMPxx_asr
+ 3U, // CMPxx_lsl
+ 3U, // CMPxx_lsr
+ 4U, // CMPxx_sxtx
+ 5U, // CMPxx_uxtx
+ 64U, // CMTSTvvv_16B
+ 32U, // CMTSTvvv_2D
+ 80U, // CMTSTvvv_2S
+ 96U, // CMTSTvvv_4H
+ 48U, // CMTSTvvv_4S
+ 112U, // CMTSTvvv_8B
+ 16U, // CMTSTvvv_8H
+ 0U, // CRC32B_www
+ 0U, // CRC32CB_www
+ 0U, // CRC32CH_www
+ 0U, // CRC32CW_www
+ 0U, // CRC32CX_wwx
+ 0U, // CRC32H_www
+ 0U, // CRC32W_www
+ 0U, // CRC32X_wwx
+ 3712U, // CSELwwwc
+ 3712U, // CSELxxxc
+ 3712U, // CSINCwwwc
+ 3712U, // CSINCxxxc
+ 3712U, // CSINVwwwc
+ 3712U, // CSINVxxxc
+ 3712U, // CSNEGwwwc
+ 3712U, // CSNEGxxxc
+ 0U, // DCPS1i
+ 0U, // DCPS2i
+ 0U, // DCPS3i
+ 0U, // DCix
+ 0U, // DMBi
+ 0U, // DRPS
+ 0U, // DSBi
+ 128U, // EONwww_asr
+ 384U, // EONwww_lsl
+ 640U, // EONwww_lsr
+ 2944U, // EONwww_ror
+ 128U, // EONxxx_asr
+ 384U, // EONxxx_lsl
+ 640U, // EONxxx_lsr
+ 2944U, // EONxxx_ror
+ 64U, // EORvvv_16B
+ 112U, // EORvvv_8B
+ 1U, // EORwwi
+ 128U, // EORwww_asr
+ 384U, // EORwww_lsl
+ 640U, // EORwww_lsr
+ 2944U, // EORwww_ror
+ 1U, // EORxxi
+ 128U, // EORxxx_asr
+ 384U, // EORxxx_lsl
+ 640U, // EORxxx_lsr
+ 2944U, // EORxxx_ror
+ 0U, // ERET
+ 3968U, // EXTRwwwi
+ 3968U, // EXTRxxxi
+ 0U, // F128CSEL
+ 32U, // FABDvvv_2D
+ 80U, // FABDvvv_2S
+ 48U, // FABDvvv_4S
+ 0U, // FABSdd
+ 0U, // FABSss
+ 32U, // FACGEvvv_2D
+ 80U, // FACGEvvv_2S
+ 48U, // FACGEvvv_4S
+ 32U, // FACGTvvv_2D
+ 80U, // FACGTvvv_2S
+ 48U, // FACGTvvv_4S
+ 32U, // FADDP_2D
+ 80U, // FADDP_2S
+ 48U, // FADDP_4S
+ 0U, // FADDPvv_D_2D
+ 0U, // FADDPvv_S_2S
+ 0U, // FADDddd
+ 0U, // FADDsss
+ 32U, // FADDvvv_2D
+ 80U, // FADDvvv_2S
+ 48U, // FADDvvv_4S
+ 3712U, // FCCMPEdd
+ 3712U, // FCCMPEss
+ 3712U, // FCCMPdd
+ 3712U, // FCCMPss
+ 5U, // FCMEQvvi_2D
+ 5U, // FCMEQvvi_2S
+ 5U, // FCMEQvvi_4S
+ 32U, // FCMEQvvv_2D
+ 80U, // FCMEQvvv_2S
+ 48U, // FCMEQvvv_4S
+ 5U, // FCMGEvvi_2D
+ 5U, // FCMGEvvi_2S
+ 5U, // FCMGEvvi_4S
+ 32U, // FCMGEvvv_2D
+ 80U, // FCMGEvvv_2S
+ 48U, // FCMGEvvv_4S
+ 5U, // FCMGTvvi_2D
+ 5U, // FCMGTvvi_2S
+ 5U, // FCMGTvvi_4S
+ 32U, // FCMGTvvv_2D
+ 80U, // FCMGTvvv_2S
+ 48U, // FCMGTvvv_4S
+ 5U, // FCMLEvvi_2D
+ 5U, // FCMLEvvi_2S
+ 5U, // FCMLEvvi_4S
+ 5U, // FCMLTvvi_2D
+ 5U, // FCMLTvvi_2S
+ 5U, // FCMLTvvi_4S
+ 0U, // FCMPdd_quiet
+ 0U, // FCMPdd_sig
+ 0U, // FCMPdi_quiet
+ 0U, // FCMPdi_sig
+ 0U, // FCMPsi_quiet
+ 0U, // FCMPsi_sig
+ 0U, // FCMPss_quiet
+ 0U, // FCMPss_sig
+ 3712U, // FCSELdddc
+ 3712U, // FCSELsssc
+ 0U, // FCVTASwd
+ 0U, // FCVTASws
+ 0U, // FCVTASxd
+ 0U, // FCVTASxs
+ 0U, // FCVTAUwd
+ 0U, // FCVTAUws
+ 0U, // FCVTAUxd
+ 0U, // FCVTAUxs
+ 0U, // FCVTMSwd
+ 0U, // FCVTMSws
+ 0U, // FCVTMSxd
+ 0U, // FCVTMSxs
+ 0U, // FCVTMUwd
+ 0U, // FCVTMUws
+ 0U, // FCVTMUxd
+ 0U, // FCVTMUxs
+ 0U, // FCVTNSwd
+ 0U, // FCVTNSws
+ 0U, // FCVTNSxd
+ 0U, // FCVTNSxs
+ 0U, // FCVTNUwd
+ 0U, // FCVTNUws
+ 0U, // FCVTNUxd
+ 0U, // FCVTNUxs
+ 0U, // FCVTPSwd
+ 0U, // FCVTPSws
+ 0U, // FCVTPSxd
+ 0U, // FCVTPSxs
+ 0U, // FCVTPUwd
+ 0U, // FCVTPUws
+ 0U, // FCVTPUxd
+ 0U, // FCVTPUxs
+ 0U, // FCVTZSwd
+ 5U, // FCVTZSwdi
+ 0U, // FCVTZSws
+ 5U, // FCVTZSwsi
+ 0U, // FCVTZSxd
+ 5U, // FCVTZSxdi
+ 0U, // FCVTZSxs
+ 5U, // FCVTZSxsi
+ 0U, // FCVTZUwd
+ 5U, // FCVTZUwdi
+ 0U, // FCVTZUws
+ 5U, // FCVTZUwsi
+ 0U, // FCVTZUxd
+ 5U, // FCVTZUxdi
+ 0U, // FCVTZUxs
+ 5U, // FCVTZUxsi
+ 0U, // FCVTdh
+ 0U, // FCVTds
+ 0U, // FCVThd
+ 0U, // FCVThs
+ 0U, // FCVTsd
+ 0U, // FCVTsh
+ 0U, // FDIVddd
+ 0U, // FDIVsss
+ 32U, // FDIVvvv_2D
+ 80U, // FDIVvvv_2S
+ 48U, // FDIVvvv_4S
+ 3968U, // FMADDdddd
+ 3968U, // FMADDssss
+ 0U, // FMAXNMPvv_D_2D
+ 0U, // FMAXNMPvv_S_2S
+ 32U, // FMAXNMPvvv_2D
+ 80U, // FMAXNMPvvv_2S
+ 48U, // FMAXNMPvvv_4S
+ 0U, // FMAXNMddd
+ 0U, // FMAXNMsss
+ 32U, // FMAXNMvvv_2D
+ 80U, // FMAXNMvvv_2S
+ 48U, // FMAXNMvvv_4S
+ 0U, // FMAXPvv_D_2D
+ 0U, // FMAXPvv_S_2S
+ 32U, // FMAXPvvv_2D
+ 80U, // FMAXPvvv_2S
+ 48U, // FMAXPvvv_4S
+ 0U, // FMAXddd
+ 0U, // FMAXsss
+ 32U, // FMAXvvv_2D
+ 80U, // FMAXvvv_2S
+ 48U, // FMAXvvv_4S
+ 0U, // FMINNMPvv_D_2D
+ 0U, // FMINNMPvv_S_2S
+ 32U, // FMINNMPvvv_2D
+ 80U, // FMINNMPvvv_2S
+ 48U, // FMINNMPvvv_4S
+ 0U, // FMINNMddd
+ 0U, // FMINNMsss
+ 32U, // FMINNMvvv_2D
+ 80U, // FMINNMvvv_2S
+ 48U, // FMINNMvvv_4S
+ 0U, // FMINPvv_D_2D
+ 0U, // FMINPvv_S_2S
+ 32U, // FMINPvvv_2D
+ 80U, // FMINPvvv_2S
+ 48U, // FMINPvvv_4S
+ 0U, // FMINddd
+ 0U, // FMINsss
+ 32U, // FMINvvv_2D
+ 80U, // FMINvvv_2S
+ 48U, // FMINvvv_4S
+ 32U, // FMLAvvv_2D
+ 80U, // FMLAvvv_2S
+ 48U, // FMLAvvv_4S
+ 32U, // FMLSvvv_2D
+ 80U, // FMLSvvv_2S
+ 48U, // FMLSvvv_4S
+ 0U, // FMOVdd
+ 0U, // FMOVdi
+ 0U, // FMOVdx
+ 0U, // FMOVsi
+ 0U, // FMOVss
+ 0U, // FMOVsw
+ 0U, // FMOVvi_2D
+ 0U, // FMOVvi_2S
+ 0U, // FMOVvi_4S
+ 0U, // FMOVvx
+ 0U, // FMOVws
+ 0U, // FMOVxd
+ 6U, // FMOVxv
+ 3968U, // FMSUBdddd
+ 3968U, // FMSUBssss
+ 32U, // FMULXvvv_2D
+ 80U, // FMULXvvv_2S
+ 48U, // FMULXvvv_4S
+ 0U, // FMULddd
+ 0U, // FMULsss
+ 32U, // FMULvvv_2D
+ 80U, // FMULvvv_2S
+ 48U, // FMULvvv_4S
+ 0U, // FNEGdd
+ 0U, // FNEGss
+ 3968U, // FNMADDdddd
+ 3968U, // FNMADDssss
+ 3968U, // FNMSUBdddd
+ 3968U, // FNMSUBssss
+ 0U, // FNMULddd
+ 0U, // FNMULsss
+ 32U, // FRECPSvvv_2D
+ 80U, // FRECPSvvv_2S
+ 48U, // FRECPSvvv_4S
+ 0U, // FRINTAdd
+ 0U, // FRINTAss
+ 0U, // FRINTIdd
+ 0U, // FRINTIss
+ 0U, // FRINTMdd
+ 0U, // FRINTMss
+ 0U, // FRINTNdd
+ 0U, // FRINTNss
+ 0U, // FRINTPdd
+ 0U, // FRINTPss
+ 0U, // FRINTXdd
+ 0U, // FRINTXss
+ 0U, // FRINTZdd
+ 0U, // FRINTZss
+ 32U, // FRSQRTSvvv_2D
+ 80U, // FRSQRTSvvv_2S
+ 48U, // FRSQRTSvvv_4S
+ 0U, // FSQRTdd
+ 0U, // FSQRTss
+ 0U, // FSUBddd
+ 0U, // FSUBsss
+ 32U, // FSUBvvv_2D
+ 80U, // FSUBvvv_2S
+ 48U, // FSUBvvv_4S
+ 0U, // HINTi
+ 0U, // HLTi
+ 0U, // HVCi
+ 0U, // ICi
+ 0U, // ICix
+ 6U, // INSELb
+ 0U, // INSELd
+ 6U, // INSELh
+ 6U, // INSELs
+ 0U, // INSbw
+ 0U, // INSdx
+ 0U, // INShw
+ 0U, // INSsw
+ 0U, // ISBi
+ 0U, // LDAR_byte
+ 0U, // LDAR_dword
+ 0U, // LDAR_hword
+ 0U, // LDAR_word
+ 144U, // LDAXP_dword
+ 144U, // LDAXP_word
+ 0U, // LDAXR_byte
+ 0U, // LDAXR_dword
+ 0U, // LDAXR_hword
+ 0U, // LDAXR_word
+ 4224U, // LDPSWx
+ 4514U, // LDPSWx_PostInd
+ 20866U, // LDPSWx_PreInd
+ 6U, // LDRSBw
+ 0U, // LDRSBw_PostInd
+ 6U, // LDRSBw_PreInd
+ 7U, // LDRSBw_U
+ 4736U, // LDRSBw_Wm_RegOffset
+ 4992U, // LDRSBw_Xm_RegOffset
+ 6U, // LDRSBx
+ 0U, // LDRSBx_PostInd
+ 6U, // LDRSBx_PreInd
+ 7U, // LDRSBx_U
+ 4736U, // LDRSBx_Wm_RegOffset
+ 4992U, // LDRSBx_Xm_RegOffset
+ 7U, // LDRSHw
+ 0U, // LDRSHw_PostInd
+ 6U, // LDRSHw_PreInd
+ 7U, // LDRSHw_U
+ 5248U, // LDRSHw_Wm_RegOffset
+ 5504U, // LDRSHw_Xm_RegOffset
+ 7U, // LDRSHx
+ 0U, // LDRSHx_PostInd
+ 6U, // LDRSHx_PreInd
+ 7U, // LDRSHx_U
+ 5248U, // LDRSHx_Wm_RegOffset
+ 5504U, // LDRSHx_Xm_RegOffset
+ 7U, // LDRSWx
+ 0U, // LDRSWx_PostInd
+ 6U, // LDRSWx_PreInd
+ 5760U, // LDRSWx_Wm_RegOffset
+ 6016U, // LDRSWx_Xm_RegOffset
+ 0U, // LDRSWx_lit
+ 0U, // LDRd_lit
+ 0U, // LDRq_lit
+ 0U, // LDRs_lit
+ 0U, // LDRw_lit
+ 0U, // LDRx_lit
+ 7U, // LDTRSBw
+ 7U, // LDTRSBx
+ 7U, // LDTRSHw
+ 7U, // LDTRSHx
+ 7U, // LDTRSWx
+ 7U, // LDURSWx
+ 144U, // LDXP_dword
+ 144U, // LDXP_word
+ 0U, // LDXR_byte
+ 0U, // LDXR_dword
+ 0U, // LDXR_hword
+ 0U, // LDXR_word
+ 7U, // LS16_LDR
+ 7U, // LS16_LDUR
+ 0U, // LS16_PostInd_LDR
+ 0U, // LS16_PostInd_STR
+ 6U, // LS16_PreInd_LDR
+ 6U, // LS16_PreInd_STR
+ 7U, // LS16_STR
+ 7U, // LS16_STUR
+ 7U, // LS16_UnPriv_LDR
+ 7U, // LS16_UnPriv_STR
+ 5248U, // LS16_Wm_RegOffset_LDR
+ 5248U, // LS16_Wm_RegOffset_STR
+ 5504U, // LS16_Xm_RegOffset_LDR
+ 5504U, // LS16_Xm_RegOffset_STR
+ 7U, // LS32_LDR
+ 7U, // LS32_LDUR
+ 0U, // LS32_PostInd_LDR
+ 0U, // LS32_PostInd_STR
+ 6U, // LS32_PreInd_LDR
+ 6U, // LS32_PreInd_STR
+ 7U, // LS32_STR
+ 7U, // LS32_STUR
+ 7U, // LS32_UnPriv_LDR
+ 7U, // LS32_UnPriv_STR
+ 5760U, // LS32_Wm_RegOffset_LDR
+ 5760U, // LS32_Wm_RegOffset_STR
+ 6016U, // LS32_Xm_RegOffset_LDR
+ 6016U, // LS32_Xm_RegOffset_STR
+ 7U, // LS64_LDR
+ 7U, // LS64_LDUR
+ 0U, // LS64_PostInd_LDR
+ 0U, // LS64_PostInd_STR
+ 6U, // LS64_PreInd_LDR
+ 6U, // LS64_PreInd_STR
+ 7U, // LS64_STR
+ 7U, // LS64_STUR
+ 7U, // LS64_UnPriv_LDR
+ 7U, // LS64_UnPriv_STR
+ 6272U, // LS64_Wm_RegOffset_LDR
+ 6272U, // LS64_Wm_RegOffset_STR
+ 6528U, // LS64_Xm_RegOffset_LDR
+ 6528U, // LS64_Xm_RegOffset_STR
+ 6U, // LS8_LDR
+ 7U, // LS8_LDUR
+ 0U, // LS8_PostInd_LDR
+ 0U, // LS8_PostInd_STR
+ 6U, // LS8_PreInd_LDR
+ 6U, // LS8_PreInd_STR
+ 6U, // LS8_STR
+ 7U, // LS8_STUR
+ 7U, // LS8_UnPriv_LDR
+ 7U, // LS8_UnPriv_STR
+ 4736U, // LS8_Wm_RegOffset_LDR
+ 4736U, // LS8_Wm_RegOffset_STR
+ 4992U, // LS8_Xm_RegOffset_LDR
+ 4992U, // LS8_Xm_RegOffset_STR
+ 8U, // LSFP128_LDR
+ 7U, // LSFP128_LDUR
+ 0U, // LSFP128_PostInd_LDR
+ 0U, // LSFP128_PostInd_STR
+ 6U, // LSFP128_PreInd_LDR
+ 6U, // LSFP128_PreInd_STR
+ 8U, // LSFP128_STR
+ 7U, // LSFP128_STUR
+ 6784U, // LSFP128_Wm_RegOffset_LDR
+ 6784U, // LSFP128_Wm_RegOffset_STR
+ 7040U, // LSFP128_Xm_RegOffset_LDR
+ 7040U, // LSFP128_Xm_RegOffset_STR
+ 7U, // LSFP16_LDR
+ 7U, // LSFP16_LDUR
+ 0U, // LSFP16_PostInd_LDR
+ 0U, // LSFP16_PostInd_STR
+ 6U, // LSFP16_PreInd_LDR
+ 6U, // LSFP16_PreInd_STR
+ 7U, // LSFP16_STR
+ 7U, // LSFP16_STUR
+ 5248U, // LSFP16_Wm_RegOffset_LDR
+ 5248U, // LSFP16_Wm_RegOffset_STR
+ 5504U, // LSFP16_Xm_RegOffset_LDR
+ 5504U, // LSFP16_Xm_RegOffset_STR
+ 7U, // LSFP32_LDR
+ 7U, // LSFP32_LDUR
+ 0U, // LSFP32_PostInd_LDR
+ 0U, // LSFP32_PostInd_STR
+ 6U, // LSFP32_PreInd_LDR
+ 6U, // LSFP32_PreInd_STR
+ 7U, // LSFP32_STR
+ 7U, // LSFP32_STUR
+ 5760U, // LSFP32_Wm_RegOffset_LDR
+ 5760U, // LSFP32_Wm_RegOffset_STR
+ 6016U, // LSFP32_Xm_RegOffset_LDR
+ 6016U, // LSFP32_Xm_RegOffset_STR
+ 7U, // LSFP64_LDR
+ 7U, // LSFP64_LDUR
+ 0U, // LSFP64_PostInd_LDR
+ 0U, // LSFP64_PostInd_STR
+ 6U, // LSFP64_PreInd_LDR
+ 6U, // LSFP64_PreInd_STR
+ 7U, // LSFP64_STR
+ 7U, // LSFP64_STUR
+ 6272U, // LSFP64_Wm_RegOffset_LDR
+ 6272U, // LSFP64_Wm_RegOffset_STR
+ 6528U, // LSFP64_Xm_RegOffset_LDR
+ 6528U, // LSFP64_Xm_RegOffset_STR
+ 6U, // LSFP8_LDR
+ 7U, // LSFP8_LDUR
+ 0U, // LSFP8_PostInd_LDR
+ 0U, // LSFP8_PostInd_STR
+ 6U, // LSFP8_PreInd_LDR
+ 6U, // LSFP8_PreInd_STR
+ 6U, // LSFP8_STR
+ 7U, // LSFP8_STUR
+ 4736U, // LSFP8_Wm_RegOffset_LDR
+ 4736U, // LSFP8_Wm_RegOffset_STR
+ 4992U, // LSFP8_Xm_RegOffset_LDR
+ 4992U, // LSFP8_Xm_RegOffset_STR
+ 7296U, // LSFPPair128_LDR
+ 7296U, // LSFPPair128_NonTemp_LDR
+ 7296U, // LSFPPair128_NonTemp_STR
+ 7586U, // LSFPPair128_PostInd_LDR
+ 7586U, // LSFPPair128_PostInd_STR
+ 23938U, // LSFPPair128_PreInd_LDR
+ 23938U, // LSFPPair128_PreInd_STR
+ 7296U, // LSFPPair128_STR
+ 4224U, // LSFPPair32_LDR
+ 4224U, // LSFPPair32_NonTemp_LDR
+ 4224U, // LSFPPair32_NonTemp_STR
+ 4514U, // LSFPPair32_PostInd_LDR
+ 4514U, // LSFPPair32_PostInd_STR
+ 20866U, // LSFPPair32_PreInd_LDR
+ 20866U, // LSFPPair32_PreInd_STR
+ 4224U, // LSFPPair32_STR
+ 7808U, // LSFPPair64_LDR
+ 7808U, // LSFPPair64_NonTemp_LDR
+ 7808U, // LSFPPair64_NonTemp_STR
+ 8098U, // LSFPPair64_PostInd_LDR
+ 8098U, // LSFPPair64_PostInd_STR
+ 24450U, // LSFPPair64_PreInd_LDR
+ 24450U, // LSFPPair64_PreInd_STR
+ 7808U, // LSFPPair64_STR
+ 0U, // LSLVwww
+ 0U, // LSLVxxx
+ 0U, // LSLwwi
+ 0U, // LSLxxi
+ 4224U, // LSPair32_LDR
+ 4224U, // LSPair32_NonTemp_LDR
+ 4224U, // LSPair32_NonTemp_STR
+ 4514U, // LSPair32_PostInd_LDR
+ 4514U, // LSPair32_PostInd_STR
+ 20866U, // LSPair32_PreInd_LDR
+ 20866U, // LSPair32_PreInd_STR
+ 4224U, // LSPair32_STR
+ 7808U, // LSPair64_LDR
+ 7808U, // LSPair64_NonTemp_LDR
+ 7808U, // LSPair64_NonTemp_STR
+ 8098U, // LSPair64_PostInd_LDR
+ 8098U, // LSPair64_PostInd_STR
+ 24450U, // LSPair64_PreInd_LDR
+ 24450U, // LSPair64_PreInd_STR
+ 7808U, // LSPair64_STR
+ 0U, // LSRVwww
+ 0U, // LSRVxxx
+ 0U, // LSRwwi
+ 0U, // LSRxxi
+ 3968U, // MADDwwww
+ 3968U, // MADDxxxx
+ 64U, // MLAvvv_16B
+ 80U, // MLAvvv_2S
+ 96U, // MLAvvv_4H
+ 48U, // MLAvvv_4S
+ 112U, // MLAvvv_8B
+ 16U, // MLAvvv_8H
+ 64U, // MLSvvv_16B
+ 80U, // MLSvvv_2S
+ 96U, // MLSvvv_4H
+ 48U, // MLSvvv_4S
+ 112U, // MLSvvv_8B
+ 16U, // MLSvvv_8H
+ 0U, // MOVIdi
+ 0U, // MOVIvi_16B
+ 0U, // MOVIvi_2D
+ 0U, // MOVIvi_8B
+ 0U, // MOVIvi_lsl_2S
+ 0U, // MOVIvi_lsl_4H
+ 0U, // MOVIvi_lsl_4S
+ 0U, // MOVIvi_lsl_8H
+ 0U, // MOVIvi_msl_2S
+ 0U, // MOVIvi_msl_4S
+ 0U, // MOVKwii
+ 0U, // MOVKxii
+ 0U, // MOVNwii
+ 0U, // MOVNxii
+ 0U, // MOVZwii
+ 0U, // MOVZxii
+ 0U, // MRSxi
+ 0U, // MSRii
+ 0U, // MSRix
+ 3968U, // MSUBwwww
+ 3968U, // MSUBxxxx
+ 64U, // MULvvv_16B
+ 80U, // MULvvv_2S
+ 96U, // MULvvv_4H
+ 48U, // MULvvv_4S
+ 112U, // MULvvv_8B
+ 16U, // MULvvv_8H
+ 0U, // MVNIvi_lsl_2S
+ 0U, // MVNIvi_lsl_4H
+ 0U, // MVNIvi_lsl_4S
+ 0U, // MVNIvi_lsl_8H
+ 0U, // MVNIvi_msl_2S
+ 0U, // MVNIvi_msl_4S
+ 2U, // MVNww_asr
+ 3U, // MVNww_lsl
+ 3U, // MVNww_lsr
+ 8U, // MVNww_ror
+ 2U, // MVNxx_asr
+ 3U, // MVNxx_lsl
+ 3U, // MVNxx_lsr
+ 8U, // MVNxx_ror
+ 64U, // ORNvvv_16B
+ 112U, // ORNvvv_8B
+ 128U, // ORNwww_asr
+ 384U, // ORNwww_lsl
+ 640U, // ORNwww_lsr
+ 2944U, // ORNwww_ror
+ 128U, // ORNxxx_asr
+ 384U, // ORNxxx_lsl
+ 640U, // ORNxxx_lsr
+ 2944U, // ORNxxx_ror
+ 0U, // ORRvi_lsl_2S
+ 0U, // ORRvi_lsl_4H
+ 0U, // ORRvi_lsl_4S
+ 0U, // ORRvi_lsl_8H
+ 64U, // ORRvvv_16B
+ 112U, // ORRvvv_8B
+ 1U, // ORRwwi
+ 128U, // ORRwww_asr
+ 384U, // ORRwww_lsl
+ 640U, // ORRwww_lsr
+ 2944U, // ORRwww_ror
+ 1U, // ORRxxi
+ 128U, // ORRxxx_asr
+ 384U, // ORRxxx_lsl
+ 640U, // ORRxxx_lsr
+ 2944U, // ORRxxx_ror
+ 64U, // PMULL2vvv_8h16b
+ 112U, // PMULLvvv_8h8b
+ 64U, // PMULvvv_16B
+ 112U, // PMULvvv_8B
+ 7U, // PRFM
+ 6272U, // PRFM_Wm_RegOffset
+ 6528U, // PRFM_Xm_RegOffset
+ 0U, // PRFM_lit
+ 7U, // PRFUM
+ 2U, // QRSHRUNvvi_16B
+ 0U, // QRSHRUNvvi_2S
+ 0U, // QRSHRUNvvi_4H
+ 2U, // QRSHRUNvvi_4S
+ 0U, // QRSHRUNvvi_8B
+ 2U, // QRSHRUNvvi_8H
+ 2U, // QSHRUNvvi_16B
+ 0U, // QSHRUNvvi_2S
+ 0U, // QSHRUNvvi_4H
+ 2U, // QSHRUNvvi_4S
+ 0U, // QSHRUNvvi_8B
+ 2U, // QSHRUNvvi_8H
+ 16U, // RADDHN2vvv_16b8h
+ 32U, // RADDHN2vvv_4s2d
+ 48U, // RADDHN2vvv_8h4s
+ 32U, // RADDHNvvv_2s2d
+ 48U, // RADDHNvvv_4h4s
+ 16U, // RADDHNvvv_8b8h
+ 0U, // RBITww
+ 0U, // RBITxx
+ 0U, // RET
+ 0U, // RETx
+ 0U, // REV16ww
+ 0U, // REV16xx
+ 0U, // REV32xx
+ 0U, // REVww
+ 0U, // REVxx
+ 0U, // RORVwww
+ 0U, // RORVxxx
+ 2U, // RSHRNvvi_16B
+ 0U, // RSHRNvvi_2S
+ 0U, // RSHRNvvi_4H
+ 2U, // RSHRNvvi_4S
+ 0U, // RSHRNvvi_8B
+ 2U, // RSHRNvvi_8H
+ 16U, // RSUBHN2vvv_16b8h
+ 32U, // RSUBHN2vvv_4s2d
+ 48U, // RSUBHN2vvv_8h4s
+ 32U, // RSUBHNvvv_2s2d
+ 48U, // RSUBHNvvv_4h4s
+ 16U, // RSUBHNvvv_8b8h
+ 48U, // SABAL2vvv_2d2s
+ 16U, // SABAL2vvv_4s4h
+ 64U, // SABAL2vvv_8h8b
+ 80U, // SABALvvv_2d2s
+ 96U, // SABALvvv_4s4h
+ 112U, // SABALvvv_8h8b
+ 64U, // SABAvvv_16B
+ 80U, // SABAvvv_2S
+ 96U, // SABAvvv_4H
+ 48U, // SABAvvv_4S
+ 112U, // SABAvvv_8B
+ 16U, // SABAvvv_8H
+ 48U, // SABDL2vvv_2d2s
+ 16U, // SABDL2vvv_4s4h
+ 64U, // SABDL2vvv_8h8b
+ 80U, // SABDLvvv_2d2s
+ 96U, // SABDLvvv_4s4h
+ 112U, // SABDLvvv_8h8b
+ 64U, // SABDvvv_16B
+ 80U, // SABDvvv_2S
+ 96U, // SABDvvv_4H
+ 48U, // SABDvvv_4S
+ 112U, // SABDvvv_8B
+ 16U, // SABDvvv_8H
+ 48U, // SADDL2vvv_2d4s
+ 16U, // SADDL2vvv_4s8h
+ 64U, // SADDL2vvv_8h16b
+ 80U, // SADDLvvv_2d2s
+ 96U, // SADDLvvv_4s4h
+ 112U, // SADDLvvv_8h8b
+ 48U, // SADDW2vvv_2d4s
+ 16U, // SADDW2vvv_4s8h
+ 64U, // SADDW2vvv_8h16b
+ 80U, // SADDWvvv_2d2s
+ 96U, // SADDWvvv_4s4h
+ 112U, // SADDWvvv_8h8b
+ 0U, // SBCSwww
+ 0U, // SBCSxxx
+ 0U, // SBCwww
+ 0U, // SBCxxx
+ 8U, // SBFIZwwii
+ 8U, // SBFIZxxii
+ 3968U, // SBFMwwii
+ 3968U, // SBFMxxii
+ 8320U, // SBFXwwii
+ 8320U, // SBFXxxii
+ 0U, // SCVTFdw
+ 5U, // SCVTFdwi
+ 0U, // SCVTFdx
+ 5U, // SCVTFdxi
+ 0U, // SCVTFsw
+ 5U, // SCVTFswi
+ 0U, // SCVTFsx
+ 5U, // SCVTFsxi
+ 0U, // SDIVwww
+ 0U, // SDIVxxx
+ 64U, // SHADDvvv_16B
+ 80U, // SHADDvvv_2S
+ 96U, // SHADDvvv_4H
+ 48U, // SHADDvvv_4S
+ 112U, // SHADDvvv_8B
+ 16U, // SHADDvvv_8H
+ 0U, // SHLvvi_16B
+ 0U, // SHLvvi_2D
+ 0U, // SHLvvi_2S
+ 0U, // SHLvvi_4H
+ 0U, // SHLvvi_4S
+ 0U, // SHLvvi_8B
+ 0U, // SHLvvi_8H
+ 2U, // SHRNvvi_16B
+ 0U, // SHRNvvi_2S
+ 0U, // SHRNvvi_4H
+ 2U, // SHRNvvi_4S
+ 0U, // SHRNvvi_8B
+ 2U, // SHRNvvi_8H
+ 64U, // SHSUBvvv_16B
+ 80U, // SHSUBvvv_2S
+ 96U, // SHSUBvvv_4H
+ 48U, // SHSUBvvv_4S
+ 112U, // SHSUBvvv_8B
+ 16U, // SHSUBvvv_8H
+ 2U, // SLIvvi_16B
+ 2U, // SLIvvi_2D
+ 2U, // SLIvvi_2S
+ 2U, // SLIvvi_4H
+ 2U, // SLIvvi_4S
+ 2U, // SLIvvi_8B
+ 2U, // SLIvvi_8H
+ 3968U, // SMADDLxwwx
+ 64U, // SMAXPvvv_16B
+ 80U, // SMAXPvvv_2S
+ 96U, // SMAXPvvv_4H
+ 48U, // SMAXPvvv_4S
+ 112U, // SMAXPvvv_8B
+ 16U, // SMAXPvvv_8H
+ 64U, // SMAXvvv_16B
+ 80U, // SMAXvvv_2S
+ 96U, // SMAXvvv_4H
+ 48U, // SMAXvvv_4S
+ 112U, // SMAXvvv_8B
+ 16U, // SMAXvvv_8H
+ 0U, // SMCi
+ 64U, // SMINPvvv_16B
+ 80U, // SMINPvvv_2S
+ 96U, // SMINPvvv_4H
+ 48U, // SMINPvvv_4S
+ 112U, // SMINPvvv_8B
+ 16U, // SMINPvvv_8H
+ 64U, // SMINvvv_16B
+ 80U, // SMINvvv_2S
+ 96U, // SMINvvv_4H
+ 48U, // SMINvvv_4S
+ 112U, // SMINvvv_8B
+ 16U, // SMINvvv_8H
+ 48U, // SMLAL2vvv_2d4s
+ 16U, // SMLAL2vvv_4s8h
+ 64U, // SMLAL2vvv_8h16b
+ 80U, // SMLALvvv_2d2s
+ 96U, // SMLALvvv_4s4h
+ 112U, // SMLALvvv_8h8b
+ 48U, // SMLSL2vvv_2d4s
+ 16U, // SMLSL2vvv_4s8h
+ 64U, // SMLSL2vvv_8h16b
+ 80U, // SMLSLvvv_2d2s
+ 96U, // SMLSLvvv_4s4h
+ 112U, // SMLSLvvv_8h8b
+ 9U, // SMOVwb
+ 9U, // SMOVwh
+ 9U, // SMOVxb
+ 9U, // SMOVxh
+ 9U, // SMOVxs
+ 3968U, // SMSUBLxwwx
+ 0U, // SMULHxxx
+ 48U, // SMULL2vvv_2d4s
+ 16U, // SMULL2vvv_4s8h
+ 64U, // SMULL2vvv_8h16b
+ 80U, // SMULLvvv_2d2s
+ 96U, // SMULLvvv_4s4h
+ 112U, // SMULLvvv_8h8b
+ 0U, // SQADDbbb
+ 0U, // SQADDddd
+ 0U, // SQADDhhh
+ 0U, // SQADDsss
+ 64U, // SQADDvvv_16B
+ 32U, // SQADDvvv_2D
+ 80U, // SQADDvvv_2S
+ 96U, // SQADDvvv_4H
+ 48U, // SQADDvvv_4S
+ 112U, // SQADDvvv_8B
+ 16U, // SQADDvvv_8H
+ 48U, // SQDMLAL2vvv_2d4s
+ 16U, // SQDMLAL2vvv_4s8h
+ 80U, // SQDMLALvvv_2d2s
+ 96U, // SQDMLALvvv_4s4h
+ 48U, // SQDMLSL2vvv_2d4s
+ 16U, // SQDMLSL2vvv_4s8h
+ 80U, // SQDMLSLvvv_2d2s
+ 96U, // SQDMLSLvvv_4s4h
+ 80U, // SQDMULHvvv_2S
+ 96U, // SQDMULHvvv_4H
+ 48U, // SQDMULHvvv_4S
+ 16U, // SQDMULHvvv_8H
+ 48U, // SQDMULL2vvv_2d4s
+ 16U, // SQDMULL2vvv_4s8h
+ 80U, // SQDMULLvvv_2d2s
+ 96U, // SQDMULLvvv_4s4h
+ 80U, // SQRDMULHvvv_2S
+ 96U, // SQRDMULHvvv_4H
+ 48U, // SQRDMULHvvv_4S
+ 16U, // SQRDMULHvvv_8H
+ 0U, // SQRSHLbbb
+ 0U, // SQRSHLddd
+ 0U, // SQRSHLhhh
+ 0U, // SQRSHLsss
+ 64U, // SQRSHLvvv_16B
+ 32U, // SQRSHLvvv_2D
+ 80U, // SQRSHLvvv_2S
+ 96U, // SQRSHLvvv_4H
+ 48U, // SQRSHLvvv_4S
+ 112U, // SQRSHLvvv_8B
+ 16U, // SQRSHLvvv_8H
+ 2U, // SQRSHRNvvi_16B
+ 0U, // SQRSHRNvvi_2S
+ 0U, // SQRSHRNvvi_4H
+ 2U, // SQRSHRNvvi_4S
+ 0U, // SQRSHRNvvi_8B
+ 2U, // SQRSHRNvvi_8H
+ 0U, // SQSHLUvvi_16B
+ 0U, // SQSHLUvvi_2D
+ 0U, // SQSHLUvvi_2S
+ 0U, // SQSHLUvvi_4H
+ 0U, // SQSHLUvvi_4S
+ 0U, // SQSHLUvvi_8B
+ 0U, // SQSHLUvvi_8H
+ 0U, // SQSHLbbb
+ 0U, // SQSHLddd
+ 0U, // SQSHLhhh
+ 0U, // SQSHLsss
+ 0U, // SQSHLvvi_16B
+ 0U, // SQSHLvvi_2D
+ 0U, // SQSHLvvi_2S
+ 0U, // SQSHLvvi_4H
+ 0U, // SQSHLvvi_4S
+ 0U, // SQSHLvvi_8B
+ 0U, // SQSHLvvi_8H
+ 64U, // SQSHLvvv_16B
+ 32U, // SQSHLvvv_2D
+ 80U, // SQSHLvvv_2S
+ 96U, // SQSHLvvv_4H
+ 48U, // SQSHLvvv_4S
+ 112U, // SQSHLvvv_8B
+ 16U, // SQSHLvvv_8H
+ 2U, // SQSHRNvvi_16B
+ 0U, // SQSHRNvvi_2S
+ 0U, // SQSHRNvvi_4H
+ 2U, // SQSHRNvvi_4S
+ 0U, // SQSHRNvvi_8B
+ 2U, // SQSHRNvvi_8H
+ 0U, // SQSUBbbb
+ 0U, // SQSUBddd
+ 0U, // SQSUBhhh
+ 0U, // SQSUBsss
+ 64U, // SQSUBvvv_16B
+ 32U, // SQSUBvvv_2D
+ 80U, // SQSUBvvv_2S
+ 96U, // SQSUBvvv_4H
+ 48U, // SQSUBvvv_4S
+ 112U, // SQSUBvvv_8B
+ 16U, // SQSUBvvv_8H
+ 64U, // SRHADDvvv_16B
+ 80U, // SRHADDvvv_2S
+ 96U, // SRHADDvvv_4H
+ 48U, // SRHADDvvv_4S
+ 112U, // SRHADDvvv_8B
+ 16U, // SRHADDvvv_8H
+ 2U, // SRIvvi_16B
+ 2U, // SRIvvi_2D
+ 2U, // SRIvvi_2S
+ 2U, // SRIvvi_4H
+ 2U, // SRIvvi_4S
+ 2U, // SRIvvi_8B
+ 2U, // SRIvvi_8H
+ 0U, // SRSHLddd
+ 64U, // SRSHLvvv_16B
+ 32U, // SRSHLvvv_2D
+ 80U, // SRSHLvvv_2S
+ 96U, // SRSHLvvv_4H
+ 48U, // SRSHLvvv_4S
+ 112U, // SRSHLvvv_8B
+ 16U, // SRSHLvvv_8H
+ 0U, // SRSHRvvi_16B
+ 0U, // SRSHRvvi_2D
+ 0U, // SRSHRvvi_2S
+ 0U, // SRSHRvvi_4H
+ 0U, // SRSHRvvi_4S
+ 0U, // SRSHRvvi_8B
+ 0U, // SRSHRvvi_8H
+ 2U, // SRSRAvvi_16B
+ 2U, // SRSRAvvi_2D
+ 2U, // SRSRAvvi_2S
+ 2U, // SRSRAvvi_4H
+ 2U, // SRSRAvvi_4S
+ 2U, // SRSRAvvi_8B
+ 2U, // SRSRAvvi_8H
+ 0U, // SSHLLvvi_16B
+ 0U, // SSHLLvvi_2S
+ 0U, // SSHLLvvi_4H
+ 0U, // SSHLLvvi_4S
+ 0U, // SSHLLvvi_8B
+ 0U, // SSHLLvvi_8H
+ 0U, // SSHLddd
+ 64U, // SSHLvvv_16B
+ 32U, // SSHLvvv_2D
+ 80U, // SSHLvvv_2S
+ 96U, // SSHLvvv_4H
+ 48U, // SSHLvvv_4S
+ 112U, // SSHLvvv_8B
+ 16U, // SSHLvvv_8H
+ 0U, // SSHRvvi_16B
+ 0U, // SSHRvvi_2D
+ 0U, // SSHRvvi_2S
+ 0U, // SSHRvvi_4H
+ 0U, // SSHRvvi_4S
+ 0U, // SSHRvvi_8B
+ 0U, // SSHRvvi_8H
+ 2U, // SSRAvvi_16B
+ 2U, // SSRAvvi_2D
+ 2U, // SSRAvvi_2S
+ 2U, // SSRAvvi_4H
+ 2U, // SSRAvvi_4S
+ 2U, // SSRAvvi_8B
+ 2U, // SSRAvvi_8H
+ 48U, // SSUBL2vvv_2d4s
+ 16U, // SSUBL2vvv_4s8h
+ 64U, // SSUBL2vvv_8h16b
+ 80U, // SSUBLvvv_2d2s
+ 96U, // SSUBLvvv_4s4h
+ 112U, // SSUBLvvv_8h8b
+ 48U, // SSUBW2vvv_2d4s
+ 16U, // SSUBW2vvv_4s8h
+ 64U, // SSUBW2vvv_8h16b
+ 80U, // SSUBWvvv_2d2s
+ 96U, // SSUBWvvv_4s4h
+ 112U, // SSUBWvvv_8h8b
+ 0U, // STLR_byte
+ 0U, // STLR_dword
+ 0U, // STLR_hword
+ 0U, // STLR_word
+ 176U, // STLXP_dword
+ 176U, // STLXP_word
+ 144U, // STLXR_byte
+ 144U, // STLXR_dword
+ 144U, // STLXR_hword
+ 144U, // STLXR_word
+ 176U, // STXP_dword
+ 176U, // STXP_word
+ 144U, // STXR_byte
+ 144U, // STXR_dword
+ 144U, // STXR_hword
+ 144U, // STXR_word
+ 16U, // SUBHN2vvv_16b8h
+ 32U, // SUBHN2vvv_4s2d
+ 48U, // SUBHN2vvv_8h4s
+ 32U, // SUBHNvvv_2s2d
+ 48U, // SUBHNvvv_4h4s
+ 16U, // SUBHNvvv_8b8h
+ 128U, // SUBSwww_asr
+ 384U, // SUBSwww_lsl
+ 640U, // SUBSwww_lsr
+ 896U, // SUBSwww_sxtb
+ 1152U, // SUBSwww_sxth
+ 1408U, // SUBSwww_sxtw
+ 1664U, // SUBSwww_sxtx
+ 1920U, // SUBSwww_uxtb
+ 2176U, // SUBSwww_uxth
+ 2432U, // SUBSwww_uxtw
+ 2688U, // SUBSwww_uxtx
+ 896U, // SUBSxxw_sxtb
+ 1152U, // SUBSxxw_sxth
+ 1408U, // SUBSxxw_sxtw
+ 1920U, // SUBSxxw_uxtb
+ 2176U, // SUBSxxw_uxth
+ 2432U, // SUBSxxw_uxtw
+ 128U, // SUBSxxx_asr
+ 384U, // SUBSxxx_lsl
+ 640U, // SUBSxxx_lsr
+ 1664U, // SUBSxxx_sxtx
+ 2688U, // SUBSxxx_uxtx
+ 0U, // SUBddd
+ 64U, // SUBvvv_16B
+ 32U, // SUBvvv_2D
+ 80U, // SUBvvv_2S
+ 96U, // SUBvvv_4H
+ 48U, // SUBvvv_4S
+ 112U, // SUBvvv_8B
+ 16U, // SUBvvv_8H
+ 0U, // SUBwwi_lsl0_S
+ 0U, // SUBwwi_lsl0_cmp
+ 0U, // SUBwwi_lsl0_s
+ 1U, // SUBwwi_lsl12_S
+ 0U, // SUBwwi_lsl12_cmp
+ 1U, // SUBwwi_lsl12_s
+ 128U, // SUBwww_asr
+ 384U, // SUBwww_lsl
+ 640U, // SUBwww_lsr
+ 896U, // SUBwww_sxtb
+ 1152U, // SUBwww_sxth
+ 1408U, // SUBwww_sxtw
+ 1664U, // SUBwww_sxtx
+ 1920U, // SUBwww_uxtb
+ 2176U, // SUBwww_uxth
+ 2432U, // SUBwww_uxtw
+ 2688U, // SUBwww_uxtx
+ 0U, // SUBxxi_lsl0_S
+ 0U, // SUBxxi_lsl0_cmp
+ 0U, // SUBxxi_lsl0_s
+ 1U, // SUBxxi_lsl12_S
+ 0U, // SUBxxi_lsl12_cmp
+ 1U, // SUBxxi_lsl12_s
+ 896U, // SUBxxw_sxtb
+ 1152U, // SUBxxw_sxth
+ 1408U, // SUBxxw_sxtw
+ 1920U, // SUBxxw_uxtb
+ 2176U, // SUBxxw_uxth
+ 2432U, // SUBxxw_uxtw
+ 128U, // SUBxxx_asr
+ 384U, // SUBxxx_lsl
+ 640U, // SUBxxx_lsr
+ 1664U, // SUBxxx_sxtx
+ 2688U, // SUBxxx_uxtx
+ 0U, // SVCi
+ 0U, // SXTBww
+ 0U, // SXTBxw
+ 0U, // SXTHww
+ 0U, // SXTHxw
+ 0U, // SXTWxw
+ 9U, // SYSLxicci
+ 0U, // SYSiccix
+ 0U, // TAIL_BRx
+ 0U, // TAIL_Bimm
+ 9U, // TBNZwii
+ 9U, // TBNZxii
+ 9U, // TBZwii
+ 9U, // TBZxii
+ 0U, // TC_RETURNdi
+ 0U, // TC_RETURNxi
+ 0U, // TLBIi
+ 0U, // TLBIix
+ 0U, // TLSDESCCALL
+ 0U, // TLSDESC_BLRx
+ 2U, // TSTww_asr
+ 3U, // TSTww_lsl
+ 3U, // TSTww_lsr
+ 8U, // TSTww_ror
+ 2U, // TSTxx_asr
+ 3U, // TSTxx_lsl
+ 3U, // TSTxx_lsr
+ 8U, // TSTxx_ror
+ 48U, // UABAL2vvv_2d2s
+ 16U, // UABAL2vvv_4s4h
+ 64U, // UABAL2vvv_8h8b
+ 80U, // UABALvvv_2d2s
+ 96U, // UABALvvv_4s4h
+ 112U, // UABALvvv_8h8b
+ 64U, // UABAvvv_16B
+ 80U, // UABAvvv_2S
+ 96U, // UABAvvv_4H
+ 48U, // UABAvvv_4S
+ 112U, // UABAvvv_8B
+ 16U, // UABAvvv_8H
+ 48U, // UABDL2vvv_2d2s
+ 16U, // UABDL2vvv_4s4h
+ 64U, // UABDL2vvv_8h8b
+ 80U, // UABDLvvv_2d2s
+ 96U, // UABDLvvv_4s4h
+ 112U, // UABDLvvv_8h8b
+ 64U, // UABDvvv_16B
+ 80U, // UABDvvv_2S
+ 96U, // UABDvvv_4H
+ 48U, // UABDvvv_4S
+ 112U, // UABDvvv_8B
+ 16U, // UABDvvv_8H
+ 48U, // UADDL2vvv_2d4s
+ 16U, // UADDL2vvv_4s8h
+ 64U, // UADDL2vvv_8h16b
+ 80U, // UADDLvvv_2d2s
+ 96U, // UADDLvvv_4s4h
+ 112U, // UADDLvvv_8h8b
+ 48U, // UADDW2vvv_2d4s
+ 16U, // UADDW2vvv_4s8h
+ 64U, // UADDW2vvv_8h16b
+ 80U, // UADDWvvv_2d2s
+ 96U, // UADDWvvv_4s4h
+ 112U, // UADDWvvv_8h8b
+ 8U, // UBFIZwwii
+ 8U, // UBFIZxxii
+ 3968U, // UBFMwwii
+ 3968U, // UBFMxxii
+ 8320U, // UBFXwwii
+ 8320U, // UBFXxxii
+ 0U, // UCVTFdw
+ 5U, // UCVTFdwi
+ 0U, // UCVTFdx
+ 5U, // UCVTFdxi
+ 0U, // UCVTFsw
+ 5U, // UCVTFswi
+ 0U, // UCVTFsx
+ 5U, // UCVTFsxi
+ 0U, // UDIVwww
+ 0U, // UDIVxxx
+ 64U, // UHADDvvv_16B
+ 80U, // UHADDvvv_2S
+ 96U, // UHADDvvv_4H
+ 48U, // UHADDvvv_4S
+ 112U, // UHADDvvv_8B
+ 16U, // UHADDvvv_8H
+ 64U, // UHSUBvvv_16B
+ 80U, // UHSUBvvv_2S
+ 96U, // UHSUBvvv_4H
+ 48U, // UHSUBvvv_4S
+ 112U, // UHSUBvvv_8B
+ 16U, // UHSUBvvv_8H
+ 3968U, // UMADDLxwwx
+ 64U, // UMAXPvvv_16B
+ 80U, // UMAXPvvv_2S
+ 96U, // UMAXPvvv_4H
+ 48U, // UMAXPvvv_4S
+ 112U, // UMAXPvvv_8B
+ 16U, // UMAXPvvv_8H
+ 64U, // UMAXvvv_16B
+ 80U, // UMAXvvv_2S
+ 96U, // UMAXvvv_4H
+ 48U, // UMAXvvv_4S
+ 112U, // UMAXvvv_8B
+ 16U, // UMAXvvv_8H
+ 64U, // UMINPvvv_16B
+ 80U, // UMINPvvv_2S
+ 96U, // UMINPvvv_4H
+ 48U, // UMINPvvv_4S
+ 112U, // UMINPvvv_8B
+ 16U, // UMINPvvv_8H
+ 64U, // UMINvvv_16B
+ 80U, // UMINvvv_2S
+ 96U, // UMINvvv_4H
+ 48U, // UMINvvv_4S
+ 112U, // UMINvvv_8B
+ 16U, // UMINvvv_8H
+ 48U, // UMLAL2vvv_2d4s
+ 16U, // UMLAL2vvv_4s8h
+ 64U, // UMLAL2vvv_8h16b
+ 80U, // UMLALvvv_2d2s
+ 96U, // UMLALvvv_4s4h
+ 112U, // UMLALvvv_8h8b
+ 48U, // UMLSL2vvv_2d4s
+ 16U, // UMLSL2vvv_4s8h
+ 64U, // UMLSL2vvv_8h16b
+ 80U, // UMLSLvvv_2d2s
+ 96U, // UMLSLvvv_4s4h
+ 112U, // UMLSLvvv_8h8b
+ 9U, // UMOVwb
+ 9U, // UMOVwh
+ 9U, // UMOVws
+ 9U, // UMOVxd
+ 3968U, // UMSUBLxwwx
+ 0U, // UMULHxxx
+ 48U, // UMULL2vvv_2d4s
+ 16U, // UMULL2vvv_4s8h
+ 64U, // UMULL2vvv_8h16b
+ 80U, // UMULLvvv_2d2s
+ 96U, // UMULLvvv_4s4h
+ 112U, // UMULLvvv_8h8b
+ 0U, // UQADDbbb
+ 0U, // UQADDddd
+ 0U, // UQADDhhh
+ 0U, // UQADDsss
+ 64U, // UQADDvvv_16B
+ 32U, // UQADDvvv_2D
+ 80U, // UQADDvvv_2S
+ 96U, // UQADDvvv_4H
+ 48U, // UQADDvvv_4S
+ 112U, // UQADDvvv_8B
+ 16U, // UQADDvvv_8H
+ 0U, // UQRSHLbbb
+ 0U, // UQRSHLddd
+ 0U, // UQRSHLhhh
+ 0U, // UQRSHLsss
+ 64U, // UQRSHLvvv_16B
+ 32U, // UQRSHLvvv_2D
+ 80U, // UQRSHLvvv_2S
+ 96U, // UQRSHLvvv_4H
+ 48U, // UQRSHLvvv_4S
+ 112U, // UQRSHLvvv_8B
+ 16U, // UQRSHLvvv_8H
+ 2U, // UQRSHRNvvi_16B
+ 0U, // UQRSHRNvvi_2S
+ 0U, // UQRSHRNvvi_4H
+ 2U, // UQRSHRNvvi_4S
+ 0U, // UQRSHRNvvi_8B
+ 2U, // UQRSHRNvvi_8H
+ 0U, // UQSHLbbb
+ 0U, // UQSHLddd
+ 0U, // UQSHLhhh
+ 0U, // UQSHLsss
+ 0U, // UQSHLvvi_16B
+ 0U, // UQSHLvvi_2D
+ 0U, // UQSHLvvi_2S
+ 0U, // UQSHLvvi_4H
+ 0U, // UQSHLvvi_4S
+ 0U, // UQSHLvvi_8B
+ 0U, // UQSHLvvi_8H
+ 64U, // UQSHLvvv_16B
+ 32U, // UQSHLvvv_2D
+ 80U, // UQSHLvvv_2S
+ 96U, // UQSHLvvv_4H
+ 48U, // UQSHLvvv_4S
+ 112U, // UQSHLvvv_8B
+ 16U, // UQSHLvvv_8H
+ 2U, // UQSHRNvvi_16B
+ 0U, // UQSHRNvvi_2S
+ 0U, // UQSHRNvvi_4H
+ 2U, // UQSHRNvvi_4S
+ 0U, // UQSHRNvvi_8B
+ 2U, // UQSHRNvvi_8H
+ 0U, // UQSUBbbb
+ 0U, // UQSUBddd
+ 0U, // UQSUBhhh
+ 0U, // UQSUBsss
+ 64U, // UQSUBvvv_16B
+ 32U, // UQSUBvvv_2D
+ 80U, // UQSUBvvv_2S
+ 96U, // UQSUBvvv_4H
+ 48U, // UQSUBvvv_4S
+ 112U, // UQSUBvvv_8B
+ 16U, // UQSUBvvv_8H
+ 64U, // URHADDvvv_16B
+ 80U, // URHADDvvv_2S
+ 96U, // URHADDvvv_4H
+ 48U, // URHADDvvv_4S
+ 112U, // URHADDvvv_8B
+ 16U, // URHADDvvv_8H
+ 0U, // URSHLddd
+ 64U, // URSHLvvv_16B
+ 32U, // URSHLvvv_2D
+ 80U, // URSHLvvv_2S
+ 96U, // URSHLvvv_4H
+ 48U, // URSHLvvv_4S
+ 112U, // URSHLvvv_8B
+ 16U, // URSHLvvv_8H
+ 0U, // URSHRvvi_16B
+ 0U, // URSHRvvi_2D
+ 0U, // URSHRvvi_2S
+ 0U, // URSHRvvi_4H
+ 0U, // URSHRvvi_4S
+ 0U, // URSHRvvi_8B
+ 0U, // URSHRvvi_8H
+ 2U, // URSRAvvi_16B
+ 2U, // URSRAvvi_2D
+ 2U, // URSRAvvi_2S
+ 2U, // URSRAvvi_4H
+ 2U, // URSRAvvi_4S
+ 2U, // URSRAvvi_8B
+ 2U, // URSRAvvi_8H
+ 0U, // USHLLvvi_16B
+ 0U, // USHLLvvi_2S
+ 0U, // USHLLvvi_4H
+ 0U, // USHLLvvi_4S
+ 0U, // USHLLvvi_8B
+ 0U, // USHLLvvi_8H
+ 0U, // USHLddd
+ 64U, // USHLvvv_16B
+ 32U, // USHLvvv_2D
+ 80U, // USHLvvv_2S
+ 96U, // USHLvvv_4H
+ 48U, // USHLvvv_4S
+ 112U, // USHLvvv_8B
+ 16U, // USHLvvv_8H
+ 0U, // USHRvvi_16B
+ 0U, // USHRvvi_2D
+ 0U, // USHRvvi_2S
+ 0U, // USHRvvi_4H
+ 0U, // USHRvvi_4S
+ 0U, // USHRvvi_8B
+ 0U, // USHRvvi_8H
+ 2U, // USRAvvi_16B
+ 2U, // USRAvvi_2D
+ 2U, // USRAvvi_2S
+ 2U, // USRAvvi_4H
+ 2U, // USRAvvi_4S
+ 2U, // USRAvvi_8B
+ 2U, // USRAvvi_8H
+ 48U, // USUBL2vvv_2d4s
+ 16U, // USUBL2vvv_4s8h
+ 64U, // USUBL2vvv_8h16b
+ 80U, // USUBLvvv_2d2s
+ 96U, // USUBLvvv_4s4h
+ 112U, // USUBLvvv_8h8b
+ 48U, // USUBW2vvv_2d4s
+ 16U, // USUBW2vvv_4s8h
+ 64U, // USUBW2vvv_8h16b
+ 80U, // USUBWvvv_2d2s
+ 96U, // USUBWvvv_4s4h
+ 112U, // USUBWvvv_8h8b
+ 0U, // UXTBww
+ 0U, // UXTBxw
+ 0U, // UXTHww
+ 0U, // UXTHxw
+ 0U, // VCVTf2xs_2D
+ 0U, // VCVTf2xs_2S
+ 0U, // VCVTf2xs_4S
+ 0U, // VCVTf2xu_2D
+ 0U, // VCVTf2xu_2S
+ 0U, // VCVTf2xu_4S
+ 0U, // VCVTxs2f_2D
+ 0U, // VCVTxs2f_2S
+ 0U, // VCVTxs2f_4S
+ 0U, // VCVTxu2f_2D
+ 0U, // VCVTxu2f_2S
+ 0U, // VCVTxu2f_4S
+ 0U
+ };
+
+ char AsmStrs[] = {
+ /* 0 */ 'd', 'c', 'p', 's', '1', 9, 0,
+ /* 7 */ 'r', 'e', 'v', '3', '2', 9, 0,
+ /* 14 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0,
+ /* 22 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0,
+ /* 30 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0,
+ /* 40 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0,
+ /* 48 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0,
+ /* 56 */ 's', 's', 'u', 'b', 'l', '2', 9, 0,
+ /* 64 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0,
+ /* 72 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0,
+ /* 80 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0,
+ /* 88 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0,
+ /* 96 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0,
+ /* 104 */ 's', 's', 'h', 'l', 'l', '2', 9, 0,
+ /* 112 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0,
+ /* 120 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0,
+ /* 130 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0,
+ /* 138 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0,
+ /* 146 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0,
+ /* 154 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0,
+ /* 164 */ 's', 'm', 'l', 's', 'l', '2', 9, 0,
+ /* 172 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0,
+ /* 180 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0,
+ /* 189 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0,
+ /* 198 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
+ /* 207 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0,
+ /* 216 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
+ /* 226 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0,
+ /* 236 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
+ /* 246 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0,
+ /* 257 */ 'd', 'c', 'p', 's', '2', 9, 0,
+ /* 264 */ 's', 's', 'u', 'b', 'w', '2', 9, 0,
+ /* 272 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0,
+ /* 280 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0,
+ /* 288 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0,
+ /* 296 */ 'd', 'c', 'p', 's', '3', 9, 0,
+ /* 303 */ 'r', 'e', 'v', '1', '6', 9, 0,
+ /* 310 */ 's', 'a', 'b', 'a', 9, 0,
+ /* 316 */ 'u', 'a', 'b', 'a', 9, 0,
+ /* 322 */ 'f', 'm', 'l', 'a', 9, 0,
+ /* 328 */ 's', 'r', 's', 'r', 'a', 9, 0,
+ /* 335 */ 'u', 'r', 's', 'r', 'a', 9, 0,
+ /* 342 */ 's', 's', 'r', 'a', 9, 0,
+ /* 348 */ 'u', 's', 'r', 'a', 9, 0,
+ /* 354 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0,
+ /* 362 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0,
+ /* 370 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0,
+ /* 379 */ 'd', 'm', 'b', 9, 0,
+ /* 384 */ 'l', 'd', 'a', 'r', 'b', 9, 0,
+ /* 391 */ 'l', 'd', 'r', 'b', 9, 0,
+ /* 397 */ 's', 't', 'l', 'r', 'b', 9, 0,
+ /* 404 */ 'l', 'd', 't', 'r', 'b', 9, 0,
+ /* 411 */ 's', 't', 'r', 'b', 9, 0,
+ /* 417 */ 's', 't', 't', 'r', 'b', 9, 0,
+ /* 424 */ 'l', 'd', 'u', 'r', 'b', 9, 0,
+ /* 431 */ 's', 't', 'u', 'r', 'b', 9, 0,
+ /* 438 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0,
+ /* 446 */ 'l', 'd', 'x', 'r', 'b', 9, 0,
+ /* 453 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0,
+ /* 461 */ 's', 't', 'x', 'r', 'b', 9, 0,
+ /* 468 */ 'd', 's', 'b', 9, 0,
+ /* 473 */ 'i', 's', 'b', 9, 0,
+ /* 478 */ 'l', 'd', 'r', 's', 'b', 9, 0,
+ /* 485 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0,
+ /* 493 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0,
+ /* 501 */ 's', 'x', 't', 'b', 9, 0,
+ /* 507 */ 'u', 'x', 't', 'b', 9, 0,
+ /* 513 */ 'f', 's', 'u', 'b', 9, 0,
+ /* 519 */ 's', 'h', 's', 'u', 'b', 9, 0,
+ /* 526 */ 'u', 'h', 's', 'u', 'b', 9, 0,
+ /* 533 */ 'f', 'm', 's', 'u', 'b', 9, 0,
+ /* 540 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0,
+ /* 548 */ 's', 'q', 's', 'u', 'b', 9, 0,
+ /* 555 */ 'u', 'q', 's', 'u', 'b', 9, 0,
+ /* 562 */ 's', 'b', 'c', 9, 0,
+ /* 567 */ 'a', 'd', 'c', 9, 0,
+ /* 572 */ 'b', 'i', 'c', 9, 0,
+ /* 577 */ 's', 'm', 'c', 9, 0,
+ /* 582 */ 'c', 's', 'i', 'n', 'c', 9, 0,
+ /* 589 */ 'h', 'v', 'c', 9, 0,
+ /* 594 */ 's', 'v', 'c', 9, 0,
+ /* 599 */ 'f', 'a', 'b', 'd', 9, 0,
+ /* 605 */ 's', 'a', 'b', 'd', 9, 0,
+ /* 611 */ 'u', 'a', 'b', 'd', 9, 0,
+ /* 617 */ 'f', 'a', 'd', 'd', 9, 0,
+ /* 623 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0,
+ /* 631 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0,
+ /* 639 */ 's', 'h', 'a', 'd', 'd', 9, 0,
+ /* 646 */ 'u', 'h', 'a', 'd', 'd', 9, 0,
+ /* 653 */ 'f', 'm', 'a', 'd', 'd', 9, 0,
+ /* 660 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0,
+ /* 668 */ 's', 'q', 'a', 'd', 'd', 9, 0,
+ /* 675 */ 'u', 'q', 'a', 'd', 'd', 9, 0,
+ /* 682 */ 'a', 'n', 'd', 9, 0,
+ /* 687 */ 'f', 'a', 'c', 'g', 'e', 9, 0,
+ /* 694 */ 'f', 'c', 'm', 'g', 'e', 9, 0,
+ /* 701 */ 'f', 'c', 'm', 'l', 'e', 9, 0,
+ /* 708 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0,
+ /* 716 */ 'f', 'c', 'm', 'p', 'e', 9, 0,
+ /* 723 */ 'b', 'i', 'f', 9, 0,
+ /* 728 */ 's', 'c', 'v', 't', 'f', 9, 0,
+ /* 735 */ 'u', 'c', 'v', 't', 'f', 9, 0,
+ /* 742 */ 'f', 'n', 'e', 'g', 9, 0,
+ /* 748 */ 'c', 's', 'n', 'e', 'g', 9, 0,
+ /* 755 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0,
+ /* 763 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0,
+ /* 772 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0,
+ /* 781 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0,
+ /* 791 */ 's', 'm', 'u', 'l', 'h', 9, 0,
+ /* 798 */ 'u', 'm', 'u', 'l', 'h', 9, 0,
+ /* 805 */ 'l', 'd', 'a', 'r', 'h', 9, 0,
+ /* 812 */ 'l', 'd', 'r', 'h', 9, 0,
+ /* 818 */ 's', 't', 'l', 'r', 'h', 9, 0,
+ /* 825 */ 'l', 'd', 't', 'r', 'h', 9, 0,
+ /* 832 */ 's', 't', 'r', 'h', 9, 0,
+ /* 838 */ 's', 't', 't', 'r', 'h', 9, 0,
+ /* 845 */ 'l', 'd', 'u', 'r', 'h', 9, 0,
+ /* 852 */ 's', 't', 'u', 'r', 'h', 9, 0,
+ /* 859 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0,
+ /* 867 */ 'l', 'd', 'x', 'r', 'h', 9, 0,
+ /* 874 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0,
+ /* 882 */ 's', 't', 'x', 'r', 'h', 9, 0,
+ /* 889 */ 'l', 'd', 'r', 's', 'h', 9, 0,
+ /* 896 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0,
+ /* 904 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0,
+ /* 912 */ 's', 'x', 't', 'h', 9, 0,
+ /* 918 */ 'u', 'x', 't', 'h', 9, 0,
+ /* 924 */ 't', 'l', 'b', 'i', 9, 0,
+ /* 930 */ 'b', 'f', 'i', 9, 0,
+ /* 935 */ 'c', 'm', 'h', 'i', 9, 0,
+ /* 941 */ 's', 'l', 'i', 9, 0,
+ /* 946 */ 's', 'r', 'i', 9, 0,
+ /* 951 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0,
+ /* 959 */ 'm', 'o', 'v', 'i', 9, 0,
+ /* 965 */ 'b', 'r', 'k', 9, 0,
+ /* 970 */ 'm', 'o', 'v', 'k', 9, 0,
+ /* 976 */ 's', 'a', 'b', 'a', 'l', 9, 0,
+ /* 983 */ 'u', 'a', 'b', 'a', 'l', 9, 0,
+ /* 990 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0,
+ /* 999 */ 's', 'm', 'l', 'a', 'l', 9, 0,
+ /* 1006 */ 'u', 'm', 'l', 'a', 'l', 9, 0,
+ /* 1013 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0,
+ /* 1021 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0,
+ /* 1029 */ 's', 's', 'u', 'b', 'l', 9, 0,
+ /* 1036 */ 'u', 's', 'u', 'b', 'l', 9, 0,
+ /* 1043 */ 's', 'a', 'b', 'd', 'l', 9, 0,
+ /* 1050 */ 'u', 'a', 'b', 'd', 'l', 9, 0,
+ /* 1057 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0,
+ /* 1065 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0,
+ /* 1073 */ 's', 'a', 'd', 'd', 'l', 9, 0,
+ /* 1080 */ 'u', 'a', 'd', 'd', 'l', 9, 0,
+ /* 1087 */ 'f', 'c', 's', 'e', 'l', 9, 0,
+ /* 1094 */ 's', 'q', 's', 'h', 'l', 9, 0,
+ /* 1101 */ 'u', 'q', 's', 'h', 'l', 9, 0,
+ /* 1108 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0,
+ /* 1116 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0,
+ /* 1124 */ 's', 'r', 's', 'h', 'l', 9, 0,
+ /* 1131 */ 'u', 'r', 's', 'h', 'l', 9, 0,
+ /* 1138 */ 's', 's', 'h', 'l', 9, 0,
+ /* 1144 */ 'u', 's', 'h', 'l', 9, 0,
+ /* 1150 */ 'b', 'f', 'x', 'i', 'l', 9, 0,
+ /* 1157 */ 's', 's', 'h', 'l', 'l', 9, 0,
+ /* 1164 */ 'u', 's', 'h', 'l', 'l', 9, 0,
+ /* 1171 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0,
+ /* 1180 */ 'p', 'm', 'u', 'l', 'l', 9, 0,
+ /* 1187 */ 's', 'm', 'u', 'l', 'l', 9, 0,
+ /* 1194 */ 'u', 'm', 'u', 'l', 'l', 9, 0,
+ /* 1201 */ 'b', 's', 'l', 9, 0,
+ /* 1206 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0,
+ /* 1215 */ 's', 'm', 'l', 's', 'l', 9, 0,
+ /* 1222 */ 'u', 'm', 'l', 's', 'l', 9, 0,
+ /* 1229 */ 's', 'y', 's', 'l', 9, 0,
+ /* 1235 */ 'f', 'm', 'u', 'l', 9, 0,
+ /* 1241 */ 'f', 'n', 'm', 'u', 'l', 9, 0,
+ /* 1248 */ 'p', 'm', 'u', 'l', 9, 0,
+ /* 1254 */ 's', 'b', 'f', 'm', 9, 0,
+ /* 1260 */ 'u', 'b', 'f', 'm', 9, 0,
+ /* 1266 */ 'p', 'r', 'f', 'm', 9, 0,
+ /* 1272 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0,
+ /* 1280 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0,
+ /* 1288 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0,
+ /* 1296 */ 'p', 'r', 'f', 'u', 'm', 9, 0,
+ /* 1303 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0,
+ /* 1311 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0,
+ /* 1319 */ 'f', 'm', 'i', 'n', 9, 0,
+ /* 1325 */ 's', 'm', 'i', 'n', 9, 0,
+ /* 1331 */ 'u', 'm', 'i', 'n', 9, 0,
+ /* 1337 */ 'c', 'c', 'm', 'n', 9, 0,
+ /* 1343 */ 'e', 'o', 'n', 9, 0,
+ /* 1348 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0,
+ /* 1356 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0,
+ /* 1364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
+ /* 1373 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0,
+ /* 1382 */ 'o', 'r', 'n', 9, 0,
+ /* 1387 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0,
+ /* 1395 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0,
+ /* 1404 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0,
+ /* 1414 */ 'm', 'v', 'n', 9, 0,
+ /* 1419 */ 'm', 'o', 'v', 'n', 9, 0,
+ /* 1425 */ 'f', 'a', 'd', 'd', 'p', 9, 0,
+ /* 1432 */ 'l', 'd', 'p', 9, 0,
+ /* 1437 */ 'f', 'c', 'c', 'm', 'p', 9, 0,
+ /* 1444 */ 'f', 'c', 'm', 'p', 9, 0,
+ /* 1450 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0,
+ /* 1459 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0,
+ /* 1468 */ 'l', 'd', 'n', 'p', 9, 0,
+ /* 1474 */ 'f', 'm', 'i', 'n', 'p', 9, 0,
+ /* 1481 */ 's', 'm', 'i', 'n', 'p', 9, 0,
+ /* 1488 */ 'u', 'm', 'i', 'n', 'p', 9, 0,
+ /* 1495 */ 's', 't', 'n', 'p', 9, 0,
+ /* 1501 */ 'a', 'd', 'r', 'p', 9, 0,
+ /* 1507 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0,
+ /* 1515 */ 's', 't', 'p', 9, 0,
+ /* 1520 */ 'l', 'd', 'a', 'x', 'p', 9, 0,
+ /* 1527 */ 'f', 'm', 'a', 'x', 'p', 9, 0,
+ /* 1534 */ 's', 'm', 'a', 'x', 'p', 9, 0,
+ /* 1541 */ 'u', 'm', 'a', 'x', 'p', 9, 0,
+ /* 1548 */ 'l', 'd', 'x', 'p', 9, 0,
+ /* 1554 */ 's', 't', 'l', 'x', 'p', 9, 0,
+ /* 1561 */ 's', 't', 'x', 'p', 9, 0,
+ /* 1567 */ 'f', 'c', 'm', 'e', 'q', 9, 0,
+ /* 1574 */ 'l', 'd', 'a', 'r', 9, 0,
+ /* 1580 */ 'b', 'r', 9, 0,
+ /* 1584 */ 'a', 'd', 'r', 9, 0,
+ /* 1589 */ 'l', 'd', 'r', 9, 0,
+ /* 1594 */ 's', 'r', 's', 'h', 'r', 9, 0,
+ /* 1601 */ 'u', 'r', 's', 'h', 'r', 9, 0,
+ /* 1608 */ 's', 's', 'h', 'r', 9, 0,
+ /* 1614 */ 'u', 's', 'h', 'r', 9, 0,
+ /* 1620 */ 'b', 'l', 'r', 9, 0,
+ /* 1625 */ 's', 't', 'l', 'r', 9, 0,
+ /* 1631 */ 'e', 'o', 'r', 9, 0,
+ /* 1636 */ 'r', 'o', 'r', 9, 0,
+ /* 1641 */ 'o', 'r', 'r', 9, 0,
+ /* 1646 */ 'a', 's', 'r', 9, 0,
+ /* 1651 */ 'l', 's', 'r', 9, 0,
+ /* 1656 */ 'm', 's', 'r', 9, 0,
+ /* 1661 */ 'l', 'd', 't', 'r', 9, 0,
+ /* 1667 */ 's', 't', 'r', 9, 0,
+ /* 1672 */ 's', 't', 't', 'r', 9, 0,
+ /* 1678 */ 'e', 'x', 't', 'r', 9, 0,
+ /* 1684 */ 'l', 'd', 'u', 'r', 9, 0,
+ /* 1690 */ 's', 't', 'u', 'r', 9, 0,
+ /* 1696 */ 'l', 'd', 'a', 'x', 'r', 9, 0,
+ /* 1703 */ 'l', 'd', 'x', 'r', 9, 0,
+ /* 1709 */ 's', 't', 'l', 'x', 'r', 9, 0,
+ /* 1716 */ 's', 't', 'x', 'r', 9, 0,
+ /* 1722 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0,
+ /* 1730 */ 'f', 'a', 'b', 's', 9, 0,
+ /* 1736 */ 's', 'u', 'b', 's', 9, 0,
+ /* 1742 */ 's', 'b', 'c', 's', 9, 0,
+ /* 1748 */ 'a', 'd', 'c', 's', 9, 0,
+ /* 1754 */ 'b', 'i', 'c', 's', 9, 0,
+ /* 1760 */ 'a', 'd', 'd', 's', 9, 0,
+ /* 1766 */ 'a', 'n', 'd', 's', 9, 0,
+ /* 1772 */ 'c', 'm', 'h', 's', 9, 0,
+ /* 1778 */ 'c', 'l', 's', 9, 0,
+ /* 1783 */ 'f', 'm', 'l', 's', 9, 0,
+ /* 1789 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0,
+ /* 1797 */ 'i', 'n', 's', 9, 0,
+ /* 1802 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0,
+ /* 1810 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0,
+ /* 1818 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0,
+ /* 1826 */ 'm', 'r', 's', 9, 0,
+ /* 1831 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0,
+ /* 1840 */ 's', 'y', 's', 9, 0,
+ /* 1845 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0,
+ /* 1853 */ 'a', 't', 9, 0,
+ /* 1857 */ 'r', 'e', 't', 9, 0,
+ /* 1862 */ 'f', 'a', 'c', 'g', 't', 9, 0,
+ /* 1869 */ 'f', 'c', 'm', 'g', 't', 9, 0,
+ /* 1876 */ 'r', 'b', 'i', 't', 9, 0,
+ /* 1882 */ 'h', 'l', 't', 9, 0,
+ /* 1887 */ 'f', 'c', 'm', 'l', 't', 9, 0,
+ /* 1894 */ 'h', 'i', 'n', 't', 9, 0,
+ /* 1900 */ 'f', 's', 'q', 'r', 't', 9, 0,
+ /* 1907 */ 'c', 'm', 't', 's', 't', 9, 0,
+ /* 1914 */ 'f', 'c', 'v', 't', 9, 0,
+ /* 1920 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0,
+ /* 1928 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0,
+ /* 1936 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0,
+ /* 1944 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0,
+ /* 1952 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0,
+ /* 1960 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0,
+ /* 1968 */ 'r', 'e', 'v', 9, 0,
+ /* 1973 */ 'f', 'd', 'i', 'v', 9, 0,
+ /* 1979 */ 's', 'd', 'i', 'v', 9, 0,
+ /* 1985 */ 'u', 'd', 'i', 'v', 9, 0,
+ /* 1991 */ 'c', 's', 'i', 'n', 'v', 9, 0,
+ /* 1998 */ 'f', 'm', 'o', 'v', 9, 0,
+ /* 2004 */ 's', 'm', 'o', 'v', 9, 0,
+ /* 2010 */ 'u', 'm', 'o', 'v', 9, 0,
+ /* 2016 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0,
+ /* 2024 */ 's', 's', 'u', 'b', 'w', 9, 0,
+ /* 2031 */ 'u', 's', 'u', 'b', 'w', 9, 0,
+ /* 2038 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0,
+ /* 2047 */ 's', 'a', 'd', 'd', 'w', 9, 0,
+ /* 2054 */ 'u', 'a', 'd', 'd', 'w', 9, 0,
+ /* 2061 */ 'l', 'd', 'p', 's', 'w', 9, 0,
+ /* 2068 */ 'l', 'd', 'r', 's', 'w', 9, 0,
+ /* 2075 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0,
+ /* 2083 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0,
+ /* 2091 */ 's', 'x', 't', 'w', 9, 0,
+ /* 2097 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0,
+ /* 2105 */ 'f', 'm', 'a', 'x', 9, 0,
+ /* 2111 */ 's', 'm', 'a', 'x', 9, 0,
+ /* 2117 */ 'u', 'm', 'a', 'x', 9, 0,
+ /* 2123 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0,
+ /* 2132 */ 'c', 'l', 'r', 'e', 'x', 9, 0,
+ /* 2139 */ 's', 'b', 'f', 'x', 9, 0,
+ /* 2145 */ 'u', 'b', 'f', 'x', 9, 0,
+ /* 2151 */ 'f', 'm', 'u', 'l', 'x', 9, 0,
+ /* 2158 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0,
+ /* 2166 */ 'c', 'b', 'z', 9, 0,
+ /* 2171 */ 't', 'b', 'z', 9, 0,
+ /* 2176 */ 's', 'b', 'f', 'i', 'z', 9, 0,
+ /* 2183 */ 'u', 'b', 'f', 'i', 'z', 9, 0,
+ /* 2190 */ 'c', 'l', 'z', 9, 0,
+ /* 2195 */ 'c', 'b', 'n', 'z', 9, 0,
+ /* 2201 */ 't', 'b', 'n', 'z', 9, 0,
+ /* 2207 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0,
+ /* 2215 */ 'm', 'o', 'v', 'z', 9, 0,
+ /* 2221 */ 'm', 'o', 'v', 'i', 9, 32, 0,
+ /* 2228 */ 's', 'q', 's', 'u', 'b', 32, 0,
+ /* 2235 */ 'u', 'q', 's', 'u', 'b', 32, 0,
+ /* 2242 */ 'b', 'i', 'c', 32, 0,
+ /* 2247 */ 's', 'q', 'a', 'd', 'd', 32, 0,
+ /* 2254 */ 'u', 'q', 'a', 'd', 'd', 32, 0,
+ /* 2261 */ 'm', 'v', 'n', 'i', 32, 0,
+ /* 2267 */ 'm', 'o', 'v', 'i', 32, 0,
+ /* 2273 */ 's', 'q', 's', 'h', 'l', 32, 0,
+ /* 2280 */ 'u', 'q', 's', 'h', 'l', 32, 0,
+ /* 2287 */ 's', 'q', 'r', 's', 'h', 'l', 32, 0,
+ /* 2295 */ 'u', 'q', 'r', 's', 'h', 'l', 32, 0,
+ /* 2303 */ 's', 'r', 's', 'h', 'l', 32, 0,
+ /* 2310 */ 'u', 'r', 's', 'h', 'l', 32, 0,
+ /* 2317 */ 's', 's', 'h', 'l', 32, 0,
+ /* 2323 */ 'u', 's', 'h', 'l', 32, 0,
+ /* 2329 */ 'c', 'm', 'n', 32, 0,
+ /* 2334 */ 'f', 'a', 'd', 'd', 'p', 32, 0,
+ /* 2341 */ 'c', 'm', 'p', 32, 0,
+ /* 2346 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 32, 0,
+ /* 2355 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 32, 0,
+ /* 2364 */ 'f', 'm', 'i', 'n', 'p', 32, 0,
+ /* 2371 */ 'f', 'm', 'a', 'x', 'p', 32, 0,
+ /* 2378 */ 'o', 'r', 'r', 32, 0,
+ /* 2383 */ 'b', '.', 0,
+ /* 2386 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 2399 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 2406 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 2416 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 2431 */ 'd', 'r', 'p', 's', 0,
+ /* 2436 */ 'e', 'r', 'e', 't', 0,
+ };
+
+ // Emit the opcode for the instruction.
+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
+ uint64_t Bits = (Bits2 << 32) | Bits1;
+ SStream_concat(O, AsmStrs+(Bits & 4095)-1);
+
+ // printf("Frag-0 : %lu\n", (Bits >> 12) & 15);
+ // Fragment 0 encoded into 4 bits for 15 unique commands.
+ switch ((Bits >> 12) & 15) {
+ default: // unreachable.
+ case 0:
+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET
+ return;
+ break;
+ case 1:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADDSwww_ls...
+ printOperand(MI, 0, O);
+ break;
+ case 2:
+ // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, ADDHNvvv_2s2d, ADDHNv...
+ printVPRRegister(MI, 0, O);
+ break;
+ case 3:
+ // ATix
+ printNamedImmOperand(&AArch64_ATMapper, MI, 0, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // BLimm, Bimm
+ printLabelOperand(MI, 0, O, 26, 4);
+ return;
+ break;
+ case 5:
+ // Bcc
+ printCondCodeOperand(MI, 0, O);
+ SStream_concat(O, " ");
+ printLabelOperand(MI, 1, O, 19, 4);
+ return;
+ break;
+ case 6:
+ // DCix
+ printNamedImmOperand(&AArch64_DCMapper, MI, 0, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 7:
+ // DMBi, DSBi
+ printNamedImmOperand(&AArch64_DBarrierMapper, MI, 0, O);
+ return;
+ break;
+ case 8:
+ // ICi, ICix
+ printNamedImmOperand(&AArch64_ICMapper, MI, 0, O);
+ break;
+ case 9:
+ // ISBi
+ printNamedImmOperand(&AArch64_ISBMapper, MI, 0, O);
+ return;
+ break;
+ case 10:
+ // LS16_PostInd_STR, LS16_PreInd_STR, LS32_PostInd_STR, LS32_PreInd_STR, ...
+ printOperand(MI, 1, O);
+ break;
+ case 11:
+ // MSRii
+ printNamedImmOperand(&AArch64_PStateMapper, MI, 0, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 12:
+ // MSRix
+ printMSROperand(MI, 0, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 13:
+ // PRFM, PRFM_Wm_RegOffset, PRFM_Xm_RegOffset, PRFM_lit, PRFUM
+ printNamedImmOperand(&AArch64_PRFMMapper, MI, 0, O);
+ break;
+ case 14:
+ // TLBIi, TLBIix
+ printNamedImmOperand(&AArch64_TLBIMapper, MI, 0, O);
+ break;
+ }
+
+
+ // printf(">> Frag-1: %lu\n", (Bits >> 16) & 15);
+ // Fragment 1 encoded into 4 bits for 14 unique commands.
+ switch ((Bits >> 16) & 15) {
+ default: // unreachable.
+ case 0:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDPvv_D_2D, ADDSwww_asr, ADDSwww_ls...
+ SStream_concat(O, ", ");
+ break;
+ case 1:
+ // ADDHN2vvv_16b8h, ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_...
+ SStream_concat(O, ".16b, ");
+ break;
+ case 2:
+ // ADDHN2vvv_4s2d, ADDP_4S, ADDvvv_4S, BICvi_lsl_4S, CMEQvvi_4S, CMEQvvv_...
+ SStream_concat(O, ".4s, ");
+ break;
+ case 3:
+ // ADDHN2vvv_8h4s, ADDP_8H, ADDvvv_8H, BICvi_lsl_8H, CMEQvvi_8H, CMEQvvv_...
+ SStream_concat(O, ".8h, ");
+ break;
+ case 4:
+ // ADDHNvvv_2s2d, ADDP_2S, ADDvvv_2S, BICvi_lsl_2S, CMEQvvi_2S, CMEQvvv_2...
+ SStream_concat(O, ".2s, ");
+ break;
+ case 5:
+ // ADDHNvvv_4h4s, ADDP_4H, ADDvvv_4H, BICvi_lsl_4H, CMEQvvi_4H, CMEQvvv_4...
+ SStream_concat(O, ".4h, ");
+ break;
+ case 6:
+ // ADDHNvvv_8b8h, ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BI...
+ SStream_concat(O, ".8b, ");
+ break;
+ case 7:
+ // ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv_2D, CMGEvvi_2D, CMGEvvv_2D, CM...
+ SStream_concat(O, ".2d, ");
+ break;
+ case 8:
+ // BLRx, BRKi, BRx, CLREXi, DCPS1i, DCPS2i, DCPS3i, HINTi, HLTi, HVCi, IC...
+ return;
+ break;
+ case 9:
+ // FMOVvx, INSELd, INSdx
+ SStream_concat(O, ".d[");
+ set_mem_access(MI, true);
+ break;
+ case 10:
+ // INSELb, INSbw
+ SStream_concat(O, ".b[");
+ set_mem_access(MI, true);
+ printNeonUImm8OperandBare(MI, 3, O);
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ break;
+ case 11:
+ // INSELh, INShw
+ SStream_concat(O, ".h[");
+ set_mem_access(MI, true);
+ printNeonUImm8OperandBare(MI, 3, O);
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ break;
+ case 12:
+ // INSELs, INSsw
+ SStream_concat(O, ".s[");
+ set_mem_access(MI, true);
+ printNeonUImm8OperandBare(MI, 3, O);
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ break;
+ case 13:
+ // LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,...
+ SStream_concat(O, ", [");
+ set_mem_access(MI, true);
+ break;
+ }
+
+
+ // printf(">> Frag-2: %lu\n", (Bits >> 20) & 31);
+ // Fragment 2 encoded into 5 bits for 20 unique commands.
+ switch ((Bits >> 20) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls...
+ printOperand(MI, 1, O);
+ break;
+ case 1:
+ // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, BIFvvv_16B, BIFvvv_8B...
+ printVPRRegister(MI, 2, O);
+ break;
+ case 2:
+ // ADDHNvvv_2s2d, ADDHNvvv_4h4s, ADDHNvvv_8b8h, ADDP_16B, ADDP_2D, ADDP_2...
+ printVPRRegister(MI, 1, O);
+ break;
+ case 3:
+ // ADDwwi_lsl0_cmp, ADDxxi_lsl0_cmp, SUBwwi_lsl0_cmp, SUBxxi_lsl0_cmp
+ printAddSubImmLSL0Operand(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // ADDwwi_lsl12_cmp, ADDxxi_lsl12_cmp, SUBwwi_lsl12_cmp, SUBxxi_lsl12_cmp
+ printAddSubImmLSL12Operand(MI, 1, O);
+ return;
+ break;
+ case 5:
+ // ADRPxi
+ printLabelOperand(MI, 1, O, 21, 4096);
+ return;
+ break;
+ case 6:
+ // ADRxi
+ printLabelOperand(MI, 1, O, 21, 1);
+ return;
+ break;
+ case 7:
+ // BFIwwii, BFIxxii, BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, INSbw, INShw...
+ printOperand(MI, 2, O);
+ break;
+ case 8:
+ // BICvi_lsl_2S, BICvi_lsl_4H, BICvi_lsl_4S, BICvi_lsl_8H, ORRvi_lsl_2S, ...
+ printNeonUImm8Operand(MI, 2, O);
+ break;
+ case 9:
+ // CBNZw, CBNZx, CBZw, CBZx, LDRSWx_lit, LDRd_lit, LDRq_lit, LDRs_lit, LD...
+ printLabelOperand(MI, 1, O, 19, 4);
+ return;
+ break;
+ case 10:
+ // FCMPdi_quiet, FCMPdi_sig, FCMPsi_quiet, FCMPsi_sig
+ printFPZeroOperand(MI, 1, O);
+ return;
+ break;
+ case 11:
+ // FMOVdi, FMOVsi, FMOVvi_2D, FMOVvi_2S, FMOVvi_4S
+ printFPImmOperand(MI, 1, O);
+ return;
+ break;
+ case 12:
+ // FMOVvx
+ printBareImmOperand(MI, 2, O);
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 13:
+ // INSELd, INSdx
+ printNeonUImm8OperandBare(MI, 3, O);
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ break;
+ case 14:
+ // MOVIdi, MOVIvi_2D
+ printNeonUImm64MaskOperand(MI, 1, O);
+ return;
+ break;
+ case 15:
+ // MOVIvi_16B, MOVIvi_8B, MOVIvi_lsl_2S, MOVIvi_lsl_4H, MOVIvi_lsl_4S, MO...
+ printNeonUImm8Operand(MI, 1, O);
+ break;
+ case 16:
+ // MOVKwii, MOVKxii
+ printMoveWideImmOperand(MI, 2, O);
+ return;
+ break;
+ case 17:
+ // MOVNwii, MOVNxii, MOVZwii, MOVZxii
+ printMoveWideImmOperand(MI, 1, O);
+ return;
+ break;
+ case 18:
+ // MRSxi
+ printMRSOperand(MI, 1, O);
+ return;
+ break;
+ case 19:
+ // SYSiccix
+ printCRxOperand(MI, 1, O);
+ SStream_concat(O, ", ");
+ printCRxOperand(MI, 2, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 3, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 4, O);
+ return;
+ break;
+ }
+
+
+ // printf(">> Frag-3: %lu\n", (Bits >> 25) & 31);
+ // Fragment 3 encoded into 5 bits for 25 unique commands.
+ switch ((Bits >> 25) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls...
+ SStream_concat(O, ", ");
+ break;
+ case 1:
+ // ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvi_8H, CMEQvv...
+ SStream_concat(O, ".8h, ");
+ break;
+ case 2:
+ // ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvi_2D, CMEQvvv...
+ SStream_concat(O, ".2d, ");
+ break;
+ case 3:
+ // ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvi_4S, CMEQvvv...
+ SStream_concat(O, ".4s, ");
+ break;
+ case 4:
+ // ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ...
+ SStream_concat(O, ".16b, ");
+ break;
+ case 5:
+ // ADDP_2S, ADDvvv_2S, CMEQvvi_2S, CMEQvvv_2S, CMGEvvi_2S, CMGEvvv_2S, CM...
+ SStream_concat(O, ".2s, ");
+ break;
+ case 6:
+ // ADDP_4H, ADDvvv_4H, CMEQvvi_4H, CMEQvvv_4H, CMGEvvi_4H, CMGEvvv_4H, CM...
+ SStream_concat(O, ".4h, ");
+ break;
+ case 7:
+ // ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv...
+ SStream_concat(O, ".8b, ");
+ break;
+ case 8:
+ // ADDPvv_D_2D, FADDPvv_D_2D, FMAXNMPvv_D_2D, FMAXPvv_D_2D, FMINNMPvv_D_2...
+ SStream_concat(O, ".2d");
+ return;
+ break;
+ case 9:
+ // BICvi_lsl_2S, BICvi_lsl_4S, ORRvi_lsl_2S, ORRvi_lsl_4S
+ printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, false);
+ return;
+ break;
+ case 10:
+ // BICvi_lsl_4H, BICvi_lsl_8H, ORRvi_lsl_4H, ORRvi_lsl_8H
+ printNeonMovImmShiftOperand(MI, 3, O, A64SE_LSL, true);
+ return;
+ break;
+ case 11:
+ // CLSww, CLSxx, CLZww, CLZxx, FABSdd, FABSss, FCMPdd_quiet, FCMPdd_sig, ...
+ return;
+ break;
+ case 12:
+ // FADDPvv_S_2S, FMAXNMPvv_S_2S, FMAXPvv_S_2S, FMINNMPvv_S_2S, FMINPvv_S_...
+ SStream_concat(O, ".2s");
+ return;
+ break;
+ case 13:
+ // FMOVxv, UMOVxd
+ SStream_concat(O, ".d[");
+ set_mem_access(MI, true);
+ break;
+ case 14:
+ // INSELb, SMOVwb, SMOVxb, UMOVwb
+ SStream_concat(O, ".b[");
+ set_mem_access(MI, true);
+ break;
+ case 15:
+ // INSELd
+ printVPRRegister(MI, 2, O);
+ SStream_concat(O, ".d[");
+ set_mem_access(MI, true);
+ printNeonUImm8OperandBare(MI, 4, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 16:
+ // INSELh, SMOVwh, SMOVxh, UMOVwh
+ SStream_concat(O, ".h[");
+ set_mem_access(MI, true);
+ break;
+ case 17:
+ // INSELs, SMOVxs, UMOVws
+ SStream_concat(O, ".s[");
+ set_mem_access(MI, true);
+ break;
+ case 18:
+ // INSdx
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 19:
+ // LDAR_byte, LDAR_dword, LDAR_hword, LDAR_word, LDAXR_byte, LDAXR_dword,...
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 20:
+ // LDAXP_dword, LDAXP_word, LDPSWx, LDPSWx_PostInd, LDPSWx_PreInd, LDXP_d...
+ SStream_concat(O, ", [");
+ set_mem_access(MI, true);
+ break;
+ case 21:
+ // LDRSBw_PostInd, LDRSBx_PostInd, LDRSHw_PostInd, LDRSHx_PostInd, LDRSWx...
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ printOffsetSImm9Operand(MI, 3, O);
+ return;
+ break;
+ case 22:
+ // MOVIvi_lsl_2S, MOVIvi_lsl_4S, MVNIvi_lsl_2S, MVNIvi_lsl_4S
+ printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, false);
+ return;
+ break;
+ case 23:
+ // MOVIvi_lsl_4H, MOVIvi_lsl_8H, MVNIvi_lsl_4H, MVNIvi_lsl_8H
+ printNeonMovImmShiftOperand(MI, 2, O, A64SE_LSL, true);
+ return;
+ break;
+ case 24:
+ // MOVIvi_msl_2S, MOVIvi_msl_4S, MVNIvi_msl_2S, MVNIvi_msl_4S
+ printNeonMovImmShiftOperand(MI, 2, O, A64SE_MSL, false);
+ return;
+ break;
+ }
+
+
+ // printf(">> Frag-4: %lu\n", (Bits >> 30) & 63);
+ // Fragment 4 encoded into 6 bits for 39 unique commands.
+ switch ((Bits >> 30) & 63) {
+ default: // unreachable.
+ case 0:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDSwww_asr, ADDSwww_lsl, ADDSwww_ls...
+ printOperand(MI, 2, O);
+ break;
+ case 1:
+ // ADDHN2vvv_16b8h, ADDHN2vvv_4s2d, ADDHN2vvv_8h4s, BIFvvv_16B, BIFvvv_8B...
+ printVPRRegister(MI, 3, O);
+ break;
+ case 2:
+ // ADDHNvvv_2s2d, ADDHNvvv_4h4s, ADDHNvvv_8b8h, ADDP_16B, ADDP_2D, ADDP_2...
+ printVPRRegister(MI, 2, O);
+ break;
+ case 3:
+ // ADDwwi_lsl0_S, ADDwwi_lsl0_s, ADDxxi_lsl0_S, ADDxxi_lsl0_s, SUBwwi_lsl...
+ printAddSubImmLSL0Operand(MI, 2, O);
+ return;
+ break;
+ case 4:
+ // ADDwwi_lsl12_S, ADDwwi_lsl12_s, ADDxxi_lsl12_S, ADDxxi_lsl12_s, SUBwwi...
+ printAddSubImmLSL12Operand(MI, 2, O);
+ return;
+ break;
+ case 5:
+ // ANDSwwi, ANDwwi, EORwwi, ORRwwi
+ printLogicalImmOperand(MI, 2, O, 32);
+ return;
+ break;
+ case 6:
+ // ANDSxxi, ANDxxi, EORxxi, ORRxxi
+ printLogicalImmOperand(MI, 2, O, 64);
+ return;
+ break;
+ case 7:
+ // BFIwwii
+ printBFILSBOperand(MI, 3, O, 32);
+ SStream_concat(O, ", ");
+ printBFIWidthOperand(MI, 4, O);
+ return;
+ break;
+ case 8:
+ // BFIxxii
+ printBFILSBOperand(MI, 3, O, 64);
+ SStream_concat(O, ", ");
+ printBFIWidthOperand(MI, 4, O);
+ return;
+ break;
+ case 9:
+ // BFMwwii, BFMxxii, BFXILwwii, BFXILxxii, LDPSWx_PostInd, LDPSWx_PreInd,...
+ printOperand(MI, 3, O);
+ break;
+ case 10:
+ // CMEQvvi_16B, CMEQvvi_2D, CMEQvvi_2S, CMEQvvi_4H, CMEQvvi_4S, CMEQvvi_8...
+ printNeonUImm0Operand(MI, 2, O);
+ return;
+ break;
+ case 11:
+ // CMNww_asr, CMNxx_asr, CMPww_asr, CMPxx_asr, MVNww_asr, MVNxx_asr, TSTw...
+ printShiftOperand(MI, 2, O, A64SE_ASR);
+ return;
+ break;
+ case 12:
+ // CMNww_lsl, CMNxx_lsl, CMPww_lsl, CMPxx_lsl, MVNww_lsl, MVNxx_lsl, TSTw...
+ printShiftOperand(MI, 2, O, A64SE_LSL);
+ return;
+ break;
+ case 13:
+ // CMNww_lsr, CMNxx_lsr, CMPww_lsr, CMPxx_lsr, MVNww_lsr, MVNxx_lsr, TSTw...
+ printShiftOperand(MI, 2, O, A64SE_LSR);
+ return;
+ break;
+ case 14:
+ // CMNww_sxtb, CMNxw_sxtb, CMPww_sxtb, CMPxw_sxtb
+ printRegExtendOperand(MI, 2, O, A64SE_SXTB);
+ return;
+ break;
+ case 15:
+ // CMNww_sxth, CMNxw_sxth, CMPww_sxth, CMPxw_sxth
+ printRegExtendOperand(MI, 2, O, A64SE_SXTH);
+ return;
+ break;
+ case 16:
+ // CMNww_sxtw, CMNxw_sxtw, CMPww_sxtw, CMPxw_sxtw
+ printRegExtendOperand(MI, 2, O, A64SE_SXTW);
+ return;
+ break;
+ case 17:
+ // CMNww_sxtx, CMNxx_sxtx, CMPww_sxtx, CMPxx_sxtx
+ printRegExtendOperand(MI, 2, O, A64SE_SXTX);
+ return;
+ break;
+ case 18:
+ // CMNww_uxtb, CMNxw_uxtb, CMPww_uxtb, CMPxw_uxtb
+ printRegExtendOperand(MI, 2, O, A64SE_UXTB);
+ return;
+ break;
+ case 19:
+ // CMNww_uxth, CMNxw_uxth, CMPww_uxth, CMPxw_uxth
+ printRegExtendOperand(MI, 2, O, A64SE_UXTH);
+ return;
+ break;
+ case 20:
+ // CMNww_uxtw, CMNxw_uxtw, CMPww_uxtw, CMPxw_uxtw
+ printRegExtendOperand(MI, 2, O, A64SE_UXTW);
+ return;
+ break;
+ case 21:
+ // CMNww_uxtx, CMNxx_uxtx, CMPww_uxtx, CMPxx_uxtx
+ printRegExtendOperand(MI, 2, O, A64SE_UXTX);
+ return;
+ break;
+ case 22:
+ // FCMEQvvi_2D, FCMEQvvi_2S, FCMEQvvi_4S, FCMGEvvi_2D, FCMGEvvi_2S, FCMGE...
+ printFPZeroOperand(MI, 2, O);
+ return;
+ break;
+ case 23:
+ // FCVTZSwdi, FCVTZSwsi, FCVTZSxdi, FCVTZSxsi, FCVTZUwdi, FCVTZUwsi, FCVT...
+ printCVTFixedPosOperand(MI, 2, O);
+ return;
+ break;
+ case 24:
+ // FMOVxv
+ printBareImmOperand(MI, 2, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 25:
+ // INSELb, INSELh, INSELs
+ printNeonUImm8OperandBare(MI, 4, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 26:
+ // LDRSBw, LDRSBx, LS8_LDR, LS8_STR, LSFP8_LDR, LSFP8_STR
+ printOffsetUImm12Operand(MI, 2, O, 1);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 27:
+ // LDRSBw_PreInd, LDRSBx_PreInd, LDRSHw_PreInd, LDRSHx_PreInd, LDRSWx_Pre...
+ printOffsetSImm9Operand(MI, 3, O);
+ SStream_concat(O, "]!");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 28:
+ // LDRSBw_U, LDRSBx_U, LDRSHw_U, LDRSHx_U, LDTRSBw, LDTRSBx, LDTRSHw, LDT...
+ printOffsetSImm9Operand(MI, 2, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 29:
+ // LDRSHw, LDRSHx, LS16_LDR, LS16_STR, LSFP16_LDR, LSFP16_STR
+ printOffsetUImm12Operand(MI, 2, O, 2);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 30:
+ // LDRSWx, LS32_LDR, LS32_STR, LSFP32_LDR, LSFP32_STR
+ printOffsetUImm12Operand(MI, 2, O, 4);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 31:
+ // LS64_LDR, LS64_STR, LSFP64_LDR, LSFP64_STR, PRFM
+ printOffsetUImm12Operand(MI, 2, O, 8);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 32:
+ // LSFP128_LDR, LSFP128_STR
+ printOffsetUImm12Operand(MI, 2, O, 16);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 33:
+ // MVNww_ror, MVNxx_ror, TSTww_ror, TSTxx_ror
+ printShiftOperand(MI, 2, O, A64SE_ROR);
+ return;
+ break;
+ case 34:
+ // SBFIZwwii, UBFIZwwii
+ printBFILSBOperand(MI, 2, O, 32);
+ SStream_concat(O, ", ");
+ printBFIWidthOperand(MI, 3, O);
+ return;
+ break;
+ case 35:
+ // SBFIZxxii, UBFIZxxii
+ printBFILSBOperand(MI, 2, O, 64);
+ SStream_concat(O, ", ");
+ printBFIWidthOperand(MI, 3, O);
+ return;
+ break;
+ case 36:
+ // SMOVwb, SMOVwh, SMOVxb, SMOVxh, SMOVxs, UMOVwb, UMOVwh, UMOVws, UMOVxd
+ printNeonUImm8OperandBare(MI, 2, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 37:
+ // SYSLxicci
+ printCRxOperand(MI, 2, O);
+ SStream_concat(O, ", ");
+ printCRxOperand(MI, 3, O);
+ SStream_concat(O, ", ");
+ printOperand(MI, 4, O);
+ return;
+ break;
+ case 38:
+ // TBNZwii, TBNZxii, TBZwii, TBZxii
+ printLabelOperand(MI, 2, O, 14, 4);
+ return;
+ break;
+ }
+
+
+ // printf(">> Frag-5: %lu\n", (Bits >> 36) & 15);
+ // Fragment 5 encoded into 4 bits for 12 unique commands.
+ switch ((Bits >> 36) & 15) {
+ default: // unreachable.
+ case 0:
+ // ADCSwww, ADCSxxx, ADCwww, ADCxxx, ADDddd, ASRVwww, ASRVxxx, ASRwwi, AS...
+ return;
+ break;
+ case 1:
+ // ADDHN2vvv_16b8h, ADDHNvvv_8b8h, ADDP_8H, ADDvvv_8H, CMEQvvv_8H, CMGEvv...
+ SStream_concat(O, ".8h");
+ return;
+ break;
+ case 2:
+ // ADDHN2vvv_4s2d, ADDHNvvv_2s2d, ADDP_2D, ADDvvv_2D, CMEQvvv_2D, CMGEvvv...
+ SStream_concat(O, ".2d");
+ return;
+ break;
+ case 3:
+ // ADDHN2vvv_8h4s, ADDHNvvv_4h4s, ADDP_4S, ADDvvv_4S, CMEQvvv_4S, CMGEvvv...
+ SStream_concat(O, ".4s");
+ return;
+ break;
+ case 4:
+ // ADDP_16B, ADDvvv_16B, ANDvvv_16B, BICvvv_16B, BIFvvv_16B, BITvvv_16B, ...
+ SStream_concat(O, ".16b");
+ return;
+ break;
+ case 5:
+ // ADDP_2S, ADDvvv_2S, CMEQvvv_2S, CMGEvvv_2S, CMGTvvv_2S, CMHIvvv_2S, CM...
+ SStream_concat(O, ".2s");
+ return;
+ break;
+ case 6:
+ // ADDP_4H, ADDvvv_4H, CMEQvvv_4H, CMGEvvv_4H, CMGTvvv_4H, CMHIvvv_4H, CM...
+ SStream_concat(O, ".4h");
+ return;
+ break;
+ case 7:
+ // ADDP_8B, ADDvvv_8B, ANDvvv_8B, BICvvv_8B, BIFvvv_8B, BITvvv_8B, BSLvvv...
+ SStream_concat(O, ".8b");
+ return;
+ break;
+ case 8:
+ // ADDSwww_asr, ADDSwww_lsl, ADDSwww_lsr, ADDSwww_sxtb, ADDSwww_sxth, ADD...
+ SStream_concat(O, ", ");
+ break;
+ case 9:
+ // LDAXP_dword, LDAXP_word, LDXP_dword, LDXP_word, STLXR_byte, STLXR_dwor...
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 10:
+ // LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP...
+ SStream_concat(O, "], ");
+ set_mem_access(MI, false);
+ break;
+ case 11:
+ // STLXP_dword, STLXP_word, STXP_dword, STXP_word
+ SStream_concat(O, ", [");
+ set_mem_access(MI, true);
+ printOperand(MI, 3, O);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ }
+
+
+ // printf(">> Frag-6: %lu\n", (Bits >> 40) & 63);
+ // Fragment 6 encoded into 6 bits for 33 unique commands.
+ switch ((Bits >> 40) & 63) {
+ default: // unreachable.
+ case 0:
+ // ADDSwww_asr, ADDSxxx_asr, ADDwww_asr, ADDxxx_asr, ANDSwww_asr, ANDSxxx...
+ printShiftOperand(MI, 3, O, A64SE_ASR);
+ return;
+ break;
+ case 1:
+ // ADDSwww_lsl, ADDSxxx_lsl, ADDwww_lsl, ADDxxx_lsl, ANDSwww_lsl, ANDSxxx...
+ printShiftOperand(MI, 3, O, A64SE_LSL);
+ return;
+ break;
+ case 2:
+ // ADDSwww_lsr, ADDSxxx_lsr, ADDwww_lsr, ADDxxx_lsr, ANDSwww_lsr, ANDSxxx...
+ printShiftOperand(MI, 3, O, A64SE_LSR);
+ return;
+ break;
+ case 3:
+ // ADDSwww_sxtb, ADDSxxw_sxtb, ADDwww_sxtb, ADDxxw_sxtb, SUBSwww_sxtb, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_SXTB);
+ return;
+ break;
+ case 4:
+ // ADDSwww_sxth, ADDSxxw_sxth, ADDwww_sxth, ADDxxw_sxth, SUBSwww_sxth, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_SXTH);
+ return;
+ break;
+ case 5:
+ // ADDSwww_sxtw, ADDSxxw_sxtw, ADDwww_sxtw, ADDxxw_sxtw, SUBSwww_sxtw, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_SXTW);
+ return;
+ break;
+ case 6:
+ // ADDSwww_sxtx, ADDSxxx_sxtx, ADDwww_sxtx, ADDxxx_sxtx, SUBSwww_sxtx, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_SXTX);
+ return;
+ break;
+ case 7:
+ // ADDSwww_uxtb, ADDSxxw_uxtb, ADDwww_uxtb, ADDxxw_uxtb, SUBSwww_uxtb, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_UXTB);
+ return;
+ break;
+ case 8:
+ // ADDSwww_uxth, ADDSxxw_uxth, ADDwww_uxth, ADDxxw_uxth, SUBSwww_uxth, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_UXTH);
+ return;
+ break;
+ case 9:
+ // ADDSwww_uxtw, ADDSxxw_uxtw, ADDwww_uxtw, ADDxxw_uxtw, SUBSwww_uxtw, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_UXTW);
+ return;
+ break;
+ case 10:
+ // ADDSwww_uxtx, ADDSxxx_uxtx, ADDwww_uxtx, ADDxxx_uxtx, SUBSwww_uxtx, SU...
+ printRegExtendOperand(MI, 3, O, A64SE_UXTX);
+ return;
+ break;
+ case 11:
+ // ANDSwww_ror, ANDSxxx_ror, ANDwww_ror, ANDxxx_ror, BICSwww_ror, BICSxxx...
+ printShiftOperand(MI, 3, O, A64SE_ROR);
+ return;
+ break;
+ case 12:
+ // BFMwwii, BFMxxii
+ printOperand(MI, 4, O);
+ return;
+ break;
+ case 13:
+ // BFXILwwii, BFXILxxii
+ printBFXWidthOperand(MI, 4, O);
+ return;
+ break;
+ case 14:
+ // CCMNwi, CCMNww, CCMNxi, CCMNxx, CCMPwi, CCMPww, CCMPxi, CCMPxx, CSELww...
+ printCondCodeOperand(MI, 3, O);
+ return;
+ break;
+ case 15:
+ // EXTRwwwi, EXTRxxxi, FMADDdddd, FMADDssss, FMSUBdddd, FMSUBssss, FNMADD...
+ printOperand(MI, 3, O);
+ return;
+ break;
+ case 16:
+ // LDPSWx, LSFPPair32_LDR, LSFPPair32_NonTemp_LDR, LSFPPair32_NonTemp_STR...
+ printSImm7ScaledOperand(MI, 3, O, 4);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 17:
+ // LDPSWx_PostInd, LDPSWx_PreInd, LSFPPair32_PostInd_LDR, LSFPPair32_Post...
+ printSImm7ScaledOperand(MI, 4, O, 4);
+ break;
+ case 18:
+ // LDRSBw_Wm_RegOffset, LDRSBx_Wm_RegOffset, LS8_Wm_RegOffset_LDR, LS8_Wm...
+ printAddrRegExtendOperand(MI, 3, O, 1, 32);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 19:
+ // LDRSBw_Xm_RegOffset, LDRSBx_Xm_RegOffset, LS8_Xm_RegOffset_LDR, LS8_Xm...
+ printAddrRegExtendOperand(MI, 3, O, 1, 64);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 20:
+ // LDRSHw_Wm_RegOffset, LDRSHx_Wm_RegOffset, LS16_Wm_RegOffset_LDR, LS16_...
+ printAddrRegExtendOperand(MI, 3, O, 2, 32);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 21:
+ // LDRSHw_Xm_RegOffset, LDRSHx_Xm_RegOffset, LS16_Xm_RegOffset_LDR, LS16_...
+ printAddrRegExtendOperand(MI, 3, O, 2, 64);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 22:
+ // LDRSWx_Wm_RegOffset, LS32_Wm_RegOffset_LDR, LS32_Wm_RegOffset_STR, LSF...
+ printAddrRegExtendOperand(MI, 3, O, 4, 32);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 23:
+ // LDRSWx_Xm_RegOffset, LS32_Xm_RegOffset_LDR, LS32_Xm_RegOffset_STR, LSF...
+ printAddrRegExtendOperand(MI, 3, O, 4, 64);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 24:
+ // LS64_Wm_RegOffset_LDR, LS64_Wm_RegOffset_STR, LSFP64_Wm_RegOffset_LDR,...
+ printAddrRegExtendOperand(MI, 3, O, 8, 32);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 25:
+ // LS64_Xm_RegOffset_LDR, LS64_Xm_RegOffset_STR, LSFP64_Xm_RegOffset_LDR,...
+ printAddrRegExtendOperand(MI, 3, O, 8, 64);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 26:
+ // LSFP128_Wm_RegOffset_LDR, LSFP128_Wm_RegOffset_STR
+ printAddrRegExtendOperand(MI, 3, O, 16, 32);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 27:
+ // LSFP128_Xm_RegOffset_LDR, LSFP128_Xm_RegOffset_STR
+ printAddrRegExtendOperand(MI, 3, O, 16, 64);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 28:
+ // LSFPPair128_LDR, LSFPPair128_NonTemp_LDR, LSFPPair128_NonTemp_STR, LSF...
+ printSImm7ScaledOperand(MI, 3, O, 16);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 29:
+ // LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFPPair128_PreInd_L...
+ printSImm7ScaledOperand(MI, 4, O, 16);
+ break;
+ case 30:
+ // LSFPPair64_LDR, LSFPPair64_NonTemp_LDR, LSFPPair64_NonTemp_STR, LSFPPa...
+ printSImm7ScaledOperand(MI, 3, O, 8);
+ SStream_concat(O, "]");
+ set_mem_access(MI, false);
+ return;
+ break;
+ case 31:
+ // LSFPPair64_PostInd_LDR, LSFPPair64_PostInd_STR, LSFPPair64_PreInd_LDR,...
+ printSImm7ScaledOperand(MI, 4, O, 8);
+ break;
+ case 32:
+ // SBFXwwii, SBFXxxii, UBFXwwii, UBFXxxii
+ printBFXWidthOperand(MI, 3, O);
+ return;
+ break;
+ }
+
+
+ // printf(">> Frag-7: %lu\n", (Bits >> 46) & 1);
+ // Fragment 7 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 46) & 1) {
+ // LDPSWx_PreInd, LSFPPair128_PreInd_LDR, LSFPPair128_PreInd_STR, LSFPPai...
+ SStream_concat(O, "]!"); // qqq
+ set_mem_access(MI, false);
+ return;
+ } else {
+ // LDPSWx_PostInd, LSFPPair128_PostInd_LDR, LSFPPair128_PostInd_STR, LSFP...
+ return;
+ }
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+static char *getRegisterName(unsigned RegNo)
+{
+ //assert(RegNo && RegNo < 228 && "Invalid register number!");
+
+ static char AsmStrs[] = {
+ /* 0 */ 'b', '1', '0', 0,
+ /* 4 */ 'd', '1', '0', 0,
+ /* 8 */ 'h', '1', '0', 0,
+ /* 12 */ 'q', '1', '0', 0,
+ /* 16 */ 's', '1', '0', 0,
+ /* 20 */ 'w', '1', '0', 0,
+ /* 24 */ 'x', '1', '0', 0,
+ /* 28 */ 'b', '2', '0', 0,
+ /* 32 */ 'd', '2', '0', 0,
+ /* 36 */ 'h', '2', '0', 0,
+ /* 40 */ 'q', '2', '0', 0,
+ /* 44 */ 's', '2', '0', 0,
+ /* 48 */ 'w', '2', '0', 0,
+ /* 52 */ 'x', '2', '0', 0,
+ /* 56 */ 'b', '3', '0', 0,
+ /* 60 */ 'd', '3', '0', 0,
+ /* 64 */ 'h', '3', '0', 0,
+ /* 68 */ 'q', '3', '0', 0,
+ /* 72 */ 's', '3', '0', 0,
+ /* 76 */ 'w', '3', '0', 0,
+ /* 80 */ 'x', '3', '0', 0,
+ /* 84 */ 'b', '0', 0,
+ /* 87 */ 'd', '0', 0,
+ /* 90 */ 'h', '0', 0,
+ /* 93 */ 'q', '0', 0,
+ /* 96 */ 's', '0', 0,
+ /* 99 */ 'w', '0', 0,
+ /* 102 */ 'x', '0', 0,
+ /* 105 */ 'b', '1', '1', 0,
+ /* 109 */ 'd', '1', '1', 0,
+ /* 113 */ 'h', '1', '1', 0,
+ /* 117 */ 'q', '1', '1', 0,
+ /* 121 */ 's', '1', '1', 0,
+ /* 125 */ 'w', '1', '1', 0,
+ /* 129 */ 'x', '1', '1', 0,
+ /* 133 */ 'b', '2', '1', 0,
+ /* 137 */ 'd', '2', '1', 0,
+ /* 141 */ 'h', '2', '1', 0,
+ /* 145 */ 'q', '2', '1', 0,
+ /* 149 */ 's', '2', '1', 0,
+ /* 153 */ 'w', '2', '1', 0,
+ /* 157 */ 'x', '2', '1', 0,
+ /* 161 */ 'b', '3', '1', 0,
+ /* 165 */ 'd', '3', '1', 0,
+ /* 169 */ 'h', '3', '1', 0,
+ /* 173 */ 'q', '3', '1', 0,
+ /* 177 */ 's', '3', '1', 0,
+ /* 181 */ 'b', '1', 0,
+ /* 184 */ 'd', '1', 0,
+ /* 187 */ 'h', '1', 0,
+ /* 190 */ 'q', '1', 0,
+ /* 193 */ 's', '1', 0,
+ /* 196 */ 'w', '1', 0,
+ /* 199 */ 'x', '1', 0,
+ /* 202 */ 'b', '1', '2', 0,
+ /* 206 */ 'd', '1', '2', 0,
+ /* 210 */ 'h', '1', '2', 0,
+ /* 214 */ 'q', '1', '2', 0,
+ /* 218 */ 's', '1', '2', 0,
+ /* 222 */ 'w', '1', '2', 0,
+ /* 226 */ 'x', '1', '2', 0,
+ /* 230 */ 'b', '2', '2', 0,
+ /* 234 */ 'd', '2', '2', 0,
+ /* 238 */ 'h', '2', '2', 0,
+ /* 242 */ 'q', '2', '2', 0,
+ /* 246 */ 's', '2', '2', 0,
+ /* 250 */ 'w', '2', '2', 0,
+ /* 254 */ 'x', '2', '2', 0,
+ /* 258 */ 'b', '2', 0,
+ /* 261 */ 'd', '2', 0,
+ /* 264 */ 'h', '2', 0,
+ /* 267 */ 'q', '2', 0,
+ /* 270 */ 's', '2', 0,
+ /* 273 */ 'w', '2', 0,
+ /* 276 */ 'x', '2', 0,
+ /* 279 */ 'b', '1', '3', 0,
+ /* 283 */ 'd', '1', '3', 0,
+ /* 287 */ 'h', '1', '3', 0,
+ /* 291 */ 'q', '1', '3', 0,
+ /* 295 */ 's', '1', '3', 0,
+ /* 299 */ 'w', '1', '3', 0,
+ /* 303 */ 'x', '1', '3', 0,
+ /* 307 */ 'b', '2', '3', 0,
+ /* 311 */ 'd', '2', '3', 0,
+ /* 315 */ 'h', '2', '3', 0,
+ /* 319 */ 'q', '2', '3', 0,
+ /* 323 */ 's', '2', '3', 0,
+ /* 327 */ 'w', '2', '3', 0,
+ /* 331 */ 'x', '2', '3', 0,
+ /* 335 */ 'b', '3', 0,
+ /* 338 */ 'd', '3', 0,
+ /* 341 */ 'h', '3', 0,
+ /* 344 */ 'q', '3', 0,
+ /* 347 */ 's', '3', 0,
+ /* 350 */ 'w', '3', 0,
+ /* 353 */ 'x', '3', 0,
+ /* 356 */ 'b', '1', '4', 0,
+ /* 360 */ 'd', '1', '4', 0,
+ /* 364 */ 'h', '1', '4', 0,
+ /* 368 */ 'q', '1', '4', 0,
+ /* 372 */ 's', '1', '4', 0,
+ /* 376 */ 'w', '1', '4', 0,
+ /* 380 */ 'x', '1', '4', 0,
+ /* 384 */ 'b', '2', '4', 0,
+ /* 388 */ 'd', '2', '4', 0,
+ /* 392 */ 'h', '2', '4', 0,
+ /* 396 */ 'q', '2', '4', 0,
+ /* 400 */ 's', '2', '4', 0,
+ /* 404 */ 'w', '2', '4', 0,
+ /* 408 */ 'x', '2', '4', 0,
+ /* 412 */ 'b', '4', 0,
+ /* 415 */ 'd', '4', 0,
+ /* 418 */ 'h', '4', 0,
+ /* 421 */ 'q', '4', 0,
+ /* 424 */ 's', '4', 0,
+ /* 427 */ 'w', '4', 0,
+ /* 430 */ 'x', '4', 0,
+ /* 433 */ 'b', '1', '5', 0,
+ /* 437 */ 'd', '1', '5', 0,
+ /* 441 */ 'h', '1', '5', 0,
+ /* 445 */ 'q', '1', '5', 0,
+ /* 449 */ 's', '1', '5', 0,
+ /* 453 */ 'w', '1', '5', 0,
+ /* 457 */ 'x', '1', '5', 0,
+ /* 461 */ 'b', '2', '5', 0,
+ /* 465 */ 'd', '2', '5', 0,
+ /* 469 */ 'h', '2', '5', 0,
+ /* 473 */ 'q', '2', '5', 0,
+ /* 477 */ 's', '2', '5', 0,
+ /* 481 */ 'w', '2', '5', 0,
+ /* 485 */ 'x', '2', '5', 0,
+ /* 489 */ 'b', '5', 0,
+ /* 492 */ 'd', '5', 0,
+ /* 495 */ 'h', '5', 0,
+ /* 498 */ 'q', '5', 0,
+ /* 501 */ 's', '5', 0,
+ /* 504 */ 'w', '5', 0,
+ /* 507 */ 'x', '5', 0,
+ /* 510 */ 'b', '1', '6', 0,
+ /* 514 */ 'd', '1', '6', 0,
+ /* 518 */ 'h', '1', '6', 0,
+ /* 522 */ 'q', '1', '6', 0,
+ /* 526 */ 's', '1', '6', 0,
+ /* 530 */ 'w', '1', '6', 0,
+ /* 534 */ 'x', '1', '6', 0,
+ /* 538 */ 'b', '2', '6', 0,
+ /* 542 */ 'd', '2', '6', 0,
+ /* 546 */ 'h', '2', '6', 0,
+ /* 550 */ 'q', '2', '6', 0,
+ /* 554 */ 's', '2', '6', 0,
+ /* 558 */ 'w', '2', '6', 0,
+ /* 562 */ 'x', '2', '6', 0,
+ /* 566 */ 'b', '6', 0,
+ /* 569 */ 'd', '6', 0,
+ /* 572 */ 'h', '6', 0,
+ /* 575 */ 'q', '6', 0,
+ /* 578 */ 's', '6', 0,
+ /* 581 */ 'w', '6', 0,
+ /* 584 */ 'x', '6', 0,
+ /* 587 */ 'b', '1', '7', 0,
+ /* 591 */ 'd', '1', '7', 0,
+ /* 595 */ 'h', '1', '7', 0,
+ /* 599 */ 'q', '1', '7', 0,
+ /* 603 */ 's', '1', '7', 0,
+ /* 607 */ 'w', '1', '7', 0,
+ /* 611 */ 'x', '1', '7', 0,
+ /* 615 */ 'b', '2', '7', 0,
+ /* 619 */ 'd', '2', '7', 0,
+ /* 623 */ 'h', '2', '7', 0,
+ /* 627 */ 'q', '2', '7', 0,
+ /* 631 */ 's', '2', '7', 0,
+ /* 635 */ 'w', '2', '7', 0,
+ /* 639 */ 'x', '2', '7', 0,
+ /* 643 */ 'b', '7', 0,
+ /* 646 */ 'd', '7', 0,
+ /* 649 */ 'h', '7', 0,
+ /* 652 */ 'q', '7', 0,
+ /* 655 */ 's', '7', 0,
+ /* 658 */ 'w', '7', 0,
+ /* 661 */ 'x', '7', 0,
+ /* 664 */ 'b', '1', '8', 0,
+ /* 668 */ 'd', '1', '8', 0,
+ /* 672 */ 'h', '1', '8', 0,
+ /* 676 */ 'q', '1', '8', 0,
+ /* 680 */ 's', '1', '8', 0,
+ /* 684 */ 'w', '1', '8', 0,
+ /* 688 */ 'x', '1', '8', 0,
+ /* 692 */ 'b', '2', '8', 0,
+ /* 696 */ 'd', '2', '8', 0,
+ /* 700 */ 'h', '2', '8', 0,
+ /* 704 */ 'q', '2', '8', 0,
+ /* 708 */ 's', '2', '8', 0,
+ /* 712 */ 'w', '2', '8', 0,
+ /* 716 */ 'x', '2', '8', 0,
+ /* 720 */ 'b', '8', 0,
+ /* 723 */ 'd', '8', 0,
+ /* 726 */ 'h', '8', 0,
+ /* 729 */ 'q', '8', 0,
+ /* 732 */ 's', '8', 0,
+ /* 735 */ 'w', '8', 0,
+ /* 738 */ 'x', '8', 0,
+ /* 741 */ 'b', '1', '9', 0,
+ /* 745 */ 'd', '1', '9', 0,
+ /* 749 */ 'h', '1', '9', 0,
+ /* 753 */ 'q', '1', '9', 0,
+ /* 757 */ 's', '1', '9', 0,
+ /* 761 */ 'w', '1', '9', 0,
+ /* 765 */ 'x', '1', '9', 0,
+ /* 769 */ 'b', '2', '9', 0,
+ /* 773 */ 'd', '2', '9', 0,
+ /* 777 */ 'h', '2', '9', 0,
+ /* 781 */ 'q', '2', '9', 0,
+ /* 785 */ 's', '2', '9', 0,
+ /* 789 */ 'w', '2', '9', 0,
+ /* 793 */ 'x', '2', '9', 0,
+ /* 797 */ 'b', '9', 0,
+ /* 800 */ 'd', '9', 0,
+ /* 803 */ 'h', '9', 0,
+ /* 806 */ 'q', '9', 0,
+ /* 809 */ 's', '9', 0,
+ /* 812 */ 'w', '9', 0,
+ /* 815 */ 'x', '9', 0,
+ /* 818 */ 'w', 's', 'p', 0,
+ /* 822 */ 'w', 'z', 'r', 0,
+ /* 826 */ 'x', 'z', 'r', 0,
+ /* 830 */ 'n', 'z', 'c', 'v', 0,
+ };
+
+ static uint32_t RegAsmOffset[] = {
+ 830, 818, 822, 819, 826, 84, 181, 258, 335, 412, 489, 566, 643, 720,
+ 797, 0, 105, 202, 279, 356, 433, 510, 587, 664, 741, 28, 133, 230,
+ 307, 384, 461, 538, 615, 692, 769, 56, 161, 87, 184, 261, 338, 415,
+ 492, 569, 646, 723, 800, 4, 109, 206, 283, 360, 437, 514, 591, 668,
+ 745, 32, 137, 234, 311, 388, 465, 542, 619, 696, 773, 60, 165, 90,
+ 187, 264, 341, 418, 495, 572, 649, 726, 803, 8, 113, 210, 287, 364,
+ 441, 518, 595, 672, 749, 36, 141, 238, 315, 392, 469, 546, 623, 700,
+ 777, 64, 169, 93, 190, 267, 344, 421, 498, 575, 652, 729, 806, 12,
+ 117, 214, 291, 368, 445, 522, 599, 676, 753, 40, 145, 242, 319, 396,
+ 473, 550, 627, 704, 781, 68, 173, 96, 193, 270, 347, 424, 501, 578,
+ 655, 732, 809, 16, 121, 218, 295, 372, 449, 526, 603, 680, 757, 44,
+ 149, 246, 323, 400, 477, 554, 631, 708, 785, 72, 177, 99, 196, 273,
+ 350, 427, 504, 581, 658, 735, 812, 20, 125, 222, 299, 376, 453, 530,
+ 607, 684, 761, 48, 153, 250, 327, 404, 481, 558, 635, 712, 789, 76,
+ 102, 199, 276, 353, 430, 507, 584, 661, 738, 815, 24, 129, 226, 303,
+ 380, 457, 534, 611, 688, 765, 52, 157, 254, 331, 408, 485, 562, 639,
+ 716, 793, 80,
+ };
+
+ //assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
+ // "Invalid alt name index for register!");
+ //int i;
+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
+ //printf("*************************\n");
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+static bool printAliasInstr(MCInst *MI, SStream *OS, void *info)
+{
+ char *AsmString;
+
+#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
+
+ MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+
+ switch (MCInst_getOpcode(MI)) {
+ default: return false;
+ case AArch64_ADDSwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "adds $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDSwww_uxtw:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "adds $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDSxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "adds $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDSxxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "adds $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDwwi_lsl0_s:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (ADDwwi_lsl0_s GPR32wsp:$Rd, Rwsp:$Rn, 0)
+ AsmString = "mov $\x01, $\x02";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (ADDwwi_lsl0_s Rwsp:$Rd, GPR32wsp:$Rn, 0)
+ AsmString = "mov $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_ADDwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDwww_uxtw:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDxxi_lsl0_s:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (ADDxxi_lsl0_s GPR64xsp:$Rd, Rxsp:$Rn, 0)
+ AsmString = "mov $\x01, $\x02";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (ADDxxi_lsl0_s Rxsp:$Rd, GPR64xsp:$Rn, 0)
+ AsmString = "mov $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_ADDxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ADDxxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ADDxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "add $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ANDSwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ANDSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "ands $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ANDSxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ANDSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "ands $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ANDwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ANDwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "and $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ANDxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ANDxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "and $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_BICSwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (BICSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "bics $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_BICSxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (BICSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "bics $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_BICwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (BICwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "bic $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_BICxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (BICxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "bic $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_CLREXi:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
+ // (CLREXi 15)
+ AsmString = "clrex";
+ break;
+ }
+ return false;
+ case AArch64_CMNww_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMNww_lsl GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "cmn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMNww_uxtw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMNww_uxtw Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "cmn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMNxx_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMNxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "cmn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMNxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMNxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "cmn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMPww_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMPww_lsl GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "cmp $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMPww_uxtw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMPww_uxtw Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "cmp $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMPxx_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMPxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "cmp $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_CMPxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (CMPxx_uxtx Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "cmp $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_DCPS1i:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (DCPS1i 0)
+ AsmString = "dcps1";
+ break;
+ }
+ return false;
+ case AArch64_DCPS2i:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (DCPS2i 0)
+ AsmString = "dcps2";
+ break;
+ }
+ return false;
+ case AArch64_DCPS3i:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (DCPS3i 0)
+ AsmString = "dcps3";
+ break;
+ }
+ return false;
+ case AArch64_EONwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (EONwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "eon $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_EONxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (EONxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "eon $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_EORwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (EORwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "eor $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_EORxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (EORxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "eor $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_HINTi:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (HINTi 0)
+ AsmString = "nop";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) {
+ // (HINTi 1)
+ AsmString = "yield";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) {
+ // (HINTi 2)
+ AsmString = "wfe";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) {
+ // (HINTi 3)
+ AsmString = "wfi";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) {
+ // (HINTi 4)
+ AsmString = "sev";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) {
+ // (HINTi 5)
+ AsmString = "sevl";
+ break;
+ }
+ return false;
+ case AArch64_ISBi:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) {
+ // (ISBi 15)
+ AsmString = "isb";
+ break;
+ }
+ return false;
+ case AArch64_LDPSWx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldpsw $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSBw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDRSBw GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrsb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSBw_Xm_RegOffset:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LDRSBw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrsb $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSBx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDRSBx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrsb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSBx_Xm_RegOffset:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LDRSBx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrsb $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSHw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDRSHw GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrsh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSHw_Xm_RegOffset:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LDRSHw_Xm_RegOffset GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrsh $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSHx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDRSHx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrsh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSHx_Xm_RegOffset:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LDRSHx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrsh $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSWx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrsw $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDRSWx_Xm_RegOffset:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrsw $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LDTRSBw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDTRSBw GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrsb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDTRSBx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDTRSBx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrsb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDTRSHw:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDTRSHw GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrsh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDTRSHx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDTRSHx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrsh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDTRSWx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrsw $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LDURSWx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldursw $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldurh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "strh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sturh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_UnPriv_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_UnPriv_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS16_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sttrh $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS16_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrh $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS16_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS16_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "strh $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_UnPriv_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_UnPriv_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS32_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sttr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS32_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS32_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS32_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_LDR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_LDUR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_STR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_STUR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_UnPriv_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_UnPriv_LDR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_UnPriv_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS64_UnPriv_STR GPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sttr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS64_Xm_RegOffset_LDR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS64_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS64_Xm_RegOffset_STR GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldrb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_LDUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldurb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "strb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_STUR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sturb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_UnPriv_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_UnPriv_LDR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldtrb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_UnPriv_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LS8_UnPriv_STR GPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "sttrb $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS8_Xm_RegOffset_LDR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldrb $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LS8_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LS8_Xm_RegOffset_STR GPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "strb $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP128_LDR FPR128:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP128_LDUR FPR128:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP128_STR FPR128:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP128_STUR FPR128:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP128_Xm_RegOffset_LDR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP128_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP128_Xm_RegOffset_STR FPR128:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP16_LDR FPR16:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP16_LDUR FPR16:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP16_STR FPR16:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP16_STUR FPR16:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP16_Xm_RegOffset_LDR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP16_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR16RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP16_Xm_RegOffset_STR FPR16:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP32_LDR FPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP32_LDUR FPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP32_STR FPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP32_STUR FPR32:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP32_Xm_RegOffset_LDR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP32_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP32_Xm_RegOffset_STR FPR32:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP64_LDR FPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP64_LDUR FPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP64_STR FPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP64_STUR FPR64:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP64_Xm_RegOffset_LDR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP64_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP64_Xm_RegOffset_STR FPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_LDR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP8_LDR FPR8:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldr $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_LDUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP8_LDUR FPR8:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "ldur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_STR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP8_STR FPR8:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "str $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_STUR:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (LSFP8_STUR FPR8:$Rt, GPR64xsp:$Rn, 0)
+ AsmString = "stur $\x01, [$\x02]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_Xm_RegOffset_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP8_Xm_RegOffset_LDR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "ldr $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFP8_Xm_RegOffset_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR8RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
+ // (LSFP8_Xm_RegOffset_STR FPR8:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)
+ AsmString = "str $\x01, [$\x02, $\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair128_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair128_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair128_NonTemp_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair128_NonTemp_LDR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair128_NonTemp_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair128_NonTemp_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair128_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR128RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair128_STR FPR128:$Rt, FPR128:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair32_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair32_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair32_NonTemp_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair32_NonTemp_LDR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair32_NonTemp_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair32_NonTemp_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair32_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair32_STR FPR32:$Rt, FPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair64_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair64_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair64_NonTemp_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair64_NonTemp_LDR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair64_NonTemp_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair64_NonTemp_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSFPPair64_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_FPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSFPPair64_STR FPR64:$Rt, FPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair32_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair32_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair32_NonTemp_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair32_NonTemp_LDR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair32_NonTemp_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair32_NonTemp_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair32_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair32_STR GPR32:$Rt, GPR32:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair64_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair64_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair64_NonTemp_LDR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair64_NonTemp_LDR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "ldnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair64_NonTemp_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair64_NonTemp_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stnp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_LSPair64_STR:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (LSPair64_STR GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)
+ AsmString = "stp $\x01, $\x02, [$\x03]";
+ break;
+ }
+ return false;
+ case AArch64_MADDwwww:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
+ // (MADDwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR)
+ AsmString = "mul $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_MADDxxxx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (MADDxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR)
+ AsmString = "mul $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_MSUBwwww:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) {
+ // (MSUBwwww GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, WZR)
+ AsmString = "mneg $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_MSUBxxxx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (MSUBxxxx GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, XZR)
+ AsmString = "mneg $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_MVNww_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (MVNww_lsl GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "mvn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_MVNxx_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (MVNxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "mvn $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_ORNwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORNwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "orn $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ORNxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORNxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "orn $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ORRwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
+ AsmString = "mov $\x01, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORRwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "orr $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_ORRxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
+ AsmString = "mov $\x01, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (ORRxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "orr $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_RETx:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_X30) {
+ // (RETx X30)
+ AsmString = "ret";
+ break;
+ }
+ return false;
+ case AArch64_SBCSwww:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))))
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+ // (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)
+ AsmString = "ngcs $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SBCSxxx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))))
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
+ // (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)
+ AsmString = "ngcs $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SBCwww:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))))
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) {
+ // (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)
+ AsmString = "ngc $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SBCxxx:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))))
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) {
+ // (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)
+ AsmString = "ngc $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SMADDLxwwx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (SMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
+ AsmString = "smull $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SMSUBLxwwx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (SMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
+ AsmString = "smnegl $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBSwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "subs $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
+ AsmString = "negs $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBSwww_uxtw:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSwww_uxtw GPR32:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "subs $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBSxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "subs $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
+ AsmString = "negs $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBSxxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBSxxx_uxtx GPR64:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "subs $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBwww_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBwww_lsl GPR32:$Rd, GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBwww_uxtw:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBwww_uxtw Rwsp:$Rd, GPR32wsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32wspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32wspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RwspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RwspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBwww_uxtw GPR32wsp:$Rd, Rwsp:$Rn, GPR32:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBxxx_lsl:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBxxx_lsl GPR64:$Rd, GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_SUBxxx_uxtx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBxxx_uxtx Rxsp:$Rd, GPR64xsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64xspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64xspRegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_RxspRegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_RxspRegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
+ // (SUBxxx_uxtx GPR64xsp:$Rd, Rxsp:$Rn, GPR64:$Rm, 0)
+ AsmString = "sub $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_TSTww_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TSTww_lsl GPR32:$Rn, GPR32:$Rm, 0)
+ AsmString = "tst $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_TSTxx_lsl:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TSTxx_lsl GPR64:$Rn, GPR64:$Rm, 0)
+ AsmString = "tst $\x01, $\x02";
+ break;
+ }
+ return false;
+ case AArch64_UMADDLxwwx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (UMADDLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
+ AsmString = "umull $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ case AArch64_UMSUBLxwwx:
+ if (MCInst_getNumOperands(MI) == 4 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ //MRI.getRegClass(AArch64_GPR64RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ //MRI.getRegClass(AArch64_GPR32RegClassID).contains(MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) {
+ // (UMSUBLxwwx GPR64:$Rd, GPR32:$Rn, GPR32:$Rm, XZR)
+ AsmString = "umnegl $\x01, $\x02, $\x03";
+ break;
+ }
+ return false;
+ }
+
+ char *tmp = strdup(AsmString), *AsmMnem, *AsmOps;
+ AsmMnem = tmp;
+ AsmOps = strchr(tmp, ' ');
+ if (AsmOps) {
+ *AsmOps = '\0';
+ AsmOps += 1;
+ }
+
+ SStream_concat(OS, "%s", AsmMnem);
+ if (AsmOps) {
+ SStream_concat(OS, "\t");
+
+ char *c;
+ for (c = AsmOps; *c; c++) {
+ if (*c == '$') {
+ c += 1;
+ printOperand(MI, *c - 1, OS);
+ } else {
+ SStream_concat(OS, "%c", *c);
+ }
+ }
+ }
+
+ free(tmp);
+
+ return true;
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc
new file mode 100644
index 0000000..4adcf25
--- /dev/null
+++ b/arch/AArch64/AArch64GenDisassemblerTables.inc
@@ -0,0 +1,8009 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * AArch64 Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+static uint32_t fieldFromInstruction(uint32_t insn, unsigned startBit,
+ unsigned numBits)
+{
+ //assert(startBit + numBits <= (sizeof(uint32_t)*8) &&
+ // "Instruction field out of bounds!");
+ uint32_t fieldMask;
+ if (numBits == sizeof(uint32_t)*8)
+ fieldMask = (uint32_t)(-1LL);
+ else
+ fieldMask = (((uint32_t)1 << numBits) - 1) << startBit;
+ return (insn & fieldMask) >> startBit;
+}
+
+static const uint8_t DecoderTableA6432[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ...
+/* 3 */ MCD_OPC_FilterValue, 2, 152, 11, // Skip to: 2975
+/* 7 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 10 */ MCD_OPC_FilterValue, 0, 195, 0, // Skip to: 209
+/* 14 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 17 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 52
+/* 21 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 24 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 38
+/* 28 */ MCD_OPC_CheckField, 21, 1, 0, 179, 99, // Skip to: 25557
+/* 34 */ MCD_OPC_Decode, 160, 10, 0, // Opcode: STXR_byte
+/* 38 */ MCD_OPC_FilterValue, 1, 171, 99, // Skip to: 25557
+/* 42 */ MCD_OPC_CheckField, 21, 1, 0, 165, 99, // Skip to: 25557
+/* 48 */ MCD_OPC_Decode, 154, 10, 0, // Opcode: STLXR_byte
+/* 52 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 60
+/* 56 */ MCD_OPC_Decode, 207, 6, 1, // Opcode: LSPair32_NonTemp_STR
+/* 60 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 95
+/* 64 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 67 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 81
+/* 71 */ MCD_OPC_CheckField, 21, 1, 0, 136, 99, // Skip to: 25557
+/* 77 */ MCD_OPC_Decode, 162, 10, 0, // Opcode: STXR_hword
+/* 81 */ MCD_OPC_FilterValue, 1, 128, 99, // Skip to: 25557
+/* 85 */ MCD_OPC_CheckField, 21, 1, 0, 122, 99, // Skip to: 25557
+/* 91 */ MCD_OPC_Decode, 156, 10, 0, // Opcode: STLXR_hword
+/* 95 */ MCD_OPC_FilterValue, 4, 49, 0, // Skip to: 148
+/* 99 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 102 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 125
+/* 106 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 109 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 117
+/* 113 */ MCD_OPC_Decode, 163, 10, 0, // Opcode: STXR_word
+/* 117 */ MCD_OPC_FilterValue, 1, 92, 99, // Skip to: 25557
+/* 121 */ MCD_OPC_Decode, 159, 10, 2, // Opcode: STXP_word
+/* 125 */ MCD_OPC_FilterValue, 1, 84, 99, // Skip to: 25557
+/* 129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 132 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 140
+/* 136 */ MCD_OPC_Decode, 157, 10, 0, // Opcode: STLXR_word
+/* 140 */ MCD_OPC_FilterValue, 1, 69, 99, // Skip to: 25557
+/* 144 */ MCD_OPC_Decode, 153, 10, 2, // Opcode: STLXP_word
+/* 148 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 156
+/* 152 */ MCD_OPC_Decode, 215, 6, 1, // Opcode: LSPair64_NonTemp_STR
+/* 156 */ MCD_OPC_FilterValue, 6, 53, 99, // Skip to: 25557
+/* 160 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 163 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 186
+/* 167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 170 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 178
+/* 174 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: STXR_dword
+/* 178 */ MCD_OPC_FilterValue, 1, 31, 99, // Skip to: 25557
+/* 182 */ MCD_OPC_Decode, 158, 10, 4, // Opcode: STXP_dword
+/* 186 */ MCD_OPC_FilterValue, 1, 23, 99, // Skip to: 25557
+/* 190 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 193 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 201
+/* 197 */ MCD_OPC_Decode, 155, 10, 3, // Opcode: STLXR_dword
+/* 201 */ MCD_OPC_FilterValue, 1, 8, 99, // Skip to: 25557
+/* 205 */ MCD_OPC_Decode, 152, 10, 4, // Opcode: STLXP_dword
+/* 209 */ MCD_OPC_FilterValue, 1, 195, 0, // Skip to: 408
+/* 213 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 216 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 251
+/* 220 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 223 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 237
+/* 227 */ MCD_OPC_CheckField, 21, 1, 0, 236, 98, // Skip to: 25557
+/* 233 */ MCD_OPC_Decode, 185, 5, 5, // Opcode: LDXR_byte
+/* 237 */ MCD_OPC_FilterValue, 1, 228, 98, // Skip to: 25557
+/* 241 */ MCD_OPC_CheckField, 21, 1, 0, 222, 98, // Skip to: 25557
+/* 247 */ MCD_OPC_Decode, 135, 5, 5, // Opcode: LDAXR_byte
+/* 251 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 259
+/* 255 */ MCD_OPC_Decode, 206, 6, 1, // Opcode: LSPair32_NonTemp_LDR
+/* 259 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 294
+/* 263 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 266 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 280
+/* 270 */ MCD_OPC_CheckField, 21, 1, 0, 193, 98, // Skip to: 25557
+/* 276 */ MCD_OPC_Decode, 187, 5, 5, // Opcode: LDXR_hword
+/* 280 */ MCD_OPC_FilterValue, 1, 185, 98, // Skip to: 25557
+/* 284 */ MCD_OPC_CheckField, 21, 1, 0, 179, 98, // Skip to: 25557
+/* 290 */ MCD_OPC_Decode, 137, 5, 5, // Opcode: LDAXR_hword
+/* 294 */ MCD_OPC_FilterValue, 4, 49, 0, // Skip to: 347
+/* 298 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 301 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 324
+/* 305 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 308 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 316
+/* 312 */ MCD_OPC_Decode, 188, 5, 5, // Opcode: LDXR_word
+/* 316 */ MCD_OPC_FilterValue, 1, 149, 98, // Skip to: 25557
+/* 320 */ MCD_OPC_Decode, 184, 5, 6, // Opcode: LDXP_word
+/* 324 */ MCD_OPC_FilterValue, 1, 141, 98, // Skip to: 25557
+/* 328 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 331 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 339
+/* 335 */ MCD_OPC_Decode, 138, 5, 5, // Opcode: LDAXR_word
+/* 339 */ MCD_OPC_FilterValue, 1, 126, 98, // Skip to: 25557
+/* 343 */ MCD_OPC_Decode, 134, 5, 6, // Opcode: LDAXP_word
+/* 347 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 355
+/* 351 */ MCD_OPC_Decode, 214, 6, 1, // Opcode: LSPair64_NonTemp_LDR
+/* 355 */ MCD_OPC_FilterValue, 6, 110, 98, // Skip to: 25557
+/* 359 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 362 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 385
+/* 366 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 369 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 377
+/* 373 */ MCD_OPC_Decode, 186, 5, 7, // Opcode: LDXR_dword
+/* 377 */ MCD_OPC_FilterValue, 1, 88, 98, // Skip to: 25557
+/* 381 */ MCD_OPC_Decode, 183, 5, 6, // Opcode: LDXP_dword
+/* 385 */ MCD_OPC_FilterValue, 1, 80, 98, // Skip to: 25557
+/* 389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 392 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 400
+/* 396 */ MCD_OPC_Decode, 136, 5, 7, // Opcode: LDAXR_dword
+/* 400 */ MCD_OPC_FilterValue, 1, 65, 98, // Skip to: 25557
+/* 404 */ MCD_OPC_Decode, 133, 5, 6, // Opcode: LDAXP_dword
+/* 408 */ MCD_OPC_FilterValue, 2, 99, 0, // Skip to: 511
+/* 412 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 415 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 435
+/* 419 */ MCD_OPC_CheckField, 21, 1, 0, 44, 98, // Skip to: 25557
+/* 425 */ MCD_OPC_CheckField, 15, 1, 1, 38, 98, // Skip to: 25557
+/* 431 */ MCD_OPC_Decode, 148, 10, 5, // Opcode: STLR_byte
+/* 435 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 443
+/* 439 */ MCD_OPC_Decode, 209, 6, 1, // Opcode: LSPair32_PostInd_STR
+/* 443 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 463
+/* 447 */ MCD_OPC_CheckField, 21, 1, 0, 16, 98, // Skip to: 25557
+/* 453 */ MCD_OPC_CheckField, 15, 1, 1, 10, 98, // Skip to: 25557
+/* 459 */ MCD_OPC_Decode, 150, 10, 5, // Opcode: STLR_hword
+/* 463 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 483
+/* 467 */ MCD_OPC_CheckField, 21, 1, 0, 252, 97, // Skip to: 25557
+/* 473 */ MCD_OPC_CheckField, 15, 1, 1, 246, 97, // Skip to: 25557
+/* 479 */ MCD_OPC_Decode, 151, 10, 5, // Opcode: STLR_word
+/* 483 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 491
+/* 487 */ MCD_OPC_Decode, 217, 6, 1, // Opcode: LSPair64_PostInd_STR
+/* 491 */ MCD_OPC_FilterValue, 6, 230, 97, // Skip to: 25557
+/* 495 */ MCD_OPC_CheckField, 21, 1, 0, 224, 97, // Skip to: 25557
+/* 501 */ MCD_OPC_CheckField, 15, 1, 1, 218, 97, // Skip to: 25557
+/* 507 */ MCD_OPC_Decode, 149, 10, 7, // Opcode: STLR_dword
+/* 511 */ MCD_OPC_FilterValue, 3, 107, 0, // Skip to: 622
+/* 515 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 518 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 538
+/* 522 */ MCD_OPC_CheckField, 21, 1, 0, 197, 97, // Skip to: 25557
+/* 528 */ MCD_OPC_CheckField, 15, 1, 1, 191, 97, // Skip to: 25557
+/* 534 */ MCD_OPC_Decode, 129, 5, 5, // Opcode: LDAR_byte
+/* 538 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 546
+/* 542 */ MCD_OPC_Decode, 208, 6, 1, // Opcode: LSPair32_PostInd_LDR
+/* 546 */ MCD_OPC_FilterValue, 2, 16, 0, // Skip to: 566
+/* 550 */ MCD_OPC_CheckField, 21, 1, 0, 169, 97, // Skip to: 25557
+/* 556 */ MCD_OPC_CheckField, 15, 1, 1, 163, 97, // Skip to: 25557
+/* 562 */ MCD_OPC_Decode, 131, 5, 5, // Opcode: LDAR_hword
+/* 566 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 574
+/* 570 */ MCD_OPC_Decode, 140, 5, 1, // Opcode: LDPSWx_PostInd
+/* 574 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 594
+/* 578 */ MCD_OPC_CheckField, 21, 1, 0, 141, 97, // Skip to: 25557
+/* 584 */ MCD_OPC_CheckField, 15, 1, 1, 135, 97, // Skip to: 25557
+/* 590 */ MCD_OPC_Decode, 132, 5, 5, // Opcode: LDAR_word
+/* 594 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 602
+/* 598 */ MCD_OPC_Decode, 216, 6, 1, // Opcode: LSPair64_PostInd_LDR
+/* 602 */ MCD_OPC_FilterValue, 6, 119, 97, // Skip to: 25557
+/* 606 */ MCD_OPC_CheckField, 21, 1, 0, 113, 97, // Skip to: 25557
+/* 612 */ MCD_OPC_CheckField, 15, 1, 1, 107, 97, // Skip to: 25557
+/* 618 */ MCD_OPC_Decode, 130, 5, 7, // Opcode: LDAR_dword
+/* 622 */ MCD_OPC_FilterValue, 4, 19, 0, // Skip to: 645
+/* 626 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 629 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 637
+/* 633 */ MCD_OPC_Decode, 212, 6, 1, // Opcode: LSPair32_STR
+/* 637 */ MCD_OPC_FilterValue, 5, 84, 97, // Skip to: 25557
+/* 641 */ MCD_OPC_Decode, 220, 6, 1, // Opcode: LSPair64_STR
+/* 645 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 676
+/* 649 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 652 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 660
+/* 656 */ MCD_OPC_Decode, 205, 6, 1, // Opcode: LSPair32_LDR
+/* 660 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 668
+/* 664 */ MCD_OPC_Decode, 139, 5, 1, // Opcode: LDPSWx
+/* 668 */ MCD_OPC_FilterValue, 5, 53, 97, // Skip to: 25557
+/* 672 */ MCD_OPC_Decode, 213, 6, 1, // Opcode: LSPair64_LDR
+/* 676 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 699
+/* 680 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 683 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 691
+/* 687 */ MCD_OPC_Decode, 211, 6, 1, // Opcode: LSPair32_PreInd_STR
+/* 691 */ MCD_OPC_FilterValue, 5, 30, 97, // Skip to: 25557
+/* 695 */ MCD_OPC_Decode, 219, 6, 1, // Opcode: LSPair64_PreInd_STR
+/* 699 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 730
+/* 703 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 706 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 714
+/* 710 */ MCD_OPC_Decode, 210, 6, 1, // Opcode: LSPair32_PreInd_LDR
+/* 714 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 722
+/* 718 */ MCD_OPC_Decode, 141, 5, 1, // Opcode: LDPSWx_PreInd
+/* 722 */ MCD_OPC_FilterValue, 5, 255, 96, // Skip to: 25557
+/* 726 */ MCD_OPC_Decode, 218, 6, 1, // Opcode: LSPair64_PreInd_LDR
+/* 730 */ MCD_OPC_FilterValue, 8, 223, 0, // Skip to: 957
+/* 734 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 737 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 759
+/* 741 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 744 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 751
+/* 748 */ MCD_OPC_Decode, 117, 8, // Opcode: ANDwww_lsl
+/* 751 */ MCD_OPC_FilterValue, 1, 226, 96, // Skip to: 25557
+/* 755 */ MCD_OPC_Decode, 199, 1, 8, // Opcode: BICwww_lsl
+/* 759 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 792
+/* 763 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 766 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 774
+/* 770 */ MCD_OPC_Decode, 170, 7, 8, // Opcode: ORRwww_lsl
+/* 774 */ MCD_OPC_FilterValue, 1, 203, 96, // Skip to: 25557
+/* 778 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 788
+/* 784 */ MCD_OPC_Decode, 145, 7, 9, // Opcode: MVNww_lsl
+/* 788 */ MCD_OPC_Decode, 155, 7, 8, // Opcode: ORNwww_lsl
+/* 792 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 815
+/* 796 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 799 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 807
+/* 803 */ MCD_OPC_Decode, 135, 3, 8, // Opcode: EORwww_lsl
+/* 807 */ MCD_OPC_FilterValue, 1, 170, 96, // Skip to: 25557
+/* 811 */ MCD_OPC_Decode, 252, 2, 8, // Opcode: EONwww_lsl
+/* 815 */ MCD_OPC_FilterValue, 3, 28, 0, // Skip to: 847
+/* 819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 822 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 839
+/* 826 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 836
+/* 832 */ MCD_OPC_Decode, 255, 10, 10, // Opcode: TSTww_lsl
+/* 836 */ MCD_OPC_Decode, 105, 8, // Opcode: ANDSwww_lsl
+/* 839 */ MCD_OPC_FilterValue, 1, 138, 96, // Skip to: 25557
+/* 843 */ MCD_OPC_Decode, 185, 1, 8, // Opcode: BICSwww_lsl
+/* 847 */ MCD_OPC_FilterValue, 4, 18, 0, // Skip to: 869
+/* 851 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 854 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 861
+/* 858 */ MCD_OPC_Decode, 122, 11, // Opcode: ANDxxx_lsl
+/* 861 */ MCD_OPC_FilterValue, 1, 116, 96, // Skip to: 25557
+/* 865 */ MCD_OPC_Decode, 203, 1, 11, // Opcode: BICxxx_lsl
+/* 869 */ MCD_OPC_FilterValue, 5, 29, 0, // Skip to: 902
+/* 873 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 876 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 884
+/* 880 */ MCD_OPC_Decode, 175, 7, 11, // Opcode: ORRxxx_lsl
+/* 884 */ MCD_OPC_FilterValue, 1, 93, 96, // Skip to: 25557
+/* 888 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 898
+/* 894 */ MCD_OPC_Decode, 149, 7, 12, // Opcode: MVNxx_lsl
+/* 898 */ MCD_OPC_Decode, 159, 7, 11, // Opcode: ORNxxx_lsl
+/* 902 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 925
+/* 906 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 909 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 917
+/* 913 */ MCD_OPC_Decode, 140, 3, 11, // Opcode: EORxxx_lsl
+/* 917 */ MCD_OPC_FilterValue, 1, 60, 96, // Skip to: 25557
+/* 921 */ MCD_OPC_Decode, 128, 3, 11, // Opcode: EONxxx_lsl
+/* 925 */ MCD_OPC_FilterValue, 7, 52, 96, // Skip to: 25557
+/* 929 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 932 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 949
+/* 936 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 946
+/* 942 */ MCD_OPC_Decode, 131, 11, 13, // Opcode: TSTxx_lsl
+/* 946 */ MCD_OPC_Decode, 110, 11, // Opcode: ANDSxxx_lsl
+/* 949 */ MCD_OPC_FilterValue, 1, 28, 96, // Skip to: 25557
+/* 953 */ MCD_OPC_Decode, 189, 1, 11, // Opcode: BICSxxx_lsl
+/* 957 */ MCD_OPC_FilterValue, 9, 223, 0, // Skip to: 1184
+/* 961 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 964 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 986
+/* 968 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 971 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 978
+/* 975 */ MCD_OPC_Decode, 118, 8, // Opcode: ANDwww_lsr
+/* 978 */ MCD_OPC_FilterValue, 1, 255, 95, // Skip to: 25557
+/* 982 */ MCD_OPC_Decode, 200, 1, 8, // Opcode: BICwww_lsr
+/* 986 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 1019
+/* 990 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 993 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1001
+/* 997 */ MCD_OPC_Decode, 171, 7, 8, // Opcode: ORRwww_lsr
+/* 1001 */ MCD_OPC_FilterValue, 1, 232, 95, // Skip to: 25557
+/* 1005 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1015
+/* 1011 */ MCD_OPC_Decode, 146, 7, 9, // Opcode: MVNww_lsr
+/* 1015 */ MCD_OPC_Decode, 156, 7, 8, // Opcode: ORNwww_lsr
+/* 1019 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1042
+/* 1023 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1026 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1034
+/* 1030 */ MCD_OPC_Decode, 136, 3, 8, // Opcode: EORwww_lsr
+/* 1034 */ MCD_OPC_FilterValue, 1, 199, 95, // Skip to: 25557
+/* 1038 */ MCD_OPC_Decode, 253, 2, 8, // Opcode: EONwww_lsr
+/* 1042 */ MCD_OPC_FilterValue, 3, 28, 0, // Skip to: 1074
+/* 1046 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1049 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1066
+/* 1053 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1063
+/* 1059 */ MCD_OPC_Decode, 128, 11, 10, // Opcode: TSTww_lsr
+/* 1063 */ MCD_OPC_Decode, 106, 8, // Opcode: ANDSwww_lsr
+/* 1066 */ MCD_OPC_FilterValue, 1, 167, 95, // Skip to: 25557
+/* 1070 */ MCD_OPC_Decode, 186, 1, 8, // Opcode: BICSwww_lsr
+/* 1074 */ MCD_OPC_FilterValue, 4, 18, 0, // Skip to: 1096
+/* 1078 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1081 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1088
+/* 1085 */ MCD_OPC_Decode, 123, 11, // Opcode: ANDxxx_lsr
+/* 1088 */ MCD_OPC_FilterValue, 1, 145, 95, // Skip to: 25557
+/* 1092 */ MCD_OPC_Decode, 204, 1, 11, // Opcode: BICxxx_lsr
+/* 1096 */ MCD_OPC_FilterValue, 5, 29, 0, // Skip to: 1129
+/* 1100 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1103 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1111
+/* 1107 */ MCD_OPC_Decode, 176, 7, 11, // Opcode: ORRxxx_lsr
+/* 1111 */ MCD_OPC_FilterValue, 1, 122, 95, // Skip to: 25557
+/* 1115 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1125
+/* 1121 */ MCD_OPC_Decode, 150, 7, 12, // Opcode: MVNxx_lsr
+/* 1125 */ MCD_OPC_Decode, 160, 7, 11, // Opcode: ORNxxx_lsr
+/* 1129 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 1152
+/* 1133 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1136 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1144
+/* 1140 */ MCD_OPC_Decode, 141, 3, 11, // Opcode: EORxxx_lsr
+/* 1144 */ MCD_OPC_FilterValue, 1, 89, 95, // Skip to: 25557
+/* 1148 */ MCD_OPC_Decode, 129, 3, 11, // Opcode: EONxxx_lsr
+/* 1152 */ MCD_OPC_FilterValue, 7, 81, 95, // Skip to: 25557
+/* 1156 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1159 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1176
+/* 1163 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1173
+/* 1169 */ MCD_OPC_Decode, 132, 11, 13, // Opcode: TSTxx_lsr
+/* 1173 */ MCD_OPC_Decode, 111, 11, // Opcode: ANDSxxx_lsr
+/* 1176 */ MCD_OPC_FilterValue, 1, 57, 95, // Skip to: 25557
+/* 1180 */ MCD_OPC_Decode, 190, 1, 11, // Opcode: BICSxxx_lsr
+/* 1184 */ MCD_OPC_FilterValue, 10, 223, 0, // Skip to: 1411
+/* 1188 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 1191 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1213
+/* 1195 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1198 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1205
+/* 1202 */ MCD_OPC_Decode, 116, 8, // Opcode: ANDwww_asr
+/* 1205 */ MCD_OPC_FilterValue, 1, 28, 95, // Skip to: 25557
+/* 1209 */ MCD_OPC_Decode, 198, 1, 8, // Opcode: BICwww_asr
+/* 1213 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 1246
+/* 1217 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1220 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1228
+/* 1224 */ MCD_OPC_Decode, 169, 7, 8, // Opcode: ORRwww_asr
+/* 1228 */ MCD_OPC_FilterValue, 1, 5, 95, // Skip to: 25557
+/* 1232 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1242
+/* 1238 */ MCD_OPC_Decode, 144, 7, 9, // Opcode: MVNww_asr
+/* 1242 */ MCD_OPC_Decode, 154, 7, 8, // Opcode: ORNwww_asr
+/* 1246 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1269
+/* 1250 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1253 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1261
+/* 1257 */ MCD_OPC_Decode, 134, 3, 8, // Opcode: EORwww_asr
+/* 1261 */ MCD_OPC_FilterValue, 1, 228, 94, // Skip to: 25557
+/* 1265 */ MCD_OPC_Decode, 251, 2, 8, // Opcode: EONwww_asr
+/* 1269 */ MCD_OPC_FilterValue, 3, 28, 0, // Skip to: 1301
+/* 1273 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1276 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1293
+/* 1280 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1290
+/* 1286 */ MCD_OPC_Decode, 254, 10, 10, // Opcode: TSTww_asr
+/* 1290 */ MCD_OPC_Decode, 104, 8, // Opcode: ANDSwww_asr
+/* 1293 */ MCD_OPC_FilterValue, 1, 196, 94, // Skip to: 25557
+/* 1297 */ MCD_OPC_Decode, 184, 1, 8, // Opcode: BICSwww_asr
+/* 1301 */ MCD_OPC_FilterValue, 4, 18, 0, // Skip to: 1323
+/* 1305 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1308 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1315
+/* 1312 */ MCD_OPC_Decode, 121, 11, // Opcode: ANDxxx_asr
+/* 1315 */ MCD_OPC_FilterValue, 1, 174, 94, // Skip to: 25557
+/* 1319 */ MCD_OPC_Decode, 202, 1, 11, // Opcode: BICxxx_asr
+/* 1323 */ MCD_OPC_FilterValue, 5, 29, 0, // Skip to: 1356
+/* 1327 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1330 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1338
+/* 1334 */ MCD_OPC_Decode, 174, 7, 11, // Opcode: ORRxxx_asr
+/* 1338 */ MCD_OPC_FilterValue, 1, 151, 94, // Skip to: 25557
+/* 1342 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1352
+/* 1348 */ MCD_OPC_Decode, 148, 7, 12, // Opcode: MVNxx_asr
+/* 1352 */ MCD_OPC_Decode, 158, 7, 11, // Opcode: ORNxxx_asr
+/* 1356 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 1379
+/* 1360 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1363 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1371
+/* 1367 */ MCD_OPC_Decode, 139, 3, 11, // Opcode: EORxxx_asr
+/* 1371 */ MCD_OPC_FilterValue, 1, 118, 94, // Skip to: 25557
+/* 1375 */ MCD_OPC_Decode, 255, 2, 11, // Opcode: EONxxx_asr
+/* 1379 */ MCD_OPC_FilterValue, 7, 110, 94, // Skip to: 25557
+/* 1383 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1386 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1403
+/* 1390 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1400
+/* 1396 */ MCD_OPC_Decode, 130, 11, 13, // Opcode: TSTxx_asr
+/* 1400 */ MCD_OPC_Decode, 109, 11, // Opcode: ANDSxxx_asr
+/* 1403 */ MCD_OPC_FilterValue, 1, 86, 94, // Skip to: 25557
+/* 1407 */ MCD_OPC_Decode, 188, 1, 11, // Opcode: BICSxxx_asr
+/* 1411 */ MCD_OPC_FilterValue, 11, 223, 0, // Skip to: 1638
+/* 1415 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 1418 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1440
+/* 1422 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1425 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1432
+/* 1429 */ MCD_OPC_Decode, 119, 8, // Opcode: ANDwww_ror
+/* 1432 */ MCD_OPC_FilterValue, 1, 57, 94, // Skip to: 25557
+/* 1436 */ MCD_OPC_Decode, 201, 1, 8, // Opcode: BICwww_ror
+/* 1440 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 1473
+/* 1444 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1447 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1455
+/* 1451 */ MCD_OPC_Decode, 172, 7, 8, // Opcode: ORRwww_ror
+/* 1455 */ MCD_OPC_FilterValue, 1, 34, 94, // Skip to: 25557
+/* 1459 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1469
+/* 1465 */ MCD_OPC_Decode, 147, 7, 9, // Opcode: MVNww_ror
+/* 1469 */ MCD_OPC_Decode, 157, 7, 8, // Opcode: ORNwww_ror
+/* 1473 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1496
+/* 1477 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1480 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1488
+/* 1484 */ MCD_OPC_Decode, 137, 3, 8, // Opcode: EORwww_ror
+/* 1488 */ MCD_OPC_FilterValue, 1, 1, 94, // Skip to: 25557
+/* 1492 */ MCD_OPC_Decode, 254, 2, 8, // Opcode: EONwww_ror
+/* 1496 */ MCD_OPC_FilterValue, 3, 28, 0, // Skip to: 1528
+/* 1500 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1503 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1520
+/* 1507 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1517
+/* 1513 */ MCD_OPC_Decode, 129, 11, 10, // Opcode: TSTww_ror
+/* 1517 */ MCD_OPC_Decode, 107, 8, // Opcode: ANDSwww_ror
+/* 1520 */ MCD_OPC_FilterValue, 1, 225, 93, // Skip to: 25557
+/* 1524 */ MCD_OPC_Decode, 187, 1, 8, // Opcode: BICSwww_ror
+/* 1528 */ MCD_OPC_FilterValue, 4, 18, 0, // Skip to: 1550
+/* 1532 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1535 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1542
+/* 1539 */ MCD_OPC_Decode, 124, 11, // Opcode: ANDxxx_ror
+/* 1542 */ MCD_OPC_FilterValue, 1, 203, 93, // Skip to: 25557
+/* 1546 */ MCD_OPC_Decode, 205, 1, 11, // Opcode: BICxxx_ror
+/* 1550 */ MCD_OPC_FilterValue, 5, 29, 0, // Skip to: 1583
+/* 1554 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1557 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1565
+/* 1561 */ MCD_OPC_Decode, 177, 7, 11, // Opcode: ORRxxx_ror
+/* 1565 */ MCD_OPC_FilterValue, 1, 180, 93, // Skip to: 25557
+/* 1569 */ MCD_OPC_CheckField, 5, 5, 31, 4, 0, // Skip to: 1579
+/* 1575 */ MCD_OPC_Decode, 151, 7, 12, // Opcode: MVNxx_ror
+/* 1579 */ MCD_OPC_Decode, 161, 7, 11, // Opcode: ORNxxx_ror
+/* 1583 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 1606
+/* 1587 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1590 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1598
+/* 1594 */ MCD_OPC_Decode, 142, 3, 11, // Opcode: EORxxx_ror
+/* 1598 */ MCD_OPC_FilterValue, 1, 147, 93, // Skip to: 25557
+/* 1602 */ MCD_OPC_Decode, 130, 3, 11, // Opcode: EONxxx_ror
+/* 1606 */ MCD_OPC_FilterValue, 7, 139, 93, // Skip to: 25557
+/* 1610 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1613 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1630
+/* 1617 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1627
+/* 1623 */ MCD_OPC_Decode, 133, 11, 13, // Opcode: TSTxx_ror
+/* 1627 */ MCD_OPC_Decode, 112, 11, // Opcode: ANDSxxx_ror
+/* 1630 */ MCD_OPC_FilterValue, 1, 115, 93, // Skip to: 25557
+/* 1634 */ MCD_OPC_Decode, 191, 1, 11, // Opcode: BICSxxx_ror
+/* 1638 */ MCD_OPC_FilterValue, 12, 247, 3, // Skip to: 2657
+/* 1642 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 1645 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 1722
+/* 1649 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1652 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1659
+/* 1656 */ MCD_OPC_Decode, 72, 8, // Opcode: ADDwww_lsl
+/* 1659 */ MCD_OPC_FilterValue, 1, 86, 93, // Skip to: 25557
+/* 1663 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 1666 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1673
+/* 1670 */ MCD_OPC_Decode, 78, 14, // Opcode: ADDwww_uxtb
+/* 1673 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1680
+/* 1677 */ MCD_OPC_Decode, 79, 14, // Opcode: ADDwww_uxth
+/* 1680 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1687
+/* 1684 */ MCD_OPC_Decode, 80, 14, // Opcode: ADDwww_uxtw
+/* 1687 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1694
+/* 1691 */ MCD_OPC_Decode, 81, 14, // Opcode: ADDwww_uxtx
+/* 1694 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1701
+/* 1698 */ MCD_OPC_Decode, 74, 14, // Opcode: ADDwww_sxtb
+/* 1701 */ MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 1708
+/* 1705 */ MCD_OPC_Decode, 75, 14, // Opcode: ADDwww_sxth
+/* 1708 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 1715
+/* 1712 */ MCD_OPC_Decode, 76, 14, // Opcode: ADDwww_sxtw
+/* 1715 */ MCD_OPC_FilterValue, 7, 30, 93, // Skip to: 25557
+/* 1719 */ MCD_OPC_Decode, 77, 14, // Opcode: ADDwww_sxtx
+/* 1722 */ MCD_OPC_FilterValue, 1, 163, 0, // Skip to: 1889
+/* 1726 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1729 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1746
+/* 1733 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1743
+/* 1739 */ MCD_OPC_Decode, 178, 2, 10, // Opcode: CMNww_lsl
+/* 1743 */ MCD_OPC_Decode, 36, 8, // Opcode: ADDSwww_lsl
+/* 1746 */ MCD_OPC_FilterValue, 1, 255, 92, // Skip to: 25557
+/* 1750 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 1753 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 1770
+/* 1757 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1767
+/* 1763 */ MCD_OPC_Decode, 184, 2, 15, // Opcode: CMNww_uxtb
+/* 1767 */ MCD_OPC_Decode, 42, 16, // Opcode: ADDSwww_uxtb
+/* 1770 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 1787
+/* 1774 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1784
+/* 1780 */ MCD_OPC_Decode, 185, 2, 15, // Opcode: CMNww_uxth
+/* 1784 */ MCD_OPC_Decode, 43, 16, // Opcode: ADDSwww_uxth
+/* 1787 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 1804
+/* 1791 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1801
+/* 1797 */ MCD_OPC_Decode, 186, 2, 15, // Opcode: CMNww_uxtw
+/* 1801 */ MCD_OPC_Decode, 44, 16, // Opcode: ADDSwww_uxtw
+/* 1804 */ MCD_OPC_FilterValue, 3, 13, 0, // Skip to: 1821
+/* 1808 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1818
+/* 1814 */ MCD_OPC_Decode, 187, 2, 15, // Opcode: CMNww_uxtx
+/* 1818 */ MCD_OPC_Decode, 45, 16, // Opcode: ADDSwww_uxtx
+/* 1821 */ MCD_OPC_FilterValue, 4, 13, 0, // Skip to: 1838
+/* 1825 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1835
+/* 1831 */ MCD_OPC_Decode, 180, 2, 15, // Opcode: CMNww_sxtb
+/* 1835 */ MCD_OPC_Decode, 38, 16, // Opcode: ADDSwww_sxtb
+/* 1838 */ MCD_OPC_FilterValue, 5, 13, 0, // Skip to: 1855
+/* 1842 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1852
+/* 1848 */ MCD_OPC_Decode, 181, 2, 15, // Opcode: CMNww_sxth
+/* 1852 */ MCD_OPC_Decode, 39, 16, // Opcode: ADDSwww_sxth
+/* 1855 */ MCD_OPC_FilterValue, 6, 13, 0, // Skip to: 1872
+/* 1859 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1869
+/* 1865 */ MCD_OPC_Decode, 182, 2, 15, // Opcode: CMNww_sxtw
+/* 1869 */ MCD_OPC_Decode, 40, 16, // Opcode: ADDSwww_sxtw
+/* 1872 */ MCD_OPC_FilterValue, 7, 129, 92, // Skip to: 25557
+/* 1876 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1886
+/* 1882 */ MCD_OPC_Decode, 183, 2, 15, // Opcode: CMNww_sxtx
+/* 1886 */ MCD_OPC_Decode, 41, 16, // Opcode: ADDSwww_sxtx
+/* 1889 */ MCD_OPC_FilterValue, 2, 82, 0, // Skip to: 1975
+/* 1893 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1896 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1904
+/* 1900 */ MCD_OPC_Decode, 207, 10, 8, // Opcode: SUBwww_lsl
+/* 1904 */ MCD_OPC_FilterValue, 1, 97, 92, // Skip to: 25557
+/* 1908 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 1911 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1919
+/* 1915 */ MCD_OPC_Decode, 213, 10, 14, // Opcode: SUBwww_uxtb
+/* 1919 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1927
+/* 1923 */ MCD_OPC_Decode, 214, 10, 14, // Opcode: SUBwww_uxth
+/* 1927 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1935
+/* 1931 */ MCD_OPC_Decode, 215, 10, 14, // Opcode: SUBwww_uxtw
+/* 1935 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1943
+/* 1939 */ MCD_OPC_Decode, 216, 10, 14, // Opcode: SUBwww_uxtx
+/* 1943 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1951
+/* 1947 */ MCD_OPC_Decode, 209, 10, 14, // Opcode: SUBwww_sxtb
+/* 1951 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1959
+/* 1955 */ MCD_OPC_Decode, 210, 10, 14, // Opcode: SUBwww_sxth
+/* 1959 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1967
+/* 1963 */ MCD_OPC_Decode, 211, 10, 14, // Opcode: SUBwww_sxtw
+/* 1967 */ MCD_OPC_FilterValue, 7, 34, 92, // Skip to: 25557
+/* 1971 */ MCD_OPC_Decode, 212, 10, 14, // Opcode: SUBwww_sxtx
+/* 1975 */ MCD_OPC_FilterValue, 3, 172, 0, // Skip to: 2151
+/* 1979 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 1982 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2000
+/* 1986 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 1996
+/* 1992 */ MCD_OPC_Decode, 200, 2, 10, // Opcode: CMPww_lsl
+/* 1996 */ MCD_OPC_Decode, 171, 10, 8, // Opcode: SUBSwww_lsl
+/* 2000 */ MCD_OPC_FilterValue, 1, 1, 92, // Skip to: 25557
+/* 2004 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 2007 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2025
+/* 2011 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2021
+/* 2017 */ MCD_OPC_Decode, 206, 2, 15, // Opcode: CMPww_uxtb
+/* 2021 */ MCD_OPC_Decode, 177, 10, 16, // Opcode: SUBSwww_uxtb
+/* 2025 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2043
+/* 2029 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2039
+/* 2035 */ MCD_OPC_Decode, 207, 2, 15, // Opcode: CMPww_uxth
+/* 2039 */ MCD_OPC_Decode, 178, 10, 16, // Opcode: SUBSwww_uxth
+/* 2043 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2061
+/* 2047 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2057
+/* 2053 */ MCD_OPC_Decode, 208, 2, 15, // Opcode: CMPww_uxtw
+/* 2057 */ MCD_OPC_Decode, 179, 10, 16, // Opcode: SUBSwww_uxtw
+/* 2061 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2079
+/* 2065 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2075
+/* 2071 */ MCD_OPC_Decode, 209, 2, 15, // Opcode: CMPww_uxtx
+/* 2075 */ MCD_OPC_Decode, 180, 10, 16, // Opcode: SUBSwww_uxtx
+/* 2079 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2097
+/* 2083 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2093
+/* 2089 */ MCD_OPC_Decode, 202, 2, 15, // Opcode: CMPww_sxtb
+/* 2093 */ MCD_OPC_Decode, 173, 10, 16, // Opcode: SUBSwww_sxtb
+/* 2097 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2115
+/* 2101 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2111
+/* 2107 */ MCD_OPC_Decode, 203, 2, 15, // Opcode: CMPww_sxth
+/* 2111 */ MCD_OPC_Decode, 174, 10, 16, // Opcode: SUBSwww_sxth
+/* 2115 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2133
+/* 2119 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2129
+/* 2125 */ MCD_OPC_Decode, 204, 2, 15, // Opcode: CMPww_sxtw
+/* 2129 */ MCD_OPC_Decode, 175, 10, 16, // Opcode: SUBSwww_sxtw
+/* 2133 */ MCD_OPC_FilterValue, 7, 124, 91, // Skip to: 25557
+/* 2137 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2147
+/* 2143 */ MCD_OPC_Decode, 205, 2, 15, // Opcode: CMPww_sxtx
+/* 2147 */ MCD_OPC_Decode, 176, 10, 16, // Opcode: SUBSwww_sxtx
+/* 2151 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 2228
+/* 2155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2158 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2165
+/* 2162 */ MCD_OPC_Decode, 95, 11, // Opcode: ADDxxx_lsl
+/* 2165 */ MCD_OPC_FilterValue, 1, 92, 91, // Skip to: 25557
+/* 2169 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 2172 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2179
+/* 2176 */ MCD_OPC_Decode, 91, 17, // Opcode: ADDxxw_uxtb
+/* 2179 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 2186
+/* 2183 */ MCD_OPC_Decode, 92, 17, // Opcode: ADDxxw_uxth
+/* 2186 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 2193
+/* 2190 */ MCD_OPC_Decode, 93, 17, // Opcode: ADDxxw_uxtw
+/* 2193 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 2200
+/* 2197 */ MCD_OPC_Decode, 98, 18, // Opcode: ADDxxx_uxtx
+/* 2200 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 2207
+/* 2204 */ MCD_OPC_Decode, 88, 17, // Opcode: ADDxxw_sxtb
+/* 2207 */ MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 2214
+/* 2211 */ MCD_OPC_Decode, 89, 17, // Opcode: ADDxxw_sxth
+/* 2214 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 2221
+/* 2218 */ MCD_OPC_Decode, 90, 17, // Opcode: ADDxxw_sxtw
+/* 2221 */ MCD_OPC_FilterValue, 7, 36, 91, // Skip to: 25557
+/* 2225 */ MCD_OPC_Decode, 97, 18, // Opcode: ADDxxx_sxtx
+/* 2228 */ MCD_OPC_FilterValue, 5, 163, 0, // Skip to: 2395
+/* 2232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2235 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 2252
+/* 2239 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2249
+/* 2245 */ MCD_OPC_Decode, 195, 2, 13, // Opcode: CMNxx_lsl
+/* 2249 */ MCD_OPC_Decode, 53, 11, // Opcode: ADDSxxx_lsl
+/* 2252 */ MCD_OPC_FilterValue, 1, 5, 91, // Skip to: 25557
+/* 2256 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 2259 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 2276
+/* 2263 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2273
+/* 2269 */ MCD_OPC_Decode, 191, 2, 19, // Opcode: CMNxw_uxtb
+/* 2273 */ MCD_OPC_Decode, 49, 20, // Opcode: ADDSxxw_uxtb
+/* 2276 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 2293
+/* 2280 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2290
+/* 2286 */ MCD_OPC_Decode, 192, 2, 19, // Opcode: CMNxw_uxth
+/* 2290 */ MCD_OPC_Decode, 50, 20, // Opcode: ADDSxxw_uxth
+/* 2293 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 2310
+/* 2297 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2307
+/* 2303 */ MCD_OPC_Decode, 193, 2, 19, // Opcode: CMNxw_uxtw
+/* 2307 */ MCD_OPC_Decode, 51, 20, // Opcode: ADDSxxw_uxtw
+/* 2310 */ MCD_OPC_FilterValue, 3, 13, 0, // Skip to: 2327
+/* 2314 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2324
+/* 2320 */ MCD_OPC_Decode, 198, 2, 21, // Opcode: CMNxx_uxtx
+/* 2324 */ MCD_OPC_Decode, 56, 22, // Opcode: ADDSxxx_uxtx
+/* 2327 */ MCD_OPC_FilterValue, 4, 13, 0, // Skip to: 2344
+/* 2331 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2341
+/* 2337 */ MCD_OPC_Decode, 188, 2, 19, // Opcode: CMNxw_sxtb
+/* 2341 */ MCD_OPC_Decode, 46, 20, // Opcode: ADDSxxw_sxtb
+/* 2344 */ MCD_OPC_FilterValue, 5, 13, 0, // Skip to: 2361
+/* 2348 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2358
+/* 2354 */ MCD_OPC_Decode, 189, 2, 19, // Opcode: CMNxw_sxth
+/* 2358 */ MCD_OPC_Decode, 47, 20, // Opcode: ADDSxxw_sxth
+/* 2361 */ MCD_OPC_FilterValue, 6, 13, 0, // Skip to: 2378
+/* 2365 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2375
+/* 2371 */ MCD_OPC_Decode, 190, 2, 19, // Opcode: CMNxw_sxtw
+/* 2375 */ MCD_OPC_Decode, 48, 20, // Opcode: ADDSxxw_sxtw
+/* 2378 */ MCD_OPC_FilterValue, 7, 135, 90, // Skip to: 25557
+/* 2382 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2392
+/* 2388 */ MCD_OPC_Decode, 197, 2, 21, // Opcode: CMNxx_sxtx
+/* 2392 */ MCD_OPC_Decode, 55, 22, // Opcode: ADDSxxx_sxtx
+/* 2395 */ MCD_OPC_FilterValue, 6, 82, 0, // Skip to: 2481
+/* 2399 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2402 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2410
+/* 2406 */ MCD_OPC_Decode, 230, 10, 11, // Opcode: SUBxxx_lsl
+/* 2410 */ MCD_OPC_FilterValue, 1, 103, 90, // Skip to: 25557
+/* 2414 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 2417 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2425
+/* 2421 */ MCD_OPC_Decode, 226, 10, 17, // Opcode: SUBxxw_uxtb
+/* 2425 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2433
+/* 2429 */ MCD_OPC_Decode, 227, 10, 17, // Opcode: SUBxxw_uxth
+/* 2433 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 2441
+/* 2437 */ MCD_OPC_Decode, 228, 10, 17, // Opcode: SUBxxw_uxtw
+/* 2441 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2449
+/* 2445 */ MCD_OPC_Decode, 233, 10, 18, // Opcode: SUBxxx_uxtx
+/* 2449 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 2457
+/* 2453 */ MCD_OPC_Decode, 223, 10, 17, // Opcode: SUBxxw_sxtb
+/* 2457 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 2465
+/* 2461 */ MCD_OPC_Decode, 224, 10, 17, // Opcode: SUBxxw_sxth
+/* 2465 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 2473
+/* 2469 */ MCD_OPC_Decode, 225, 10, 17, // Opcode: SUBxxw_sxtw
+/* 2473 */ MCD_OPC_FilterValue, 7, 40, 90, // Skip to: 25557
+/* 2477 */ MCD_OPC_Decode, 232, 10, 18, // Opcode: SUBxxx_sxtx
+/* 2481 */ MCD_OPC_FilterValue, 7, 32, 90, // Skip to: 25557
+/* 2485 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2488 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2506
+/* 2492 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2502
+/* 2498 */ MCD_OPC_Decode, 217, 2, 13, // Opcode: CMPxx_lsl
+/* 2502 */ MCD_OPC_Decode, 188, 10, 11, // Opcode: SUBSxxx_lsl
+/* 2506 */ MCD_OPC_FilterValue, 1, 7, 90, // Skip to: 25557
+/* 2510 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 2513 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2531
+/* 2517 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2527
+/* 2523 */ MCD_OPC_Decode, 213, 2, 19, // Opcode: CMPxw_uxtb
+/* 2527 */ MCD_OPC_Decode, 184, 10, 20, // Opcode: SUBSxxw_uxtb
+/* 2531 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2549
+/* 2535 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2545
+/* 2541 */ MCD_OPC_Decode, 214, 2, 19, // Opcode: CMPxw_uxth
+/* 2545 */ MCD_OPC_Decode, 185, 10, 20, // Opcode: SUBSxxw_uxth
+/* 2549 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2567
+/* 2553 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2563
+/* 2559 */ MCD_OPC_Decode, 215, 2, 19, // Opcode: CMPxw_uxtw
+/* 2563 */ MCD_OPC_Decode, 186, 10, 20, // Opcode: SUBSxxw_uxtw
+/* 2567 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2585
+/* 2571 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2581
+/* 2577 */ MCD_OPC_Decode, 220, 2, 21, // Opcode: CMPxx_uxtx
+/* 2581 */ MCD_OPC_Decode, 191, 10, 22, // Opcode: SUBSxxx_uxtx
+/* 2585 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2603
+/* 2589 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2599
+/* 2595 */ MCD_OPC_Decode, 210, 2, 19, // Opcode: CMPxw_sxtb
+/* 2599 */ MCD_OPC_Decode, 181, 10, 20, // Opcode: SUBSxxw_sxtb
+/* 2603 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2621
+/* 2607 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2617
+/* 2613 */ MCD_OPC_Decode, 211, 2, 19, // Opcode: CMPxw_sxth
+/* 2617 */ MCD_OPC_Decode, 182, 10, 20, // Opcode: SUBSxxw_sxth
+/* 2621 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2639
+/* 2625 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2635
+/* 2631 */ MCD_OPC_Decode, 212, 2, 19, // Opcode: CMPxw_sxtw
+/* 2635 */ MCD_OPC_Decode, 183, 10, 20, // Opcode: SUBSxxw_sxtw
+/* 2639 */ MCD_OPC_FilterValue, 7, 130, 89, // Skip to: 25557
+/* 2643 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2653
+/* 2649 */ MCD_OPC_Decode, 219, 2, 21, // Opcode: CMPxx_sxtx
+/* 2653 */ MCD_OPC_Decode, 190, 10, 22, // Opcode: SUBSxxx_sxtx
+/* 2657 */ MCD_OPC_FilterValue, 13, 155, 0, // Skip to: 2816
+/* 2661 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 2664 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 2677
+/* 2668 */ MCD_OPC_CheckField, 21, 1, 0, 99, 89, // Skip to: 25557
+/* 2674 */ MCD_OPC_Decode, 73, 8, // Opcode: ADDwww_lsr
+/* 2677 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 2701
+/* 2681 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2684 */ MCD_OPC_FilterValue, 0, 85, 89, // Skip to: 25557
+/* 2688 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2698
+/* 2694 */ MCD_OPC_Decode, 179, 2, 10, // Opcode: CMNww_lsr
+/* 2698 */ MCD_OPC_Decode, 37, 8, // Opcode: ADDSwww_lsr
+/* 2701 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2715
+/* 2705 */ MCD_OPC_CheckField, 21, 1, 0, 62, 89, // Skip to: 25557
+/* 2711 */ MCD_OPC_Decode, 208, 10, 8, // Opcode: SUBwww_lsr
+/* 2715 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 2740
+/* 2719 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2722 */ MCD_OPC_FilterValue, 0, 47, 89, // Skip to: 25557
+/* 2726 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2736
+/* 2732 */ MCD_OPC_Decode, 201, 2, 10, // Opcode: CMPww_lsr
+/* 2736 */ MCD_OPC_Decode, 172, 10, 8, // Opcode: SUBSwww_lsr
+/* 2740 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 2753
+/* 2744 */ MCD_OPC_CheckField, 21, 1, 0, 23, 89, // Skip to: 25557
+/* 2750 */ MCD_OPC_Decode, 96, 11, // Opcode: ADDxxx_lsr
+/* 2753 */ MCD_OPC_FilterValue, 5, 20, 0, // Skip to: 2777
+/* 2757 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2760 */ MCD_OPC_FilterValue, 0, 9, 89, // Skip to: 25557
+/* 2764 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2774
+/* 2770 */ MCD_OPC_Decode, 196, 2, 13, // Opcode: CMNxx_lsr
+/* 2774 */ MCD_OPC_Decode, 54, 11, // Opcode: ADDSxxx_lsr
+/* 2777 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2791
+/* 2781 */ MCD_OPC_CheckField, 21, 1, 0, 242, 88, // Skip to: 25557
+/* 2787 */ MCD_OPC_Decode, 231, 10, 11, // Opcode: SUBxxx_lsr
+/* 2791 */ MCD_OPC_FilterValue, 7, 234, 88, // Skip to: 25557
+/* 2795 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2798 */ MCD_OPC_FilterValue, 0, 227, 88, // Skip to: 25557
+/* 2802 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2812
+/* 2808 */ MCD_OPC_Decode, 218, 2, 13, // Opcode: CMPxx_lsr
+/* 2812 */ MCD_OPC_Decode, 189, 10, 11, // Opcode: SUBSxxx_lsr
+/* 2816 */ MCD_OPC_FilterValue, 14, 209, 88, // Skip to: 25557
+/* 2820 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 2823 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 2836
+/* 2827 */ MCD_OPC_CheckField, 21, 1, 0, 196, 88, // Skip to: 25557
+/* 2833 */ MCD_OPC_Decode, 71, 8, // Opcode: ADDwww_asr
+/* 2836 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 2860
+/* 2840 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2843 */ MCD_OPC_FilterValue, 0, 182, 88, // Skip to: 25557
+/* 2847 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2857
+/* 2853 */ MCD_OPC_Decode, 177, 2, 10, // Opcode: CMNww_asr
+/* 2857 */ MCD_OPC_Decode, 35, 8, // Opcode: ADDSwww_asr
+/* 2860 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2874
+/* 2864 */ MCD_OPC_CheckField, 21, 1, 0, 159, 88, // Skip to: 25557
+/* 2870 */ MCD_OPC_Decode, 206, 10, 8, // Opcode: SUBwww_asr
+/* 2874 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 2899
+/* 2878 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2881 */ MCD_OPC_FilterValue, 0, 144, 88, // Skip to: 25557
+/* 2885 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2895
+/* 2891 */ MCD_OPC_Decode, 199, 2, 10, // Opcode: CMPww_asr
+/* 2895 */ MCD_OPC_Decode, 170, 10, 8, // Opcode: SUBSwww_asr
+/* 2899 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 2912
+/* 2903 */ MCD_OPC_CheckField, 21, 1, 0, 120, 88, // Skip to: 25557
+/* 2909 */ MCD_OPC_Decode, 94, 11, // Opcode: ADDxxx_asr
+/* 2912 */ MCD_OPC_FilterValue, 5, 20, 0, // Skip to: 2936
+/* 2916 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2919 */ MCD_OPC_FilterValue, 0, 106, 88, // Skip to: 25557
+/* 2923 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2933
+/* 2929 */ MCD_OPC_Decode, 194, 2, 13, // Opcode: CMNxx_asr
+/* 2933 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDSxxx_asr
+/* 2936 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2950
+/* 2940 */ MCD_OPC_CheckField, 21, 1, 0, 83, 88, // Skip to: 25557
+/* 2946 */ MCD_OPC_Decode, 229, 10, 11, // Opcode: SUBxxx_asr
+/* 2950 */ MCD_OPC_FilterValue, 7, 75, 88, // Skip to: 25557
+/* 2954 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 2957 */ MCD_OPC_FilterValue, 0, 68, 88, // Skip to: 25557
+/* 2961 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 2971
+/* 2967 */ MCD_OPC_Decode, 216, 2, 13, // Opcode: CMPxx_asr
+/* 2971 */ MCD_OPC_Decode, 187, 10, 11, // Opcode: SUBSxxx_asr
+/* 2975 */ MCD_OPC_FilterValue, 3, 127, 59, // Skip to: 18210
+/* 2979 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 2982 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 3013
+/* 2986 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 2989 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2997
+/* 2993 */ MCD_OPC_Decode, 187, 6, 1, // Opcode: LSFPPair32_NonTemp_STR
+/* 2997 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3005
+/* 3001 */ MCD_OPC_Decode, 195, 6, 1, // Opcode: LSFPPair64_NonTemp_STR
+/* 3005 */ MCD_OPC_FilterValue, 5, 20, 88, // Skip to: 25557
+/* 3009 */ MCD_OPC_Decode, 179, 6, 1, // Opcode: LSFPPair128_NonTemp_STR
+/* 3013 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 3044
+/* 3017 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3020 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3028
+/* 3024 */ MCD_OPC_Decode, 186, 6, 1, // Opcode: LSFPPair32_NonTemp_LDR
+/* 3028 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3036
+/* 3032 */ MCD_OPC_Decode, 194, 6, 1, // Opcode: LSFPPair64_NonTemp_LDR
+/* 3036 */ MCD_OPC_FilterValue, 5, 245, 87, // Skip to: 25557
+/* 3040 */ MCD_OPC_Decode, 178, 6, 1, // Opcode: LSFPPair128_NonTemp_LDR
+/* 3044 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 3075
+/* 3048 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3051 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3059
+/* 3055 */ MCD_OPC_Decode, 189, 6, 1, // Opcode: LSFPPair32_PostInd_STR
+/* 3059 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3067
+/* 3063 */ MCD_OPC_Decode, 197, 6, 1, // Opcode: LSFPPair64_PostInd_STR
+/* 3067 */ MCD_OPC_FilterValue, 5, 214, 87, // Skip to: 25557
+/* 3071 */ MCD_OPC_Decode, 181, 6, 1, // Opcode: LSFPPair128_PostInd_STR
+/* 3075 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 3106
+/* 3079 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3082 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3090
+/* 3086 */ MCD_OPC_Decode, 188, 6, 1, // Opcode: LSFPPair32_PostInd_LDR
+/* 3090 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3098
+/* 3094 */ MCD_OPC_Decode, 196, 6, 1, // Opcode: LSFPPair64_PostInd_LDR
+/* 3098 */ MCD_OPC_FilterValue, 5, 183, 87, // Skip to: 25557
+/* 3102 */ MCD_OPC_Decode, 180, 6, 1, // Opcode: LSFPPair128_PostInd_LDR
+/* 3106 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 3137
+/* 3110 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3113 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3121
+/* 3117 */ MCD_OPC_Decode, 192, 6, 1, // Opcode: LSFPPair32_STR
+/* 3121 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3129
+/* 3125 */ MCD_OPC_Decode, 200, 6, 1, // Opcode: LSFPPair64_STR
+/* 3129 */ MCD_OPC_FilterValue, 5, 152, 87, // Skip to: 25557
+/* 3133 */ MCD_OPC_Decode, 184, 6, 1, // Opcode: LSFPPair128_STR
+/* 3137 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 3168
+/* 3141 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3144 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3152
+/* 3148 */ MCD_OPC_Decode, 185, 6, 1, // Opcode: LSFPPair32_LDR
+/* 3152 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3160
+/* 3156 */ MCD_OPC_Decode, 193, 6, 1, // Opcode: LSFPPair64_LDR
+/* 3160 */ MCD_OPC_FilterValue, 5, 121, 87, // Skip to: 25557
+/* 3164 */ MCD_OPC_Decode, 177, 6, 1, // Opcode: LSFPPair128_LDR
+/* 3168 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3199
+/* 3172 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3175 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3183
+/* 3179 */ MCD_OPC_Decode, 191, 6, 1, // Opcode: LSFPPair32_PreInd_STR
+/* 3183 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3191
+/* 3187 */ MCD_OPC_Decode, 199, 6, 1, // Opcode: LSFPPair64_PreInd_STR
+/* 3191 */ MCD_OPC_FilterValue, 5, 90, 87, // Skip to: 25557
+/* 3195 */ MCD_OPC_Decode, 183, 6, 1, // Opcode: LSFPPair128_PreInd_STR
+/* 3199 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 3230
+/* 3203 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3206 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3214
+/* 3210 */ MCD_OPC_Decode, 190, 6, 1, // Opcode: LSFPPair32_PreInd_LDR
+/* 3214 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3222
+/* 3218 */ MCD_OPC_Decode, 198, 6, 1, // Opcode: LSFPPair64_PreInd_LDR
+/* 3222 */ MCD_OPC_FilterValue, 5, 59, 87, // Skip to: 25557
+/* 3226 */ MCD_OPC_Decode, 182, 6, 1, // Opcode: LSFPPair128_PreInd_LDR
+/* 3230 */ MCD_OPC_FilterValue, 8, 88, 13, // Skip to: 6650
+/* 3234 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 3237 */ MCD_OPC_FilterValue, 0, 136, 3, // Skip to: 4145
+/* 3241 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 3244 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3262
+/* 3248 */ MCD_OPC_CheckPredicate, 0, 33, 87, // Skip to: 25557
+/* 3252 */ MCD_OPC_CheckField, 21, 1, 1, 27, 87, // Skip to: 25557
+/* 3258 */ MCD_OPC_Decode, 129, 8, 23, // Opcode: SADDLvvv_8h8b
+/* 3262 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3280
+/* 3266 */ MCD_OPC_CheckPredicate, 0, 15, 87, // Skip to: 25557
+/* 3270 */ MCD_OPC_CheckField, 21, 1, 1, 9, 87, // Skip to: 25557
+/* 3276 */ MCD_OPC_Decode, 160, 8, 24, // Opcode: SHADDvvv_8B
+/* 3280 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3298
+/* 3284 */ MCD_OPC_CheckPredicate, 0, 253, 86, // Skip to: 25557
+/* 3288 */ MCD_OPC_CheckField, 21, 1, 1, 247, 86, // Skip to: 25557
+/* 3294 */ MCD_OPC_Decode, 248, 8, 24, // Opcode: SQADDvvv_8B
+/* 3298 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3316
+/* 3302 */ MCD_OPC_CheckPredicate, 0, 235, 86, // Skip to: 25557
+/* 3306 */ MCD_OPC_CheckField, 21, 1, 1, 229, 86, // Skip to: 25557
+/* 3312 */ MCD_OPC_Decode, 135, 8, 25, // Opcode: SADDWvvv_8h8b
+/* 3316 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3334
+/* 3320 */ MCD_OPC_CheckPredicate, 0, 217, 86, // Skip to: 25557
+/* 3324 */ MCD_OPC_CheckField, 21, 1, 1, 211, 86, // Skip to: 25557
+/* 3330 */ MCD_OPC_Decode, 205, 9, 24, // Opcode: SRHADDvvv_8B
+/* 3334 */ MCD_OPC_FilterValue, 7, 13, 0, // Skip to: 3351
+/* 3338 */ MCD_OPC_CheckPredicate, 0, 199, 86, // Skip to: 25557
+/* 3342 */ MCD_OPC_CheckField, 21, 1, 1, 193, 86, // Skip to: 25557
+/* 3348 */ MCD_OPC_Decode, 114, 24, // Opcode: ANDvvv_8B
+/* 3351 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3369
+/* 3355 */ MCD_OPC_CheckPredicate, 0, 182, 86, // Skip to: 25557
+/* 3359 */ MCD_OPC_CheckField, 21, 1, 1, 176, 86, // Skip to: 25557
+/* 3365 */ MCD_OPC_Decode, 141, 10, 23, // Opcode: SSUBLvvv_8h8b
+/* 3369 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3387
+/* 3373 */ MCD_OPC_CheckPredicate, 0, 164, 86, // Skip to: 25557
+/* 3377 */ MCD_OPC_CheckField, 21, 1, 1, 158, 86, // Skip to: 25557
+/* 3383 */ MCD_OPC_Decode, 179, 8, 24, // Opcode: SHSUBvvv_8B
+/* 3387 */ MCD_OPC_FilterValue, 11, 52, 0, // Skip to: 3443
+/* 3391 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 3394 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 3431
+/* 3398 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ...
+/* 3401 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3419
+/* 3405 */ MCD_OPC_CheckPredicate, 0, 132, 86, // Skip to: 25557
+/* 3409 */ MCD_OPC_CheckField, 17, 1, 1, 126, 86, // Skip to: 25557
+/* 3415 */ MCD_OPC_Decode, 227, 8, 26, // Opcode: SMOVwh
+/* 3419 */ MCD_OPC_FilterValue, 1, 118, 86, // Skip to: 25557
+/* 3423 */ MCD_OPC_CheckPredicate, 0, 114, 86, // Skip to: 25557
+/* 3427 */ MCD_OPC_Decode, 226, 8, 27, // Opcode: SMOVwb
+/* 3431 */ MCD_OPC_FilterValue, 1, 106, 86, // Skip to: 25557
+/* 3435 */ MCD_OPC_CheckPredicate, 0, 102, 86, // Skip to: 25557
+/* 3439 */ MCD_OPC_Decode, 199, 9, 24, // Opcode: SQSUBvvv_8B
+/* 3443 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 3461
+/* 3447 */ MCD_OPC_CheckPredicate, 0, 90, 86, // Skip to: 25557
+/* 3451 */ MCD_OPC_CheckField, 21, 1, 1, 84, 86, // Skip to: 25557
+/* 3457 */ MCD_OPC_Decode, 147, 10, 25, // Opcode: SSUBWvvv_8h8b
+/* 3461 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3479
+/* 3465 */ MCD_OPC_CheckPredicate, 0, 72, 86, // Skip to: 25557
+/* 3469 */ MCD_OPC_CheckField, 21, 1, 1, 66, 86, // Skip to: 25557
+/* 3475 */ MCD_OPC_Decode, 147, 2, 24, // Opcode: CMGTvvv_8B
+/* 3479 */ MCD_OPC_FilterValue, 15, 71, 0, // Skip to: 3554
+/* 3483 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 3486 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 3542
+/* 3490 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ...
+/* 3493 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 3530
+/* 3497 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ...
+/* 3500 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3518
+/* 3504 */ MCD_OPC_CheckPredicate, 0, 33, 86, // Skip to: 25557
+/* 3508 */ MCD_OPC_CheckField, 18, 1, 1, 27, 86, // Skip to: 25557
+/* 3514 */ MCD_OPC_Decode, 237, 11, 28, // Opcode: UMOVws
+/* 3518 */ MCD_OPC_FilterValue, 1, 19, 86, // Skip to: 25557
+/* 3522 */ MCD_OPC_CheckPredicate, 0, 15, 86, // Skip to: 25557
+/* 3526 */ MCD_OPC_Decode, 236, 11, 26, // Opcode: UMOVwh
+/* 3530 */ MCD_OPC_FilterValue, 1, 7, 86, // Skip to: 25557
+/* 3534 */ MCD_OPC_CheckPredicate, 0, 3, 86, // Skip to: 25557
+/* 3538 */ MCD_OPC_Decode, 235, 11, 27, // Opcode: UMOVwb
+/* 3542 */ MCD_OPC_FilterValue, 1, 251, 85, // Skip to: 25557
+/* 3546 */ MCD_OPC_CheckPredicate, 0, 247, 85, // Skip to: 25557
+/* 3550 */ MCD_OPC_Decode, 133, 2, 24, // Opcode: CMGEvvv_8B
+/* 3554 */ MCD_OPC_FilterValue, 16, 13, 0, // Skip to: 3571
+/* 3558 */ MCD_OPC_CheckPredicate, 0, 235, 85, // Skip to: 25557
+/* 3562 */ MCD_OPC_CheckField, 21, 1, 1, 229, 85, // Skip to: 25557
+/* 3568 */ MCD_OPC_Decode, 26, 29, // Opcode: ADDHNvvv_8b8h
+/* 3571 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3589
+/* 3575 */ MCD_OPC_CheckPredicate, 0, 218, 85, // Skip to: 25557
+/* 3579 */ MCD_OPC_CheckField, 21, 1, 1, 212, 85, // Skip to: 25557
+/* 3585 */ MCD_OPC_Decode, 248, 9, 24, // Opcode: SSHLvvv_8B
+/* 3589 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 3607
+/* 3593 */ MCD_OPC_CheckPredicate, 0, 200, 85, // Skip to: 25557
+/* 3597 */ MCD_OPC_CheckField, 21, 1, 1, 194, 85, // Skip to: 25557
+/* 3603 */ MCD_OPC_Decode, 182, 9, 24, // Opcode: SQSHLvvv_8B
+/* 3607 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 3625
+/* 3611 */ MCD_OPC_CheckPredicate, 0, 182, 85, // Skip to: 25557
+/* 3615 */ MCD_OPC_CheckField, 21, 1, 1, 176, 85, // Skip to: 25557
+/* 3621 */ MCD_OPC_Decode, 233, 7, 30, // Opcode: SABALvvv_8h8b
+/* 3625 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 3643
+/* 3629 */ MCD_OPC_CheckPredicate, 0, 164, 85, // Skip to: 25557
+/* 3633 */ MCD_OPC_CheckField, 21, 1, 1, 158, 85, // Skip to: 25557
+/* 3639 */ MCD_OPC_Decode, 220, 9, 24, // Opcode: SRSHLvvv_8B
+/* 3643 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3661
+/* 3647 */ MCD_OPC_CheckPredicate, 0, 146, 85, // Skip to: 25557
+/* 3651 */ MCD_OPC_CheckField, 21, 1, 1, 140, 85, // Skip to: 25557
+/* 3657 */ MCD_OPC_Decode, 151, 9, 24, // Opcode: SQRSHLvvv_8B
+/* 3661 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3679
+/* 3665 */ MCD_OPC_CheckPredicate, 0, 128, 85, // Skip to: 25557
+/* 3669 */ MCD_OPC_CheckField, 21, 1, 1, 122, 85, // Skip to: 25557
+/* 3675 */ MCD_OPC_Decode, 169, 10, 29, // Opcode: SUBHNvvv_8b8h
+/* 3679 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3697
+/* 3683 */ MCD_OPC_CheckPredicate, 0, 110, 85, // Skip to: 25557
+/* 3687 */ MCD_OPC_CheckField, 21, 1, 1, 104, 85, // Skip to: 25557
+/* 3693 */ MCD_OPC_Decode, 199, 8, 24, // Opcode: SMAXvvv_8B
+/* 3697 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3715
+/* 3701 */ MCD_OPC_CheckPredicate, 0, 92, 85, // Skip to: 25557
+/* 3705 */ MCD_OPC_CheckField, 21, 1, 1, 86, 85, // Skip to: 25557
+/* 3711 */ MCD_OPC_Decode, 212, 8, 24, // Opcode: SMINvvv_8B
+/* 3715 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3733
+/* 3719 */ MCD_OPC_CheckPredicate, 0, 74, 85, // Skip to: 25557
+/* 3723 */ MCD_OPC_CheckField, 21, 1, 1, 68, 85, // Skip to: 25557
+/* 3729 */ MCD_OPC_Decode, 245, 7, 23, // Opcode: SABDLvvv_8h8b
+/* 3733 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3751
+/* 3737 */ MCD_OPC_CheckPredicate, 0, 56, 85, // Skip to: 25557
+/* 3741 */ MCD_OPC_CheckField, 21, 1, 1, 50, 85, // Skip to: 25557
+/* 3747 */ MCD_OPC_Decode, 250, 7, 24, // Opcode: SABDvvv_8B
+/* 3751 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3769
+/* 3755 */ MCD_OPC_CheckPredicate, 0, 38, 85, // Skip to: 25557
+/* 3759 */ MCD_OPC_CheckField, 21, 1, 1, 32, 85, // Skip to: 25557
+/* 3765 */ MCD_OPC_Decode, 238, 7, 31, // Opcode: SABAvvv_8B
+/* 3769 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3787
+/* 3773 */ MCD_OPC_CheckPredicate, 0, 20, 85, // Skip to: 25557
+/* 3777 */ MCD_OPC_CheckField, 21, 1, 1, 14, 85, // Skip to: 25557
+/* 3783 */ MCD_OPC_Decode, 219, 8, 30, // Opcode: SMLALvvv_8h8b
+/* 3787 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 3804
+/* 3791 */ MCD_OPC_CheckPredicate, 0, 2, 85, // Skip to: 25557
+/* 3795 */ MCD_OPC_CheckField, 21, 1, 1, 252, 84, // Skip to: 25557
+/* 3801 */ MCD_OPC_Decode, 63, 24, // Opcode: ADDvvv_8B
+/* 3804 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3822
+/* 3808 */ MCD_OPC_CheckPredicate, 0, 241, 84, // Skip to: 25557
+/* 3812 */ MCD_OPC_CheckField, 16, 6, 32, 235, 84, // Skip to: 25557
+/* 3818 */ MCD_OPC_Decode, 140, 2, 32, // Opcode: CMGTvvi_8B
+/* 3822 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 3840
+/* 3826 */ MCD_OPC_CheckPredicate, 0, 223, 84, // Skip to: 25557
+/* 3830 */ MCD_OPC_CheckField, 21, 1, 1, 217, 84, // Skip to: 25557
+/* 3836 */ MCD_OPC_Decode, 226, 2, 24, // Opcode: CMTSTvvv_8B
+/* 3840 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 3858
+/* 3844 */ MCD_OPC_CheckPredicate, 0, 205, 84, // Skip to: 25557
+/* 3848 */ MCD_OPC_CheckField, 21, 1, 1, 199, 84, // Skip to: 25557
+/* 3854 */ MCD_OPC_Decode, 231, 6, 31, // Opcode: MLAvvv_8B
+/* 3858 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 3876
+/* 3862 */ MCD_OPC_CheckPredicate, 0, 187, 84, // Skip to: 25557
+/* 3866 */ MCD_OPC_CheckField, 16, 6, 32, 181, 84, // Skip to: 25557
+/* 3872 */ MCD_OPC_Decode, 240, 1, 32, // Opcode: CMEQvvi_8B
+/* 3876 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 3894
+/* 3880 */ MCD_OPC_CheckPredicate, 0, 169, 84, // Skip to: 25557
+/* 3884 */ MCD_OPC_CheckField, 21, 1, 1, 163, 84, // Skip to: 25557
+/* 3890 */ MCD_OPC_Decode, 136, 7, 24, // Opcode: MULvvv_8B
+/* 3894 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3912
+/* 3898 */ MCD_OPC_CheckPredicate, 0, 151, 84, // Skip to: 25557
+/* 3902 */ MCD_OPC_CheckField, 21, 1, 1, 145, 84, // Skip to: 25557
+/* 3908 */ MCD_OPC_Decode, 225, 8, 30, // Opcode: SMLSLvvv_8h8b
+/* 3912 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3930
+/* 3916 */ MCD_OPC_CheckPredicate, 0, 133, 84, // Skip to: 25557
+/* 3920 */ MCD_OPC_CheckField, 21, 1, 1, 127, 84, // Skip to: 25557
+/* 3926 */ MCD_OPC_Decode, 193, 8, 24, // Opcode: SMAXPvvv_8B
+/* 3930 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3948
+/* 3934 */ MCD_OPC_CheckPredicate, 0, 115, 84, // Skip to: 25557
+/* 3938 */ MCD_OPC_CheckField, 16, 6, 32, 109, 84, // Skip to: 25557
+/* 3944 */ MCD_OPC_Decode, 175, 2, 32, // Opcode: CMLTvvi_8B
+/* 3948 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 3966
+/* 3952 */ MCD_OPC_CheckPredicate, 0, 97, 84, // Skip to: 25557
+/* 3956 */ MCD_OPC_CheckField, 21, 1, 1, 91, 84, // Skip to: 25557
+/* 3962 */ MCD_OPC_Decode, 206, 8, 24, // Opcode: SMINPvvv_8B
+/* 3966 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 3983
+/* 3970 */ MCD_OPC_CheckPredicate, 0, 79, 84, // Skip to: 25557
+/* 3974 */ MCD_OPC_CheckField, 21, 1, 1, 73, 84, // Skip to: 25557
+/* 3980 */ MCD_OPC_Decode, 32, 24, // Opcode: ADDP_8B
+/* 3983 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 4001
+/* 3987 */ MCD_OPC_CheckPredicate, 0, 62, 84, // Skip to: 25557
+/* 3991 */ MCD_OPC_CheckField, 21, 1, 1, 56, 84, // Skip to: 25557
+/* 3997 */ MCD_OPC_Decode, 238, 8, 23, // Opcode: SMULLvvv_8h8b
+/* 4001 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 4019
+/* 4005 */ MCD_OPC_CheckPredicate, 0, 44, 84, // Skip to: 25557
+/* 4009 */ MCD_OPC_CheckField, 21, 1, 1, 38, 84, // Skip to: 25557
+/* 4015 */ MCD_OPC_Decode, 147, 4, 24, // Opcode: FMAXNMvvv_2S
+/* 4019 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 4037
+/* 4023 */ MCD_OPC_CheckPredicate, 0, 26, 84, // Skip to: 25557
+/* 4027 */ MCD_OPC_CheckField, 21, 1, 1, 20, 84, // Skip to: 25557
+/* 4033 */ MCD_OPC_Decode, 180, 4, 31, // Opcode: FMLAvvv_2S
+/* 4037 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 4055
+/* 4041 */ MCD_OPC_CheckPredicate, 0, 8, 84, // Skip to: 25557
+/* 4045 */ MCD_OPC_CheckField, 21, 1, 1, 2, 84, // Skip to: 25557
+/* 4051 */ MCD_OPC_Decode, 166, 3, 24, // Opcode: FADDvvv_2S
+/* 4055 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 4073
+/* 4059 */ MCD_OPC_CheckPredicate, 0, 246, 83, // Skip to: 25557
+/* 4063 */ MCD_OPC_CheckField, 21, 1, 1, 240, 83, // Skip to: 25557
+/* 4069 */ MCD_OPC_Decode, 201, 4, 24, // Opcode: FMULXvvv_2S
+/* 4073 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 4091
+/* 4077 */ MCD_OPC_CheckPredicate, 0, 228, 83, // Skip to: 25557
+/* 4081 */ MCD_OPC_CheckField, 21, 1, 1, 222, 83, // Skip to: 25557
+/* 4087 */ MCD_OPC_Decode, 179, 7, 23, // Opcode: PMULLvvv_8h8b
+/* 4091 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 4109
+/* 4095 */ MCD_OPC_CheckPredicate, 0, 210, 83, // Skip to: 25557
+/* 4099 */ MCD_OPC_CheckField, 21, 1, 1, 204, 83, // Skip to: 25557
+/* 4105 */ MCD_OPC_Decode, 176, 3, 24, // Opcode: FCMEQvvv_2S
+/* 4109 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4127
+/* 4113 */ MCD_OPC_CheckPredicate, 0, 192, 83, // Skip to: 25557
+/* 4117 */ MCD_OPC_CheckField, 21, 1, 1, 186, 83, // Skip to: 25557
+/* 4123 */ MCD_OPC_Decode, 157, 4, 24, // Opcode: FMAXvvv_2S
+/* 4127 */ MCD_OPC_FilterValue, 63, 178, 83, // Skip to: 25557
+/* 4131 */ MCD_OPC_CheckPredicate, 0, 174, 83, // Skip to: 25557
+/* 4135 */ MCD_OPC_CheckField, 21, 1, 1, 168, 83, // Skip to: 25557
+/* 4141 */ MCD_OPC_Decode, 217, 4, 24, // Opcode: FRECPSvvv_2S
+/* 4145 */ MCD_OPC_FilterValue, 1, 247, 2, // Skip to: 4908
+/* 4149 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 4152 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4170
+/* 4156 */ MCD_OPC_CheckPredicate, 0, 149, 83, // Skip to: 25557
+/* 4160 */ MCD_OPC_CheckField, 21, 1, 1, 143, 83, // Skip to: 25557
+/* 4166 */ MCD_OPC_Decode, 163, 11, 23, // Opcode: UADDLvvv_8h8b
+/* 4170 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4188
+/* 4174 */ MCD_OPC_CheckPredicate, 0, 131, 83, // Skip to: 25557
+/* 4178 */ MCD_OPC_CheckField, 21, 1, 1, 125, 83, // Skip to: 25557
+/* 4184 */ MCD_OPC_Decode, 190, 11, 24, // Opcode: UHADDvvv_8B
+/* 4188 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 4206
+/* 4192 */ MCD_OPC_CheckPredicate, 0, 113, 83, // Skip to: 25557
+/* 4196 */ MCD_OPC_CheckField, 21, 1, 1, 107, 83, // Skip to: 25557
+/* 4202 */ MCD_OPC_Decode, 128, 12, 24, // Opcode: UQADDvvv_8B
+/* 4206 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 4224
+/* 4210 */ MCD_OPC_CheckPredicate, 0, 95, 83, // Skip to: 25557
+/* 4214 */ MCD_OPC_CheckField, 21, 1, 1, 89, 83, // Skip to: 25557
+/* 4220 */ MCD_OPC_Decode, 169, 11, 25, // Opcode: UADDWvvv_8h8b
+/* 4224 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 4242
+/* 4228 */ MCD_OPC_CheckPredicate, 0, 77, 83, // Skip to: 25557
+/* 4232 */ MCD_OPC_CheckField, 21, 1, 1, 71, 83, // Skip to: 25557
+/* 4238 */ MCD_OPC_Decode, 186, 12, 24, // Opcode: URHADDvvv_8B
+/* 4242 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 4260
+/* 4246 */ MCD_OPC_CheckPredicate, 0, 59, 83, // Skip to: 25557
+/* 4250 */ MCD_OPC_CheckField, 21, 1, 1, 53, 83, // Skip to: 25557
+/* 4256 */ MCD_OPC_Decode, 132, 3, 24, // Opcode: EORvvv_8B
+/* 4260 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 4278
+/* 4264 */ MCD_OPC_CheckPredicate, 0, 41, 83, // Skip to: 25557
+/* 4268 */ MCD_OPC_CheckField, 21, 1, 1, 35, 83, // Skip to: 25557
+/* 4274 */ MCD_OPC_Decode, 243, 12, 23, // Opcode: USUBLvvv_8h8b
+/* 4278 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 4296
+/* 4282 */ MCD_OPC_CheckPredicate, 0, 23, 83, // Skip to: 25557
+/* 4286 */ MCD_OPC_CheckField, 21, 1, 1, 17, 83, // Skip to: 25557
+/* 4292 */ MCD_OPC_Decode, 196, 11, 24, // Opcode: UHSUBvvv_8B
+/* 4296 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 4314
+/* 4300 */ MCD_OPC_CheckPredicate, 0, 5, 83, // Skip to: 25557
+/* 4304 */ MCD_OPC_CheckField, 21, 1, 1, 255, 82, // Skip to: 25557
+/* 4310 */ MCD_OPC_Decode, 180, 12, 24, // Opcode: UQSUBvvv_8B
+/* 4314 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 4332
+/* 4318 */ MCD_OPC_CheckPredicate, 0, 243, 82, // Skip to: 25557
+/* 4322 */ MCD_OPC_CheckField, 21, 1, 1, 237, 82, // Skip to: 25557
+/* 4328 */ MCD_OPC_Decode, 249, 12, 25, // Opcode: USUBWvvv_8h8b
+/* 4332 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 4350
+/* 4336 */ MCD_OPC_CheckPredicate, 0, 225, 82, // Skip to: 25557
+/* 4340 */ MCD_OPC_CheckField, 21, 1, 1, 219, 82, // Skip to: 25557
+/* 4346 */ MCD_OPC_Decode, 154, 2, 24, // Opcode: CMHIvvv_8B
+/* 4350 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 4368
+/* 4354 */ MCD_OPC_CheckPredicate, 0, 207, 82, // Skip to: 25557
+/* 4358 */ MCD_OPC_CheckField, 21, 1, 1, 201, 82, // Skip to: 25557
+/* 4364 */ MCD_OPC_Decode, 161, 2, 24, // Opcode: CMHSvvv_8B
+/* 4368 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 4386
+/* 4372 */ MCD_OPC_CheckPredicate, 0, 189, 82, // Skip to: 25557
+/* 4376 */ MCD_OPC_CheckField, 21, 1, 1, 183, 82, // Skip to: 25557
+/* 4382 */ MCD_OPC_Decode, 204, 7, 29, // Opcode: RADDHNvvv_8b8h
+/* 4386 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 4404
+/* 4390 */ MCD_OPC_CheckPredicate, 0, 171, 82, // Skip to: 25557
+/* 4394 */ MCD_OPC_CheckField, 21, 1, 1, 165, 82, // Skip to: 25557
+/* 4400 */ MCD_OPC_Decode, 222, 12, 24, // Opcode: USHLvvv_8B
+/* 4404 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 4422
+/* 4408 */ MCD_OPC_CheckPredicate, 0, 153, 82, // Skip to: 25557
+/* 4412 */ MCD_OPC_CheckField, 21, 1, 1, 147, 82, // Skip to: 25557
+/* 4418 */ MCD_OPC_Decode, 163, 12, 24, // Opcode: UQSHLvvv_8B
+/* 4422 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 4440
+/* 4426 */ MCD_OPC_CheckPredicate, 0, 135, 82, // Skip to: 25557
+/* 4430 */ MCD_OPC_CheckField, 21, 1, 1, 129, 82, // Skip to: 25557
+/* 4436 */ MCD_OPC_Decode, 139, 11, 30, // Opcode: UABALvvv_8h8b
+/* 4440 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 4458
+/* 4444 */ MCD_OPC_CheckPredicate, 0, 117, 82, // Skip to: 25557
+/* 4448 */ MCD_OPC_CheckField, 21, 1, 1, 111, 82, // Skip to: 25557
+/* 4454 */ MCD_OPC_Decode, 194, 12, 24, // Opcode: URSHLvvv_8B
+/* 4458 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 4476
+/* 4462 */ MCD_OPC_CheckPredicate, 0, 99, 82, // Skip to: 25557
+/* 4466 */ MCD_OPC_CheckField, 21, 1, 1, 93, 82, // Skip to: 25557
+/* 4472 */ MCD_OPC_Decode, 139, 12, 24, // Opcode: UQRSHLvvv_8B
+/* 4476 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 4494
+/* 4480 */ MCD_OPC_CheckPredicate, 0, 81, 82, // Skip to: 25557
+/* 4484 */ MCD_OPC_CheckField, 21, 1, 1, 75, 82, // Skip to: 25557
+/* 4490 */ MCD_OPC_Decode, 227, 7, 29, // Opcode: RSUBHNvvv_8b8h
+/* 4494 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 4512
+/* 4498 */ MCD_OPC_CheckPredicate, 0, 63, 82, // Skip to: 25557
+/* 4502 */ MCD_OPC_CheckField, 21, 1, 1, 57, 82, // Skip to: 25557
+/* 4508 */ MCD_OPC_Decode, 209, 11, 24, // Opcode: UMAXvvv_8B
+/* 4512 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 4530
+/* 4516 */ MCD_OPC_CheckPredicate, 0, 45, 82, // Skip to: 25557
+/* 4520 */ MCD_OPC_CheckField, 21, 1, 1, 39, 82, // Skip to: 25557
+/* 4526 */ MCD_OPC_Decode, 221, 11, 24, // Opcode: UMINvvv_8B
+/* 4530 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 4548
+/* 4534 */ MCD_OPC_CheckPredicate, 0, 27, 82, // Skip to: 25557
+/* 4538 */ MCD_OPC_CheckField, 21, 1, 1, 21, 82, // Skip to: 25557
+/* 4544 */ MCD_OPC_Decode, 151, 11, 23, // Opcode: UABDLvvv_8h8b
+/* 4548 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 4566
+/* 4552 */ MCD_OPC_CheckPredicate, 0, 9, 82, // Skip to: 25557
+/* 4556 */ MCD_OPC_CheckField, 21, 1, 1, 3, 82, // Skip to: 25557
+/* 4562 */ MCD_OPC_Decode, 156, 11, 24, // Opcode: UABDvvv_8B
+/* 4566 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 4584
+/* 4570 */ MCD_OPC_CheckPredicate, 0, 247, 81, // Skip to: 25557
+/* 4574 */ MCD_OPC_CheckField, 21, 1, 1, 241, 81, // Skip to: 25557
+/* 4580 */ MCD_OPC_Decode, 144, 11, 31, // Opcode: UABAvvv_8B
+/* 4584 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 4602
+/* 4588 */ MCD_OPC_CheckPredicate, 0, 229, 81, // Skip to: 25557
+/* 4592 */ MCD_OPC_CheckField, 21, 1, 1, 223, 81, // Skip to: 25557
+/* 4598 */ MCD_OPC_Decode, 228, 11, 30, // Opcode: UMLALvvv_8h8b
+/* 4602 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 4620
+/* 4606 */ MCD_OPC_CheckPredicate, 0, 211, 81, // Skip to: 25557
+/* 4610 */ MCD_OPC_CheckField, 21, 1, 1, 205, 81, // Skip to: 25557
+/* 4616 */ MCD_OPC_Decode, 198, 10, 24, // Opcode: SUBvvv_8B
+/* 4620 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 4638
+/* 4624 */ MCD_OPC_CheckPredicate, 0, 193, 81, // Skip to: 25557
+/* 4628 */ MCD_OPC_CheckField, 16, 6, 32, 187, 81, // Skip to: 25557
+/* 4634 */ MCD_OPC_Decode, 254, 1, 32, // Opcode: CMGEvvi_8B
+/* 4638 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 4656
+/* 4642 */ MCD_OPC_CheckPredicate, 0, 175, 81, // Skip to: 25557
+/* 4646 */ MCD_OPC_CheckField, 21, 1, 1, 169, 81, // Skip to: 25557
+/* 4652 */ MCD_OPC_Decode, 247, 1, 24, // Opcode: CMEQvvv_8B
+/* 4656 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 4674
+/* 4660 */ MCD_OPC_CheckPredicate, 0, 157, 81, // Skip to: 25557
+/* 4664 */ MCD_OPC_CheckField, 21, 1, 1, 151, 81, // Skip to: 25557
+/* 4670 */ MCD_OPC_Decode, 237, 6, 31, // Opcode: MLSvvv_8B
+/* 4674 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 4692
+/* 4678 */ MCD_OPC_CheckPredicate, 0, 139, 81, // Skip to: 25557
+/* 4682 */ MCD_OPC_CheckField, 16, 6, 32, 133, 81, // Skip to: 25557
+/* 4688 */ MCD_OPC_Decode, 168, 2, 32, // Opcode: CMLEvvi_8B
+/* 4692 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 4710
+/* 4696 */ MCD_OPC_CheckPredicate, 0, 121, 81, // Skip to: 25557
+/* 4700 */ MCD_OPC_CheckField, 21, 1, 1, 115, 81, // Skip to: 25557
+/* 4706 */ MCD_OPC_Decode, 181, 7, 24, // Opcode: PMULvvv_8B
+/* 4710 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 4728
+/* 4714 */ MCD_OPC_CheckPredicate, 0, 103, 81, // Skip to: 25557
+/* 4718 */ MCD_OPC_CheckField, 21, 1, 1, 97, 81, // Skip to: 25557
+/* 4724 */ MCD_OPC_Decode, 234, 11, 30, // Opcode: UMLSLvvv_8h8b
+/* 4728 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 4746
+/* 4732 */ MCD_OPC_CheckPredicate, 0, 85, 81, // Skip to: 25557
+/* 4736 */ MCD_OPC_CheckField, 21, 1, 1, 79, 81, // Skip to: 25557
+/* 4742 */ MCD_OPC_Decode, 203, 11, 24, // Opcode: UMAXPvvv_8B
+/* 4746 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 4764
+/* 4750 */ MCD_OPC_CheckPredicate, 0, 67, 81, // Skip to: 25557
+/* 4754 */ MCD_OPC_CheckField, 21, 1, 1, 61, 81, // Skip to: 25557
+/* 4760 */ MCD_OPC_Decode, 215, 11, 24, // Opcode: UMINPvvv_8B
+/* 4764 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 4782
+/* 4768 */ MCD_OPC_CheckPredicate, 0, 49, 81, // Skip to: 25557
+/* 4772 */ MCD_OPC_CheckField, 21, 1, 1, 43, 81, // Skip to: 25557
+/* 4778 */ MCD_OPC_Decode, 246, 11, 23, // Opcode: UMULLvvv_8h8b
+/* 4782 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 4800
+/* 4786 */ MCD_OPC_CheckPredicate, 0, 31, 81, // Skip to: 25557
+/* 4790 */ MCD_OPC_CheckField, 21, 1, 1, 25, 81, // Skip to: 25557
+/* 4796 */ MCD_OPC_Decode, 142, 4, 24, // Opcode: FMAXNMPvvv_2S
+/* 4800 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 4818
+/* 4804 */ MCD_OPC_CheckPredicate, 0, 13, 81, // Skip to: 25557
+/* 4808 */ MCD_OPC_CheckField, 21, 1, 1, 7, 81, // Skip to: 25557
+/* 4814 */ MCD_OPC_Decode, 159, 3, 24, // Opcode: FADDP_2S
+/* 4818 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 4836
+/* 4822 */ MCD_OPC_CheckPredicate, 0, 251, 80, // Skip to: 25557
+/* 4826 */ MCD_OPC_CheckField, 21, 1, 1, 245, 80, // Skip to: 25557
+/* 4832 */ MCD_OPC_Decode, 206, 4, 24, // Opcode: FMULvvv_2S
+/* 4836 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 4854
+/* 4840 */ MCD_OPC_CheckPredicate, 0, 233, 80, // Skip to: 25557
+/* 4844 */ MCD_OPC_CheckField, 21, 1, 1, 227, 80, // Skip to: 25557
+/* 4850 */ MCD_OPC_Decode, 182, 3, 24, // Opcode: FCMGEvvv_2S
+/* 4854 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 4872
+/* 4858 */ MCD_OPC_CheckPredicate, 0, 215, 80, // Skip to: 25557
+/* 4862 */ MCD_OPC_CheckField, 21, 1, 1, 209, 80, // Skip to: 25557
+/* 4868 */ MCD_OPC_Decode, 153, 3, 24, // Opcode: FACGEvvv_2S
+/* 4872 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4890
+/* 4876 */ MCD_OPC_CheckPredicate, 0, 197, 80, // Skip to: 25557
+/* 4880 */ MCD_OPC_CheckField, 21, 1, 1, 191, 80, // Skip to: 25557
+/* 4886 */ MCD_OPC_Decode, 152, 4, 24, // Opcode: FMAXPvvv_2S
+/* 4890 */ MCD_OPC_FilterValue, 63, 183, 80, // Skip to: 25557
+/* 4894 */ MCD_OPC_CheckPredicate, 0, 179, 80, // Skip to: 25557
+/* 4898 */ MCD_OPC_CheckField, 21, 1, 1, 173, 80, // Skip to: 25557
+/* 4904 */ MCD_OPC_Decode, 135, 4, 24, // Opcode: FDIVvvv_2S
+/* 4908 */ MCD_OPC_FilterValue, 2, 193, 3, // Skip to: 5873
+/* 4912 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 4915 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4933
+/* 4919 */ MCD_OPC_CheckPredicate, 0, 154, 80, // Skip to: 25557
+/* 4923 */ MCD_OPC_CheckField, 21, 1, 1, 148, 80, // Skip to: 25557
+/* 4929 */ MCD_OPC_Decode, 254, 7, 33, // Opcode: SADDL2vvv_8h16b
+/* 4933 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4951
+/* 4937 */ MCD_OPC_CheckPredicate, 0, 136, 80, // Skip to: 25557
+/* 4941 */ MCD_OPC_CheckField, 21, 1, 1, 130, 80, // Skip to: 25557
+/* 4947 */ MCD_OPC_Decode, 156, 8, 33, // Opcode: SHADDvvv_16B
+/* 4951 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 4969
+/* 4955 */ MCD_OPC_CheckPredicate, 0, 118, 80, // Skip to: 25557
+/* 4959 */ MCD_OPC_CheckField, 21, 1, 1, 112, 80, // Skip to: 25557
+/* 4965 */ MCD_OPC_Decode, 243, 8, 33, // Opcode: SQADDvvv_16B
+/* 4969 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 4987
+/* 4973 */ MCD_OPC_CheckPredicate, 0, 100, 80, // Skip to: 25557
+/* 4977 */ MCD_OPC_CheckField, 21, 1, 1, 94, 80, // Skip to: 25557
+/* 4983 */ MCD_OPC_Decode, 132, 8, 33, // Opcode: SADDW2vvv_8h16b
+/* 4987 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 5005
+/* 4991 */ MCD_OPC_CheckPredicate, 0, 82, 80, // Skip to: 25557
+/* 4995 */ MCD_OPC_CheckField, 21, 1, 1, 76, 80, // Skip to: 25557
+/* 5001 */ MCD_OPC_Decode, 201, 9, 33, // Opcode: SRHADDvvv_16B
+/* 5005 */ MCD_OPC_FilterValue, 7, 89, 0, // Skip to: 5098
+/* 5009 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5012 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 5087
+/* 5016 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ...
+/* 5019 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 5075
+/* 5023 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ...
+/* 5026 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 5063
+/* 5030 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ...
+/* 5033 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5051
+/* 5037 */ MCD_OPC_CheckPredicate, 0, 36, 80, // Skip to: 25557
+/* 5041 */ MCD_OPC_CheckField, 19, 1, 1, 30, 80, // Skip to: 25557
+/* 5047 */ MCD_OPC_Decode, 253, 4, 34, // Opcode: INSdx
+/* 5051 */ MCD_OPC_FilterValue, 1, 22, 80, // Skip to: 25557
+/* 5055 */ MCD_OPC_CheckPredicate, 0, 18, 80, // Skip to: 25557
+/* 5059 */ MCD_OPC_Decode, 255, 4, 35, // Opcode: INSsw
+/* 5063 */ MCD_OPC_FilterValue, 1, 10, 80, // Skip to: 25557
+/* 5067 */ MCD_OPC_CheckPredicate, 0, 6, 80, // Skip to: 25557
+/* 5071 */ MCD_OPC_Decode, 254, 4, 36, // Opcode: INShw
+/* 5075 */ MCD_OPC_FilterValue, 1, 254, 79, // Skip to: 25557
+/* 5079 */ MCD_OPC_CheckPredicate, 0, 250, 79, // Skip to: 25557
+/* 5083 */ MCD_OPC_Decode, 252, 4, 37, // Opcode: INSbw
+/* 5087 */ MCD_OPC_FilterValue, 1, 242, 79, // Skip to: 25557
+/* 5091 */ MCD_OPC_CheckPredicate, 0, 238, 79, // Skip to: 25557
+/* 5095 */ MCD_OPC_Decode, 113, 33, // Opcode: ANDvvv_16B
+/* 5098 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 5116
+/* 5102 */ MCD_OPC_CheckPredicate, 0, 227, 79, // Skip to: 25557
+/* 5106 */ MCD_OPC_CheckField, 21, 1, 1, 221, 79, // Skip to: 25557
+/* 5112 */ MCD_OPC_Decode, 138, 10, 33, // Opcode: SSUBL2vvv_8h16b
+/* 5116 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 5134
+/* 5120 */ MCD_OPC_CheckPredicate, 0, 209, 79, // Skip to: 25557
+/* 5124 */ MCD_OPC_CheckField, 21, 1, 1, 203, 79, // Skip to: 25557
+/* 5130 */ MCD_OPC_Decode, 175, 8, 33, // Opcode: SHSUBvvv_16B
+/* 5134 */ MCD_OPC_FilterValue, 11, 71, 0, // Skip to: 5209
+/* 5138 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5141 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 5197
+/* 5145 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ...
+/* 5148 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 5185
+/* 5152 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ...
+/* 5155 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5173
+/* 5159 */ MCD_OPC_CheckPredicate, 0, 170, 79, // Skip to: 25557
+/* 5163 */ MCD_OPC_CheckField, 18, 1, 1, 164, 79, // Skip to: 25557
+/* 5169 */ MCD_OPC_Decode, 230, 8, 38, // Opcode: SMOVxs
+/* 5173 */ MCD_OPC_FilterValue, 1, 156, 79, // Skip to: 25557
+/* 5177 */ MCD_OPC_CheckPredicate, 0, 152, 79, // Skip to: 25557
+/* 5181 */ MCD_OPC_Decode, 229, 8, 39, // Opcode: SMOVxh
+/* 5185 */ MCD_OPC_FilterValue, 1, 144, 79, // Skip to: 25557
+/* 5189 */ MCD_OPC_CheckPredicate, 0, 140, 79, // Skip to: 25557
+/* 5193 */ MCD_OPC_Decode, 228, 8, 40, // Opcode: SMOVxb
+/* 5197 */ MCD_OPC_FilterValue, 1, 132, 79, // Skip to: 25557
+/* 5201 */ MCD_OPC_CheckPredicate, 0, 128, 79, // Skip to: 25557
+/* 5205 */ MCD_OPC_Decode, 194, 9, 33, // Opcode: SQSUBvvv_16B
+/* 5209 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 5227
+/* 5213 */ MCD_OPC_CheckPredicate, 0, 116, 79, // Skip to: 25557
+/* 5217 */ MCD_OPC_CheckField, 21, 1, 1, 110, 79, // Skip to: 25557
+/* 5223 */ MCD_OPC_Decode, 144, 10, 33, // Opcode: SSUBW2vvv_8h16b
+/* 5227 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 5245
+/* 5231 */ MCD_OPC_CheckPredicate, 0, 98, 79, // Skip to: 25557
+/* 5235 */ MCD_OPC_CheckField, 21, 1, 1, 92, 79, // Skip to: 25557
+/* 5241 */ MCD_OPC_Decode, 142, 2, 33, // Opcode: CMGTvvv_16B
+/* 5245 */ MCD_OPC_FilterValue, 15, 33, 0, // Skip to: 5282
+/* 5249 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5252 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5270
+/* 5256 */ MCD_OPC_CheckPredicate, 0, 73, 79, // Skip to: 25557
+/* 5260 */ MCD_OPC_CheckField, 16, 4, 8, 67, 79, // Skip to: 25557
+/* 5266 */ MCD_OPC_Decode, 238, 11, 41, // Opcode: UMOVxd
+/* 5270 */ MCD_OPC_FilterValue, 1, 59, 79, // Skip to: 25557
+/* 5274 */ MCD_OPC_CheckPredicate, 0, 55, 79, // Skip to: 25557
+/* 5278 */ MCD_OPC_Decode, 128, 2, 33, // Opcode: CMGEvvv_16B
+/* 5282 */ MCD_OPC_FilterValue, 16, 13, 0, // Skip to: 5299
+/* 5286 */ MCD_OPC_CheckPredicate, 0, 43, 79, // Skip to: 25557
+/* 5290 */ MCD_OPC_CheckField, 21, 1, 1, 37, 79, // Skip to: 25557
+/* 5296 */ MCD_OPC_Decode, 21, 42, // Opcode: ADDHN2vvv_16b8h
+/* 5299 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 5317
+/* 5303 */ MCD_OPC_CheckPredicate, 0, 26, 79, // Skip to: 25557
+/* 5307 */ MCD_OPC_CheckField, 21, 1, 1, 20, 79, // Skip to: 25557
+/* 5313 */ MCD_OPC_Decode, 243, 9, 33, // Opcode: SSHLvvv_16B
+/* 5317 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 5335
+/* 5321 */ MCD_OPC_CheckPredicate, 0, 8, 79, // Skip to: 25557
+/* 5325 */ MCD_OPC_CheckField, 21, 1, 1, 2, 79, // Skip to: 25557
+/* 5331 */ MCD_OPC_Decode, 177, 9, 33, // Opcode: SQSHLvvv_16B
+/* 5335 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 5353
+/* 5339 */ MCD_OPC_CheckPredicate, 0, 246, 78, // Skip to: 25557
+/* 5343 */ MCD_OPC_CheckField, 21, 1, 1, 240, 78, // Skip to: 25557
+/* 5349 */ MCD_OPC_Decode, 230, 7, 42, // Opcode: SABAL2vvv_8h8b
+/* 5353 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 5371
+/* 5357 */ MCD_OPC_CheckPredicate, 0, 228, 78, // Skip to: 25557
+/* 5361 */ MCD_OPC_CheckField, 21, 1, 1, 222, 78, // Skip to: 25557
+/* 5367 */ MCD_OPC_Decode, 215, 9, 33, // Opcode: SRSHLvvv_16B
+/* 5371 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 5389
+/* 5375 */ MCD_OPC_CheckPredicate, 0, 210, 78, // Skip to: 25557
+/* 5379 */ MCD_OPC_CheckField, 21, 1, 1, 204, 78, // Skip to: 25557
+/* 5385 */ MCD_OPC_Decode, 146, 9, 33, // Opcode: SQRSHLvvv_16B
+/* 5389 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 5407
+/* 5393 */ MCD_OPC_CheckPredicate, 0, 192, 78, // Skip to: 25557
+/* 5397 */ MCD_OPC_CheckField, 21, 1, 1, 186, 78, // Skip to: 25557
+/* 5403 */ MCD_OPC_Decode, 164, 10, 42, // Opcode: SUBHN2vvv_16b8h
+/* 5407 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 5425
+/* 5411 */ MCD_OPC_CheckPredicate, 0, 174, 78, // Skip to: 25557
+/* 5415 */ MCD_OPC_CheckField, 21, 1, 1, 168, 78, // Skip to: 25557
+/* 5421 */ MCD_OPC_Decode, 195, 8, 33, // Opcode: SMAXvvv_16B
+/* 5425 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 5443
+/* 5429 */ MCD_OPC_CheckPredicate, 0, 156, 78, // Skip to: 25557
+/* 5433 */ MCD_OPC_CheckField, 21, 1, 1, 150, 78, // Skip to: 25557
+/* 5439 */ MCD_OPC_Decode, 208, 8, 33, // Opcode: SMINvvv_16B
+/* 5443 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 5461
+/* 5447 */ MCD_OPC_CheckPredicate, 0, 138, 78, // Skip to: 25557
+/* 5451 */ MCD_OPC_CheckField, 21, 1, 1, 132, 78, // Skip to: 25557
+/* 5457 */ MCD_OPC_Decode, 242, 7, 33, // Opcode: SABDL2vvv_8h8b
+/* 5461 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 5479
+/* 5465 */ MCD_OPC_CheckPredicate, 0, 120, 78, // Skip to: 25557
+/* 5469 */ MCD_OPC_CheckField, 21, 1, 1, 114, 78, // Skip to: 25557
+/* 5475 */ MCD_OPC_Decode, 246, 7, 33, // Opcode: SABDvvv_16B
+/* 5479 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 5497
+/* 5483 */ MCD_OPC_CheckPredicate, 0, 102, 78, // Skip to: 25557
+/* 5487 */ MCD_OPC_CheckField, 21, 1, 1, 96, 78, // Skip to: 25557
+/* 5493 */ MCD_OPC_Decode, 234, 7, 42, // Opcode: SABAvvv_16B
+/* 5497 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 5515
+/* 5501 */ MCD_OPC_CheckPredicate, 0, 84, 78, // Skip to: 25557
+/* 5505 */ MCD_OPC_CheckField, 21, 1, 1, 78, 78, // Skip to: 25557
+/* 5511 */ MCD_OPC_Decode, 216, 8, 42, // Opcode: SMLAL2vvv_8h16b
+/* 5515 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 5532
+/* 5519 */ MCD_OPC_CheckPredicate, 0, 66, 78, // Skip to: 25557
+/* 5523 */ MCD_OPC_CheckField, 21, 1, 1, 60, 78, // Skip to: 25557
+/* 5529 */ MCD_OPC_Decode, 58, 33, // Opcode: ADDvvv_16B
+/* 5532 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 5550
+/* 5536 */ MCD_OPC_CheckPredicate, 0, 49, 78, // Skip to: 25557
+/* 5540 */ MCD_OPC_CheckField, 16, 6, 32, 43, 78, // Skip to: 25557
+/* 5546 */ MCD_OPC_Decode, 135, 2, 43, // Opcode: CMGTvvi_16B
+/* 5550 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 5568
+/* 5554 */ MCD_OPC_CheckPredicate, 0, 31, 78, // Skip to: 25557
+/* 5558 */ MCD_OPC_CheckField, 21, 1, 1, 25, 78, // Skip to: 25557
+/* 5564 */ MCD_OPC_Decode, 221, 2, 33, // Opcode: CMTSTvvv_16B
+/* 5568 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 5586
+/* 5572 */ MCD_OPC_CheckPredicate, 0, 13, 78, // Skip to: 25557
+/* 5576 */ MCD_OPC_CheckField, 21, 1, 1, 7, 78, // Skip to: 25557
+/* 5582 */ MCD_OPC_Decode, 227, 6, 42, // Opcode: MLAvvv_16B
+/* 5586 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 5604
+/* 5590 */ MCD_OPC_CheckPredicate, 0, 251, 77, // Skip to: 25557
+/* 5594 */ MCD_OPC_CheckField, 16, 6, 32, 245, 77, // Skip to: 25557
+/* 5600 */ MCD_OPC_Decode, 235, 1, 43, // Opcode: CMEQvvi_16B
+/* 5604 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 5622
+/* 5608 */ MCD_OPC_CheckPredicate, 0, 233, 77, // Skip to: 25557
+/* 5612 */ MCD_OPC_CheckField, 21, 1, 1, 227, 77, // Skip to: 25557
+/* 5618 */ MCD_OPC_Decode, 132, 7, 33, // Opcode: MULvvv_16B
+/* 5622 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 5640
+/* 5626 */ MCD_OPC_CheckPredicate, 0, 215, 77, // Skip to: 25557
+/* 5630 */ MCD_OPC_CheckField, 21, 1, 1, 209, 77, // Skip to: 25557
+/* 5636 */ MCD_OPC_Decode, 222, 8, 42, // Opcode: SMLSL2vvv_8h16b
+/* 5640 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 5658
+/* 5644 */ MCD_OPC_CheckPredicate, 0, 197, 77, // Skip to: 25557
+/* 5648 */ MCD_OPC_CheckField, 21, 1, 1, 191, 77, // Skip to: 25557
+/* 5654 */ MCD_OPC_Decode, 189, 8, 33, // Opcode: SMAXPvvv_16B
+/* 5658 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 5676
+/* 5662 */ MCD_OPC_CheckPredicate, 0, 179, 77, // Skip to: 25557
+/* 5666 */ MCD_OPC_CheckField, 16, 6, 32, 173, 77, // Skip to: 25557
+/* 5672 */ MCD_OPC_Decode, 170, 2, 43, // Opcode: CMLTvvi_16B
+/* 5676 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 5694
+/* 5680 */ MCD_OPC_CheckPredicate, 0, 161, 77, // Skip to: 25557
+/* 5684 */ MCD_OPC_CheckField, 21, 1, 1, 155, 77, // Skip to: 25557
+/* 5690 */ MCD_OPC_Decode, 202, 8, 33, // Opcode: SMINPvvv_16B
+/* 5694 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 5711
+/* 5698 */ MCD_OPC_CheckPredicate, 0, 143, 77, // Skip to: 25557
+/* 5702 */ MCD_OPC_CheckField, 21, 1, 1, 137, 77, // Skip to: 25557
+/* 5708 */ MCD_OPC_Decode, 27, 33, // Opcode: ADDP_16B
+/* 5711 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 5729
+/* 5715 */ MCD_OPC_CheckPredicate, 0, 126, 77, // Skip to: 25557
+/* 5719 */ MCD_OPC_CheckField, 21, 1, 1, 120, 77, // Skip to: 25557
+/* 5725 */ MCD_OPC_Decode, 235, 8, 33, // Opcode: SMULL2vvv_8h16b
+/* 5729 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 5747
+/* 5733 */ MCD_OPC_CheckPredicate, 0, 108, 77, // Skip to: 25557
+/* 5737 */ MCD_OPC_CheckField, 21, 1, 1, 102, 77, // Skip to: 25557
+/* 5743 */ MCD_OPC_Decode, 148, 4, 33, // Opcode: FMAXNMvvv_4S
+/* 5747 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 5765
+/* 5751 */ MCD_OPC_CheckPredicate, 0, 90, 77, // Skip to: 25557
+/* 5755 */ MCD_OPC_CheckField, 21, 1, 1, 84, 77, // Skip to: 25557
+/* 5761 */ MCD_OPC_Decode, 181, 4, 42, // Opcode: FMLAvvv_4S
+/* 5765 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 5783
+/* 5769 */ MCD_OPC_CheckPredicate, 0, 72, 77, // Skip to: 25557
+/* 5773 */ MCD_OPC_CheckField, 21, 1, 1, 66, 77, // Skip to: 25557
+/* 5779 */ MCD_OPC_Decode, 167, 3, 33, // Opcode: FADDvvv_4S
+/* 5783 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 5801
+/* 5787 */ MCD_OPC_CheckPredicate, 0, 54, 77, // Skip to: 25557
+/* 5791 */ MCD_OPC_CheckField, 21, 1, 1, 48, 77, // Skip to: 25557
+/* 5797 */ MCD_OPC_Decode, 202, 4, 33, // Opcode: FMULXvvv_4S
+/* 5801 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 5819
+/* 5805 */ MCD_OPC_CheckPredicate, 0, 36, 77, // Skip to: 25557
+/* 5809 */ MCD_OPC_CheckField, 21, 1, 1, 30, 77, // Skip to: 25557
+/* 5815 */ MCD_OPC_Decode, 178, 7, 33, // Opcode: PMULL2vvv_8h16b
+/* 5819 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 5837
+/* 5823 */ MCD_OPC_CheckPredicate, 0, 18, 77, // Skip to: 25557
+/* 5827 */ MCD_OPC_CheckField, 21, 1, 1, 12, 77, // Skip to: 25557
+/* 5833 */ MCD_OPC_Decode, 177, 3, 33, // Opcode: FCMEQvvv_4S
+/* 5837 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 5855
+/* 5841 */ MCD_OPC_CheckPredicate, 0, 0, 77, // Skip to: 25557
+/* 5845 */ MCD_OPC_CheckField, 21, 1, 1, 250, 76, // Skip to: 25557
+/* 5851 */ MCD_OPC_Decode, 158, 4, 33, // Opcode: FMAXvvv_4S
+/* 5855 */ MCD_OPC_FilterValue, 63, 242, 76, // Skip to: 25557
+/* 5859 */ MCD_OPC_CheckPredicate, 0, 238, 76, // Skip to: 25557
+/* 5863 */ MCD_OPC_CheckField, 21, 1, 1, 232, 76, // Skip to: 25557
+/* 5869 */ MCD_OPC_Decode, 218, 4, 33, // Opcode: FRECPSvvv_4S
+/* 5873 */ MCD_OPC_FilterValue, 3, 224, 76, // Skip to: 25557
+/* 5877 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 5880 */ MCD_OPC_FilterValue, 0, 237, 0, // Skip to: 6121
+/* 5884 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 5887 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5905
+/* 5891 */ MCD_OPC_CheckPredicate, 0, 206, 76, // Skip to: 25557
+/* 5895 */ MCD_OPC_CheckField, 21, 1, 1, 200, 76, // Skip to: 25557
+/* 5901 */ MCD_OPC_Decode, 160, 11, 33, // Opcode: UADDL2vvv_8h16b
+/* 5905 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 5923
+/* 5909 */ MCD_OPC_CheckPredicate, 0, 188, 76, // Skip to: 25557
+/* 5913 */ MCD_OPC_CheckField, 21, 1, 1, 182, 76, // Skip to: 25557
+/* 5919 */ MCD_OPC_Decode, 166, 11, 33, // Opcode: UADDW2vvv_8h16b
+/* 5923 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 5941
+/* 5927 */ MCD_OPC_CheckPredicate, 0, 170, 76, // Skip to: 25557
+/* 5931 */ MCD_OPC_CheckField, 21, 1, 1, 164, 76, // Skip to: 25557
+/* 5937 */ MCD_OPC_Decode, 240, 12, 33, // Opcode: USUBL2vvv_8h16b
+/* 5941 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 5959
+/* 5945 */ MCD_OPC_CheckPredicate, 0, 152, 76, // Skip to: 25557
+/* 5949 */ MCD_OPC_CheckField, 21, 1, 1, 146, 76, // Skip to: 25557
+/* 5955 */ MCD_OPC_Decode, 246, 12, 33, // Opcode: USUBW2vvv_8h16b
+/* 5959 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 5977
+/* 5963 */ MCD_OPC_CheckPredicate, 0, 134, 76, // Skip to: 25557
+/* 5967 */ MCD_OPC_CheckField, 21, 1, 1, 128, 76, // Skip to: 25557
+/* 5973 */ MCD_OPC_Decode, 199, 7, 42, // Opcode: RADDHN2vvv_16b8h
+/* 5977 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 5995
+/* 5981 */ MCD_OPC_CheckPredicate, 0, 116, 76, // Skip to: 25557
+/* 5985 */ MCD_OPC_CheckField, 21, 1, 1, 110, 76, // Skip to: 25557
+/* 5991 */ MCD_OPC_Decode, 136, 11, 42, // Opcode: UABAL2vvv_8h8b
+/* 5995 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 6013
+/* 5999 */ MCD_OPC_CheckPredicate, 0, 98, 76, // Skip to: 25557
+/* 6003 */ MCD_OPC_CheckField, 21, 1, 1, 92, 76, // Skip to: 25557
+/* 6009 */ MCD_OPC_Decode, 222, 7, 42, // Opcode: RSUBHN2vvv_16b8h
+/* 6013 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 6031
+/* 6017 */ MCD_OPC_CheckPredicate, 0, 80, 76, // Skip to: 25557
+/* 6021 */ MCD_OPC_CheckField, 21, 1, 1, 74, 76, // Skip to: 25557
+/* 6027 */ MCD_OPC_Decode, 148, 11, 33, // Opcode: UABDL2vvv_8h8b
+/* 6031 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 6049
+/* 6035 */ MCD_OPC_CheckPredicate, 0, 62, 76, // Skip to: 25557
+/* 6039 */ MCD_OPC_CheckField, 21, 1, 1, 56, 76, // Skip to: 25557
+/* 6045 */ MCD_OPC_Decode, 225, 11, 42, // Opcode: UMLAL2vvv_8h16b
+/* 6049 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 6067
+/* 6053 */ MCD_OPC_CheckPredicate, 0, 44, 76, // Skip to: 25557
+/* 6057 */ MCD_OPC_CheckField, 16, 6, 32, 38, 76, // Skip to: 25557
+/* 6063 */ MCD_OPC_Decode, 249, 1, 43, // Opcode: CMGEvvi_16B
+/* 6067 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 6085
+/* 6071 */ MCD_OPC_CheckPredicate, 0, 26, 76, // Skip to: 25557
+/* 6075 */ MCD_OPC_CheckField, 16, 6, 32, 20, 76, // Skip to: 25557
+/* 6081 */ MCD_OPC_Decode, 163, 2, 43, // Opcode: CMLEvvi_16B
+/* 6085 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 6103
+/* 6089 */ MCD_OPC_CheckPredicate, 0, 8, 76, // Skip to: 25557
+/* 6093 */ MCD_OPC_CheckField, 21, 1, 1, 2, 76, // Skip to: 25557
+/* 6099 */ MCD_OPC_Decode, 231, 11, 42, // Opcode: UMLSL2vvv_8h16b
+/* 6103 */ MCD_OPC_FilterValue, 24, 250, 75, // Skip to: 25557
+/* 6107 */ MCD_OPC_CheckPredicate, 0, 246, 75, // Skip to: 25557
+/* 6111 */ MCD_OPC_CheckField, 21, 1, 1, 240, 75, // Skip to: 25557
+/* 6117 */ MCD_OPC_Decode, 243, 11, 33, // Opcode: UMULL2vvv_8h16b
+/* 6121 */ MCD_OPC_FilterValue, 1, 232, 75, // Skip to: 25557
+/* 6125 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 6128 */ MCD_OPC_FilterValue, 0, 21, 1, // Skip to: 6409
+/* 6132 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6135 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 6210
+/* 6139 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ...
+/* 6142 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 6198
+/* 6146 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ...
+/* 6149 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 6186
+/* 6153 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ...
+/* 6156 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6174
+/* 6160 */ MCD_OPC_CheckPredicate, 0, 193, 75, // Skip to: 25557
+/* 6164 */ MCD_OPC_CheckField, 19, 1, 1, 187, 75, // Skip to: 25557
+/* 6170 */ MCD_OPC_Decode, 249, 4, 44, // Opcode: INSELd
+/* 6174 */ MCD_OPC_FilterValue, 1, 179, 75, // Skip to: 25557
+/* 6178 */ MCD_OPC_CheckPredicate, 0, 175, 75, // Skip to: 25557
+/* 6182 */ MCD_OPC_Decode, 251, 4, 45, // Opcode: INSELs
+/* 6186 */ MCD_OPC_FilterValue, 1, 167, 75, // Skip to: 25557
+/* 6190 */ MCD_OPC_CheckPredicate, 0, 163, 75, // Skip to: 25557
+/* 6194 */ MCD_OPC_Decode, 250, 4, 46, // Opcode: INSELh
+/* 6198 */ MCD_OPC_FilterValue, 1, 155, 75, // Skip to: 25557
+/* 6202 */ MCD_OPC_CheckPredicate, 0, 151, 75, // Skip to: 25557
+/* 6206 */ MCD_OPC_Decode, 248, 4, 47, // Opcode: INSELb
+/* 6210 */ MCD_OPC_FilterValue, 1, 143, 75, // Skip to: 25557
+/* 6214 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ...
+/* 6217 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6229
+/* 6221 */ MCD_OPC_CheckPredicate, 0, 132, 75, // Skip to: 25557
+/* 6225 */ MCD_OPC_Decode, 186, 11, 33, // Opcode: UHADDvvv_16B
+/* 6229 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6241
+/* 6233 */ MCD_OPC_CheckPredicate, 0, 120, 75, // Skip to: 25557
+/* 6237 */ MCD_OPC_Decode, 251, 11, 33, // Opcode: UQADDvvv_16B
+/* 6241 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6253
+/* 6245 */ MCD_OPC_CheckPredicate, 0, 108, 75, // Skip to: 25557
+/* 6249 */ MCD_OPC_Decode, 182, 12, 33, // Opcode: URHADDvvv_16B
+/* 6253 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6265
+/* 6257 */ MCD_OPC_CheckPredicate, 0, 96, 75, // Skip to: 25557
+/* 6261 */ MCD_OPC_Decode, 131, 3, 33, // Opcode: EORvvv_16B
+/* 6265 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6277
+/* 6269 */ MCD_OPC_CheckPredicate, 0, 84, 75, // Skip to: 25557
+/* 6273 */ MCD_OPC_Decode, 192, 11, 33, // Opcode: UHSUBvvv_16B
+/* 6277 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6289
+/* 6281 */ MCD_OPC_CheckPredicate, 0, 72, 75, // Skip to: 25557
+/* 6285 */ MCD_OPC_Decode, 175, 12, 33, // Opcode: UQSUBvvv_16B
+/* 6289 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6301
+/* 6293 */ MCD_OPC_CheckPredicate, 0, 60, 75, // Skip to: 25557
+/* 6297 */ MCD_OPC_Decode, 149, 2, 33, // Opcode: CMHIvvv_16B
+/* 6301 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6313
+/* 6305 */ MCD_OPC_CheckPredicate, 0, 48, 75, // Skip to: 25557
+/* 6309 */ MCD_OPC_Decode, 156, 2, 33, // Opcode: CMHSvvv_16B
+/* 6313 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6325
+/* 6317 */ MCD_OPC_CheckPredicate, 0, 36, 75, // Skip to: 25557
+/* 6321 */ MCD_OPC_Decode, 217, 12, 33, // Opcode: USHLvvv_16B
+/* 6325 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6337
+/* 6329 */ MCD_OPC_CheckPredicate, 0, 24, 75, // Skip to: 25557
+/* 6333 */ MCD_OPC_Decode, 158, 12, 33, // Opcode: UQSHLvvv_16B
+/* 6337 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6349
+/* 6341 */ MCD_OPC_CheckPredicate, 0, 12, 75, // Skip to: 25557
+/* 6345 */ MCD_OPC_Decode, 189, 12, 33, // Opcode: URSHLvvv_16B
+/* 6349 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6361
+/* 6353 */ MCD_OPC_CheckPredicate, 0, 0, 75, // Skip to: 25557
+/* 6357 */ MCD_OPC_Decode, 134, 12, 33, // Opcode: UQRSHLvvv_16B
+/* 6361 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6373
+/* 6365 */ MCD_OPC_CheckPredicate, 0, 244, 74, // Skip to: 25557
+/* 6369 */ MCD_OPC_Decode, 205, 11, 33, // Opcode: UMAXvvv_16B
+/* 6373 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6385
+/* 6377 */ MCD_OPC_CheckPredicate, 0, 232, 74, // Skip to: 25557
+/* 6381 */ MCD_OPC_Decode, 217, 11, 33, // Opcode: UMINvvv_16B
+/* 6385 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6397
+/* 6389 */ MCD_OPC_CheckPredicate, 0, 220, 74, // Skip to: 25557
+/* 6393 */ MCD_OPC_Decode, 152, 11, 33, // Opcode: UABDvvv_16B
+/* 6397 */ MCD_OPC_FilterValue, 15, 212, 74, // Skip to: 25557
+/* 6401 */ MCD_OPC_CheckPredicate, 0, 208, 74, // Skip to: 25557
+/* 6405 */ MCD_OPC_Decode, 140, 11, 42, // Opcode: UABAvvv_16B
+/* 6409 */ MCD_OPC_FilterValue, 1, 200, 74, // Skip to: 25557
+/* 6413 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ...
+/* 6416 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6434
+/* 6420 */ MCD_OPC_CheckPredicate, 0, 189, 74, // Skip to: 25557
+/* 6424 */ MCD_OPC_CheckField, 21, 1, 1, 183, 74, // Skip to: 25557
+/* 6430 */ MCD_OPC_Decode, 193, 10, 33, // Opcode: SUBvvv_16B
+/* 6434 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6452
+/* 6438 */ MCD_OPC_CheckPredicate, 0, 171, 74, // Skip to: 25557
+/* 6442 */ MCD_OPC_CheckField, 21, 1, 1, 165, 74, // Skip to: 25557
+/* 6448 */ MCD_OPC_Decode, 242, 1, 33, // Opcode: CMEQvvv_16B
+/* 6452 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 6470
+/* 6456 */ MCD_OPC_CheckPredicate, 0, 153, 74, // Skip to: 25557
+/* 6460 */ MCD_OPC_CheckField, 21, 1, 1, 147, 74, // Skip to: 25557
+/* 6466 */ MCD_OPC_Decode, 233, 6, 42, // Opcode: MLSvvv_16B
+/* 6470 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 6488
+/* 6474 */ MCD_OPC_CheckPredicate, 0, 135, 74, // Skip to: 25557
+/* 6478 */ MCD_OPC_CheckField, 21, 1, 1, 129, 74, // Skip to: 25557
+/* 6484 */ MCD_OPC_Decode, 180, 7, 33, // Opcode: PMULvvv_16B
+/* 6488 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 6506
+/* 6492 */ MCD_OPC_CheckPredicate, 0, 117, 74, // Skip to: 25557
+/* 6496 */ MCD_OPC_CheckField, 21, 1, 1, 111, 74, // Skip to: 25557
+/* 6502 */ MCD_OPC_Decode, 199, 11, 33, // Opcode: UMAXPvvv_16B
+/* 6506 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 6524
+/* 6510 */ MCD_OPC_CheckPredicate, 0, 99, 74, // Skip to: 25557
+/* 6514 */ MCD_OPC_CheckField, 21, 1, 1, 93, 74, // Skip to: 25557
+/* 6520 */ MCD_OPC_Decode, 211, 11, 33, // Opcode: UMINPvvv_16B
+/* 6524 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 6542
+/* 6528 */ MCD_OPC_CheckPredicate, 0, 81, 74, // Skip to: 25557
+/* 6532 */ MCD_OPC_CheckField, 21, 1, 1, 75, 74, // Skip to: 25557
+/* 6538 */ MCD_OPC_Decode, 143, 4, 33, // Opcode: FMAXNMPvvv_4S
+/* 6542 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 6560
+/* 6546 */ MCD_OPC_CheckPredicate, 0, 63, 74, // Skip to: 25557
+/* 6550 */ MCD_OPC_CheckField, 21, 1, 1, 57, 74, // Skip to: 25557
+/* 6556 */ MCD_OPC_Decode, 160, 3, 33, // Opcode: FADDP_4S
+/* 6560 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 6578
+/* 6564 */ MCD_OPC_CheckPredicate, 0, 45, 74, // Skip to: 25557
+/* 6568 */ MCD_OPC_CheckField, 21, 1, 1, 39, 74, // Skip to: 25557
+/* 6574 */ MCD_OPC_Decode, 207, 4, 33, // Opcode: FMULvvv_4S
+/* 6578 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 6596
+/* 6582 */ MCD_OPC_CheckPredicate, 0, 27, 74, // Skip to: 25557
+/* 6586 */ MCD_OPC_CheckField, 21, 1, 1, 21, 74, // Skip to: 25557
+/* 6592 */ MCD_OPC_Decode, 183, 3, 33, // Opcode: FCMGEvvv_4S
+/* 6596 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 6614
+/* 6600 */ MCD_OPC_CheckPredicate, 0, 9, 74, // Skip to: 25557
+/* 6604 */ MCD_OPC_CheckField, 21, 1, 1, 3, 74, // Skip to: 25557
+/* 6610 */ MCD_OPC_Decode, 154, 3, 33, // Opcode: FACGEvvv_4S
+/* 6614 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 6632
+/* 6618 */ MCD_OPC_CheckPredicate, 0, 247, 73, // Skip to: 25557
+/* 6622 */ MCD_OPC_CheckField, 21, 1, 1, 241, 73, // Skip to: 25557
+/* 6628 */ MCD_OPC_Decode, 153, 4, 33, // Opcode: FMAXPvvv_4S
+/* 6632 */ MCD_OPC_FilterValue, 15, 233, 73, // Skip to: 25557
+/* 6636 */ MCD_OPC_CheckPredicate, 0, 229, 73, // Skip to: 25557
+/* 6640 */ MCD_OPC_CheckField, 21, 1, 1, 223, 73, // Skip to: 25557
+/* 6646 */ MCD_OPC_Decode, 136, 4, 33, // Opcode: FDIVvvv_4S
+/* 6650 */ MCD_OPC_FilterValue, 9, 254, 12, // Skip to: 9980
+/* 6654 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 6657 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 6736
+/* 6661 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 6664 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6682
+/* 6668 */ MCD_OPC_CheckPredicate, 0, 197, 73, // Skip to: 25557
+/* 6672 */ MCD_OPC_CheckField, 21, 1, 1, 191, 73, // Skip to: 25557
+/* 6678 */ MCD_OPC_Decode, 128, 8, 23, // Opcode: SADDLvvv_4s4h
+/* 6682 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6700
+/* 6686 */ MCD_OPC_CheckPredicate, 0, 179, 73, // Skip to: 25557
+/* 6690 */ MCD_OPC_CheckField, 21, 1, 1, 173, 73, // Skip to: 25557
+/* 6696 */ MCD_OPC_Decode, 162, 11, 23, // Opcode: UADDLvvv_4s4h
+/* 6700 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 6718
+/* 6704 */ MCD_OPC_CheckPredicate, 0, 161, 73, // Skip to: 25557
+/* 6708 */ MCD_OPC_CheckField, 21, 1, 1, 155, 73, // Skip to: 25557
+/* 6714 */ MCD_OPC_Decode, 253, 7, 33, // Opcode: SADDL2vvv_4s8h
+/* 6718 */ MCD_OPC_FilterValue, 3, 147, 73, // Skip to: 25557
+/* 6722 */ MCD_OPC_CheckPredicate, 0, 143, 73, // Skip to: 25557
+/* 6726 */ MCD_OPC_CheckField, 21, 1, 1, 137, 73, // Skip to: 25557
+/* 6732 */ MCD_OPC_Decode, 159, 11, 33, // Opcode: UADDL2vvv_4s8h
+/* 6736 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 6815
+/* 6740 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 6743 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6761
+/* 6747 */ MCD_OPC_CheckPredicate, 0, 118, 73, // Skip to: 25557
+/* 6751 */ MCD_OPC_CheckField, 21, 1, 1, 112, 73, // Skip to: 25557
+/* 6757 */ MCD_OPC_Decode, 158, 8, 24, // Opcode: SHADDvvv_4H
+/* 6761 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6779
+/* 6765 */ MCD_OPC_CheckPredicate, 0, 100, 73, // Skip to: 25557
+/* 6769 */ MCD_OPC_CheckField, 21, 1, 1, 94, 73, // Skip to: 25557
+/* 6775 */ MCD_OPC_Decode, 188, 11, 24, // Opcode: UHADDvvv_4H
+/* 6779 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 6797
+/* 6783 */ MCD_OPC_CheckPredicate, 0, 82, 73, // Skip to: 25557
+/* 6787 */ MCD_OPC_CheckField, 21, 1, 1, 76, 73, // Skip to: 25557
+/* 6793 */ MCD_OPC_Decode, 161, 8, 33, // Opcode: SHADDvvv_8H
+/* 6797 */ MCD_OPC_FilterValue, 3, 68, 73, // Skip to: 25557
+/* 6801 */ MCD_OPC_CheckPredicate, 0, 64, 73, // Skip to: 25557
+/* 6805 */ MCD_OPC_CheckField, 21, 1, 1, 58, 73, // Skip to: 25557
+/* 6811 */ MCD_OPC_Decode, 191, 11, 33, // Opcode: UHADDvvv_8H
+/* 6815 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 6894
+/* 6819 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 6822 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6840
+/* 6826 */ MCD_OPC_CheckPredicate, 0, 39, 73, // Skip to: 25557
+/* 6830 */ MCD_OPC_CheckField, 21, 1, 1, 33, 73, // Skip to: 25557
+/* 6836 */ MCD_OPC_Decode, 246, 8, 24, // Opcode: SQADDvvv_4H
+/* 6840 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6858
+/* 6844 */ MCD_OPC_CheckPredicate, 0, 21, 73, // Skip to: 25557
+/* 6848 */ MCD_OPC_CheckField, 21, 1, 1, 15, 73, // Skip to: 25557
+/* 6854 */ MCD_OPC_Decode, 254, 11, 24, // Opcode: UQADDvvv_4H
+/* 6858 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 6876
+/* 6862 */ MCD_OPC_CheckPredicate, 0, 3, 73, // Skip to: 25557
+/* 6866 */ MCD_OPC_CheckField, 21, 1, 1, 253, 72, // Skip to: 25557
+/* 6872 */ MCD_OPC_Decode, 249, 8, 33, // Opcode: SQADDvvv_8H
+/* 6876 */ MCD_OPC_FilterValue, 3, 245, 72, // Skip to: 25557
+/* 6880 */ MCD_OPC_CheckPredicate, 0, 241, 72, // Skip to: 25557
+/* 6884 */ MCD_OPC_CheckField, 21, 1, 1, 235, 72, // Skip to: 25557
+/* 6890 */ MCD_OPC_Decode, 129, 12, 33, // Opcode: UQADDvvv_8H
+/* 6894 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 6973
+/* 6898 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 6901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6919
+/* 6905 */ MCD_OPC_CheckPredicate, 0, 216, 72, // Skip to: 25557
+/* 6909 */ MCD_OPC_CheckField, 21, 1, 1, 210, 72, // Skip to: 25557
+/* 6915 */ MCD_OPC_Decode, 134, 8, 25, // Opcode: SADDWvvv_4s4h
+/* 6919 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6937
+/* 6923 */ MCD_OPC_CheckPredicate, 0, 198, 72, // Skip to: 25557
+/* 6927 */ MCD_OPC_CheckField, 21, 1, 1, 192, 72, // Skip to: 25557
+/* 6933 */ MCD_OPC_Decode, 168, 11, 25, // Opcode: UADDWvvv_4s4h
+/* 6937 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 6955
+/* 6941 */ MCD_OPC_CheckPredicate, 0, 180, 72, // Skip to: 25557
+/* 6945 */ MCD_OPC_CheckField, 21, 1, 1, 174, 72, // Skip to: 25557
+/* 6951 */ MCD_OPC_Decode, 131, 8, 33, // Opcode: SADDW2vvv_4s8h
+/* 6955 */ MCD_OPC_FilterValue, 3, 166, 72, // Skip to: 25557
+/* 6959 */ MCD_OPC_CheckPredicate, 0, 162, 72, // Skip to: 25557
+/* 6963 */ MCD_OPC_CheckField, 21, 1, 1, 156, 72, // Skip to: 25557
+/* 6969 */ MCD_OPC_Decode, 165, 11, 33, // Opcode: UADDW2vvv_4s8h
+/* 6973 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 7052
+/* 6977 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 6980 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6998
+/* 6984 */ MCD_OPC_CheckPredicate, 0, 137, 72, // Skip to: 25557
+/* 6988 */ MCD_OPC_CheckField, 21, 1, 1, 131, 72, // Skip to: 25557
+/* 6994 */ MCD_OPC_Decode, 203, 9, 24, // Opcode: SRHADDvvv_4H
+/* 6998 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7016
+/* 7002 */ MCD_OPC_CheckPredicate, 0, 119, 72, // Skip to: 25557
+/* 7006 */ MCD_OPC_CheckField, 21, 1, 1, 113, 72, // Skip to: 25557
+/* 7012 */ MCD_OPC_Decode, 184, 12, 24, // Opcode: URHADDvvv_4H
+/* 7016 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7034
+/* 7020 */ MCD_OPC_CheckPredicate, 0, 101, 72, // Skip to: 25557
+/* 7024 */ MCD_OPC_CheckField, 21, 1, 1, 95, 72, // Skip to: 25557
+/* 7030 */ MCD_OPC_Decode, 206, 9, 33, // Opcode: SRHADDvvv_8H
+/* 7034 */ MCD_OPC_FilterValue, 3, 87, 72, // Skip to: 25557
+/* 7038 */ MCD_OPC_CheckPredicate, 0, 83, 72, // Skip to: 25557
+/* 7042 */ MCD_OPC_CheckField, 21, 1, 1, 77, 72, // Skip to: 25557
+/* 7048 */ MCD_OPC_Decode, 187, 12, 33, // Opcode: URHADDvvv_8H
+/* 7052 */ MCD_OPC_FilterValue, 7, 75, 0, // Skip to: 7131
+/* 7056 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7059 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7077
+/* 7063 */ MCD_OPC_CheckPredicate, 0, 58, 72, // Skip to: 25557
+/* 7067 */ MCD_OPC_CheckField, 21, 1, 1, 52, 72, // Skip to: 25557
+/* 7073 */ MCD_OPC_Decode, 197, 1, 24, // Opcode: BICvvv_8B
+/* 7077 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7095
+/* 7081 */ MCD_OPC_CheckPredicate, 0, 40, 72, // Skip to: 25557
+/* 7085 */ MCD_OPC_CheckField, 21, 1, 1, 34, 72, // Skip to: 25557
+/* 7091 */ MCD_OPC_Decode, 215, 1, 31, // Opcode: BSLvvv_8B
+/* 7095 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7113
+/* 7099 */ MCD_OPC_CheckPredicate, 0, 22, 72, // Skip to: 25557
+/* 7103 */ MCD_OPC_CheckField, 21, 1, 1, 16, 72, // Skip to: 25557
+/* 7109 */ MCD_OPC_Decode, 196, 1, 33, // Opcode: BICvvv_16B
+/* 7113 */ MCD_OPC_FilterValue, 3, 8, 72, // Skip to: 25557
+/* 7117 */ MCD_OPC_CheckPredicate, 0, 4, 72, // Skip to: 25557
+/* 7121 */ MCD_OPC_CheckField, 21, 1, 1, 254, 71, // Skip to: 25557
+/* 7127 */ MCD_OPC_Decode, 214, 1, 42, // Opcode: BSLvvv_16B
+/* 7131 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 7210
+/* 7135 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7138 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7156
+/* 7142 */ MCD_OPC_CheckPredicate, 0, 235, 71, // Skip to: 25557
+/* 7146 */ MCD_OPC_CheckField, 21, 1, 1, 229, 71, // Skip to: 25557
+/* 7152 */ MCD_OPC_Decode, 140, 10, 23, // Opcode: SSUBLvvv_4s4h
+/* 7156 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7174
+/* 7160 */ MCD_OPC_CheckPredicate, 0, 217, 71, // Skip to: 25557
+/* 7164 */ MCD_OPC_CheckField, 21, 1, 1, 211, 71, // Skip to: 25557
+/* 7170 */ MCD_OPC_Decode, 242, 12, 23, // Opcode: USUBLvvv_4s4h
+/* 7174 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7192
+/* 7178 */ MCD_OPC_CheckPredicate, 0, 199, 71, // Skip to: 25557
+/* 7182 */ MCD_OPC_CheckField, 21, 1, 1, 193, 71, // Skip to: 25557
+/* 7188 */ MCD_OPC_Decode, 137, 10, 33, // Opcode: SSUBL2vvv_4s8h
+/* 7192 */ MCD_OPC_FilterValue, 3, 185, 71, // Skip to: 25557
+/* 7196 */ MCD_OPC_CheckPredicate, 0, 181, 71, // Skip to: 25557
+/* 7200 */ MCD_OPC_CheckField, 21, 1, 1, 175, 71, // Skip to: 25557
+/* 7206 */ MCD_OPC_Decode, 239, 12, 33, // Opcode: USUBL2vvv_4s8h
+/* 7210 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 7289
+/* 7214 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7217 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7235
+/* 7221 */ MCD_OPC_CheckPredicate, 0, 156, 71, // Skip to: 25557
+/* 7225 */ MCD_OPC_CheckField, 21, 1, 1, 150, 71, // Skip to: 25557
+/* 7231 */ MCD_OPC_Decode, 177, 8, 24, // Opcode: SHSUBvvv_4H
+/* 7235 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7253
+/* 7239 */ MCD_OPC_CheckPredicate, 0, 138, 71, // Skip to: 25557
+/* 7243 */ MCD_OPC_CheckField, 21, 1, 1, 132, 71, // Skip to: 25557
+/* 7249 */ MCD_OPC_Decode, 194, 11, 24, // Opcode: UHSUBvvv_4H
+/* 7253 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7271
+/* 7257 */ MCD_OPC_CheckPredicate, 0, 120, 71, // Skip to: 25557
+/* 7261 */ MCD_OPC_CheckField, 21, 1, 1, 114, 71, // Skip to: 25557
+/* 7267 */ MCD_OPC_Decode, 180, 8, 33, // Opcode: SHSUBvvv_8H
+/* 7271 */ MCD_OPC_FilterValue, 3, 106, 71, // Skip to: 25557
+/* 7275 */ MCD_OPC_CheckPredicate, 0, 102, 71, // Skip to: 25557
+/* 7279 */ MCD_OPC_CheckField, 21, 1, 1, 96, 71, // Skip to: 25557
+/* 7285 */ MCD_OPC_Decode, 197, 11, 33, // Opcode: UHSUBvvv_8H
+/* 7289 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 7368
+/* 7293 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7296 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7314
+/* 7300 */ MCD_OPC_CheckPredicate, 0, 77, 71, // Skip to: 25557
+/* 7304 */ MCD_OPC_CheckField, 21, 1, 1, 71, 71, // Skip to: 25557
+/* 7310 */ MCD_OPC_Decode, 197, 9, 24, // Opcode: SQSUBvvv_4H
+/* 7314 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7332
+/* 7318 */ MCD_OPC_CheckPredicate, 0, 59, 71, // Skip to: 25557
+/* 7322 */ MCD_OPC_CheckField, 21, 1, 1, 53, 71, // Skip to: 25557
+/* 7328 */ MCD_OPC_Decode, 178, 12, 24, // Opcode: UQSUBvvv_4H
+/* 7332 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7350
+/* 7336 */ MCD_OPC_CheckPredicate, 0, 41, 71, // Skip to: 25557
+/* 7340 */ MCD_OPC_CheckField, 21, 1, 1, 35, 71, // Skip to: 25557
+/* 7346 */ MCD_OPC_Decode, 200, 9, 33, // Opcode: SQSUBvvv_8H
+/* 7350 */ MCD_OPC_FilterValue, 3, 27, 71, // Skip to: 25557
+/* 7354 */ MCD_OPC_CheckPredicate, 0, 23, 71, // Skip to: 25557
+/* 7358 */ MCD_OPC_CheckField, 21, 1, 1, 17, 71, // Skip to: 25557
+/* 7364 */ MCD_OPC_Decode, 181, 12, 33, // Opcode: UQSUBvvv_8H
+/* 7368 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 7447
+/* 7372 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7375 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7393
+/* 7379 */ MCD_OPC_CheckPredicate, 0, 254, 70, // Skip to: 25557
+/* 7383 */ MCD_OPC_CheckField, 21, 1, 1, 248, 70, // Skip to: 25557
+/* 7389 */ MCD_OPC_Decode, 146, 10, 25, // Opcode: SSUBWvvv_4s4h
+/* 7393 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7411
+/* 7397 */ MCD_OPC_CheckPredicate, 0, 236, 70, // Skip to: 25557
+/* 7401 */ MCD_OPC_CheckField, 21, 1, 1, 230, 70, // Skip to: 25557
+/* 7407 */ MCD_OPC_Decode, 248, 12, 25, // Opcode: USUBWvvv_4s4h
+/* 7411 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7429
+/* 7415 */ MCD_OPC_CheckPredicate, 0, 218, 70, // Skip to: 25557
+/* 7419 */ MCD_OPC_CheckField, 21, 1, 1, 212, 70, // Skip to: 25557
+/* 7425 */ MCD_OPC_Decode, 143, 10, 33, // Opcode: SSUBW2vvv_4s8h
+/* 7429 */ MCD_OPC_FilterValue, 3, 204, 70, // Skip to: 25557
+/* 7433 */ MCD_OPC_CheckPredicate, 0, 200, 70, // Skip to: 25557
+/* 7437 */ MCD_OPC_CheckField, 21, 1, 1, 194, 70, // Skip to: 25557
+/* 7443 */ MCD_OPC_Decode, 245, 12, 33, // Opcode: USUBW2vvv_4s8h
+/* 7447 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 7526
+/* 7451 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7454 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7472
+/* 7458 */ MCD_OPC_CheckPredicate, 0, 175, 70, // Skip to: 25557
+/* 7462 */ MCD_OPC_CheckField, 21, 1, 1, 169, 70, // Skip to: 25557
+/* 7468 */ MCD_OPC_Decode, 145, 2, 24, // Opcode: CMGTvvv_4H
+/* 7472 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7490
+/* 7476 */ MCD_OPC_CheckPredicate, 0, 157, 70, // Skip to: 25557
+/* 7480 */ MCD_OPC_CheckField, 21, 1, 1, 151, 70, // Skip to: 25557
+/* 7486 */ MCD_OPC_Decode, 152, 2, 24, // Opcode: CMHIvvv_4H
+/* 7490 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7508
+/* 7494 */ MCD_OPC_CheckPredicate, 0, 139, 70, // Skip to: 25557
+/* 7498 */ MCD_OPC_CheckField, 21, 1, 1, 133, 70, // Skip to: 25557
+/* 7504 */ MCD_OPC_Decode, 148, 2, 33, // Opcode: CMGTvvv_8H
+/* 7508 */ MCD_OPC_FilterValue, 3, 125, 70, // Skip to: 25557
+/* 7512 */ MCD_OPC_CheckPredicate, 0, 121, 70, // Skip to: 25557
+/* 7516 */ MCD_OPC_CheckField, 21, 1, 1, 115, 70, // Skip to: 25557
+/* 7522 */ MCD_OPC_Decode, 155, 2, 33, // Opcode: CMHIvvv_8H
+/* 7526 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 7605
+/* 7530 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7533 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7551
+/* 7537 */ MCD_OPC_CheckPredicate, 0, 96, 70, // Skip to: 25557
+/* 7541 */ MCD_OPC_CheckField, 21, 1, 1, 90, 70, // Skip to: 25557
+/* 7547 */ MCD_OPC_Decode, 131, 2, 24, // Opcode: CMGEvvv_4H
+/* 7551 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7569
+/* 7555 */ MCD_OPC_CheckPredicate, 0, 78, 70, // Skip to: 25557
+/* 7559 */ MCD_OPC_CheckField, 21, 1, 1, 72, 70, // Skip to: 25557
+/* 7565 */ MCD_OPC_Decode, 159, 2, 24, // Opcode: CMHSvvv_4H
+/* 7569 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7587
+/* 7573 */ MCD_OPC_CheckPredicate, 0, 60, 70, // Skip to: 25557
+/* 7577 */ MCD_OPC_CheckField, 21, 1, 1, 54, 70, // Skip to: 25557
+/* 7583 */ MCD_OPC_Decode, 134, 2, 33, // Opcode: CMGEvvv_8H
+/* 7587 */ MCD_OPC_FilterValue, 3, 46, 70, // Skip to: 25557
+/* 7591 */ MCD_OPC_CheckPredicate, 0, 42, 70, // Skip to: 25557
+/* 7595 */ MCD_OPC_CheckField, 21, 1, 1, 36, 70, // Skip to: 25557
+/* 7601 */ MCD_OPC_Decode, 162, 2, 33, // Opcode: CMHSvvv_8H
+/* 7605 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 7682
+/* 7609 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7612 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 7629
+/* 7616 */ MCD_OPC_CheckPredicate, 0, 17, 70, // Skip to: 25557
+/* 7620 */ MCD_OPC_CheckField, 21, 1, 1, 11, 70, // Skip to: 25557
+/* 7626 */ MCD_OPC_Decode, 25, 29, // Opcode: ADDHNvvv_4h4s
+/* 7629 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7647
+/* 7633 */ MCD_OPC_CheckPredicate, 0, 0, 70, // Skip to: 25557
+/* 7637 */ MCD_OPC_CheckField, 21, 1, 1, 250, 69, // Skip to: 25557
+/* 7643 */ MCD_OPC_Decode, 203, 7, 29, // Opcode: RADDHNvvv_4h4s
+/* 7647 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 7664
+/* 7651 */ MCD_OPC_CheckPredicate, 0, 238, 69, // Skip to: 25557
+/* 7655 */ MCD_OPC_CheckField, 21, 1, 1, 232, 69, // Skip to: 25557
+/* 7661 */ MCD_OPC_Decode, 23, 42, // Opcode: ADDHN2vvv_8h4s
+/* 7664 */ MCD_OPC_FilterValue, 3, 225, 69, // Skip to: 25557
+/* 7668 */ MCD_OPC_CheckPredicate, 0, 221, 69, // Skip to: 25557
+/* 7672 */ MCD_OPC_CheckField, 21, 1, 1, 215, 69, // Skip to: 25557
+/* 7678 */ MCD_OPC_Decode, 201, 7, 42, // Opcode: RADDHN2vvv_8h4s
+/* 7682 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 7761
+/* 7686 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7689 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7707
+/* 7693 */ MCD_OPC_CheckPredicate, 0, 196, 69, // Skip to: 25557
+/* 7697 */ MCD_OPC_CheckField, 21, 1, 1, 190, 69, // Skip to: 25557
+/* 7703 */ MCD_OPC_Decode, 246, 9, 24, // Opcode: SSHLvvv_4H
+/* 7707 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7725
+/* 7711 */ MCD_OPC_CheckPredicate, 0, 178, 69, // Skip to: 25557
+/* 7715 */ MCD_OPC_CheckField, 21, 1, 1, 172, 69, // Skip to: 25557
+/* 7721 */ MCD_OPC_Decode, 220, 12, 24, // Opcode: USHLvvv_4H
+/* 7725 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7743
+/* 7729 */ MCD_OPC_CheckPredicate, 0, 160, 69, // Skip to: 25557
+/* 7733 */ MCD_OPC_CheckField, 21, 1, 1, 154, 69, // Skip to: 25557
+/* 7739 */ MCD_OPC_Decode, 249, 9, 33, // Opcode: SSHLvvv_8H
+/* 7743 */ MCD_OPC_FilterValue, 3, 146, 69, // Skip to: 25557
+/* 7747 */ MCD_OPC_CheckPredicate, 0, 142, 69, // Skip to: 25557
+/* 7751 */ MCD_OPC_CheckField, 21, 1, 1, 136, 69, // Skip to: 25557
+/* 7757 */ MCD_OPC_Decode, 223, 12, 33, // Opcode: USHLvvv_8H
+/* 7761 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 7840
+/* 7765 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7768 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7786
+/* 7772 */ MCD_OPC_CheckPredicate, 0, 117, 69, // Skip to: 25557
+/* 7776 */ MCD_OPC_CheckField, 21, 1, 1, 111, 69, // Skip to: 25557
+/* 7782 */ MCD_OPC_Decode, 180, 9, 24, // Opcode: SQSHLvvv_4H
+/* 7786 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7804
+/* 7790 */ MCD_OPC_CheckPredicate, 0, 99, 69, // Skip to: 25557
+/* 7794 */ MCD_OPC_CheckField, 21, 1, 1, 93, 69, // Skip to: 25557
+/* 7800 */ MCD_OPC_Decode, 161, 12, 24, // Opcode: UQSHLvvv_4H
+/* 7804 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7822
+/* 7808 */ MCD_OPC_CheckPredicate, 0, 81, 69, // Skip to: 25557
+/* 7812 */ MCD_OPC_CheckField, 21, 1, 1, 75, 69, // Skip to: 25557
+/* 7818 */ MCD_OPC_Decode, 183, 9, 33, // Opcode: SQSHLvvv_8H
+/* 7822 */ MCD_OPC_FilterValue, 3, 67, 69, // Skip to: 25557
+/* 7826 */ MCD_OPC_CheckPredicate, 0, 63, 69, // Skip to: 25557
+/* 7830 */ MCD_OPC_CheckField, 21, 1, 1, 57, 69, // Skip to: 25557
+/* 7836 */ MCD_OPC_Decode, 164, 12, 33, // Opcode: UQSHLvvv_8H
+/* 7840 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 7919
+/* 7844 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7865
+/* 7851 */ MCD_OPC_CheckPredicate, 0, 38, 69, // Skip to: 25557
+/* 7855 */ MCD_OPC_CheckField, 21, 1, 1, 32, 69, // Skip to: 25557
+/* 7861 */ MCD_OPC_Decode, 232, 7, 30, // Opcode: SABALvvv_4s4h
+/* 7865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7883
+/* 7869 */ MCD_OPC_CheckPredicate, 0, 20, 69, // Skip to: 25557
+/* 7873 */ MCD_OPC_CheckField, 21, 1, 1, 14, 69, // Skip to: 25557
+/* 7879 */ MCD_OPC_Decode, 138, 11, 30, // Opcode: UABALvvv_4s4h
+/* 7883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7901
+/* 7887 */ MCD_OPC_CheckPredicate, 0, 2, 69, // Skip to: 25557
+/* 7891 */ MCD_OPC_CheckField, 21, 1, 1, 252, 68, // Skip to: 25557
+/* 7897 */ MCD_OPC_Decode, 229, 7, 42, // Opcode: SABAL2vvv_4s4h
+/* 7901 */ MCD_OPC_FilterValue, 3, 244, 68, // Skip to: 25557
+/* 7905 */ MCD_OPC_CheckPredicate, 0, 240, 68, // Skip to: 25557
+/* 7909 */ MCD_OPC_CheckField, 21, 1, 1, 234, 68, // Skip to: 25557
+/* 7915 */ MCD_OPC_Decode, 135, 11, 42, // Opcode: UABAL2vvv_4s4h
+/* 7919 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 7998
+/* 7923 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 7926 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7944
+/* 7930 */ MCD_OPC_CheckPredicate, 0, 215, 68, // Skip to: 25557
+/* 7934 */ MCD_OPC_CheckField, 21, 1, 1, 209, 68, // Skip to: 25557
+/* 7940 */ MCD_OPC_Decode, 218, 9, 24, // Opcode: SRSHLvvv_4H
+/* 7944 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 7962
+/* 7948 */ MCD_OPC_CheckPredicate, 0, 197, 68, // Skip to: 25557
+/* 7952 */ MCD_OPC_CheckField, 21, 1, 1, 191, 68, // Skip to: 25557
+/* 7958 */ MCD_OPC_Decode, 192, 12, 24, // Opcode: URSHLvvv_4H
+/* 7962 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7980
+/* 7966 */ MCD_OPC_CheckPredicate, 0, 179, 68, // Skip to: 25557
+/* 7970 */ MCD_OPC_CheckField, 21, 1, 1, 173, 68, // Skip to: 25557
+/* 7976 */ MCD_OPC_Decode, 221, 9, 33, // Opcode: SRSHLvvv_8H
+/* 7980 */ MCD_OPC_FilterValue, 3, 165, 68, // Skip to: 25557
+/* 7984 */ MCD_OPC_CheckPredicate, 0, 161, 68, // Skip to: 25557
+/* 7988 */ MCD_OPC_CheckField, 21, 1, 1, 155, 68, // Skip to: 25557
+/* 7994 */ MCD_OPC_Decode, 195, 12, 33, // Opcode: URSHLvvv_8H
+/* 7998 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 8077
+/* 8002 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8005 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8023
+/* 8009 */ MCD_OPC_CheckPredicate, 0, 136, 68, // Skip to: 25557
+/* 8013 */ MCD_OPC_CheckField, 21, 1, 1, 130, 68, // Skip to: 25557
+/* 8019 */ MCD_OPC_Decode, 149, 9, 24, // Opcode: SQRSHLvvv_4H
+/* 8023 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8041
+/* 8027 */ MCD_OPC_CheckPredicate, 0, 118, 68, // Skip to: 25557
+/* 8031 */ MCD_OPC_CheckField, 21, 1, 1, 112, 68, // Skip to: 25557
+/* 8037 */ MCD_OPC_Decode, 137, 12, 24, // Opcode: UQRSHLvvv_4H
+/* 8041 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8059
+/* 8045 */ MCD_OPC_CheckPredicate, 0, 100, 68, // Skip to: 25557
+/* 8049 */ MCD_OPC_CheckField, 21, 1, 1, 94, 68, // Skip to: 25557
+/* 8055 */ MCD_OPC_Decode, 152, 9, 33, // Opcode: SQRSHLvvv_8H
+/* 8059 */ MCD_OPC_FilterValue, 3, 86, 68, // Skip to: 25557
+/* 8063 */ MCD_OPC_CheckPredicate, 0, 82, 68, // Skip to: 25557
+/* 8067 */ MCD_OPC_CheckField, 21, 1, 1, 76, 68, // Skip to: 25557
+/* 8073 */ MCD_OPC_Decode, 140, 12, 33, // Opcode: UQRSHLvvv_8H
+/* 8077 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 8156
+/* 8081 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8084 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8102
+/* 8088 */ MCD_OPC_CheckPredicate, 0, 57, 68, // Skip to: 25557
+/* 8092 */ MCD_OPC_CheckField, 21, 1, 1, 51, 68, // Skip to: 25557
+/* 8098 */ MCD_OPC_Decode, 168, 10, 29, // Opcode: SUBHNvvv_4h4s
+/* 8102 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8120
+/* 8106 */ MCD_OPC_CheckPredicate, 0, 39, 68, // Skip to: 25557
+/* 8110 */ MCD_OPC_CheckField, 21, 1, 1, 33, 68, // Skip to: 25557
+/* 8116 */ MCD_OPC_Decode, 226, 7, 29, // Opcode: RSUBHNvvv_4h4s
+/* 8120 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8138
+/* 8124 */ MCD_OPC_CheckPredicate, 0, 21, 68, // Skip to: 25557
+/* 8128 */ MCD_OPC_CheckField, 21, 1, 1, 15, 68, // Skip to: 25557
+/* 8134 */ MCD_OPC_Decode, 166, 10, 42, // Opcode: SUBHN2vvv_8h4s
+/* 8138 */ MCD_OPC_FilterValue, 3, 7, 68, // Skip to: 25557
+/* 8142 */ MCD_OPC_CheckPredicate, 0, 3, 68, // Skip to: 25557
+/* 8146 */ MCD_OPC_CheckField, 21, 1, 1, 253, 67, // Skip to: 25557
+/* 8152 */ MCD_OPC_Decode, 224, 7, 42, // Opcode: RSUBHN2vvv_8h4s
+/* 8156 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 8235
+/* 8160 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8163 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8181
+/* 8167 */ MCD_OPC_CheckPredicate, 0, 234, 67, // Skip to: 25557
+/* 8171 */ MCD_OPC_CheckField, 21, 1, 1, 228, 67, // Skip to: 25557
+/* 8177 */ MCD_OPC_Decode, 197, 8, 24, // Opcode: SMAXvvv_4H
+/* 8181 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8199
+/* 8185 */ MCD_OPC_CheckPredicate, 0, 216, 67, // Skip to: 25557
+/* 8189 */ MCD_OPC_CheckField, 21, 1, 1, 210, 67, // Skip to: 25557
+/* 8195 */ MCD_OPC_Decode, 207, 11, 24, // Opcode: UMAXvvv_4H
+/* 8199 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8217
+/* 8203 */ MCD_OPC_CheckPredicate, 0, 198, 67, // Skip to: 25557
+/* 8207 */ MCD_OPC_CheckField, 21, 1, 1, 192, 67, // Skip to: 25557
+/* 8213 */ MCD_OPC_Decode, 200, 8, 33, // Opcode: SMAXvvv_8H
+/* 8217 */ MCD_OPC_FilterValue, 3, 184, 67, // Skip to: 25557
+/* 8221 */ MCD_OPC_CheckPredicate, 0, 180, 67, // Skip to: 25557
+/* 8225 */ MCD_OPC_CheckField, 21, 1, 1, 174, 67, // Skip to: 25557
+/* 8231 */ MCD_OPC_Decode, 210, 11, 33, // Opcode: UMAXvvv_8H
+/* 8235 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 8314
+/* 8239 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8242 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8260
+/* 8246 */ MCD_OPC_CheckPredicate, 0, 155, 67, // Skip to: 25557
+/* 8250 */ MCD_OPC_CheckField, 21, 1, 1, 149, 67, // Skip to: 25557
+/* 8256 */ MCD_OPC_Decode, 210, 8, 24, // Opcode: SMINvvv_4H
+/* 8260 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8278
+/* 8264 */ MCD_OPC_CheckPredicate, 0, 137, 67, // Skip to: 25557
+/* 8268 */ MCD_OPC_CheckField, 21, 1, 1, 131, 67, // Skip to: 25557
+/* 8274 */ MCD_OPC_Decode, 219, 11, 24, // Opcode: UMINvvv_4H
+/* 8278 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8296
+/* 8282 */ MCD_OPC_CheckPredicate, 0, 119, 67, // Skip to: 25557
+/* 8286 */ MCD_OPC_CheckField, 21, 1, 1, 113, 67, // Skip to: 25557
+/* 8292 */ MCD_OPC_Decode, 213, 8, 33, // Opcode: SMINvvv_8H
+/* 8296 */ MCD_OPC_FilterValue, 3, 105, 67, // Skip to: 25557
+/* 8300 */ MCD_OPC_CheckPredicate, 0, 101, 67, // Skip to: 25557
+/* 8304 */ MCD_OPC_CheckField, 21, 1, 1, 95, 67, // Skip to: 25557
+/* 8310 */ MCD_OPC_Decode, 222, 11, 33, // Opcode: UMINvvv_8H
+/* 8314 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 8393
+/* 8318 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8321 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8339
+/* 8325 */ MCD_OPC_CheckPredicate, 0, 76, 67, // Skip to: 25557
+/* 8329 */ MCD_OPC_CheckField, 21, 1, 1, 70, 67, // Skip to: 25557
+/* 8335 */ MCD_OPC_Decode, 244, 7, 23, // Opcode: SABDLvvv_4s4h
+/* 8339 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8357
+/* 8343 */ MCD_OPC_CheckPredicate, 0, 58, 67, // Skip to: 25557
+/* 8347 */ MCD_OPC_CheckField, 21, 1, 1, 52, 67, // Skip to: 25557
+/* 8353 */ MCD_OPC_Decode, 150, 11, 23, // Opcode: UABDLvvv_4s4h
+/* 8357 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8375
+/* 8361 */ MCD_OPC_CheckPredicate, 0, 40, 67, // Skip to: 25557
+/* 8365 */ MCD_OPC_CheckField, 21, 1, 1, 34, 67, // Skip to: 25557
+/* 8371 */ MCD_OPC_Decode, 241, 7, 33, // Opcode: SABDL2vvv_4s4h
+/* 8375 */ MCD_OPC_FilterValue, 3, 26, 67, // Skip to: 25557
+/* 8379 */ MCD_OPC_CheckPredicate, 0, 22, 67, // Skip to: 25557
+/* 8383 */ MCD_OPC_CheckField, 21, 1, 1, 16, 67, // Skip to: 25557
+/* 8389 */ MCD_OPC_Decode, 147, 11, 33, // Opcode: UABDL2vvv_4s4h
+/* 8393 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 8472
+/* 8397 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8400 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8418
+/* 8404 */ MCD_OPC_CheckPredicate, 0, 253, 66, // Skip to: 25557
+/* 8408 */ MCD_OPC_CheckField, 21, 1, 1, 247, 66, // Skip to: 25557
+/* 8414 */ MCD_OPC_Decode, 248, 7, 24, // Opcode: SABDvvv_4H
+/* 8418 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8436
+/* 8422 */ MCD_OPC_CheckPredicate, 0, 235, 66, // Skip to: 25557
+/* 8426 */ MCD_OPC_CheckField, 21, 1, 1, 229, 66, // Skip to: 25557
+/* 8432 */ MCD_OPC_Decode, 154, 11, 24, // Opcode: UABDvvv_4H
+/* 8436 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8454
+/* 8440 */ MCD_OPC_CheckPredicate, 0, 217, 66, // Skip to: 25557
+/* 8444 */ MCD_OPC_CheckField, 21, 1, 1, 211, 66, // Skip to: 25557
+/* 8450 */ MCD_OPC_Decode, 251, 7, 33, // Opcode: SABDvvv_8H
+/* 8454 */ MCD_OPC_FilterValue, 3, 203, 66, // Skip to: 25557
+/* 8458 */ MCD_OPC_CheckPredicate, 0, 199, 66, // Skip to: 25557
+/* 8462 */ MCD_OPC_CheckField, 21, 1, 1, 193, 66, // Skip to: 25557
+/* 8468 */ MCD_OPC_Decode, 157, 11, 33, // Opcode: UABDvvv_8H
+/* 8472 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 8551
+/* 8476 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8479 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8497
+/* 8483 */ MCD_OPC_CheckPredicate, 0, 174, 66, // Skip to: 25557
+/* 8487 */ MCD_OPC_CheckField, 21, 1, 1, 168, 66, // Skip to: 25557
+/* 8493 */ MCD_OPC_Decode, 236, 7, 31, // Opcode: SABAvvv_4H
+/* 8497 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8515
+/* 8501 */ MCD_OPC_CheckPredicate, 0, 156, 66, // Skip to: 25557
+/* 8505 */ MCD_OPC_CheckField, 21, 1, 1, 150, 66, // Skip to: 25557
+/* 8511 */ MCD_OPC_Decode, 142, 11, 31, // Opcode: UABAvvv_4H
+/* 8515 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8533
+/* 8519 */ MCD_OPC_CheckPredicate, 0, 138, 66, // Skip to: 25557
+/* 8523 */ MCD_OPC_CheckField, 21, 1, 1, 132, 66, // Skip to: 25557
+/* 8529 */ MCD_OPC_Decode, 239, 7, 42, // Opcode: SABAvvv_8H
+/* 8533 */ MCD_OPC_FilterValue, 3, 124, 66, // Skip to: 25557
+/* 8537 */ MCD_OPC_CheckPredicate, 0, 120, 66, // Skip to: 25557
+/* 8541 */ MCD_OPC_CheckField, 21, 1, 1, 114, 66, // Skip to: 25557
+/* 8547 */ MCD_OPC_Decode, 145, 11, 42, // Opcode: UABAvvv_8H
+/* 8551 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 8630
+/* 8555 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8558 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8576
+/* 8562 */ MCD_OPC_CheckPredicate, 0, 95, 66, // Skip to: 25557
+/* 8566 */ MCD_OPC_CheckField, 21, 1, 1, 89, 66, // Skip to: 25557
+/* 8572 */ MCD_OPC_Decode, 218, 8, 30, // Opcode: SMLALvvv_4s4h
+/* 8576 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8594
+/* 8580 */ MCD_OPC_CheckPredicate, 0, 77, 66, // Skip to: 25557
+/* 8584 */ MCD_OPC_CheckField, 21, 1, 1, 71, 66, // Skip to: 25557
+/* 8590 */ MCD_OPC_Decode, 227, 11, 30, // Opcode: UMLALvvv_4s4h
+/* 8594 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8612
+/* 8598 */ MCD_OPC_CheckPredicate, 0, 59, 66, // Skip to: 25557
+/* 8602 */ MCD_OPC_CheckField, 21, 1, 1, 53, 66, // Skip to: 25557
+/* 8608 */ MCD_OPC_Decode, 215, 8, 42, // Opcode: SMLAL2vvv_4s8h
+/* 8612 */ MCD_OPC_FilterValue, 3, 45, 66, // Skip to: 25557
+/* 8616 */ MCD_OPC_CheckPredicate, 0, 41, 66, // Skip to: 25557
+/* 8620 */ MCD_OPC_CheckField, 21, 1, 1, 35, 66, // Skip to: 25557
+/* 8626 */ MCD_OPC_Decode, 224, 11, 42, // Opcode: UMLAL2vvv_4s8h
+/* 8630 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 8707
+/* 8634 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8637 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 8654
+/* 8641 */ MCD_OPC_CheckPredicate, 0, 16, 66, // Skip to: 25557
+/* 8645 */ MCD_OPC_CheckField, 21, 1, 1, 10, 66, // Skip to: 25557
+/* 8651 */ MCD_OPC_Decode, 61, 24, // Opcode: ADDvvv_4H
+/* 8654 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8672
+/* 8658 */ MCD_OPC_CheckPredicate, 0, 255, 65, // Skip to: 25557
+/* 8662 */ MCD_OPC_CheckField, 21, 1, 1, 249, 65, // Skip to: 25557
+/* 8668 */ MCD_OPC_Decode, 196, 10, 24, // Opcode: SUBvvv_4H
+/* 8672 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 8689
+/* 8676 */ MCD_OPC_CheckPredicate, 0, 237, 65, // Skip to: 25557
+/* 8680 */ MCD_OPC_CheckField, 21, 1, 1, 231, 65, // Skip to: 25557
+/* 8686 */ MCD_OPC_Decode, 64, 33, // Opcode: ADDvvv_8H
+/* 8689 */ MCD_OPC_FilterValue, 3, 224, 65, // Skip to: 25557
+/* 8693 */ MCD_OPC_CheckPredicate, 0, 220, 65, // Skip to: 25557
+/* 8697 */ MCD_OPC_CheckField, 21, 1, 1, 214, 65, // Skip to: 25557
+/* 8703 */ MCD_OPC_Decode, 199, 10, 33, // Opcode: SUBvvv_8H
+/* 8707 */ MCD_OPC_FilterValue, 34, 75, 0, // Skip to: 8786
+/* 8711 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8714 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8732
+/* 8718 */ MCD_OPC_CheckPredicate, 0, 195, 65, // Skip to: 25557
+/* 8722 */ MCD_OPC_CheckField, 16, 6, 32, 189, 65, // Skip to: 25557
+/* 8728 */ MCD_OPC_Decode, 138, 2, 32, // Opcode: CMGTvvi_4H
+/* 8732 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8750
+/* 8736 */ MCD_OPC_CheckPredicate, 0, 177, 65, // Skip to: 25557
+/* 8740 */ MCD_OPC_CheckField, 16, 6, 32, 171, 65, // Skip to: 25557
+/* 8746 */ MCD_OPC_Decode, 252, 1, 32, // Opcode: CMGEvvi_4H
+/* 8750 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8768
+/* 8754 */ MCD_OPC_CheckPredicate, 0, 159, 65, // Skip to: 25557
+/* 8758 */ MCD_OPC_CheckField, 16, 6, 32, 153, 65, // Skip to: 25557
+/* 8764 */ MCD_OPC_Decode, 141, 2, 43, // Opcode: CMGTvvi_8H
+/* 8768 */ MCD_OPC_FilterValue, 3, 145, 65, // Skip to: 25557
+/* 8772 */ MCD_OPC_CheckPredicate, 0, 141, 65, // Skip to: 25557
+/* 8776 */ MCD_OPC_CheckField, 16, 6, 32, 135, 65, // Skip to: 25557
+/* 8782 */ MCD_OPC_Decode, 255, 1, 43, // Opcode: CMGEvvi_8H
+/* 8786 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 8865
+/* 8790 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8793 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8811
+/* 8797 */ MCD_OPC_CheckPredicate, 0, 116, 65, // Skip to: 25557
+/* 8801 */ MCD_OPC_CheckField, 21, 1, 1, 110, 65, // Skip to: 25557
+/* 8807 */ MCD_OPC_Decode, 224, 2, 24, // Opcode: CMTSTvvv_4H
+/* 8811 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8829
+/* 8815 */ MCD_OPC_CheckPredicate, 0, 98, 65, // Skip to: 25557
+/* 8819 */ MCD_OPC_CheckField, 21, 1, 1, 92, 65, // Skip to: 25557
+/* 8825 */ MCD_OPC_Decode, 245, 1, 24, // Opcode: CMEQvvv_4H
+/* 8829 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8847
+/* 8833 */ MCD_OPC_CheckPredicate, 0, 80, 65, // Skip to: 25557
+/* 8837 */ MCD_OPC_CheckField, 21, 1, 1, 74, 65, // Skip to: 25557
+/* 8843 */ MCD_OPC_Decode, 227, 2, 33, // Opcode: CMTSTvvv_8H
+/* 8847 */ MCD_OPC_FilterValue, 3, 66, 65, // Skip to: 25557
+/* 8851 */ MCD_OPC_CheckPredicate, 0, 62, 65, // Skip to: 25557
+/* 8855 */ MCD_OPC_CheckField, 21, 1, 1, 56, 65, // Skip to: 25557
+/* 8861 */ MCD_OPC_Decode, 248, 1, 33, // Opcode: CMEQvvv_8H
+/* 8865 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 8908
+/* 8869 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8872 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8890
+/* 8876 */ MCD_OPC_CheckPredicate, 0, 37, 65, // Skip to: 25557
+/* 8880 */ MCD_OPC_CheckField, 21, 1, 1, 31, 65, // Skip to: 25557
+/* 8886 */ MCD_OPC_Decode, 253, 8, 30, // Opcode: SQDMLALvvv_4s4h
+/* 8890 */ MCD_OPC_FilterValue, 2, 23, 65, // Skip to: 25557
+/* 8894 */ MCD_OPC_CheckPredicate, 0, 19, 65, // Skip to: 25557
+/* 8898 */ MCD_OPC_CheckField, 21, 1, 1, 13, 65, // Skip to: 25557
+/* 8904 */ MCD_OPC_Decode, 251, 8, 42, // Opcode: SQDMLAL2vvv_4s8h
+/* 8908 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 8987
+/* 8912 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8915 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 8933
+/* 8919 */ MCD_OPC_CheckPredicate, 0, 250, 64, // Skip to: 25557
+/* 8923 */ MCD_OPC_CheckField, 21, 1, 1, 244, 64, // Skip to: 25557
+/* 8929 */ MCD_OPC_Decode, 229, 6, 31, // Opcode: MLAvvv_4H
+/* 8933 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8951
+/* 8937 */ MCD_OPC_CheckPredicate, 0, 232, 64, // Skip to: 25557
+/* 8941 */ MCD_OPC_CheckField, 21, 1, 1, 226, 64, // Skip to: 25557
+/* 8947 */ MCD_OPC_Decode, 235, 6, 31, // Opcode: MLSvvv_4H
+/* 8951 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 8969
+/* 8955 */ MCD_OPC_CheckPredicate, 0, 214, 64, // Skip to: 25557
+/* 8959 */ MCD_OPC_CheckField, 21, 1, 1, 208, 64, // Skip to: 25557
+/* 8965 */ MCD_OPC_Decode, 232, 6, 42, // Opcode: MLAvvv_8H
+/* 8969 */ MCD_OPC_FilterValue, 3, 200, 64, // Skip to: 25557
+/* 8973 */ MCD_OPC_CheckPredicate, 0, 196, 64, // Skip to: 25557
+/* 8977 */ MCD_OPC_CheckField, 21, 1, 1, 190, 64, // Skip to: 25557
+/* 8983 */ MCD_OPC_Decode, 238, 6, 42, // Opcode: MLSvvv_8H
+/* 8987 */ MCD_OPC_FilterValue, 38, 75, 0, // Skip to: 9066
+/* 8991 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 8994 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9012
+/* 8998 */ MCD_OPC_CheckPredicate, 0, 171, 64, // Skip to: 25557
+/* 9002 */ MCD_OPC_CheckField, 16, 6, 32, 165, 64, // Skip to: 25557
+/* 9008 */ MCD_OPC_Decode, 238, 1, 32, // Opcode: CMEQvvi_4H
+/* 9012 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9030
+/* 9016 */ MCD_OPC_CheckPredicate, 0, 153, 64, // Skip to: 25557
+/* 9020 */ MCD_OPC_CheckField, 16, 6, 32, 147, 64, // Skip to: 25557
+/* 9026 */ MCD_OPC_Decode, 166, 2, 32, // Opcode: CMLEvvi_4H
+/* 9030 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9048
+/* 9034 */ MCD_OPC_CheckPredicate, 0, 135, 64, // Skip to: 25557
+/* 9038 */ MCD_OPC_CheckField, 16, 6, 32, 129, 64, // Skip to: 25557
+/* 9044 */ MCD_OPC_Decode, 241, 1, 43, // Opcode: CMEQvvi_8H
+/* 9048 */ MCD_OPC_FilterValue, 3, 121, 64, // Skip to: 25557
+/* 9052 */ MCD_OPC_CheckPredicate, 0, 117, 64, // Skip to: 25557
+/* 9056 */ MCD_OPC_CheckField, 16, 6, 32, 111, 64, // Skip to: 25557
+/* 9062 */ MCD_OPC_Decode, 169, 2, 43, // Opcode: CMLEvvi_8H
+/* 9066 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 9109
+/* 9070 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9073 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9091
+/* 9077 */ MCD_OPC_CheckPredicate, 0, 92, 64, // Skip to: 25557
+/* 9081 */ MCD_OPC_CheckField, 21, 1, 1, 86, 64, // Skip to: 25557
+/* 9087 */ MCD_OPC_Decode, 134, 7, 24, // Opcode: MULvvv_4H
+/* 9091 */ MCD_OPC_FilterValue, 2, 78, 64, // Skip to: 25557
+/* 9095 */ MCD_OPC_CheckPredicate, 0, 74, 64, // Skip to: 25557
+/* 9099 */ MCD_OPC_CheckField, 21, 1, 1, 68, 64, // Skip to: 25557
+/* 9105 */ MCD_OPC_Decode, 137, 7, 33, // Opcode: MULvvv_8H
+/* 9109 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 9188
+/* 9113 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9116 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9134
+/* 9120 */ MCD_OPC_CheckPredicate, 0, 49, 64, // Skip to: 25557
+/* 9124 */ MCD_OPC_CheckField, 21, 1, 1, 43, 64, // Skip to: 25557
+/* 9130 */ MCD_OPC_Decode, 224, 8, 30, // Opcode: SMLSLvvv_4s4h
+/* 9134 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9152
+/* 9138 */ MCD_OPC_CheckPredicate, 0, 31, 64, // Skip to: 25557
+/* 9142 */ MCD_OPC_CheckField, 21, 1, 1, 25, 64, // Skip to: 25557
+/* 9148 */ MCD_OPC_Decode, 233, 11, 30, // Opcode: UMLSLvvv_4s4h
+/* 9152 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9170
+/* 9156 */ MCD_OPC_CheckPredicate, 0, 13, 64, // Skip to: 25557
+/* 9160 */ MCD_OPC_CheckField, 21, 1, 1, 7, 64, // Skip to: 25557
+/* 9166 */ MCD_OPC_Decode, 221, 8, 42, // Opcode: SMLSL2vvv_4s8h
+/* 9170 */ MCD_OPC_FilterValue, 3, 255, 63, // Skip to: 25557
+/* 9174 */ MCD_OPC_CheckPredicate, 0, 251, 63, // Skip to: 25557
+/* 9178 */ MCD_OPC_CheckField, 21, 1, 1, 245, 63, // Skip to: 25557
+/* 9184 */ MCD_OPC_Decode, 230, 11, 42, // Opcode: UMLSL2vvv_4s8h
+/* 9188 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 9267
+/* 9192 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9195 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9213
+/* 9199 */ MCD_OPC_CheckPredicate, 0, 226, 63, // Skip to: 25557
+/* 9203 */ MCD_OPC_CheckField, 21, 1, 1, 220, 63, // Skip to: 25557
+/* 9209 */ MCD_OPC_Decode, 191, 8, 24, // Opcode: SMAXPvvv_4H
+/* 9213 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9231
+/* 9217 */ MCD_OPC_CheckPredicate, 0, 208, 63, // Skip to: 25557
+/* 9221 */ MCD_OPC_CheckField, 21, 1, 1, 202, 63, // Skip to: 25557
+/* 9227 */ MCD_OPC_Decode, 201, 11, 24, // Opcode: UMAXPvvv_4H
+/* 9231 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9249
+/* 9235 */ MCD_OPC_CheckPredicate, 0, 190, 63, // Skip to: 25557
+/* 9239 */ MCD_OPC_CheckField, 21, 1, 1, 184, 63, // Skip to: 25557
+/* 9245 */ MCD_OPC_Decode, 194, 8, 33, // Opcode: SMAXPvvv_8H
+/* 9249 */ MCD_OPC_FilterValue, 3, 176, 63, // Skip to: 25557
+/* 9253 */ MCD_OPC_CheckPredicate, 0, 172, 63, // Skip to: 25557
+/* 9257 */ MCD_OPC_CheckField, 21, 1, 1, 166, 63, // Skip to: 25557
+/* 9263 */ MCD_OPC_Decode, 204, 11, 33, // Opcode: UMAXPvvv_8H
+/* 9267 */ MCD_OPC_FilterValue, 42, 39, 0, // Skip to: 9310
+/* 9271 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9274 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9292
+/* 9278 */ MCD_OPC_CheckPredicate, 0, 147, 63, // Skip to: 25557
+/* 9282 */ MCD_OPC_CheckField, 16, 6, 32, 141, 63, // Skip to: 25557
+/* 9288 */ MCD_OPC_Decode, 173, 2, 32, // Opcode: CMLTvvi_4H
+/* 9292 */ MCD_OPC_FilterValue, 2, 133, 63, // Skip to: 25557
+/* 9296 */ MCD_OPC_CheckPredicate, 0, 129, 63, // Skip to: 25557
+/* 9300 */ MCD_OPC_CheckField, 16, 6, 32, 123, 63, // Skip to: 25557
+/* 9306 */ MCD_OPC_Decode, 176, 2, 43, // Opcode: CMLTvvi_8H
+/* 9310 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 9389
+/* 9314 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9317 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9335
+/* 9321 */ MCD_OPC_CheckPredicate, 0, 104, 63, // Skip to: 25557
+/* 9325 */ MCD_OPC_CheckField, 21, 1, 1, 98, 63, // Skip to: 25557
+/* 9331 */ MCD_OPC_Decode, 204, 8, 24, // Opcode: SMINPvvv_4H
+/* 9335 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9353
+/* 9339 */ MCD_OPC_CheckPredicate, 0, 86, 63, // Skip to: 25557
+/* 9343 */ MCD_OPC_CheckField, 21, 1, 1, 80, 63, // Skip to: 25557
+/* 9349 */ MCD_OPC_Decode, 213, 11, 24, // Opcode: UMINPvvv_4H
+/* 9353 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9371
+/* 9357 */ MCD_OPC_CheckPredicate, 0, 68, 63, // Skip to: 25557
+/* 9361 */ MCD_OPC_CheckField, 21, 1, 1, 62, 63, // Skip to: 25557
+/* 9367 */ MCD_OPC_Decode, 207, 8, 33, // Opcode: SMINPvvv_8H
+/* 9371 */ MCD_OPC_FilterValue, 3, 54, 63, // Skip to: 25557
+/* 9375 */ MCD_OPC_CheckPredicate, 0, 50, 63, // Skip to: 25557
+/* 9379 */ MCD_OPC_CheckField, 21, 1, 1, 44, 63, // Skip to: 25557
+/* 9385 */ MCD_OPC_Decode, 216, 11, 33, // Opcode: UMINPvvv_8H
+/* 9389 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 9432
+/* 9393 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9396 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9414
+/* 9400 */ MCD_OPC_CheckPredicate, 0, 25, 63, // Skip to: 25557
+/* 9404 */ MCD_OPC_CheckField, 21, 1, 1, 19, 63, // Skip to: 25557
+/* 9410 */ MCD_OPC_Decode, 129, 9, 30, // Opcode: SQDMLSLvvv_4s4h
+/* 9414 */ MCD_OPC_FilterValue, 2, 11, 63, // Skip to: 25557
+/* 9418 */ MCD_OPC_CheckPredicate, 0, 7, 63, // Skip to: 25557
+/* 9422 */ MCD_OPC_CheckField, 21, 1, 1, 1, 63, // Skip to: 25557
+/* 9428 */ MCD_OPC_Decode, 255, 8, 42, // Opcode: SQDMLSL2vvv_4s8h
+/* 9432 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 9511
+/* 9436 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9439 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9457
+/* 9443 */ MCD_OPC_CheckPredicate, 0, 238, 62, // Skip to: 25557
+/* 9447 */ MCD_OPC_CheckField, 21, 1, 1, 232, 62, // Skip to: 25557
+/* 9453 */ MCD_OPC_Decode, 131, 9, 24, // Opcode: SQDMULHvvv_4H
+/* 9457 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9475
+/* 9461 */ MCD_OPC_CheckPredicate, 0, 220, 62, // Skip to: 25557
+/* 9465 */ MCD_OPC_CheckField, 21, 1, 1, 214, 62, // Skip to: 25557
+/* 9471 */ MCD_OPC_Decode, 139, 9, 24, // Opcode: SQRDMULHvvv_4H
+/* 9475 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9493
+/* 9479 */ MCD_OPC_CheckPredicate, 0, 202, 62, // Skip to: 25557
+/* 9483 */ MCD_OPC_CheckField, 21, 1, 1, 196, 62, // Skip to: 25557
+/* 9489 */ MCD_OPC_Decode, 133, 9, 33, // Opcode: SQDMULHvvv_8H
+/* 9493 */ MCD_OPC_FilterValue, 3, 188, 62, // Skip to: 25557
+/* 9497 */ MCD_OPC_CheckPredicate, 0, 184, 62, // Skip to: 25557
+/* 9501 */ MCD_OPC_CheckField, 21, 1, 1, 178, 62, // Skip to: 25557
+/* 9507 */ MCD_OPC_Decode, 141, 9, 33, // Opcode: SQRDMULHvvv_8H
+/* 9511 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 9552
+/* 9515 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9518 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 9535
+/* 9522 */ MCD_OPC_CheckPredicate, 0, 159, 62, // Skip to: 25557
+/* 9526 */ MCD_OPC_CheckField, 21, 1, 1, 153, 62, // Skip to: 25557
+/* 9532 */ MCD_OPC_Decode, 30, 24, // Opcode: ADDP_4H
+/* 9535 */ MCD_OPC_FilterValue, 2, 146, 62, // Skip to: 25557
+/* 9539 */ MCD_OPC_CheckPredicate, 0, 142, 62, // Skip to: 25557
+/* 9543 */ MCD_OPC_CheckField, 21, 1, 1, 136, 62, // Skip to: 25557
+/* 9549 */ MCD_OPC_Decode, 33, 33, // Opcode: ADDP_8H
+/* 9552 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 9631
+/* 9556 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9559 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9577
+/* 9563 */ MCD_OPC_CheckPredicate, 0, 118, 62, // Skip to: 25557
+/* 9567 */ MCD_OPC_CheckField, 21, 1, 1, 112, 62, // Skip to: 25557
+/* 9573 */ MCD_OPC_Decode, 237, 8, 23, // Opcode: SMULLvvv_4s4h
+/* 9577 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9595
+/* 9581 */ MCD_OPC_CheckPredicate, 0, 100, 62, // Skip to: 25557
+/* 9585 */ MCD_OPC_CheckField, 21, 1, 1, 94, 62, // Skip to: 25557
+/* 9591 */ MCD_OPC_Decode, 245, 11, 23, // Opcode: UMULLvvv_4s4h
+/* 9595 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9613
+/* 9599 */ MCD_OPC_CheckPredicate, 0, 82, 62, // Skip to: 25557
+/* 9603 */ MCD_OPC_CheckField, 21, 1, 1, 76, 62, // Skip to: 25557
+/* 9609 */ MCD_OPC_Decode, 234, 8, 33, // Opcode: SMULL2vvv_4s8h
+/* 9613 */ MCD_OPC_FilterValue, 3, 68, 62, // Skip to: 25557
+/* 9617 */ MCD_OPC_CheckPredicate, 0, 64, 62, // Skip to: 25557
+/* 9621 */ MCD_OPC_CheckField, 21, 1, 1, 58, 62, // Skip to: 25557
+/* 9627 */ MCD_OPC_Decode, 242, 11, 33, // Opcode: UMULL2vvv_4s8h
+/* 9631 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 9674
+/* 9635 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9638 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9656
+/* 9642 */ MCD_OPC_CheckPredicate, 0, 39, 62, // Skip to: 25557
+/* 9646 */ MCD_OPC_CheckField, 21, 1, 1, 33, 62, // Skip to: 25557
+/* 9652 */ MCD_OPC_Decode, 146, 4, 33, // Opcode: FMAXNMvvv_2D
+/* 9656 */ MCD_OPC_FilterValue, 3, 25, 62, // Skip to: 25557
+/* 9660 */ MCD_OPC_CheckPredicate, 0, 21, 62, // Skip to: 25557
+/* 9664 */ MCD_OPC_CheckField, 21, 1, 1, 15, 62, // Skip to: 25557
+/* 9670 */ MCD_OPC_Decode, 141, 4, 33, // Opcode: FMAXNMPvvv_2D
+/* 9674 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 9698
+/* 9678 */ MCD_OPC_CheckPredicate, 0, 3, 62, // Skip to: 25557
+/* 9682 */ MCD_OPC_CheckField, 29, 3, 2, 253, 61, // Skip to: 25557
+/* 9688 */ MCD_OPC_CheckField, 21, 1, 1, 247, 61, // Skip to: 25557
+/* 9694 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: FMLAvvv_2D
+/* 9698 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 9741
+/* 9702 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9705 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9723
+/* 9709 */ MCD_OPC_CheckPredicate, 0, 228, 61, // Skip to: 25557
+/* 9713 */ MCD_OPC_CheckField, 21, 1, 1, 222, 61, // Skip to: 25557
+/* 9719 */ MCD_OPC_Decode, 137, 9, 23, // Opcode: SQDMULLvvv_4s4h
+/* 9723 */ MCD_OPC_FilterValue, 2, 214, 61, // Skip to: 25557
+/* 9727 */ MCD_OPC_CheckPredicate, 0, 210, 61, // Skip to: 25557
+/* 9731 */ MCD_OPC_CheckField, 21, 1, 1, 204, 61, // Skip to: 25557
+/* 9737 */ MCD_OPC_Decode, 135, 9, 33, // Opcode: SQDMULL2vvv_4s8h
+/* 9741 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 9784
+/* 9745 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9748 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9766
+/* 9752 */ MCD_OPC_CheckPredicate, 0, 185, 61, // Skip to: 25557
+/* 9756 */ MCD_OPC_CheckField, 21, 1, 1, 179, 61, // Skip to: 25557
+/* 9762 */ MCD_OPC_Decode, 165, 3, 33, // Opcode: FADDvvv_2D
+/* 9766 */ MCD_OPC_FilterValue, 3, 171, 61, // Skip to: 25557
+/* 9770 */ MCD_OPC_CheckPredicate, 0, 167, 61, // Skip to: 25557
+/* 9774 */ MCD_OPC_CheckField, 21, 1, 1, 161, 61, // Skip to: 25557
+/* 9780 */ MCD_OPC_Decode, 158, 3, 33, // Opcode: FADDP_2D
+/* 9784 */ MCD_OPC_FilterValue, 55, 39, 0, // Skip to: 9827
+/* 9788 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9791 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9809
+/* 9795 */ MCD_OPC_CheckPredicate, 0, 142, 61, // Skip to: 25557
+/* 9799 */ MCD_OPC_CheckField, 21, 1, 1, 136, 61, // Skip to: 25557
+/* 9805 */ MCD_OPC_Decode, 200, 4, 33, // Opcode: FMULXvvv_2D
+/* 9809 */ MCD_OPC_FilterValue, 3, 128, 61, // Skip to: 25557
+/* 9813 */ MCD_OPC_CheckPredicate, 0, 124, 61, // Skip to: 25557
+/* 9817 */ MCD_OPC_CheckField, 21, 1, 1, 118, 61, // Skip to: 25557
+/* 9823 */ MCD_OPC_Decode, 205, 4, 33, // Opcode: FMULvvv_2D
+/* 9827 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 9870
+/* 9831 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9834 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9852
+/* 9838 */ MCD_OPC_CheckPredicate, 0, 99, 61, // Skip to: 25557
+/* 9842 */ MCD_OPC_CheckField, 21, 1, 1, 93, 61, // Skip to: 25557
+/* 9848 */ MCD_OPC_Decode, 175, 3, 33, // Opcode: FCMEQvvv_2D
+/* 9852 */ MCD_OPC_FilterValue, 3, 85, 61, // Skip to: 25557
+/* 9856 */ MCD_OPC_CheckPredicate, 0, 81, 61, // Skip to: 25557
+/* 9860 */ MCD_OPC_CheckField, 21, 1, 1, 75, 61, // Skip to: 25557
+/* 9866 */ MCD_OPC_Decode, 181, 3, 33, // Opcode: FCMGEvvv_2D
+/* 9870 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 9894
+/* 9874 */ MCD_OPC_CheckPredicate, 0, 63, 61, // Skip to: 25557
+/* 9878 */ MCD_OPC_CheckField, 29, 3, 3, 57, 61, // Skip to: 25557
+/* 9884 */ MCD_OPC_CheckField, 21, 1, 1, 51, 61, // Skip to: 25557
+/* 9890 */ MCD_OPC_Decode, 152, 3, 33, // Opcode: FACGEvvv_2D
+/* 9894 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 9937
+/* 9898 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9901 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9919
+/* 9905 */ MCD_OPC_CheckPredicate, 0, 32, 61, // Skip to: 25557
+/* 9909 */ MCD_OPC_CheckField, 21, 1, 1, 26, 61, // Skip to: 25557
+/* 9915 */ MCD_OPC_Decode, 156, 4, 33, // Opcode: FMAXvvv_2D
+/* 9919 */ MCD_OPC_FilterValue, 3, 18, 61, // Skip to: 25557
+/* 9923 */ MCD_OPC_CheckPredicate, 0, 14, 61, // Skip to: 25557
+/* 9927 */ MCD_OPC_CheckField, 21, 1, 1, 8, 61, // Skip to: 25557
+/* 9933 */ MCD_OPC_Decode, 151, 4, 33, // Opcode: FMAXPvvv_2D
+/* 9937 */ MCD_OPC_FilterValue, 63, 0, 61, // Skip to: 25557
+/* 9941 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9944 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9962
+/* 9948 */ MCD_OPC_CheckPredicate, 0, 245, 60, // Skip to: 25557
+/* 9952 */ MCD_OPC_CheckField, 21, 1, 1, 239, 60, // Skip to: 25557
+/* 9958 */ MCD_OPC_Decode, 216, 4, 33, // Opcode: FRECPSvvv_2D
+/* 9962 */ MCD_OPC_FilterValue, 3, 231, 60, // Skip to: 25557
+/* 9966 */ MCD_OPC_CheckPredicate, 0, 227, 60, // Skip to: 25557
+/* 9970 */ MCD_OPC_CheckField, 21, 1, 1, 221, 60, // Skip to: 25557
+/* 9976 */ MCD_OPC_Decode, 134, 4, 33, // Opcode: FDIVvvv_2D
+/* 9980 */ MCD_OPC_FilterValue, 10, 46, 14, // Skip to: 13614
+/* 9984 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 9987 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 10066
+/* 9991 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 9994 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10012
+/* 9998 */ MCD_OPC_CheckPredicate, 0, 195, 60, // Skip to: 25557
+/* 10002 */ MCD_OPC_CheckField, 21, 1, 1, 189, 60, // Skip to: 25557
+/* 10008 */ MCD_OPC_Decode, 255, 7, 23, // Opcode: SADDLvvv_2d2s
+/* 10012 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10030
+/* 10016 */ MCD_OPC_CheckPredicate, 0, 177, 60, // Skip to: 25557
+/* 10020 */ MCD_OPC_CheckField, 21, 1, 1, 171, 60, // Skip to: 25557
+/* 10026 */ MCD_OPC_Decode, 161, 11, 23, // Opcode: UADDLvvv_2d2s
+/* 10030 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10048
+/* 10034 */ MCD_OPC_CheckPredicate, 0, 159, 60, // Skip to: 25557
+/* 10038 */ MCD_OPC_CheckField, 21, 1, 1, 153, 60, // Skip to: 25557
+/* 10044 */ MCD_OPC_Decode, 252, 7, 33, // Opcode: SADDL2vvv_2d4s
+/* 10048 */ MCD_OPC_FilterValue, 3, 145, 60, // Skip to: 25557
+/* 10052 */ MCD_OPC_CheckPredicate, 0, 141, 60, // Skip to: 25557
+/* 10056 */ MCD_OPC_CheckField, 21, 1, 1, 135, 60, // Skip to: 25557
+/* 10062 */ MCD_OPC_Decode, 158, 11, 33, // Opcode: UADDL2vvv_2d4s
+/* 10066 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 10145
+/* 10070 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10073 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10091
+/* 10077 */ MCD_OPC_CheckPredicate, 0, 116, 60, // Skip to: 25557
+/* 10081 */ MCD_OPC_CheckField, 21, 1, 1, 110, 60, // Skip to: 25557
+/* 10087 */ MCD_OPC_Decode, 157, 8, 24, // Opcode: SHADDvvv_2S
+/* 10091 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10109
+/* 10095 */ MCD_OPC_CheckPredicate, 0, 98, 60, // Skip to: 25557
+/* 10099 */ MCD_OPC_CheckField, 21, 1, 1, 92, 60, // Skip to: 25557
+/* 10105 */ MCD_OPC_Decode, 187, 11, 24, // Opcode: UHADDvvv_2S
+/* 10109 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10127
+/* 10113 */ MCD_OPC_CheckPredicate, 0, 80, 60, // Skip to: 25557
+/* 10117 */ MCD_OPC_CheckField, 21, 1, 1, 74, 60, // Skip to: 25557
+/* 10123 */ MCD_OPC_Decode, 159, 8, 33, // Opcode: SHADDvvv_4S
+/* 10127 */ MCD_OPC_FilterValue, 3, 66, 60, // Skip to: 25557
+/* 10131 */ MCD_OPC_CheckPredicate, 0, 62, 60, // Skip to: 25557
+/* 10135 */ MCD_OPC_CheckField, 21, 1, 1, 56, 60, // Skip to: 25557
+/* 10141 */ MCD_OPC_Decode, 189, 11, 33, // Opcode: UHADDvvv_4S
+/* 10145 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 10224
+/* 10149 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10152 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10170
+/* 10156 */ MCD_OPC_CheckPredicate, 0, 37, 60, // Skip to: 25557
+/* 10160 */ MCD_OPC_CheckField, 21, 1, 1, 31, 60, // Skip to: 25557
+/* 10166 */ MCD_OPC_Decode, 245, 8, 24, // Opcode: SQADDvvv_2S
+/* 10170 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10188
+/* 10174 */ MCD_OPC_CheckPredicate, 0, 19, 60, // Skip to: 25557
+/* 10178 */ MCD_OPC_CheckField, 21, 1, 1, 13, 60, // Skip to: 25557
+/* 10184 */ MCD_OPC_Decode, 253, 11, 24, // Opcode: UQADDvvv_2S
+/* 10188 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10206
+/* 10192 */ MCD_OPC_CheckPredicate, 0, 1, 60, // Skip to: 25557
+/* 10196 */ MCD_OPC_CheckField, 21, 1, 1, 251, 59, // Skip to: 25557
+/* 10202 */ MCD_OPC_Decode, 247, 8, 33, // Opcode: SQADDvvv_4S
+/* 10206 */ MCD_OPC_FilterValue, 3, 243, 59, // Skip to: 25557
+/* 10210 */ MCD_OPC_CheckPredicate, 0, 239, 59, // Skip to: 25557
+/* 10214 */ MCD_OPC_CheckField, 21, 1, 1, 233, 59, // Skip to: 25557
+/* 10220 */ MCD_OPC_Decode, 255, 11, 33, // Opcode: UQADDvvv_4S
+/* 10224 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 10303
+/* 10228 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10231 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10249
+/* 10235 */ MCD_OPC_CheckPredicate, 0, 214, 59, // Skip to: 25557
+/* 10239 */ MCD_OPC_CheckField, 21, 1, 1, 208, 59, // Skip to: 25557
+/* 10245 */ MCD_OPC_Decode, 133, 8, 25, // Opcode: SADDWvvv_2d2s
+/* 10249 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10267
+/* 10253 */ MCD_OPC_CheckPredicate, 0, 196, 59, // Skip to: 25557
+/* 10257 */ MCD_OPC_CheckField, 21, 1, 1, 190, 59, // Skip to: 25557
+/* 10263 */ MCD_OPC_Decode, 167, 11, 25, // Opcode: UADDWvvv_2d2s
+/* 10267 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10285
+/* 10271 */ MCD_OPC_CheckPredicate, 0, 178, 59, // Skip to: 25557
+/* 10275 */ MCD_OPC_CheckField, 21, 1, 1, 172, 59, // Skip to: 25557
+/* 10281 */ MCD_OPC_Decode, 130, 8, 33, // Opcode: SADDW2vvv_2d4s
+/* 10285 */ MCD_OPC_FilterValue, 3, 164, 59, // Skip to: 25557
+/* 10289 */ MCD_OPC_CheckPredicate, 0, 160, 59, // Skip to: 25557
+/* 10293 */ MCD_OPC_CheckField, 21, 1, 1, 154, 59, // Skip to: 25557
+/* 10299 */ MCD_OPC_Decode, 164, 11, 33, // Opcode: UADDW2vvv_2d4s
+/* 10303 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 10382
+/* 10307 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10310 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10328
+/* 10314 */ MCD_OPC_CheckPredicate, 0, 135, 59, // Skip to: 25557
+/* 10318 */ MCD_OPC_CheckField, 21, 1, 1, 129, 59, // Skip to: 25557
+/* 10324 */ MCD_OPC_Decode, 202, 9, 24, // Opcode: SRHADDvvv_2S
+/* 10328 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10346
+/* 10332 */ MCD_OPC_CheckPredicate, 0, 117, 59, // Skip to: 25557
+/* 10336 */ MCD_OPC_CheckField, 21, 1, 1, 111, 59, // Skip to: 25557
+/* 10342 */ MCD_OPC_Decode, 183, 12, 24, // Opcode: URHADDvvv_2S
+/* 10346 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10364
+/* 10350 */ MCD_OPC_CheckPredicate, 0, 99, 59, // Skip to: 25557
+/* 10354 */ MCD_OPC_CheckField, 21, 1, 1, 93, 59, // Skip to: 25557
+/* 10360 */ MCD_OPC_Decode, 204, 9, 33, // Opcode: SRHADDvvv_4S
+/* 10364 */ MCD_OPC_FilterValue, 3, 85, 59, // Skip to: 25557
+/* 10368 */ MCD_OPC_CheckPredicate, 0, 81, 59, // Skip to: 25557
+/* 10372 */ MCD_OPC_CheckField, 21, 1, 1, 75, 59, // Skip to: 25557
+/* 10378 */ MCD_OPC_Decode, 185, 12, 33, // Opcode: URHADDvvv_4S
+/* 10382 */ MCD_OPC_FilterValue, 7, 75, 0, // Skip to: 10461
+/* 10386 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10389 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10407
+/* 10393 */ MCD_OPC_CheckPredicate, 0, 56, 59, // Skip to: 25557
+/* 10397 */ MCD_OPC_CheckField, 21, 1, 1, 50, 59, // Skip to: 25557
+/* 10403 */ MCD_OPC_Decode, 167, 7, 24, // Opcode: ORRvvv_8B
+/* 10407 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10425
+/* 10411 */ MCD_OPC_CheckPredicate, 0, 38, 59, // Skip to: 25557
+/* 10415 */ MCD_OPC_CheckField, 21, 1, 1, 32, 59, // Skip to: 25557
+/* 10421 */ MCD_OPC_Decode, 209, 1, 31, // Opcode: BITvvv_8B
+/* 10425 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10443
+/* 10429 */ MCD_OPC_CheckPredicate, 0, 20, 59, // Skip to: 25557
+/* 10433 */ MCD_OPC_CheckField, 21, 1, 1, 14, 59, // Skip to: 25557
+/* 10439 */ MCD_OPC_Decode, 166, 7, 33, // Opcode: ORRvvv_16B
+/* 10443 */ MCD_OPC_FilterValue, 3, 6, 59, // Skip to: 25557
+/* 10447 */ MCD_OPC_CheckPredicate, 0, 2, 59, // Skip to: 25557
+/* 10451 */ MCD_OPC_CheckField, 21, 1, 1, 252, 58, // Skip to: 25557
+/* 10457 */ MCD_OPC_Decode, 208, 1, 42, // Opcode: BITvvv_16B
+/* 10461 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 10540
+/* 10465 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10468 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10486
+/* 10472 */ MCD_OPC_CheckPredicate, 0, 233, 58, // Skip to: 25557
+/* 10476 */ MCD_OPC_CheckField, 21, 1, 1, 227, 58, // Skip to: 25557
+/* 10482 */ MCD_OPC_Decode, 139, 10, 23, // Opcode: SSUBLvvv_2d2s
+/* 10486 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10504
+/* 10490 */ MCD_OPC_CheckPredicate, 0, 215, 58, // Skip to: 25557
+/* 10494 */ MCD_OPC_CheckField, 21, 1, 1, 209, 58, // Skip to: 25557
+/* 10500 */ MCD_OPC_Decode, 241, 12, 23, // Opcode: USUBLvvv_2d2s
+/* 10504 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10522
+/* 10508 */ MCD_OPC_CheckPredicate, 0, 197, 58, // Skip to: 25557
+/* 10512 */ MCD_OPC_CheckField, 21, 1, 1, 191, 58, // Skip to: 25557
+/* 10518 */ MCD_OPC_Decode, 136, 10, 33, // Opcode: SSUBL2vvv_2d4s
+/* 10522 */ MCD_OPC_FilterValue, 3, 183, 58, // Skip to: 25557
+/* 10526 */ MCD_OPC_CheckPredicate, 0, 179, 58, // Skip to: 25557
+/* 10530 */ MCD_OPC_CheckField, 21, 1, 1, 173, 58, // Skip to: 25557
+/* 10536 */ MCD_OPC_Decode, 238, 12, 33, // Opcode: USUBL2vvv_2d4s
+/* 10540 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 10619
+/* 10544 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10547 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10565
+/* 10551 */ MCD_OPC_CheckPredicate, 0, 154, 58, // Skip to: 25557
+/* 10555 */ MCD_OPC_CheckField, 21, 1, 1, 148, 58, // Skip to: 25557
+/* 10561 */ MCD_OPC_Decode, 176, 8, 24, // Opcode: SHSUBvvv_2S
+/* 10565 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10583
+/* 10569 */ MCD_OPC_CheckPredicate, 0, 136, 58, // Skip to: 25557
+/* 10573 */ MCD_OPC_CheckField, 21, 1, 1, 130, 58, // Skip to: 25557
+/* 10579 */ MCD_OPC_Decode, 193, 11, 24, // Opcode: UHSUBvvv_2S
+/* 10583 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10601
+/* 10587 */ MCD_OPC_CheckPredicate, 0, 118, 58, // Skip to: 25557
+/* 10591 */ MCD_OPC_CheckField, 21, 1, 1, 112, 58, // Skip to: 25557
+/* 10597 */ MCD_OPC_Decode, 178, 8, 33, // Opcode: SHSUBvvv_4S
+/* 10601 */ MCD_OPC_FilterValue, 3, 104, 58, // Skip to: 25557
+/* 10605 */ MCD_OPC_CheckPredicate, 0, 100, 58, // Skip to: 25557
+/* 10609 */ MCD_OPC_CheckField, 21, 1, 1, 94, 58, // Skip to: 25557
+/* 10615 */ MCD_OPC_Decode, 195, 11, 33, // Opcode: UHSUBvvv_4S
+/* 10619 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 10698
+/* 10623 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10626 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10644
+/* 10630 */ MCD_OPC_CheckPredicate, 0, 75, 58, // Skip to: 25557
+/* 10634 */ MCD_OPC_CheckField, 21, 1, 1, 69, 58, // Skip to: 25557
+/* 10640 */ MCD_OPC_Decode, 196, 9, 24, // Opcode: SQSUBvvv_2S
+/* 10644 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10662
+/* 10648 */ MCD_OPC_CheckPredicate, 0, 57, 58, // Skip to: 25557
+/* 10652 */ MCD_OPC_CheckField, 21, 1, 1, 51, 58, // Skip to: 25557
+/* 10658 */ MCD_OPC_Decode, 177, 12, 24, // Opcode: UQSUBvvv_2S
+/* 10662 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10680
+/* 10666 */ MCD_OPC_CheckPredicate, 0, 39, 58, // Skip to: 25557
+/* 10670 */ MCD_OPC_CheckField, 21, 1, 1, 33, 58, // Skip to: 25557
+/* 10676 */ MCD_OPC_Decode, 198, 9, 33, // Opcode: SQSUBvvv_4S
+/* 10680 */ MCD_OPC_FilterValue, 3, 25, 58, // Skip to: 25557
+/* 10684 */ MCD_OPC_CheckPredicate, 0, 21, 58, // Skip to: 25557
+/* 10688 */ MCD_OPC_CheckField, 21, 1, 1, 15, 58, // Skip to: 25557
+/* 10694 */ MCD_OPC_Decode, 179, 12, 33, // Opcode: UQSUBvvv_4S
+/* 10698 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 10777
+/* 10702 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10705 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10723
+/* 10709 */ MCD_OPC_CheckPredicate, 0, 252, 57, // Skip to: 25557
+/* 10713 */ MCD_OPC_CheckField, 21, 1, 1, 246, 57, // Skip to: 25557
+/* 10719 */ MCD_OPC_Decode, 145, 10, 25, // Opcode: SSUBWvvv_2d2s
+/* 10723 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10741
+/* 10727 */ MCD_OPC_CheckPredicate, 0, 234, 57, // Skip to: 25557
+/* 10731 */ MCD_OPC_CheckField, 21, 1, 1, 228, 57, // Skip to: 25557
+/* 10737 */ MCD_OPC_Decode, 247, 12, 25, // Opcode: USUBWvvv_2d2s
+/* 10741 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10759
+/* 10745 */ MCD_OPC_CheckPredicate, 0, 216, 57, // Skip to: 25557
+/* 10749 */ MCD_OPC_CheckField, 21, 1, 1, 210, 57, // Skip to: 25557
+/* 10755 */ MCD_OPC_Decode, 142, 10, 33, // Opcode: SSUBW2vvv_2d4s
+/* 10759 */ MCD_OPC_FilterValue, 3, 202, 57, // Skip to: 25557
+/* 10763 */ MCD_OPC_CheckPredicate, 0, 198, 57, // Skip to: 25557
+/* 10767 */ MCD_OPC_CheckField, 21, 1, 1, 192, 57, // Skip to: 25557
+/* 10773 */ MCD_OPC_Decode, 244, 12, 33, // Opcode: USUBW2vvv_2d4s
+/* 10777 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 10856
+/* 10781 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10784 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10802
+/* 10788 */ MCD_OPC_CheckPredicate, 0, 173, 57, // Skip to: 25557
+/* 10792 */ MCD_OPC_CheckField, 21, 1, 1, 167, 57, // Skip to: 25557
+/* 10798 */ MCD_OPC_Decode, 144, 2, 24, // Opcode: CMGTvvv_2S
+/* 10802 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10820
+/* 10806 */ MCD_OPC_CheckPredicate, 0, 155, 57, // Skip to: 25557
+/* 10810 */ MCD_OPC_CheckField, 21, 1, 1, 149, 57, // Skip to: 25557
+/* 10816 */ MCD_OPC_Decode, 151, 2, 24, // Opcode: CMHIvvv_2S
+/* 10820 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10838
+/* 10824 */ MCD_OPC_CheckPredicate, 0, 137, 57, // Skip to: 25557
+/* 10828 */ MCD_OPC_CheckField, 21, 1, 1, 131, 57, // Skip to: 25557
+/* 10834 */ MCD_OPC_Decode, 146, 2, 33, // Opcode: CMGTvvv_4S
+/* 10838 */ MCD_OPC_FilterValue, 3, 123, 57, // Skip to: 25557
+/* 10842 */ MCD_OPC_CheckPredicate, 0, 119, 57, // Skip to: 25557
+/* 10846 */ MCD_OPC_CheckField, 21, 1, 1, 113, 57, // Skip to: 25557
+/* 10852 */ MCD_OPC_Decode, 153, 2, 33, // Opcode: CMHIvvv_4S
+/* 10856 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 10935
+/* 10860 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10863 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10881
+/* 10867 */ MCD_OPC_CheckPredicate, 0, 94, 57, // Skip to: 25557
+/* 10871 */ MCD_OPC_CheckField, 21, 1, 1, 88, 57, // Skip to: 25557
+/* 10877 */ MCD_OPC_Decode, 130, 2, 24, // Opcode: CMGEvvv_2S
+/* 10881 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10899
+/* 10885 */ MCD_OPC_CheckPredicate, 0, 76, 57, // Skip to: 25557
+/* 10889 */ MCD_OPC_CheckField, 21, 1, 1, 70, 57, // Skip to: 25557
+/* 10895 */ MCD_OPC_Decode, 158, 2, 24, // Opcode: CMHSvvv_2S
+/* 10899 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10917
+/* 10903 */ MCD_OPC_CheckPredicate, 0, 58, 57, // Skip to: 25557
+/* 10907 */ MCD_OPC_CheckField, 21, 1, 1, 52, 57, // Skip to: 25557
+/* 10913 */ MCD_OPC_Decode, 132, 2, 33, // Opcode: CMGEvvv_4S
+/* 10917 */ MCD_OPC_FilterValue, 3, 44, 57, // Skip to: 25557
+/* 10921 */ MCD_OPC_CheckPredicate, 0, 40, 57, // Skip to: 25557
+/* 10925 */ MCD_OPC_CheckField, 21, 1, 1, 34, 57, // Skip to: 25557
+/* 10931 */ MCD_OPC_Decode, 160, 2, 33, // Opcode: CMHSvvv_4S
+/* 10935 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 11012
+/* 10939 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 10942 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 10959
+/* 10946 */ MCD_OPC_CheckPredicate, 0, 15, 57, // Skip to: 25557
+/* 10950 */ MCD_OPC_CheckField, 21, 1, 1, 9, 57, // Skip to: 25557
+/* 10956 */ MCD_OPC_Decode, 24, 29, // Opcode: ADDHNvvv_2s2d
+/* 10959 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 10977
+/* 10963 */ MCD_OPC_CheckPredicate, 0, 254, 56, // Skip to: 25557
+/* 10967 */ MCD_OPC_CheckField, 21, 1, 1, 248, 56, // Skip to: 25557
+/* 10973 */ MCD_OPC_Decode, 202, 7, 29, // Opcode: RADDHNvvv_2s2d
+/* 10977 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 10994
+/* 10981 */ MCD_OPC_CheckPredicate, 0, 236, 56, // Skip to: 25557
+/* 10985 */ MCD_OPC_CheckField, 21, 1, 1, 230, 56, // Skip to: 25557
+/* 10991 */ MCD_OPC_Decode, 22, 42, // Opcode: ADDHN2vvv_4s2d
+/* 10994 */ MCD_OPC_FilterValue, 3, 223, 56, // Skip to: 25557
+/* 10998 */ MCD_OPC_CheckPredicate, 0, 219, 56, // Skip to: 25557
+/* 11002 */ MCD_OPC_CheckField, 21, 1, 1, 213, 56, // Skip to: 25557
+/* 11008 */ MCD_OPC_Decode, 200, 7, 42, // Opcode: RADDHN2vvv_4s2d
+/* 11012 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 11091
+/* 11016 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11019 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11037
+/* 11023 */ MCD_OPC_CheckPredicate, 0, 194, 56, // Skip to: 25557
+/* 11027 */ MCD_OPC_CheckField, 21, 1, 1, 188, 56, // Skip to: 25557
+/* 11033 */ MCD_OPC_Decode, 245, 9, 24, // Opcode: SSHLvvv_2S
+/* 11037 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11055
+/* 11041 */ MCD_OPC_CheckPredicate, 0, 176, 56, // Skip to: 25557
+/* 11045 */ MCD_OPC_CheckField, 21, 1, 1, 170, 56, // Skip to: 25557
+/* 11051 */ MCD_OPC_Decode, 219, 12, 24, // Opcode: USHLvvv_2S
+/* 11055 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11073
+/* 11059 */ MCD_OPC_CheckPredicate, 0, 158, 56, // Skip to: 25557
+/* 11063 */ MCD_OPC_CheckField, 21, 1, 1, 152, 56, // Skip to: 25557
+/* 11069 */ MCD_OPC_Decode, 247, 9, 33, // Opcode: SSHLvvv_4S
+/* 11073 */ MCD_OPC_FilterValue, 3, 144, 56, // Skip to: 25557
+/* 11077 */ MCD_OPC_CheckPredicate, 0, 140, 56, // Skip to: 25557
+/* 11081 */ MCD_OPC_CheckField, 21, 1, 1, 134, 56, // Skip to: 25557
+/* 11087 */ MCD_OPC_Decode, 221, 12, 33, // Opcode: USHLvvv_4S
+/* 11091 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 11170
+/* 11095 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11098 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11116
+/* 11102 */ MCD_OPC_CheckPredicate, 0, 115, 56, // Skip to: 25557
+/* 11106 */ MCD_OPC_CheckField, 21, 1, 1, 109, 56, // Skip to: 25557
+/* 11112 */ MCD_OPC_Decode, 179, 9, 24, // Opcode: SQSHLvvv_2S
+/* 11116 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11134
+/* 11120 */ MCD_OPC_CheckPredicate, 0, 97, 56, // Skip to: 25557
+/* 11124 */ MCD_OPC_CheckField, 21, 1, 1, 91, 56, // Skip to: 25557
+/* 11130 */ MCD_OPC_Decode, 160, 12, 24, // Opcode: UQSHLvvv_2S
+/* 11134 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11152
+/* 11138 */ MCD_OPC_CheckPredicate, 0, 79, 56, // Skip to: 25557
+/* 11142 */ MCD_OPC_CheckField, 21, 1, 1, 73, 56, // Skip to: 25557
+/* 11148 */ MCD_OPC_Decode, 181, 9, 33, // Opcode: SQSHLvvv_4S
+/* 11152 */ MCD_OPC_FilterValue, 3, 65, 56, // Skip to: 25557
+/* 11156 */ MCD_OPC_CheckPredicate, 0, 61, 56, // Skip to: 25557
+/* 11160 */ MCD_OPC_CheckField, 21, 1, 1, 55, 56, // Skip to: 25557
+/* 11166 */ MCD_OPC_Decode, 162, 12, 33, // Opcode: UQSHLvvv_4S
+/* 11170 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 11249
+/* 11174 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11177 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11195
+/* 11181 */ MCD_OPC_CheckPredicate, 0, 36, 56, // Skip to: 25557
+/* 11185 */ MCD_OPC_CheckField, 21, 1, 1, 30, 56, // Skip to: 25557
+/* 11191 */ MCD_OPC_Decode, 231, 7, 30, // Opcode: SABALvvv_2d2s
+/* 11195 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11213
+/* 11199 */ MCD_OPC_CheckPredicate, 0, 18, 56, // Skip to: 25557
+/* 11203 */ MCD_OPC_CheckField, 21, 1, 1, 12, 56, // Skip to: 25557
+/* 11209 */ MCD_OPC_Decode, 137, 11, 30, // Opcode: UABALvvv_2d2s
+/* 11213 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11231
+/* 11217 */ MCD_OPC_CheckPredicate, 0, 0, 56, // Skip to: 25557
+/* 11221 */ MCD_OPC_CheckField, 21, 1, 1, 250, 55, // Skip to: 25557
+/* 11227 */ MCD_OPC_Decode, 228, 7, 42, // Opcode: SABAL2vvv_2d2s
+/* 11231 */ MCD_OPC_FilterValue, 3, 242, 55, // Skip to: 25557
+/* 11235 */ MCD_OPC_CheckPredicate, 0, 238, 55, // Skip to: 25557
+/* 11239 */ MCD_OPC_CheckField, 21, 1, 1, 232, 55, // Skip to: 25557
+/* 11245 */ MCD_OPC_Decode, 134, 11, 42, // Opcode: UABAL2vvv_2d2s
+/* 11249 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 11328
+/* 11253 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11256 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11274
+/* 11260 */ MCD_OPC_CheckPredicate, 0, 213, 55, // Skip to: 25557
+/* 11264 */ MCD_OPC_CheckField, 21, 1, 1, 207, 55, // Skip to: 25557
+/* 11270 */ MCD_OPC_Decode, 217, 9, 24, // Opcode: SRSHLvvv_2S
+/* 11274 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11292
+/* 11278 */ MCD_OPC_CheckPredicate, 0, 195, 55, // Skip to: 25557
+/* 11282 */ MCD_OPC_CheckField, 21, 1, 1, 189, 55, // Skip to: 25557
+/* 11288 */ MCD_OPC_Decode, 191, 12, 24, // Opcode: URSHLvvv_2S
+/* 11292 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11310
+/* 11296 */ MCD_OPC_CheckPredicate, 0, 177, 55, // Skip to: 25557
+/* 11300 */ MCD_OPC_CheckField, 21, 1, 1, 171, 55, // Skip to: 25557
+/* 11306 */ MCD_OPC_Decode, 219, 9, 33, // Opcode: SRSHLvvv_4S
+/* 11310 */ MCD_OPC_FilterValue, 3, 163, 55, // Skip to: 25557
+/* 11314 */ MCD_OPC_CheckPredicate, 0, 159, 55, // Skip to: 25557
+/* 11318 */ MCD_OPC_CheckField, 21, 1, 1, 153, 55, // Skip to: 25557
+/* 11324 */ MCD_OPC_Decode, 193, 12, 33, // Opcode: URSHLvvv_4S
+/* 11328 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 11407
+/* 11332 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11335 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11353
+/* 11339 */ MCD_OPC_CheckPredicate, 0, 134, 55, // Skip to: 25557
+/* 11343 */ MCD_OPC_CheckField, 21, 1, 1, 128, 55, // Skip to: 25557
+/* 11349 */ MCD_OPC_Decode, 148, 9, 24, // Opcode: SQRSHLvvv_2S
+/* 11353 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11371
+/* 11357 */ MCD_OPC_CheckPredicate, 0, 116, 55, // Skip to: 25557
+/* 11361 */ MCD_OPC_CheckField, 21, 1, 1, 110, 55, // Skip to: 25557
+/* 11367 */ MCD_OPC_Decode, 136, 12, 24, // Opcode: UQRSHLvvv_2S
+/* 11371 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11389
+/* 11375 */ MCD_OPC_CheckPredicate, 0, 98, 55, // Skip to: 25557
+/* 11379 */ MCD_OPC_CheckField, 21, 1, 1, 92, 55, // Skip to: 25557
+/* 11385 */ MCD_OPC_Decode, 150, 9, 33, // Opcode: SQRSHLvvv_4S
+/* 11389 */ MCD_OPC_FilterValue, 3, 84, 55, // Skip to: 25557
+/* 11393 */ MCD_OPC_CheckPredicate, 0, 80, 55, // Skip to: 25557
+/* 11397 */ MCD_OPC_CheckField, 21, 1, 1, 74, 55, // Skip to: 25557
+/* 11403 */ MCD_OPC_Decode, 138, 12, 33, // Opcode: UQRSHLvvv_4S
+/* 11407 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 11486
+/* 11411 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11414 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11432
+/* 11418 */ MCD_OPC_CheckPredicate, 0, 55, 55, // Skip to: 25557
+/* 11422 */ MCD_OPC_CheckField, 21, 1, 1, 49, 55, // Skip to: 25557
+/* 11428 */ MCD_OPC_Decode, 167, 10, 29, // Opcode: SUBHNvvv_2s2d
+/* 11432 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11450
+/* 11436 */ MCD_OPC_CheckPredicate, 0, 37, 55, // Skip to: 25557
+/* 11440 */ MCD_OPC_CheckField, 21, 1, 1, 31, 55, // Skip to: 25557
+/* 11446 */ MCD_OPC_Decode, 225, 7, 29, // Opcode: RSUBHNvvv_2s2d
+/* 11450 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11468
+/* 11454 */ MCD_OPC_CheckPredicate, 0, 19, 55, // Skip to: 25557
+/* 11458 */ MCD_OPC_CheckField, 21, 1, 1, 13, 55, // Skip to: 25557
+/* 11464 */ MCD_OPC_Decode, 165, 10, 42, // Opcode: SUBHN2vvv_4s2d
+/* 11468 */ MCD_OPC_FilterValue, 3, 5, 55, // Skip to: 25557
+/* 11472 */ MCD_OPC_CheckPredicate, 0, 1, 55, // Skip to: 25557
+/* 11476 */ MCD_OPC_CheckField, 21, 1, 1, 251, 54, // Skip to: 25557
+/* 11482 */ MCD_OPC_Decode, 223, 7, 42, // Opcode: RSUBHN2vvv_4s2d
+/* 11486 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 11565
+/* 11490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11493 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11511
+/* 11497 */ MCD_OPC_CheckPredicate, 0, 232, 54, // Skip to: 25557
+/* 11501 */ MCD_OPC_CheckField, 21, 1, 1, 226, 54, // Skip to: 25557
+/* 11507 */ MCD_OPC_Decode, 196, 8, 24, // Opcode: SMAXvvv_2S
+/* 11511 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11529
+/* 11515 */ MCD_OPC_CheckPredicate, 0, 214, 54, // Skip to: 25557
+/* 11519 */ MCD_OPC_CheckField, 21, 1, 1, 208, 54, // Skip to: 25557
+/* 11525 */ MCD_OPC_Decode, 206, 11, 24, // Opcode: UMAXvvv_2S
+/* 11529 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11547
+/* 11533 */ MCD_OPC_CheckPredicate, 0, 196, 54, // Skip to: 25557
+/* 11537 */ MCD_OPC_CheckField, 21, 1, 1, 190, 54, // Skip to: 25557
+/* 11543 */ MCD_OPC_Decode, 198, 8, 33, // Opcode: SMAXvvv_4S
+/* 11547 */ MCD_OPC_FilterValue, 3, 182, 54, // Skip to: 25557
+/* 11551 */ MCD_OPC_CheckPredicate, 0, 178, 54, // Skip to: 25557
+/* 11555 */ MCD_OPC_CheckField, 21, 1, 1, 172, 54, // Skip to: 25557
+/* 11561 */ MCD_OPC_Decode, 208, 11, 33, // Opcode: UMAXvvv_4S
+/* 11565 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 11644
+/* 11569 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11572 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11590
+/* 11576 */ MCD_OPC_CheckPredicate, 0, 153, 54, // Skip to: 25557
+/* 11580 */ MCD_OPC_CheckField, 21, 1, 1, 147, 54, // Skip to: 25557
+/* 11586 */ MCD_OPC_Decode, 209, 8, 24, // Opcode: SMINvvv_2S
+/* 11590 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11608
+/* 11594 */ MCD_OPC_CheckPredicate, 0, 135, 54, // Skip to: 25557
+/* 11598 */ MCD_OPC_CheckField, 21, 1, 1, 129, 54, // Skip to: 25557
+/* 11604 */ MCD_OPC_Decode, 218, 11, 24, // Opcode: UMINvvv_2S
+/* 11608 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11626
+/* 11612 */ MCD_OPC_CheckPredicate, 0, 117, 54, // Skip to: 25557
+/* 11616 */ MCD_OPC_CheckField, 21, 1, 1, 111, 54, // Skip to: 25557
+/* 11622 */ MCD_OPC_Decode, 211, 8, 33, // Opcode: SMINvvv_4S
+/* 11626 */ MCD_OPC_FilterValue, 3, 103, 54, // Skip to: 25557
+/* 11630 */ MCD_OPC_CheckPredicate, 0, 99, 54, // Skip to: 25557
+/* 11634 */ MCD_OPC_CheckField, 21, 1, 1, 93, 54, // Skip to: 25557
+/* 11640 */ MCD_OPC_Decode, 220, 11, 33, // Opcode: UMINvvv_4S
+/* 11644 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 11723
+/* 11648 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11651 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11669
+/* 11655 */ MCD_OPC_CheckPredicate, 0, 74, 54, // Skip to: 25557
+/* 11659 */ MCD_OPC_CheckField, 21, 1, 1, 68, 54, // Skip to: 25557
+/* 11665 */ MCD_OPC_Decode, 243, 7, 23, // Opcode: SABDLvvv_2d2s
+/* 11669 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11687
+/* 11673 */ MCD_OPC_CheckPredicate, 0, 56, 54, // Skip to: 25557
+/* 11677 */ MCD_OPC_CheckField, 21, 1, 1, 50, 54, // Skip to: 25557
+/* 11683 */ MCD_OPC_Decode, 149, 11, 23, // Opcode: UABDLvvv_2d2s
+/* 11687 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11705
+/* 11691 */ MCD_OPC_CheckPredicate, 0, 38, 54, // Skip to: 25557
+/* 11695 */ MCD_OPC_CheckField, 21, 1, 1, 32, 54, // Skip to: 25557
+/* 11701 */ MCD_OPC_Decode, 240, 7, 33, // Opcode: SABDL2vvv_2d2s
+/* 11705 */ MCD_OPC_FilterValue, 3, 24, 54, // Skip to: 25557
+/* 11709 */ MCD_OPC_CheckPredicate, 0, 20, 54, // Skip to: 25557
+/* 11713 */ MCD_OPC_CheckField, 21, 1, 1, 14, 54, // Skip to: 25557
+/* 11719 */ MCD_OPC_Decode, 146, 11, 33, // Opcode: UABDL2vvv_2d2s
+/* 11723 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 11802
+/* 11727 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11730 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11748
+/* 11734 */ MCD_OPC_CheckPredicate, 0, 251, 53, // Skip to: 25557
+/* 11738 */ MCD_OPC_CheckField, 21, 1, 1, 245, 53, // Skip to: 25557
+/* 11744 */ MCD_OPC_Decode, 247, 7, 24, // Opcode: SABDvvv_2S
+/* 11748 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11766
+/* 11752 */ MCD_OPC_CheckPredicate, 0, 233, 53, // Skip to: 25557
+/* 11756 */ MCD_OPC_CheckField, 21, 1, 1, 227, 53, // Skip to: 25557
+/* 11762 */ MCD_OPC_Decode, 153, 11, 24, // Opcode: UABDvvv_2S
+/* 11766 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11784
+/* 11770 */ MCD_OPC_CheckPredicate, 0, 215, 53, // Skip to: 25557
+/* 11774 */ MCD_OPC_CheckField, 21, 1, 1, 209, 53, // Skip to: 25557
+/* 11780 */ MCD_OPC_Decode, 249, 7, 33, // Opcode: SABDvvv_4S
+/* 11784 */ MCD_OPC_FilterValue, 3, 201, 53, // Skip to: 25557
+/* 11788 */ MCD_OPC_CheckPredicate, 0, 197, 53, // Skip to: 25557
+/* 11792 */ MCD_OPC_CheckField, 21, 1, 1, 191, 53, // Skip to: 25557
+/* 11798 */ MCD_OPC_Decode, 155, 11, 33, // Opcode: UABDvvv_4S
+/* 11802 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 11881
+/* 11806 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11809 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11827
+/* 11813 */ MCD_OPC_CheckPredicate, 0, 172, 53, // Skip to: 25557
+/* 11817 */ MCD_OPC_CheckField, 21, 1, 1, 166, 53, // Skip to: 25557
+/* 11823 */ MCD_OPC_Decode, 235, 7, 31, // Opcode: SABAvvv_2S
+/* 11827 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11845
+/* 11831 */ MCD_OPC_CheckPredicate, 0, 154, 53, // Skip to: 25557
+/* 11835 */ MCD_OPC_CheckField, 21, 1, 1, 148, 53, // Skip to: 25557
+/* 11841 */ MCD_OPC_Decode, 141, 11, 31, // Opcode: UABAvvv_2S
+/* 11845 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11863
+/* 11849 */ MCD_OPC_CheckPredicate, 0, 136, 53, // Skip to: 25557
+/* 11853 */ MCD_OPC_CheckField, 21, 1, 1, 130, 53, // Skip to: 25557
+/* 11859 */ MCD_OPC_Decode, 237, 7, 42, // Opcode: SABAvvv_4S
+/* 11863 */ MCD_OPC_FilterValue, 3, 122, 53, // Skip to: 25557
+/* 11867 */ MCD_OPC_CheckPredicate, 0, 118, 53, // Skip to: 25557
+/* 11871 */ MCD_OPC_CheckField, 21, 1, 1, 112, 53, // Skip to: 25557
+/* 11877 */ MCD_OPC_Decode, 143, 11, 42, // Opcode: UABAvvv_4S
+/* 11881 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 11960
+/* 11885 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11888 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 11906
+/* 11892 */ MCD_OPC_CheckPredicate, 0, 93, 53, // Skip to: 25557
+/* 11896 */ MCD_OPC_CheckField, 21, 1, 1, 87, 53, // Skip to: 25557
+/* 11902 */ MCD_OPC_Decode, 217, 8, 30, // Opcode: SMLALvvv_2d2s
+/* 11906 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11924
+/* 11910 */ MCD_OPC_CheckPredicate, 0, 75, 53, // Skip to: 25557
+/* 11914 */ MCD_OPC_CheckField, 21, 1, 1, 69, 53, // Skip to: 25557
+/* 11920 */ MCD_OPC_Decode, 226, 11, 30, // Opcode: UMLALvvv_2d2s
+/* 11924 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 11942
+/* 11928 */ MCD_OPC_CheckPredicate, 0, 57, 53, // Skip to: 25557
+/* 11932 */ MCD_OPC_CheckField, 21, 1, 1, 51, 53, // Skip to: 25557
+/* 11938 */ MCD_OPC_Decode, 214, 8, 42, // Opcode: SMLAL2vvv_2d4s
+/* 11942 */ MCD_OPC_FilterValue, 3, 43, 53, // Skip to: 25557
+/* 11946 */ MCD_OPC_CheckPredicate, 0, 39, 53, // Skip to: 25557
+/* 11950 */ MCD_OPC_CheckField, 21, 1, 1, 33, 53, // Skip to: 25557
+/* 11956 */ MCD_OPC_Decode, 223, 11, 42, // Opcode: UMLAL2vvv_2d4s
+/* 11960 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 12037
+/* 11964 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 11967 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 11984
+/* 11971 */ MCD_OPC_CheckPredicate, 0, 14, 53, // Skip to: 25557
+/* 11975 */ MCD_OPC_CheckField, 21, 1, 1, 8, 53, // Skip to: 25557
+/* 11981 */ MCD_OPC_Decode, 60, 24, // Opcode: ADDvvv_2S
+/* 11984 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12002
+/* 11988 */ MCD_OPC_CheckPredicate, 0, 253, 52, // Skip to: 25557
+/* 11992 */ MCD_OPC_CheckField, 21, 1, 1, 247, 52, // Skip to: 25557
+/* 11998 */ MCD_OPC_Decode, 195, 10, 24, // Opcode: SUBvvv_2S
+/* 12002 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 12019
+/* 12006 */ MCD_OPC_CheckPredicate, 0, 235, 52, // Skip to: 25557
+/* 12010 */ MCD_OPC_CheckField, 21, 1, 1, 229, 52, // Skip to: 25557
+/* 12016 */ MCD_OPC_Decode, 62, 33, // Opcode: ADDvvv_4S
+/* 12019 */ MCD_OPC_FilterValue, 3, 222, 52, // Skip to: 25557
+/* 12023 */ MCD_OPC_CheckPredicate, 0, 218, 52, // Skip to: 25557
+/* 12027 */ MCD_OPC_CheckField, 21, 1, 1, 212, 52, // Skip to: 25557
+/* 12033 */ MCD_OPC_Decode, 197, 10, 33, // Opcode: SUBvvv_4S
+/* 12037 */ MCD_OPC_FilterValue, 34, 75, 0, // Skip to: 12116
+/* 12041 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12044 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12062
+/* 12048 */ MCD_OPC_CheckPredicate, 0, 193, 52, // Skip to: 25557
+/* 12052 */ MCD_OPC_CheckField, 16, 6, 32, 187, 52, // Skip to: 25557
+/* 12058 */ MCD_OPC_Decode, 137, 2, 32, // Opcode: CMGTvvi_2S
+/* 12062 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12080
+/* 12066 */ MCD_OPC_CheckPredicate, 0, 175, 52, // Skip to: 25557
+/* 12070 */ MCD_OPC_CheckField, 16, 6, 32, 169, 52, // Skip to: 25557
+/* 12076 */ MCD_OPC_Decode, 251, 1, 32, // Opcode: CMGEvvi_2S
+/* 12080 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12098
+/* 12084 */ MCD_OPC_CheckPredicate, 0, 157, 52, // Skip to: 25557
+/* 12088 */ MCD_OPC_CheckField, 16, 6, 32, 151, 52, // Skip to: 25557
+/* 12094 */ MCD_OPC_Decode, 139, 2, 43, // Opcode: CMGTvvi_4S
+/* 12098 */ MCD_OPC_FilterValue, 3, 143, 52, // Skip to: 25557
+/* 12102 */ MCD_OPC_CheckPredicate, 0, 139, 52, // Skip to: 25557
+/* 12106 */ MCD_OPC_CheckField, 16, 6, 32, 133, 52, // Skip to: 25557
+/* 12112 */ MCD_OPC_Decode, 253, 1, 43, // Opcode: CMGEvvi_4S
+/* 12116 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 12195
+/* 12120 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12123 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12141
+/* 12127 */ MCD_OPC_CheckPredicate, 0, 114, 52, // Skip to: 25557
+/* 12131 */ MCD_OPC_CheckField, 21, 1, 1, 108, 52, // Skip to: 25557
+/* 12137 */ MCD_OPC_Decode, 223, 2, 24, // Opcode: CMTSTvvv_2S
+/* 12141 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12159
+/* 12145 */ MCD_OPC_CheckPredicate, 0, 96, 52, // Skip to: 25557
+/* 12149 */ MCD_OPC_CheckField, 21, 1, 1, 90, 52, // Skip to: 25557
+/* 12155 */ MCD_OPC_Decode, 244, 1, 24, // Opcode: CMEQvvv_2S
+/* 12159 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12177
+/* 12163 */ MCD_OPC_CheckPredicate, 0, 78, 52, // Skip to: 25557
+/* 12167 */ MCD_OPC_CheckField, 21, 1, 1, 72, 52, // Skip to: 25557
+/* 12173 */ MCD_OPC_Decode, 225, 2, 33, // Opcode: CMTSTvvv_4S
+/* 12177 */ MCD_OPC_FilterValue, 3, 64, 52, // Skip to: 25557
+/* 12181 */ MCD_OPC_CheckPredicate, 0, 60, 52, // Skip to: 25557
+/* 12185 */ MCD_OPC_CheckField, 21, 1, 1, 54, 52, // Skip to: 25557
+/* 12191 */ MCD_OPC_Decode, 246, 1, 33, // Opcode: CMEQvvv_4S
+/* 12195 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 12238
+/* 12199 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12202 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12220
+/* 12206 */ MCD_OPC_CheckPredicate, 0, 35, 52, // Skip to: 25557
+/* 12210 */ MCD_OPC_CheckField, 21, 1, 1, 29, 52, // Skip to: 25557
+/* 12216 */ MCD_OPC_Decode, 252, 8, 30, // Opcode: SQDMLALvvv_2d2s
+/* 12220 */ MCD_OPC_FilterValue, 2, 21, 52, // Skip to: 25557
+/* 12224 */ MCD_OPC_CheckPredicate, 0, 17, 52, // Skip to: 25557
+/* 12228 */ MCD_OPC_CheckField, 21, 1, 1, 11, 52, // Skip to: 25557
+/* 12234 */ MCD_OPC_Decode, 250, 8, 42, // Opcode: SQDMLAL2vvv_2d4s
+/* 12238 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 12317
+/* 12242 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12245 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12263
+/* 12249 */ MCD_OPC_CheckPredicate, 0, 248, 51, // Skip to: 25557
+/* 12253 */ MCD_OPC_CheckField, 21, 1, 1, 242, 51, // Skip to: 25557
+/* 12259 */ MCD_OPC_Decode, 228, 6, 31, // Opcode: MLAvvv_2S
+/* 12263 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12281
+/* 12267 */ MCD_OPC_CheckPredicate, 0, 230, 51, // Skip to: 25557
+/* 12271 */ MCD_OPC_CheckField, 21, 1, 1, 224, 51, // Skip to: 25557
+/* 12277 */ MCD_OPC_Decode, 234, 6, 31, // Opcode: MLSvvv_2S
+/* 12281 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12299
+/* 12285 */ MCD_OPC_CheckPredicate, 0, 212, 51, // Skip to: 25557
+/* 12289 */ MCD_OPC_CheckField, 21, 1, 1, 206, 51, // Skip to: 25557
+/* 12295 */ MCD_OPC_Decode, 230, 6, 42, // Opcode: MLAvvv_4S
+/* 12299 */ MCD_OPC_FilterValue, 3, 198, 51, // Skip to: 25557
+/* 12303 */ MCD_OPC_CheckPredicate, 0, 194, 51, // Skip to: 25557
+/* 12307 */ MCD_OPC_CheckField, 21, 1, 1, 188, 51, // Skip to: 25557
+/* 12313 */ MCD_OPC_Decode, 236, 6, 42, // Opcode: MLSvvv_4S
+/* 12317 */ MCD_OPC_FilterValue, 38, 75, 0, // Skip to: 12396
+/* 12321 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12324 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12342
+/* 12328 */ MCD_OPC_CheckPredicate, 0, 169, 51, // Skip to: 25557
+/* 12332 */ MCD_OPC_CheckField, 16, 6, 32, 163, 51, // Skip to: 25557
+/* 12338 */ MCD_OPC_Decode, 237, 1, 32, // Opcode: CMEQvvi_2S
+/* 12342 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12360
+/* 12346 */ MCD_OPC_CheckPredicate, 0, 151, 51, // Skip to: 25557
+/* 12350 */ MCD_OPC_CheckField, 16, 6, 32, 145, 51, // Skip to: 25557
+/* 12356 */ MCD_OPC_Decode, 165, 2, 32, // Opcode: CMLEvvi_2S
+/* 12360 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12378
+/* 12364 */ MCD_OPC_CheckPredicate, 0, 133, 51, // Skip to: 25557
+/* 12368 */ MCD_OPC_CheckField, 16, 6, 32, 127, 51, // Skip to: 25557
+/* 12374 */ MCD_OPC_Decode, 239, 1, 43, // Opcode: CMEQvvi_4S
+/* 12378 */ MCD_OPC_FilterValue, 3, 119, 51, // Skip to: 25557
+/* 12382 */ MCD_OPC_CheckPredicate, 0, 115, 51, // Skip to: 25557
+/* 12386 */ MCD_OPC_CheckField, 16, 6, 32, 109, 51, // Skip to: 25557
+/* 12392 */ MCD_OPC_Decode, 167, 2, 43, // Opcode: CMLEvvi_4S
+/* 12396 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 12439
+/* 12400 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12403 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12421
+/* 12407 */ MCD_OPC_CheckPredicate, 0, 90, 51, // Skip to: 25557
+/* 12411 */ MCD_OPC_CheckField, 21, 1, 1, 84, 51, // Skip to: 25557
+/* 12417 */ MCD_OPC_Decode, 133, 7, 24, // Opcode: MULvvv_2S
+/* 12421 */ MCD_OPC_FilterValue, 2, 76, 51, // Skip to: 25557
+/* 12425 */ MCD_OPC_CheckPredicate, 0, 72, 51, // Skip to: 25557
+/* 12429 */ MCD_OPC_CheckField, 21, 1, 1, 66, 51, // Skip to: 25557
+/* 12435 */ MCD_OPC_Decode, 135, 7, 33, // Opcode: MULvvv_4S
+/* 12439 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 12518
+/* 12443 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12446 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12464
+/* 12450 */ MCD_OPC_CheckPredicate, 0, 47, 51, // Skip to: 25557
+/* 12454 */ MCD_OPC_CheckField, 21, 1, 1, 41, 51, // Skip to: 25557
+/* 12460 */ MCD_OPC_Decode, 223, 8, 30, // Opcode: SMLSLvvv_2d2s
+/* 12464 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12482
+/* 12468 */ MCD_OPC_CheckPredicate, 0, 29, 51, // Skip to: 25557
+/* 12472 */ MCD_OPC_CheckField, 21, 1, 1, 23, 51, // Skip to: 25557
+/* 12478 */ MCD_OPC_Decode, 232, 11, 30, // Opcode: UMLSLvvv_2d2s
+/* 12482 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12500
+/* 12486 */ MCD_OPC_CheckPredicate, 0, 11, 51, // Skip to: 25557
+/* 12490 */ MCD_OPC_CheckField, 21, 1, 1, 5, 51, // Skip to: 25557
+/* 12496 */ MCD_OPC_Decode, 220, 8, 42, // Opcode: SMLSL2vvv_2d4s
+/* 12500 */ MCD_OPC_FilterValue, 3, 253, 50, // Skip to: 25557
+/* 12504 */ MCD_OPC_CheckPredicate, 0, 249, 50, // Skip to: 25557
+/* 12508 */ MCD_OPC_CheckField, 21, 1, 1, 243, 50, // Skip to: 25557
+/* 12514 */ MCD_OPC_Decode, 229, 11, 42, // Opcode: UMLSL2vvv_2d4s
+/* 12518 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 12597
+/* 12522 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12525 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12543
+/* 12529 */ MCD_OPC_CheckPredicate, 0, 224, 50, // Skip to: 25557
+/* 12533 */ MCD_OPC_CheckField, 21, 1, 1, 218, 50, // Skip to: 25557
+/* 12539 */ MCD_OPC_Decode, 190, 8, 24, // Opcode: SMAXPvvv_2S
+/* 12543 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12561
+/* 12547 */ MCD_OPC_CheckPredicate, 0, 206, 50, // Skip to: 25557
+/* 12551 */ MCD_OPC_CheckField, 21, 1, 1, 200, 50, // Skip to: 25557
+/* 12557 */ MCD_OPC_Decode, 200, 11, 24, // Opcode: UMAXPvvv_2S
+/* 12561 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12579
+/* 12565 */ MCD_OPC_CheckPredicate, 0, 188, 50, // Skip to: 25557
+/* 12569 */ MCD_OPC_CheckField, 21, 1, 1, 182, 50, // Skip to: 25557
+/* 12575 */ MCD_OPC_Decode, 192, 8, 33, // Opcode: SMAXPvvv_4S
+/* 12579 */ MCD_OPC_FilterValue, 3, 174, 50, // Skip to: 25557
+/* 12583 */ MCD_OPC_CheckPredicate, 0, 170, 50, // Skip to: 25557
+/* 12587 */ MCD_OPC_CheckField, 21, 1, 1, 164, 50, // Skip to: 25557
+/* 12593 */ MCD_OPC_Decode, 202, 11, 33, // Opcode: UMAXPvvv_4S
+/* 12597 */ MCD_OPC_FilterValue, 42, 39, 0, // Skip to: 12640
+/* 12601 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12604 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12622
+/* 12608 */ MCD_OPC_CheckPredicate, 0, 145, 50, // Skip to: 25557
+/* 12612 */ MCD_OPC_CheckField, 16, 6, 32, 139, 50, // Skip to: 25557
+/* 12618 */ MCD_OPC_Decode, 172, 2, 32, // Opcode: CMLTvvi_2S
+/* 12622 */ MCD_OPC_FilterValue, 2, 131, 50, // Skip to: 25557
+/* 12626 */ MCD_OPC_CheckPredicate, 0, 127, 50, // Skip to: 25557
+/* 12630 */ MCD_OPC_CheckField, 16, 6, 32, 121, 50, // Skip to: 25557
+/* 12636 */ MCD_OPC_Decode, 174, 2, 43, // Opcode: CMLTvvi_4S
+/* 12640 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 12719
+/* 12644 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12647 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12665
+/* 12651 */ MCD_OPC_CheckPredicate, 0, 102, 50, // Skip to: 25557
+/* 12655 */ MCD_OPC_CheckField, 21, 1, 1, 96, 50, // Skip to: 25557
+/* 12661 */ MCD_OPC_Decode, 203, 8, 24, // Opcode: SMINPvvv_2S
+/* 12665 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12683
+/* 12669 */ MCD_OPC_CheckPredicate, 0, 84, 50, // Skip to: 25557
+/* 12673 */ MCD_OPC_CheckField, 21, 1, 1, 78, 50, // Skip to: 25557
+/* 12679 */ MCD_OPC_Decode, 212, 11, 24, // Opcode: UMINPvvv_2S
+/* 12683 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12701
+/* 12687 */ MCD_OPC_CheckPredicate, 0, 66, 50, // Skip to: 25557
+/* 12691 */ MCD_OPC_CheckField, 21, 1, 1, 60, 50, // Skip to: 25557
+/* 12697 */ MCD_OPC_Decode, 205, 8, 33, // Opcode: SMINPvvv_4S
+/* 12701 */ MCD_OPC_FilterValue, 3, 52, 50, // Skip to: 25557
+/* 12705 */ MCD_OPC_CheckPredicate, 0, 48, 50, // Skip to: 25557
+/* 12709 */ MCD_OPC_CheckField, 21, 1, 1, 42, 50, // Skip to: 25557
+/* 12715 */ MCD_OPC_Decode, 214, 11, 33, // Opcode: UMINPvvv_4S
+/* 12719 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 12762
+/* 12723 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12726 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12744
+/* 12730 */ MCD_OPC_CheckPredicate, 0, 23, 50, // Skip to: 25557
+/* 12734 */ MCD_OPC_CheckField, 21, 1, 1, 17, 50, // Skip to: 25557
+/* 12740 */ MCD_OPC_Decode, 128, 9, 30, // Opcode: SQDMLSLvvv_2d2s
+/* 12744 */ MCD_OPC_FilterValue, 2, 9, 50, // Skip to: 25557
+/* 12748 */ MCD_OPC_CheckPredicate, 0, 5, 50, // Skip to: 25557
+/* 12752 */ MCD_OPC_CheckField, 21, 1, 1, 255, 49, // Skip to: 25557
+/* 12758 */ MCD_OPC_Decode, 254, 8, 42, // Opcode: SQDMLSL2vvv_2d4s
+/* 12762 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 12841
+/* 12766 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12769 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12787
+/* 12773 */ MCD_OPC_CheckPredicate, 0, 236, 49, // Skip to: 25557
+/* 12777 */ MCD_OPC_CheckField, 21, 1, 1, 230, 49, // Skip to: 25557
+/* 12783 */ MCD_OPC_Decode, 130, 9, 24, // Opcode: SQDMULHvvv_2S
+/* 12787 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12805
+/* 12791 */ MCD_OPC_CheckPredicate, 0, 218, 49, // Skip to: 25557
+/* 12795 */ MCD_OPC_CheckField, 21, 1, 1, 212, 49, // Skip to: 25557
+/* 12801 */ MCD_OPC_Decode, 138, 9, 24, // Opcode: SQRDMULHvvv_2S
+/* 12805 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12823
+/* 12809 */ MCD_OPC_CheckPredicate, 0, 200, 49, // Skip to: 25557
+/* 12813 */ MCD_OPC_CheckField, 21, 1, 1, 194, 49, // Skip to: 25557
+/* 12819 */ MCD_OPC_Decode, 132, 9, 33, // Opcode: SQDMULHvvv_4S
+/* 12823 */ MCD_OPC_FilterValue, 3, 186, 49, // Skip to: 25557
+/* 12827 */ MCD_OPC_CheckPredicate, 0, 182, 49, // Skip to: 25557
+/* 12831 */ MCD_OPC_CheckField, 21, 1, 1, 176, 49, // Skip to: 25557
+/* 12837 */ MCD_OPC_Decode, 140, 9, 33, // Opcode: SQRDMULHvvv_4S
+/* 12841 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 12882
+/* 12845 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12848 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 12865
+/* 12852 */ MCD_OPC_CheckPredicate, 0, 157, 49, // Skip to: 25557
+/* 12856 */ MCD_OPC_CheckField, 21, 1, 1, 151, 49, // Skip to: 25557
+/* 12862 */ MCD_OPC_Decode, 29, 24, // Opcode: ADDP_2S
+/* 12865 */ MCD_OPC_FilterValue, 2, 144, 49, // Skip to: 25557
+/* 12869 */ MCD_OPC_CheckPredicate, 0, 140, 49, // Skip to: 25557
+/* 12873 */ MCD_OPC_CheckField, 21, 1, 1, 134, 49, // Skip to: 25557
+/* 12879 */ MCD_OPC_Decode, 31, 33, // Opcode: ADDP_4S
+/* 12882 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 12961
+/* 12886 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12889 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12907
+/* 12893 */ MCD_OPC_CheckPredicate, 0, 116, 49, // Skip to: 25557
+/* 12897 */ MCD_OPC_CheckField, 21, 1, 1, 110, 49, // Skip to: 25557
+/* 12903 */ MCD_OPC_Decode, 236, 8, 23, // Opcode: SMULLvvv_2d2s
+/* 12907 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12925
+/* 12911 */ MCD_OPC_CheckPredicate, 0, 98, 49, // Skip to: 25557
+/* 12915 */ MCD_OPC_CheckField, 21, 1, 1, 92, 49, // Skip to: 25557
+/* 12921 */ MCD_OPC_Decode, 244, 11, 23, // Opcode: UMULLvvv_2d2s
+/* 12925 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12943
+/* 12929 */ MCD_OPC_CheckPredicate, 0, 80, 49, // Skip to: 25557
+/* 12933 */ MCD_OPC_CheckField, 21, 1, 1, 74, 49, // Skip to: 25557
+/* 12939 */ MCD_OPC_Decode, 233, 8, 33, // Opcode: SMULL2vvv_2d4s
+/* 12943 */ MCD_OPC_FilterValue, 3, 66, 49, // Skip to: 25557
+/* 12947 */ MCD_OPC_CheckPredicate, 0, 62, 49, // Skip to: 25557
+/* 12951 */ MCD_OPC_CheckField, 21, 1, 1, 56, 49, // Skip to: 25557
+/* 12957 */ MCD_OPC_Decode, 241, 11, 33, // Opcode: UMULL2vvv_2d4s
+/* 12961 */ MCD_OPC_FilterValue, 49, 75, 0, // Skip to: 13040
+/* 12965 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 12968 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12986
+/* 12972 */ MCD_OPC_CheckPredicate, 0, 37, 49, // Skip to: 25557
+/* 12976 */ MCD_OPC_CheckField, 21, 1, 1, 31, 49, // Skip to: 25557
+/* 12982 */ MCD_OPC_Decode, 167, 4, 24, // Opcode: FMINNMvvv_2S
+/* 12986 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13004
+/* 12990 */ MCD_OPC_CheckPredicate, 0, 19, 49, // Skip to: 25557
+/* 12994 */ MCD_OPC_CheckField, 21, 1, 1, 13, 49, // Skip to: 25557
+/* 13000 */ MCD_OPC_Decode, 162, 4, 24, // Opcode: FMINNMPvvv_2S
+/* 13004 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13022
+/* 13008 */ MCD_OPC_CheckPredicate, 0, 1, 49, // Skip to: 25557
+/* 13012 */ MCD_OPC_CheckField, 21, 1, 1, 251, 48, // Skip to: 25557
+/* 13018 */ MCD_OPC_Decode, 168, 4, 33, // Opcode: FMINNMvvv_4S
+/* 13022 */ MCD_OPC_FilterValue, 3, 243, 48, // Skip to: 25557
+/* 13026 */ MCD_OPC_CheckPredicate, 0, 239, 48, // Skip to: 25557
+/* 13030 */ MCD_OPC_CheckField, 21, 1, 1, 233, 48, // Skip to: 25557
+/* 13036 */ MCD_OPC_Decode, 163, 4, 33, // Opcode: FMINNMPvvv_4S
+/* 13040 */ MCD_OPC_FilterValue, 50, 75, 0, // Skip to: 13119
+/* 13044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13047 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13065
+/* 13051 */ MCD_OPC_CheckPredicate, 0, 214, 48, // Skip to: 25557
+/* 13055 */ MCD_OPC_CheckField, 16, 6, 32, 208, 48, // Skip to: 25557
+/* 13061 */ MCD_OPC_Decode, 185, 3, 32, // Opcode: FCMGTvvi_2S
+/* 13065 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13083
+/* 13069 */ MCD_OPC_CheckPredicate, 0, 196, 48, // Skip to: 25557
+/* 13073 */ MCD_OPC_CheckField, 16, 6, 32, 190, 48, // Skip to: 25557
+/* 13079 */ MCD_OPC_Decode, 179, 3, 32, // Opcode: FCMGEvvi_2S
+/* 13083 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13101
+/* 13087 */ MCD_OPC_CheckPredicate, 0, 178, 48, // Skip to: 25557
+/* 13091 */ MCD_OPC_CheckField, 16, 6, 32, 172, 48, // Skip to: 25557
+/* 13097 */ MCD_OPC_Decode, 186, 3, 43, // Opcode: FCMGTvvi_4S
+/* 13101 */ MCD_OPC_FilterValue, 3, 164, 48, // Skip to: 25557
+/* 13105 */ MCD_OPC_CheckPredicate, 0, 160, 48, // Skip to: 25557
+/* 13109 */ MCD_OPC_CheckField, 16, 6, 32, 154, 48, // Skip to: 25557
+/* 13115 */ MCD_OPC_Decode, 180, 3, 43, // Opcode: FCMGEvvi_4S
+/* 13119 */ MCD_OPC_FilterValue, 51, 39, 0, // Skip to: 13162
+/* 13123 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13126 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13144
+/* 13130 */ MCD_OPC_CheckPredicate, 0, 135, 48, // Skip to: 25557
+/* 13134 */ MCD_OPC_CheckField, 21, 1, 1, 129, 48, // Skip to: 25557
+/* 13140 */ MCD_OPC_Decode, 183, 4, 31, // Opcode: FMLSvvv_2S
+/* 13144 */ MCD_OPC_FilterValue, 2, 121, 48, // Skip to: 25557
+/* 13148 */ MCD_OPC_CheckPredicate, 0, 117, 48, // Skip to: 25557
+/* 13152 */ MCD_OPC_CheckField, 21, 1, 1, 111, 48, // Skip to: 25557
+/* 13158 */ MCD_OPC_Decode, 184, 4, 42, // Opcode: FMLSvvv_4S
+/* 13162 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 13205
+/* 13166 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13169 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13187
+/* 13173 */ MCD_OPC_CheckPredicate, 0, 92, 48, // Skip to: 25557
+/* 13177 */ MCD_OPC_CheckField, 21, 1, 1, 86, 48, // Skip to: 25557
+/* 13183 */ MCD_OPC_Decode, 136, 9, 23, // Opcode: SQDMULLvvv_2d2s
+/* 13187 */ MCD_OPC_FilterValue, 2, 78, 48, // Skip to: 25557
+/* 13191 */ MCD_OPC_CheckPredicate, 0, 74, 48, // Skip to: 25557
+/* 13195 */ MCD_OPC_CheckField, 21, 1, 1, 68, 48, // Skip to: 25557
+/* 13201 */ MCD_OPC_Decode, 134, 9, 33, // Opcode: SQDMULL2vvv_2d4s
+/* 13205 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 13284
+/* 13209 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13212 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13230
+/* 13216 */ MCD_OPC_CheckPredicate, 0, 49, 48, // Skip to: 25557
+/* 13220 */ MCD_OPC_CheckField, 21, 1, 1, 43, 48, // Skip to: 25557
+/* 13226 */ MCD_OPC_Decode, 241, 4, 24, // Opcode: FSUBvvv_2S
+/* 13230 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13248
+/* 13234 */ MCD_OPC_CheckPredicate, 0, 31, 48, // Skip to: 25557
+/* 13238 */ MCD_OPC_CheckField, 21, 1, 1, 25, 48, // Skip to: 25557
+/* 13244 */ MCD_OPC_Decode, 148, 3, 24, // Opcode: FABDvvv_2S
+/* 13248 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13266
+/* 13252 */ MCD_OPC_CheckPredicate, 0, 13, 48, // Skip to: 25557
+/* 13256 */ MCD_OPC_CheckField, 21, 1, 1, 7, 48, // Skip to: 25557
+/* 13262 */ MCD_OPC_Decode, 242, 4, 33, // Opcode: FSUBvvv_4S
+/* 13266 */ MCD_OPC_FilterValue, 3, 255, 47, // Skip to: 25557
+/* 13270 */ MCD_OPC_CheckPredicate, 0, 251, 47, // Skip to: 25557
+/* 13274 */ MCD_OPC_CheckField, 21, 1, 1, 245, 47, // Skip to: 25557
+/* 13280 */ MCD_OPC_Decode, 149, 3, 33, // Opcode: FABDvvv_4S
+/* 13284 */ MCD_OPC_FilterValue, 54, 75, 0, // Skip to: 13363
+/* 13288 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13291 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13309
+/* 13295 */ MCD_OPC_CheckPredicate, 0, 226, 47, // Skip to: 25557
+/* 13299 */ MCD_OPC_CheckField, 16, 6, 32, 220, 47, // Skip to: 25557
+/* 13305 */ MCD_OPC_Decode, 173, 3, 32, // Opcode: FCMEQvvi_2S
+/* 13309 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13327
+/* 13313 */ MCD_OPC_CheckPredicate, 0, 208, 47, // Skip to: 25557
+/* 13317 */ MCD_OPC_CheckField, 16, 6, 32, 202, 47, // Skip to: 25557
+/* 13323 */ MCD_OPC_Decode, 191, 3, 32, // Opcode: FCMLEvvi_2S
+/* 13327 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13345
+/* 13331 */ MCD_OPC_CheckPredicate, 0, 190, 47, // Skip to: 25557
+/* 13335 */ MCD_OPC_CheckField, 16, 6, 32, 184, 47, // Skip to: 25557
+/* 13341 */ MCD_OPC_Decode, 174, 3, 43, // Opcode: FCMEQvvi_4S
+/* 13345 */ MCD_OPC_FilterValue, 3, 176, 47, // Skip to: 25557
+/* 13349 */ MCD_OPC_CheckPredicate, 0, 172, 47, // Skip to: 25557
+/* 13353 */ MCD_OPC_CheckField, 16, 6, 32, 166, 47, // Skip to: 25557
+/* 13359 */ MCD_OPC_Decode, 192, 3, 43, // Opcode: FCMLEvvi_4S
+/* 13363 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 13406
+/* 13367 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13370 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13388
+/* 13374 */ MCD_OPC_CheckPredicate, 0, 147, 47, // Skip to: 25557
+/* 13378 */ MCD_OPC_CheckField, 21, 1, 1, 141, 47, // Skip to: 25557
+/* 13384 */ MCD_OPC_Decode, 188, 3, 24, // Opcode: FCMGTvvv_2S
+/* 13388 */ MCD_OPC_FilterValue, 3, 133, 47, // Skip to: 25557
+/* 13392 */ MCD_OPC_CheckPredicate, 0, 129, 47, // Skip to: 25557
+/* 13396 */ MCD_OPC_CheckField, 21, 1, 1, 123, 47, // Skip to: 25557
+/* 13402 */ MCD_OPC_Decode, 189, 3, 33, // Opcode: FCMGTvvv_4S
+/* 13406 */ MCD_OPC_FilterValue, 58, 39, 0, // Skip to: 13449
+/* 13410 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13413 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13431
+/* 13417 */ MCD_OPC_CheckPredicate, 0, 104, 47, // Skip to: 25557
+/* 13421 */ MCD_OPC_CheckField, 16, 6, 32, 98, 47, // Skip to: 25557
+/* 13427 */ MCD_OPC_Decode, 194, 3, 32, // Opcode: FCMLTvvi_2S
+/* 13431 */ MCD_OPC_FilterValue, 2, 90, 47, // Skip to: 25557
+/* 13435 */ MCD_OPC_CheckPredicate, 0, 86, 47, // Skip to: 25557
+/* 13439 */ MCD_OPC_CheckField, 16, 6, 32, 80, 47, // Skip to: 25557
+/* 13445 */ MCD_OPC_Decode, 195, 3, 43, // Opcode: FCMLTvvi_4S
+/* 13449 */ MCD_OPC_FilterValue, 59, 39, 0, // Skip to: 13492
+/* 13453 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13456 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13474
+/* 13460 */ MCD_OPC_CheckPredicate, 0, 61, 47, // Skip to: 25557
+/* 13464 */ MCD_OPC_CheckField, 21, 1, 1, 55, 47, // Skip to: 25557
+/* 13470 */ MCD_OPC_Decode, 156, 3, 24, // Opcode: FACGTvvv_2S
+/* 13474 */ MCD_OPC_FilterValue, 3, 47, 47, // Skip to: 25557
+/* 13478 */ MCD_OPC_CheckPredicate, 0, 43, 47, // Skip to: 25557
+/* 13482 */ MCD_OPC_CheckField, 21, 1, 1, 37, 47, // Skip to: 25557
+/* 13488 */ MCD_OPC_Decode, 157, 3, 33, // Opcode: FACGTvvv_4S
+/* 13492 */ MCD_OPC_FilterValue, 61, 75, 0, // Skip to: 13571
+/* 13496 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13499 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13517
+/* 13503 */ MCD_OPC_CheckPredicate, 0, 18, 47, // Skip to: 25557
+/* 13507 */ MCD_OPC_CheckField, 21, 1, 1, 12, 47, // Skip to: 25557
+/* 13513 */ MCD_OPC_Decode, 177, 4, 24, // Opcode: FMINvvv_2S
+/* 13517 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13535
+/* 13521 */ MCD_OPC_CheckPredicate, 0, 0, 47, // Skip to: 25557
+/* 13525 */ MCD_OPC_CheckField, 21, 1, 1, 250, 46, // Skip to: 25557
+/* 13531 */ MCD_OPC_Decode, 172, 4, 24, // Opcode: FMINPvvv_2S
+/* 13535 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13553
+/* 13539 */ MCD_OPC_CheckPredicate, 0, 238, 46, // Skip to: 25557
+/* 13543 */ MCD_OPC_CheckField, 21, 1, 1, 232, 46, // Skip to: 25557
+/* 13549 */ MCD_OPC_Decode, 178, 4, 33, // Opcode: FMINvvv_4S
+/* 13553 */ MCD_OPC_FilterValue, 3, 224, 46, // Skip to: 25557
+/* 13557 */ MCD_OPC_CheckPredicate, 0, 220, 46, // Skip to: 25557
+/* 13561 */ MCD_OPC_CheckField, 21, 1, 1, 214, 46, // Skip to: 25557
+/* 13567 */ MCD_OPC_Decode, 173, 4, 33, // Opcode: FMINPvvv_4S
+/* 13571 */ MCD_OPC_FilterValue, 63, 206, 46, // Skip to: 25557
+/* 13575 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13578 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13596
+/* 13582 */ MCD_OPC_CheckPredicate, 0, 195, 46, // Skip to: 25557
+/* 13586 */ MCD_OPC_CheckField, 21, 1, 1, 189, 46, // Skip to: 25557
+/* 13592 */ MCD_OPC_Decode, 234, 4, 24, // Opcode: FRSQRTSvvv_2S
+/* 13596 */ MCD_OPC_FilterValue, 2, 181, 46, // Skip to: 25557
+/* 13600 */ MCD_OPC_CheckPredicate, 0, 177, 46, // Skip to: 25557
+/* 13604 */ MCD_OPC_CheckField, 21, 1, 1, 171, 46, // Skip to: 25557
+/* 13610 */ MCD_OPC_Decode, 235, 4, 33, // Opcode: FRSQRTSvvv_4S
+/* 13614 */ MCD_OPC_FilterValue, 11, 211, 3, // Skip to: 14597
+/* 13618 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 13621 */ MCD_OPC_FilterValue, 3, 39, 0, // Skip to: 13664
+/* 13625 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13628 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13646
+/* 13632 */ MCD_OPC_CheckPredicate, 0, 145, 46, // Skip to: 25557
+/* 13636 */ MCD_OPC_CheckField, 21, 1, 1, 139, 46, // Skip to: 25557
+/* 13642 */ MCD_OPC_Decode, 244, 8, 33, // Opcode: SQADDvvv_2D
+/* 13646 */ MCD_OPC_FilterValue, 3, 131, 46, // Skip to: 25557
+/* 13650 */ MCD_OPC_CheckPredicate, 0, 127, 46, // Skip to: 25557
+/* 13654 */ MCD_OPC_CheckField, 21, 1, 1, 121, 46, // Skip to: 25557
+/* 13660 */ MCD_OPC_Decode, 252, 11, 33, // Opcode: UQADDvvv_2D
+/* 13664 */ MCD_OPC_FilterValue, 7, 75, 0, // Skip to: 13743
+/* 13668 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13671 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13689
+/* 13675 */ MCD_OPC_CheckPredicate, 0, 102, 46, // Skip to: 25557
+/* 13679 */ MCD_OPC_CheckField, 21, 1, 1, 96, 46, // Skip to: 25557
+/* 13685 */ MCD_OPC_Decode, 153, 7, 24, // Opcode: ORNvvv_8B
+/* 13689 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13707
+/* 13693 */ MCD_OPC_CheckPredicate, 0, 84, 46, // Skip to: 25557
+/* 13697 */ MCD_OPC_CheckField, 21, 1, 1, 78, 46, // Skip to: 25557
+/* 13703 */ MCD_OPC_Decode, 207, 1, 31, // Opcode: BIFvvv_8B
+/* 13707 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13725
+/* 13711 */ MCD_OPC_CheckPredicate, 0, 66, 46, // Skip to: 25557
+/* 13715 */ MCD_OPC_CheckField, 21, 1, 1, 60, 46, // Skip to: 25557
+/* 13721 */ MCD_OPC_Decode, 152, 7, 33, // Opcode: ORNvvv_16B
+/* 13725 */ MCD_OPC_FilterValue, 3, 52, 46, // Skip to: 25557
+/* 13729 */ MCD_OPC_CheckPredicate, 0, 48, 46, // Skip to: 25557
+/* 13733 */ MCD_OPC_CheckField, 21, 1, 1, 42, 46, // Skip to: 25557
+/* 13739 */ MCD_OPC_Decode, 206, 1, 42, // Opcode: BIFvvv_16B
+/* 13743 */ MCD_OPC_FilterValue, 11, 39, 0, // Skip to: 13786
+/* 13747 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13750 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13768
+/* 13754 */ MCD_OPC_CheckPredicate, 0, 23, 46, // Skip to: 25557
+/* 13758 */ MCD_OPC_CheckField, 21, 1, 1, 17, 46, // Skip to: 25557
+/* 13764 */ MCD_OPC_Decode, 195, 9, 33, // Opcode: SQSUBvvv_2D
+/* 13768 */ MCD_OPC_FilterValue, 3, 9, 46, // Skip to: 25557
+/* 13772 */ MCD_OPC_CheckPredicate, 0, 5, 46, // Skip to: 25557
+/* 13776 */ MCD_OPC_CheckField, 21, 1, 1, 255, 45, // Skip to: 25557
+/* 13782 */ MCD_OPC_Decode, 176, 12, 33, // Opcode: UQSUBvvv_2D
+/* 13786 */ MCD_OPC_FilterValue, 13, 39, 0, // Skip to: 13829
+/* 13790 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13793 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13811
+/* 13797 */ MCD_OPC_CheckPredicate, 0, 236, 45, // Skip to: 25557
+/* 13801 */ MCD_OPC_CheckField, 21, 1, 1, 230, 45, // Skip to: 25557
+/* 13807 */ MCD_OPC_Decode, 143, 2, 33, // Opcode: CMGTvvv_2D
+/* 13811 */ MCD_OPC_FilterValue, 3, 222, 45, // Skip to: 25557
+/* 13815 */ MCD_OPC_CheckPredicate, 0, 218, 45, // Skip to: 25557
+/* 13819 */ MCD_OPC_CheckField, 21, 1, 1, 212, 45, // Skip to: 25557
+/* 13825 */ MCD_OPC_Decode, 150, 2, 33, // Opcode: CMHIvvv_2D
+/* 13829 */ MCD_OPC_FilterValue, 15, 39, 0, // Skip to: 13872
+/* 13833 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13836 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13854
+/* 13840 */ MCD_OPC_CheckPredicate, 0, 193, 45, // Skip to: 25557
+/* 13844 */ MCD_OPC_CheckField, 21, 1, 1, 187, 45, // Skip to: 25557
+/* 13850 */ MCD_OPC_Decode, 129, 2, 33, // Opcode: CMGEvvv_2D
+/* 13854 */ MCD_OPC_FilterValue, 3, 179, 45, // Skip to: 25557
+/* 13858 */ MCD_OPC_CheckPredicate, 0, 175, 45, // Skip to: 25557
+/* 13862 */ MCD_OPC_CheckField, 21, 1, 1, 169, 45, // Skip to: 25557
+/* 13868 */ MCD_OPC_Decode, 157, 2, 33, // Opcode: CMHSvvv_2D
+/* 13872 */ MCD_OPC_FilterValue, 17, 39, 0, // Skip to: 13915
+/* 13876 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13879 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13897
+/* 13883 */ MCD_OPC_CheckPredicate, 0, 150, 45, // Skip to: 25557
+/* 13887 */ MCD_OPC_CheckField, 21, 1, 1, 144, 45, // Skip to: 25557
+/* 13893 */ MCD_OPC_Decode, 244, 9, 33, // Opcode: SSHLvvv_2D
+/* 13897 */ MCD_OPC_FilterValue, 3, 136, 45, // Skip to: 25557
+/* 13901 */ MCD_OPC_CheckPredicate, 0, 132, 45, // Skip to: 25557
+/* 13905 */ MCD_OPC_CheckField, 21, 1, 1, 126, 45, // Skip to: 25557
+/* 13911 */ MCD_OPC_Decode, 218, 12, 33, // Opcode: USHLvvv_2D
+/* 13915 */ MCD_OPC_FilterValue, 19, 39, 0, // Skip to: 13958
+/* 13919 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13922 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13940
+/* 13926 */ MCD_OPC_CheckPredicate, 0, 107, 45, // Skip to: 25557
+/* 13930 */ MCD_OPC_CheckField, 21, 1, 1, 101, 45, // Skip to: 25557
+/* 13936 */ MCD_OPC_Decode, 178, 9, 33, // Opcode: SQSHLvvv_2D
+/* 13940 */ MCD_OPC_FilterValue, 3, 93, 45, // Skip to: 25557
+/* 13944 */ MCD_OPC_CheckPredicate, 0, 89, 45, // Skip to: 25557
+/* 13948 */ MCD_OPC_CheckField, 21, 1, 1, 83, 45, // Skip to: 25557
+/* 13954 */ MCD_OPC_Decode, 159, 12, 33, // Opcode: UQSHLvvv_2D
+/* 13958 */ MCD_OPC_FilterValue, 21, 39, 0, // Skip to: 14001
+/* 13962 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 13965 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13983
+/* 13969 */ MCD_OPC_CheckPredicate, 0, 64, 45, // Skip to: 25557
+/* 13973 */ MCD_OPC_CheckField, 21, 1, 1, 58, 45, // Skip to: 25557
+/* 13979 */ MCD_OPC_Decode, 216, 9, 33, // Opcode: SRSHLvvv_2D
+/* 13983 */ MCD_OPC_FilterValue, 3, 50, 45, // Skip to: 25557
+/* 13987 */ MCD_OPC_CheckPredicate, 0, 46, 45, // Skip to: 25557
+/* 13991 */ MCD_OPC_CheckField, 21, 1, 1, 40, 45, // Skip to: 25557
+/* 13997 */ MCD_OPC_Decode, 190, 12, 33, // Opcode: URSHLvvv_2D
+/* 14001 */ MCD_OPC_FilterValue, 23, 39, 0, // Skip to: 14044
+/* 14005 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14008 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14026
+/* 14012 */ MCD_OPC_CheckPredicate, 0, 21, 45, // Skip to: 25557
+/* 14016 */ MCD_OPC_CheckField, 21, 1, 1, 15, 45, // Skip to: 25557
+/* 14022 */ MCD_OPC_Decode, 147, 9, 33, // Opcode: SQRSHLvvv_2D
+/* 14026 */ MCD_OPC_FilterValue, 3, 7, 45, // Skip to: 25557
+/* 14030 */ MCD_OPC_CheckPredicate, 0, 3, 45, // Skip to: 25557
+/* 14034 */ MCD_OPC_CheckField, 21, 1, 1, 253, 44, // Skip to: 25557
+/* 14040 */ MCD_OPC_Decode, 135, 12, 33, // Opcode: UQRSHLvvv_2D
+/* 14044 */ MCD_OPC_FilterValue, 33, 38, 0, // Skip to: 14086
+/* 14048 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14051 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 14068
+/* 14055 */ MCD_OPC_CheckPredicate, 0, 234, 44, // Skip to: 25557
+/* 14059 */ MCD_OPC_CheckField, 21, 1, 1, 228, 44, // Skip to: 25557
+/* 14065 */ MCD_OPC_Decode, 59, 33, // Opcode: ADDvvv_2D
+/* 14068 */ MCD_OPC_FilterValue, 3, 221, 44, // Skip to: 25557
+/* 14072 */ MCD_OPC_CheckPredicate, 0, 217, 44, // Skip to: 25557
+/* 14076 */ MCD_OPC_CheckField, 21, 1, 1, 211, 44, // Skip to: 25557
+/* 14082 */ MCD_OPC_Decode, 194, 10, 33, // Opcode: SUBvvv_2D
+/* 14086 */ MCD_OPC_FilterValue, 34, 39, 0, // Skip to: 14129
+/* 14090 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14093 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14111
+/* 14097 */ MCD_OPC_CheckPredicate, 0, 192, 44, // Skip to: 25557
+/* 14101 */ MCD_OPC_CheckField, 16, 6, 32, 186, 44, // Skip to: 25557
+/* 14107 */ MCD_OPC_Decode, 136, 2, 43, // Opcode: CMGTvvi_2D
+/* 14111 */ MCD_OPC_FilterValue, 3, 178, 44, // Skip to: 25557
+/* 14115 */ MCD_OPC_CheckPredicate, 0, 174, 44, // Skip to: 25557
+/* 14119 */ MCD_OPC_CheckField, 16, 6, 32, 168, 44, // Skip to: 25557
+/* 14125 */ MCD_OPC_Decode, 250, 1, 43, // Opcode: CMGEvvi_2D
+/* 14129 */ MCD_OPC_FilterValue, 35, 39, 0, // Skip to: 14172
+/* 14133 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14136 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14154
+/* 14140 */ MCD_OPC_CheckPredicate, 0, 149, 44, // Skip to: 25557
+/* 14144 */ MCD_OPC_CheckField, 21, 1, 1, 143, 44, // Skip to: 25557
+/* 14150 */ MCD_OPC_Decode, 222, 2, 33, // Opcode: CMTSTvvv_2D
+/* 14154 */ MCD_OPC_FilterValue, 3, 135, 44, // Skip to: 25557
+/* 14158 */ MCD_OPC_CheckPredicate, 0, 131, 44, // Skip to: 25557
+/* 14162 */ MCD_OPC_CheckField, 21, 1, 1, 125, 44, // Skip to: 25557
+/* 14168 */ MCD_OPC_Decode, 243, 1, 33, // Opcode: CMEQvvv_2D
+/* 14172 */ MCD_OPC_FilterValue, 38, 39, 0, // Skip to: 14215
+/* 14176 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14179 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14197
+/* 14183 */ MCD_OPC_CheckPredicate, 0, 106, 44, // Skip to: 25557
+/* 14187 */ MCD_OPC_CheckField, 16, 6, 32, 100, 44, // Skip to: 25557
+/* 14193 */ MCD_OPC_Decode, 236, 1, 43, // Opcode: CMEQvvi_2D
+/* 14197 */ MCD_OPC_FilterValue, 3, 92, 44, // Skip to: 25557
+/* 14201 */ MCD_OPC_CheckPredicate, 0, 88, 44, // Skip to: 25557
+/* 14205 */ MCD_OPC_CheckField, 16, 6, 32, 82, 44, // Skip to: 25557
+/* 14211 */ MCD_OPC_Decode, 164, 2, 43, // Opcode: CMLEvvi_2D
+/* 14215 */ MCD_OPC_FilterValue, 42, 20, 0, // Skip to: 14239
+/* 14219 */ MCD_OPC_CheckPredicate, 0, 70, 44, // Skip to: 25557
+/* 14223 */ MCD_OPC_CheckField, 29, 3, 2, 64, 44, // Skip to: 25557
+/* 14229 */ MCD_OPC_CheckField, 16, 6, 32, 58, 44, // Skip to: 25557
+/* 14235 */ MCD_OPC_Decode, 171, 2, 43, // Opcode: CMLTvvi_2D
+/* 14239 */ MCD_OPC_FilterValue, 47, 19, 0, // Skip to: 14262
+/* 14243 */ MCD_OPC_CheckPredicate, 0, 46, 44, // Skip to: 25557
+/* 14247 */ MCD_OPC_CheckField, 29, 3, 2, 40, 44, // Skip to: 25557
+/* 14253 */ MCD_OPC_CheckField, 21, 1, 1, 34, 44, // Skip to: 25557
+/* 14259 */ MCD_OPC_Decode, 28, 33, // Opcode: ADDP_2D
+/* 14262 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 14305
+/* 14266 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14269 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14287
+/* 14273 */ MCD_OPC_CheckPredicate, 0, 16, 44, // Skip to: 25557
+/* 14277 */ MCD_OPC_CheckField, 21, 1, 1, 10, 44, // Skip to: 25557
+/* 14283 */ MCD_OPC_Decode, 166, 4, 33, // Opcode: FMINNMvvv_2D
+/* 14287 */ MCD_OPC_FilterValue, 3, 2, 44, // Skip to: 25557
+/* 14291 */ MCD_OPC_CheckPredicate, 0, 254, 43, // Skip to: 25557
+/* 14295 */ MCD_OPC_CheckField, 21, 1, 1, 248, 43, // Skip to: 25557
+/* 14301 */ MCD_OPC_Decode, 161, 4, 33, // Opcode: FMINNMPvvv_2D
+/* 14305 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 14348
+/* 14309 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14312 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14330
+/* 14316 */ MCD_OPC_CheckPredicate, 0, 229, 43, // Skip to: 25557
+/* 14320 */ MCD_OPC_CheckField, 16, 6, 32, 223, 43, // Skip to: 25557
+/* 14326 */ MCD_OPC_Decode, 184, 3, 43, // Opcode: FCMGTvvi_2D
+/* 14330 */ MCD_OPC_FilterValue, 3, 215, 43, // Skip to: 25557
+/* 14334 */ MCD_OPC_CheckPredicate, 0, 211, 43, // Skip to: 25557
+/* 14338 */ MCD_OPC_CheckField, 16, 6, 32, 205, 43, // Skip to: 25557
+/* 14344 */ MCD_OPC_Decode, 178, 3, 43, // Opcode: FCMGEvvi_2D
+/* 14348 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 14372
+/* 14352 */ MCD_OPC_CheckPredicate, 0, 193, 43, // Skip to: 25557
+/* 14356 */ MCD_OPC_CheckField, 29, 3, 2, 187, 43, // Skip to: 25557
+/* 14362 */ MCD_OPC_CheckField, 21, 1, 1, 181, 43, // Skip to: 25557
+/* 14368 */ MCD_OPC_Decode, 182, 4, 42, // Opcode: FMLSvvv_2D
+/* 14372 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 14415
+/* 14376 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14379 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14397
+/* 14383 */ MCD_OPC_CheckPredicate, 0, 162, 43, // Skip to: 25557
+/* 14387 */ MCD_OPC_CheckField, 21, 1, 1, 156, 43, // Skip to: 25557
+/* 14393 */ MCD_OPC_Decode, 240, 4, 33, // Opcode: FSUBvvv_2D
+/* 14397 */ MCD_OPC_FilterValue, 3, 148, 43, // Skip to: 25557
+/* 14401 */ MCD_OPC_CheckPredicate, 0, 144, 43, // Skip to: 25557
+/* 14405 */ MCD_OPC_CheckField, 21, 1, 1, 138, 43, // Skip to: 25557
+/* 14411 */ MCD_OPC_Decode, 147, 3, 33, // Opcode: FABDvvv_2D
+/* 14415 */ MCD_OPC_FilterValue, 54, 39, 0, // Skip to: 14458
+/* 14419 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14422 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14440
+/* 14426 */ MCD_OPC_CheckPredicate, 0, 119, 43, // Skip to: 25557
+/* 14430 */ MCD_OPC_CheckField, 16, 6, 32, 113, 43, // Skip to: 25557
+/* 14436 */ MCD_OPC_Decode, 172, 3, 43, // Opcode: FCMEQvvi_2D
+/* 14440 */ MCD_OPC_FilterValue, 3, 105, 43, // Skip to: 25557
+/* 14444 */ MCD_OPC_CheckPredicate, 0, 101, 43, // Skip to: 25557
+/* 14448 */ MCD_OPC_CheckField, 16, 6, 32, 95, 43, // Skip to: 25557
+/* 14454 */ MCD_OPC_Decode, 190, 3, 43, // Opcode: FCMLEvvi_2D
+/* 14458 */ MCD_OPC_FilterValue, 57, 20, 0, // Skip to: 14482
+/* 14462 */ MCD_OPC_CheckPredicate, 0, 83, 43, // Skip to: 25557
+/* 14466 */ MCD_OPC_CheckField, 29, 3, 3, 77, 43, // Skip to: 25557
+/* 14472 */ MCD_OPC_CheckField, 21, 1, 1, 71, 43, // Skip to: 25557
+/* 14478 */ MCD_OPC_Decode, 187, 3, 33, // Opcode: FCMGTvvv_2D
+/* 14482 */ MCD_OPC_FilterValue, 58, 20, 0, // Skip to: 14506
+/* 14486 */ MCD_OPC_CheckPredicate, 0, 59, 43, // Skip to: 25557
+/* 14490 */ MCD_OPC_CheckField, 29, 3, 2, 53, 43, // Skip to: 25557
+/* 14496 */ MCD_OPC_CheckField, 16, 6, 32, 47, 43, // Skip to: 25557
+/* 14502 */ MCD_OPC_Decode, 193, 3, 43, // Opcode: FCMLTvvi_2D
+/* 14506 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 14530
+/* 14510 */ MCD_OPC_CheckPredicate, 0, 35, 43, // Skip to: 25557
+/* 14514 */ MCD_OPC_CheckField, 29, 3, 3, 29, 43, // Skip to: 25557
+/* 14520 */ MCD_OPC_CheckField, 21, 1, 1, 23, 43, // Skip to: 25557
+/* 14526 */ MCD_OPC_Decode, 155, 3, 33, // Opcode: FACGTvvv_2D
+/* 14530 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 14573
+/* 14534 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14537 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14555
+/* 14541 */ MCD_OPC_CheckPredicate, 0, 4, 43, // Skip to: 25557
+/* 14545 */ MCD_OPC_CheckField, 21, 1, 1, 254, 42, // Skip to: 25557
+/* 14551 */ MCD_OPC_Decode, 176, 4, 33, // Opcode: FMINvvv_2D
+/* 14555 */ MCD_OPC_FilterValue, 3, 246, 42, // Skip to: 25557
+/* 14559 */ MCD_OPC_CheckPredicate, 0, 242, 42, // Skip to: 25557
+/* 14563 */ MCD_OPC_CheckField, 21, 1, 1, 236, 42, // Skip to: 25557
+/* 14569 */ MCD_OPC_Decode, 171, 4, 33, // Opcode: FMINPvvv_2D
+/* 14573 */ MCD_OPC_FilterValue, 63, 228, 42, // Skip to: 25557
+/* 14577 */ MCD_OPC_CheckPredicate, 0, 224, 42, // Skip to: 25557
+/* 14581 */ MCD_OPC_CheckField, 29, 3, 2, 218, 42, // Skip to: 25557
+/* 14587 */ MCD_OPC_CheckField, 21, 1, 1, 212, 42, // Skip to: 25557
+/* 14593 */ MCD_OPC_Decode, 233, 4, 33, // Opcode: FRSQRTSvvv_2D
+/* 14597 */ MCD_OPC_FilterValue, 12, 246, 12, // Skip to: 17919
+/* 14601 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 14604 */ MCD_OPC_FilterValue, 0, 24, 3, // Skip to: 15400
+/* 14608 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 14611 */ MCD_OPC_FilterValue, 1, 136, 2, // Skip to: 15263
+/* 14615 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 14618 */ MCD_OPC_FilterValue, 0, 71, 1, // Skip to: 14949
+/* 14622 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 14625 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 14751
+/* 14629 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 14632 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 14720
+/* 14636 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 14639 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 14689
+/* 14643 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 14646 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14658
+/* 14650 */ MCD_OPC_CheckPredicate, 0, 151, 42, // Skip to: 25557
+/* 14654 */ MCD_OPC_Decode, 243, 6, 48, // Opcode: MOVIvi_lsl_2S
+/* 14658 */ MCD_OPC_FilterValue, 1, 143, 42, // Skip to: 25557
+/* 14662 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14665 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14677
+/* 14669 */ MCD_OPC_CheckPredicate, 0, 132, 42, // Skip to: 25557
+/* 14673 */ MCD_OPC_Decode, 255, 9, 49, // Opcode: SSHRvvi_8B
+/* 14677 */ MCD_OPC_FilterValue, 1, 124, 42, // Skip to: 25557
+/* 14681 */ MCD_OPC_CheckPredicate, 0, 120, 42, // Skip to: 25557
+/* 14685 */ MCD_OPC_Decode, 227, 9, 49, // Opcode: SRSHRvvi_8B
+/* 14689 */ MCD_OPC_FilterValue, 1, 112, 42, // Skip to: 25557
+/* 14693 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14696 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14708
+/* 14700 */ MCD_OPC_CheckPredicate, 0, 101, 42, // Skip to: 25557
+/* 14704 */ MCD_OPC_Decode, 253, 9, 50, // Opcode: SSHRvvi_4H
+/* 14708 */ MCD_OPC_FilterValue, 1, 93, 42, // Skip to: 25557
+/* 14712 */ MCD_OPC_CheckPredicate, 0, 89, 42, // Skip to: 25557
+/* 14716 */ MCD_OPC_Decode, 225, 9, 50, // Opcode: SRSHRvvi_4H
+/* 14720 */ MCD_OPC_FilterValue, 1, 81, 42, // Skip to: 25557
+/* 14724 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14727 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14739
+/* 14731 */ MCD_OPC_CheckPredicate, 0, 70, 42, // Skip to: 25557
+/* 14735 */ MCD_OPC_Decode, 252, 9, 51, // Opcode: SSHRvvi_2S
+/* 14739 */ MCD_OPC_FilterValue, 1, 62, 42, // Skip to: 25557
+/* 14743 */ MCD_OPC_CheckPredicate, 0, 58, 42, // Skip to: 25557
+/* 14747 */ MCD_OPC_Decode, 224, 9, 51, // Opcode: SRSHRvvi_2S
+/* 14751 */ MCD_OPC_FilterValue, 1, 50, 42, // Skip to: 25557
+/* 14755 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 14758 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 14894
+/* 14762 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 14765 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 14839
+/* 14769 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 14772 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14784
+/* 14776 */ MCD_OPC_CheckPredicate, 0, 25, 42, // Skip to: 25557
+/* 14780 */ MCD_OPC_Decode, 162, 7, 52, // Opcode: ORRvi_lsl_2S
+/* 14784 */ MCD_OPC_FilterValue, 1, 17, 42, // Skip to: 25557
+/* 14788 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14791 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14803
+/* 14795 */ MCD_OPC_CheckPredicate, 0, 6, 42, // Skip to: 25557
+/* 14799 */ MCD_OPC_Decode, 134, 10, 53, // Opcode: SSRAvvi_8B
+/* 14803 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 14815
+/* 14807 */ MCD_OPC_CheckPredicate, 0, 250, 41, // Skip to: 25557
+/* 14811 */ MCD_OPC_Decode, 234, 9, 53, // Opcode: SRSRAvvi_8B
+/* 14815 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 14827
+/* 14819 */ MCD_OPC_CheckPredicate, 0, 238, 41, // Skip to: 25557
+/* 14823 */ MCD_OPC_Decode, 167, 8, 54, // Opcode: SHLvvi_8B
+/* 14827 */ MCD_OPC_FilterValue, 3, 230, 41, // Skip to: 25557
+/* 14831 */ MCD_OPC_CheckPredicate, 0, 226, 41, // Skip to: 25557
+/* 14835 */ MCD_OPC_Decode, 175, 9, 54, // Opcode: SQSHLvvi_8B
+/* 14839 */ MCD_OPC_FilterValue, 1, 218, 41, // Skip to: 25557
+/* 14843 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14846 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14858
+/* 14850 */ MCD_OPC_CheckPredicate, 0, 207, 41, // Skip to: 25557
+/* 14854 */ MCD_OPC_Decode, 132, 10, 55, // Opcode: SSRAvvi_4H
+/* 14858 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 14870
+/* 14862 */ MCD_OPC_CheckPredicate, 0, 195, 41, // Skip to: 25557
+/* 14866 */ MCD_OPC_Decode, 232, 9, 55, // Opcode: SRSRAvvi_4H
+/* 14870 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 14882
+/* 14874 */ MCD_OPC_CheckPredicate, 0, 183, 41, // Skip to: 25557
+/* 14878 */ MCD_OPC_Decode, 165, 8, 56, // Opcode: SHLvvi_4H
+/* 14882 */ MCD_OPC_FilterValue, 3, 175, 41, // Skip to: 25557
+/* 14886 */ MCD_OPC_CheckPredicate, 0, 171, 41, // Skip to: 25557
+/* 14890 */ MCD_OPC_Decode, 173, 9, 56, // Opcode: SQSHLvvi_4H
+/* 14894 */ MCD_OPC_FilterValue, 1, 163, 41, // Skip to: 25557
+/* 14898 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 14901 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14913
+/* 14905 */ MCD_OPC_CheckPredicate, 0, 152, 41, // Skip to: 25557
+/* 14909 */ MCD_OPC_Decode, 131, 10, 57, // Opcode: SSRAvvi_2S
+/* 14913 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 14925
+/* 14917 */ MCD_OPC_CheckPredicate, 0, 140, 41, // Skip to: 25557
+/* 14921 */ MCD_OPC_Decode, 231, 9, 57, // Opcode: SRSRAvvi_2S
+/* 14925 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 14937
+/* 14929 */ MCD_OPC_CheckPredicate, 0, 128, 41, // Skip to: 25557
+/* 14933 */ MCD_OPC_Decode, 164, 8, 58, // Opcode: SHLvvi_2S
+/* 14937 */ MCD_OPC_FilterValue, 3, 120, 41, // Skip to: 25557
+/* 14941 */ MCD_OPC_CheckPredicate, 0, 116, 41, // Skip to: 25557
+/* 14945 */ MCD_OPC_Decode, 172, 9, 58, // Opcode: SQSHLvvi_2S
+/* 14949 */ MCD_OPC_FilterValue, 1, 108, 41, // Skip to: 25557
+/* 14953 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ...
+/* 14956 */ MCD_OPC_FilterValue, 0, 216, 0, // Skip to: 15176
+/* 14960 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 14963 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 15089
+/* 14967 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 14970 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 15058
+/* 14974 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 14977 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15027
+/* 14981 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 14984 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14996
+/* 14988 */ MCD_OPC_CheckPredicate, 0, 69, 41, // Skip to: 25557
+/* 14992 */ MCD_OPC_Decode, 244, 6, 59, // Opcode: MOVIvi_lsl_4H
+/* 14996 */ MCD_OPC_FilterValue, 1, 61, 41, // Skip to: 25557
+/* 15000 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15003 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15015
+/* 15007 */ MCD_OPC_CheckPredicate, 0, 50, 41, // Skip to: 25557
+/* 15011 */ MCD_OPC_Decode, 173, 8, 60, // Opcode: SHRNvvi_8B
+/* 15015 */ MCD_OPC_FilterValue, 1, 42, 41, // Skip to: 25557
+/* 15019 */ MCD_OPC_CheckPredicate, 0, 38, 41, // Skip to: 25557
+/* 15023 */ MCD_OPC_Decode, 240, 9, 61, // Opcode: SSHLLvvi_8B
+/* 15027 */ MCD_OPC_FilterValue, 1, 30, 41, // Skip to: 25557
+/* 15031 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15034 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15046
+/* 15038 */ MCD_OPC_CheckPredicate, 0, 19, 41, // Skip to: 25557
+/* 15042 */ MCD_OPC_Decode, 171, 8, 62, // Opcode: SHRNvvi_4H
+/* 15046 */ MCD_OPC_FilterValue, 1, 11, 41, // Skip to: 25557
+/* 15050 */ MCD_OPC_CheckPredicate, 0, 7, 41, // Skip to: 25557
+/* 15054 */ MCD_OPC_Decode, 238, 9, 63, // Opcode: SSHLLvvi_4H
+/* 15058 */ MCD_OPC_FilterValue, 1, 255, 40, // Skip to: 25557
+/* 15062 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15065 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15077
+/* 15069 */ MCD_OPC_CheckPredicate, 0, 244, 40, // Skip to: 25557
+/* 15073 */ MCD_OPC_Decode, 170, 8, 64, // Opcode: SHRNvvi_2S
+/* 15077 */ MCD_OPC_FilterValue, 1, 236, 40, // Skip to: 25557
+/* 15081 */ MCD_OPC_CheckPredicate, 0, 232, 40, // Skip to: 25557
+/* 15085 */ MCD_OPC_Decode, 237, 9, 65, // Opcode: SSHLLvvi_2S
+/* 15089 */ MCD_OPC_FilterValue, 1, 224, 40, // Skip to: 25557
+/* 15093 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15096 */ MCD_OPC_FilterValue, 0, 58, 0, // Skip to: 15158
+/* 15100 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15103 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 15140
+/* 15107 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 15110 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15122
+/* 15114 */ MCD_OPC_CheckPredicate, 0, 199, 40, // Skip to: 25557
+/* 15118 */ MCD_OPC_Decode, 163, 7, 66, // Opcode: ORRvi_lsl_4H
+/* 15122 */ MCD_OPC_FilterValue, 1, 191, 40, // Skip to: 25557
+/* 15126 */ MCD_OPC_CheckPredicate, 0, 187, 40, // Skip to: 25557
+/* 15130 */ MCD_OPC_CheckField, 13, 1, 0, 181, 40, // Skip to: 25557
+/* 15136 */ MCD_OPC_Decode, 188, 9, 60, // Opcode: SQSHRNvvi_8B
+/* 15140 */ MCD_OPC_FilterValue, 1, 173, 40, // Skip to: 25557
+/* 15144 */ MCD_OPC_CheckPredicate, 0, 169, 40, // Skip to: 25557
+/* 15148 */ MCD_OPC_CheckField, 13, 1, 0, 163, 40, // Skip to: 25557
+/* 15154 */ MCD_OPC_Decode, 186, 9, 62, // Opcode: SQSHRNvvi_4H
+/* 15158 */ MCD_OPC_FilterValue, 1, 155, 40, // Skip to: 25557
+/* 15162 */ MCD_OPC_CheckPredicate, 0, 151, 40, // Skip to: 25557
+/* 15166 */ MCD_OPC_CheckField, 13, 1, 0, 145, 40, // Skip to: 25557
+/* 15172 */ MCD_OPC_Decode, 185, 9, 64, // Opcode: SQSHRNvvi_2S
+/* 15176 */ MCD_OPC_FilterValue, 1, 137, 40, // Skip to: 25557
+/* 15180 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15183 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15201
+/* 15187 */ MCD_OPC_CheckPredicate, 0, 126, 40, // Skip to: 25557
+/* 15191 */ MCD_OPC_CheckField, 19, 3, 0, 120, 40, // Skip to: 25557
+/* 15197 */ MCD_OPC_Decode, 247, 6, 67, // Opcode: MOVIvi_msl_2S
+/* 15201 */ MCD_OPC_FilterValue, 1, 112, 40, // Skip to: 25557
+/* 15205 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 15208 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 15245
+/* 15212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15215 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15233
+/* 15219 */ MCD_OPC_CheckPredicate, 0, 94, 40, // Skip to: 25557
+/* 15223 */ MCD_OPC_CheckField, 19, 2, 0, 88, 40, // Skip to: 25557
+/* 15229 */ MCD_OPC_Decode, 242, 6, 68, // Opcode: MOVIvi_8B
+/* 15233 */ MCD_OPC_FilterValue, 1, 80, 40, // Skip to: 25557
+/* 15237 */ MCD_OPC_CheckPredicate, 0, 76, 40, // Skip to: 25557
+/* 15241 */ MCD_OPC_Decode, 133, 13, 51, // Opcode: VCVTxs2f_2S
+/* 15245 */ MCD_OPC_FilterValue, 1, 68, 40, // Skip to: 25557
+/* 15249 */ MCD_OPC_CheckPredicate, 0, 64, 40, // Skip to: 25557
+/* 15253 */ MCD_OPC_CheckField, 19, 3, 0, 58, 40, // Skip to: 25557
+/* 15259 */ MCD_OPC_Decode, 192, 4, 68, // Opcode: FMOVvi_2S
+/* 15263 */ MCD_OPC_FilterValue, 3, 50, 40, // Skip to: 25557
+/* 15267 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 15270 */ MCD_OPC_FilterValue, 8, 52, 0, // Skip to: 15326
+/* 15274 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15277 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 15314
+/* 15281 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15302
+/* 15288 */ MCD_OPC_CheckPredicate, 0, 25, 40, // Skip to: 25557
+/* 15292 */ MCD_OPC_CheckField, 19, 1, 1, 19, 40, // Skip to: 25557
+/* 15298 */ MCD_OPC_Decode, 220, 7, 60, // Opcode: RSHRNvvi_8B
+/* 15302 */ MCD_OPC_FilterValue, 1, 11, 40, // Skip to: 25557
+/* 15306 */ MCD_OPC_CheckPredicate, 0, 7, 40, // Skip to: 25557
+/* 15310 */ MCD_OPC_Decode, 218, 7, 62, // Opcode: RSHRNvvi_4H
+/* 15314 */ MCD_OPC_FilterValue, 1, 255, 39, // Skip to: 25557
+/* 15318 */ MCD_OPC_CheckPredicate, 0, 251, 39, // Skip to: 25557
+/* 15322 */ MCD_OPC_Decode, 217, 7, 64, // Opcode: RSHRNvvi_2S
+/* 15326 */ MCD_OPC_FilterValue, 9, 52, 0, // Skip to: 15382
+/* 15330 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15333 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 15370
+/* 15337 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15340 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15358
+/* 15344 */ MCD_OPC_CheckPredicate, 0, 225, 39, // Skip to: 25557
+/* 15348 */ MCD_OPC_CheckField, 19, 1, 1, 219, 39, // Skip to: 25557
+/* 15354 */ MCD_OPC_Decode, 157, 9, 60, // Opcode: SQRSHRNvvi_8B
+/* 15358 */ MCD_OPC_FilterValue, 1, 211, 39, // Skip to: 25557
+/* 15362 */ MCD_OPC_CheckPredicate, 0, 207, 39, // Skip to: 25557
+/* 15366 */ MCD_OPC_Decode, 155, 9, 62, // Opcode: SQRSHRNvvi_4H
+/* 15370 */ MCD_OPC_FilterValue, 1, 199, 39, // Skip to: 25557
+/* 15374 */ MCD_OPC_CheckPredicate, 0, 195, 39, // Skip to: 25557
+/* 15378 */ MCD_OPC_Decode, 154, 9, 64, // Opcode: SQRSHRNvvi_2S
+/* 15382 */ MCD_OPC_FilterValue, 15, 187, 39, // Skip to: 25557
+/* 15386 */ MCD_OPC_CheckPredicate, 0, 183, 39, // Skip to: 25557
+/* 15390 */ MCD_OPC_CheckField, 21, 1, 1, 177, 39, // Skip to: 25557
+/* 15396 */ MCD_OPC_Decode, 255, 12, 51, // Opcode: VCVTf2xs_2S
+/* 15400 */ MCD_OPC_FilterValue, 1, 83, 3, // Skip to: 16255
+/* 15404 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 15407 */ MCD_OPC_FilterValue, 1, 195, 2, // Skip to: 16118
+/* 15411 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 15414 */ MCD_OPC_FilterValue, 0, 143, 1, // Skip to: 15817
+/* 15418 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 15421 */ MCD_OPC_FilterValue, 0, 194, 0, // Skip to: 15619
+/* 15425 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15428 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 15564
+/* 15432 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15435 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 15509
+/* 15439 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 15442 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15454
+/* 15446 */ MCD_OPC_CheckPredicate, 0, 123, 39, // Skip to: 25557
+/* 15450 */ MCD_OPC_Decode, 138, 7, 48, // Opcode: MVNIvi_lsl_2S
+/* 15454 */ MCD_OPC_FilterValue, 1, 115, 39, // Skip to: 25557
+/* 15458 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15461 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15473
+/* 15465 */ MCD_OPC_CheckPredicate, 0, 104, 39, // Skip to: 25557
+/* 15469 */ MCD_OPC_Decode, 229, 12, 49, // Opcode: USHRvvi_8B
+/* 15473 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15485
+/* 15477 */ MCD_OPC_CheckPredicate, 0, 92, 39, // Skip to: 25557
+/* 15481 */ MCD_OPC_Decode, 201, 12, 49, // Opcode: URSHRvvi_8B
+/* 15485 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15497
+/* 15489 */ MCD_OPC_CheckPredicate, 0, 80, 39, // Skip to: 25557
+/* 15493 */ MCD_OPC_Decode, 212, 9, 53, // Opcode: SRIvvi_8B
+/* 15497 */ MCD_OPC_FilterValue, 3, 72, 39, // Skip to: 25557
+/* 15501 */ MCD_OPC_CheckPredicate, 0, 68, 39, // Skip to: 25557
+/* 15505 */ MCD_OPC_Decode, 164, 9, 54, // Opcode: SQSHLUvvi_8B
+/* 15509 */ MCD_OPC_FilterValue, 1, 60, 39, // Skip to: 25557
+/* 15513 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15516 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15528
+/* 15520 */ MCD_OPC_CheckPredicate, 0, 49, 39, // Skip to: 25557
+/* 15524 */ MCD_OPC_Decode, 227, 12, 50, // Opcode: USHRvvi_4H
+/* 15528 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15540
+/* 15532 */ MCD_OPC_CheckPredicate, 0, 37, 39, // Skip to: 25557
+/* 15536 */ MCD_OPC_Decode, 199, 12, 50, // Opcode: URSHRvvi_4H
+/* 15540 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15552
+/* 15544 */ MCD_OPC_CheckPredicate, 0, 25, 39, // Skip to: 25557
+/* 15548 */ MCD_OPC_Decode, 210, 9, 55, // Opcode: SRIvvi_4H
+/* 15552 */ MCD_OPC_FilterValue, 3, 17, 39, // Skip to: 25557
+/* 15556 */ MCD_OPC_CheckPredicate, 0, 13, 39, // Skip to: 25557
+/* 15560 */ MCD_OPC_Decode, 162, 9, 56, // Opcode: SQSHLUvvi_4H
+/* 15564 */ MCD_OPC_FilterValue, 1, 5, 39, // Skip to: 25557
+/* 15568 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15571 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15583
+/* 15575 */ MCD_OPC_CheckPredicate, 0, 250, 38, // Skip to: 25557
+/* 15579 */ MCD_OPC_Decode, 226, 12, 51, // Opcode: USHRvvi_2S
+/* 15583 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15595
+/* 15587 */ MCD_OPC_CheckPredicate, 0, 238, 38, // Skip to: 25557
+/* 15591 */ MCD_OPC_Decode, 198, 12, 51, // Opcode: URSHRvvi_2S
+/* 15595 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15607
+/* 15599 */ MCD_OPC_CheckPredicate, 0, 226, 38, // Skip to: 25557
+/* 15603 */ MCD_OPC_Decode, 209, 9, 57, // Opcode: SRIvvi_2S
+/* 15607 */ MCD_OPC_FilterValue, 3, 218, 38, // Skip to: 25557
+/* 15611 */ MCD_OPC_CheckPredicate, 0, 214, 38, // Skip to: 25557
+/* 15615 */ MCD_OPC_Decode, 161, 9, 58, // Opcode: SQSHLUvvi_2S
+/* 15619 */ MCD_OPC_FilterValue, 1, 206, 38, // Skip to: 25557
+/* 15623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15626 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 15762
+/* 15630 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15633 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 15707
+/* 15637 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 15640 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15652
+/* 15644 */ MCD_OPC_CheckPredicate, 0, 181, 38, // Skip to: 25557
+/* 15648 */ MCD_OPC_Decode, 192, 1, 52, // Opcode: BICvi_lsl_2S
+/* 15652 */ MCD_OPC_FilterValue, 1, 173, 38, // Skip to: 25557
+/* 15656 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15659 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15671
+/* 15663 */ MCD_OPC_CheckPredicate, 0, 162, 38, // Skip to: 25557
+/* 15667 */ MCD_OPC_Decode, 236, 12, 53, // Opcode: USRAvvi_8B
+/* 15671 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15683
+/* 15675 */ MCD_OPC_CheckPredicate, 0, 150, 38, // Skip to: 25557
+/* 15679 */ MCD_OPC_Decode, 208, 12, 53, // Opcode: URSRAvvi_8B
+/* 15683 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15695
+/* 15687 */ MCD_OPC_CheckPredicate, 0, 138, 38, // Skip to: 25557
+/* 15691 */ MCD_OPC_Decode, 186, 8, 69, // Opcode: SLIvvi_8B
+/* 15695 */ MCD_OPC_FilterValue, 3, 130, 38, // Skip to: 25557
+/* 15699 */ MCD_OPC_CheckPredicate, 0, 126, 38, // Skip to: 25557
+/* 15703 */ MCD_OPC_Decode, 156, 12, 54, // Opcode: UQSHLvvi_8B
+/* 15707 */ MCD_OPC_FilterValue, 1, 118, 38, // Skip to: 25557
+/* 15711 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15714 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15726
+/* 15718 */ MCD_OPC_CheckPredicate, 0, 107, 38, // Skip to: 25557
+/* 15722 */ MCD_OPC_Decode, 234, 12, 55, // Opcode: USRAvvi_4H
+/* 15726 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15738
+/* 15730 */ MCD_OPC_CheckPredicate, 0, 95, 38, // Skip to: 25557
+/* 15734 */ MCD_OPC_Decode, 206, 12, 55, // Opcode: URSRAvvi_4H
+/* 15738 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15750
+/* 15742 */ MCD_OPC_CheckPredicate, 0, 83, 38, // Skip to: 25557
+/* 15746 */ MCD_OPC_Decode, 184, 8, 70, // Opcode: SLIvvi_4H
+/* 15750 */ MCD_OPC_FilterValue, 3, 75, 38, // Skip to: 25557
+/* 15754 */ MCD_OPC_CheckPredicate, 0, 71, 38, // Skip to: 25557
+/* 15758 */ MCD_OPC_Decode, 154, 12, 56, // Opcode: UQSHLvvi_4H
+/* 15762 */ MCD_OPC_FilterValue, 1, 63, 38, // Skip to: 25557
+/* 15766 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 15769 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15781
+/* 15773 */ MCD_OPC_CheckPredicate, 0, 52, 38, // Skip to: 25557
+/* 15777 */ MCD_OPC_Decode, 233, 12, 57, // Opcode: USRAvvi_2S
+/* 15781 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 15793
+/* 15785 */ MCD_OPC_CheckPredicate, 0, 40, 38, // Skip to: 25557
+/* 15789 */ MCD_OPC_Decode, 205, 12, 57, // Opcode: URSRAvvi_2S
+/* 15793 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 15805
+/* 15797 */ MCD_OPC_CheckPredicate, 0, 28, 38, // Skip to: 25557
+/* 15801 */ MCD_OPC_Decode, 183, 8, 71, // Opcode: SLIvvi_2S
+/* 15805 */ MCD_OPC_FilterValue, 3, 20, 38, // Skip to: 25557
+/* 15809 */ MCD_OPC_CheckPredicate, 0, 16, 38, // Skip to: 25557
+/* 15813 */ MCD_OPC_Decode, 153, 12, 58, // Opcode: UQSHLvvi_2S
+/* 15817 */ MCD_OPC_FilterValue, 1, 8, 38, // Skip to: 25557
+/* 15821 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ...
+/* 15824 */ MCD_OPC_FilterValue, 0, 216, 0, // Skip to: 16044
+/* 15828 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 15831 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 15957
+/* 15835 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15838 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 15926
+/* 15842 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15845 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15895
+/* 15849 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 15852 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15864
+/* 15856 */ MCD_OPC_CheckPredicate, 0, 225, 37, // Skip to: 25557
+/* 15860 */ MCD_OPC_Decode, 139, 7, 59, // Opcode: MVNIvi_lsl_4H
+/* 15864 */ MCD_OPC_FilterValue, 1, 217, 37, // Skip to: 25557
+/* 15868 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15871 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15883
+/* 15875 */ MCD_OPC_CheckPredicate, 0, 206, 37, // Skip to: 25557
+/* 15879 */ MCD_OPC_Decode, 197, 7, 60, // Opcode: QSHRUNvvi_8B
+/* 15883 */ MCD_OPC_FilterValue, 1, 198, 37, // Skip to: 25557
+/* 15887 */ MCD_OPC_CheckPredicate, 0, 194, 37, // Skip to: 25557
+/* 15891 */ MCD_OPC_Decode, 214, 12, 61, // Opcode: USHLLvvi_8B
+/* 15895 */ MCD_OPC_FilterValue, 1, 186, 37, // Skip to: 25557
+/* 15899 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15902 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15914
+/* 15906 */ MCD_OPC_CheckPredicate, 0, 175, 37, // Skip to: 25557
+/* 15910 */ MCD_OPC_Decode, 195, 7, 62, // Opcode: QSHRUNvvi_4H
+/* 15914 */ MCD_OPC_FilterValue, 1, 167, 37, // Skip to: 25557
+/* 15918 */ MCD_OPC_CheckPredicate, 0, 163, 37, // Skip to: 25557
+/* 15922 */ MCD_OPC_Decode, 212, 12, 63, // Opcode: USHLLvvi_4H
+/* 15926 */ MCD_OPC_FilterValue, 1, 155, 37, // Skip to: 25557
+/* 15930 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 15933 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15945
+/* 15937 */ MCD_OPC_CheckPredicate, 0, 144, 37, // Skip to: 25557
+/* 15941 */ MCD_OPC_Decode, 194, 7, 64, // Opcode: QSHRUNvvi_2S
+/* 15945 */ MCD_OPC_FilterValue, 1, 136, 37, // Skip to: 25557
+/* 15949 */ MCD_OPC_CheckPredicate, 0, 132, 37, // Skip to: 25557
+/* 15953 */ MCD_OPC_Decode, 211, 12, 65, // Opcode: USHLLvvi_2S
+/* 15957 */ MCD_OPC_FilterValue, 1, 124, 37, // Skip to: 25557
+/* 15961 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 15964 */ MCD_OPC_FilterValue, 0, 58, 0, // Skip to: 16026
+/* 15968 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 15971 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16008
+/* 15975 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 15978 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15990
+/* 15982 */ MCD_OPC_CheckPredicate, 0, 99, 37, // Skip to: 25557
+/* 15986 */ MCD_OPC_Decode, 193, 1, 66, // Opcode: BICvi_lsl_4H
+/* 15990 */ MCD_OPC_FilterValue, 1, 91, 37, // Skip to: 25557
+/* 15994 */ MCD_OPC_CheckPredicate, 0, 87, 37, // Skip to: 25557
+/* 15998 */ MCD_OPC_CheckField, 13, 1, 0, 81, 37, // Skip to: 25557
+/* 16004 */ MCD_OPC_Decode, 169, 12, 60, // Opcode: UQSHRNvvi_8B
+/* 16008 */ MCD_OPC_FilterValue, 1, 73, 37, // Skip to: 25557
+/* 16012 */ MCD_OPC_CheckPredicate, 0, 69, 37, // Skip to: 25557
+/* 16016 */ MCD_OPC_CheckField, 13, 1, 0, 63, 37, // Skip to: 25557
+/* 16022 */ MCD_OPC_Decode, 167, 12, 62, // Opcode: UQSHRNvvi_4H
+/* 16026 */ MCD_OPC_FilterValue, 1, 55, 37, // Skip to: 25557
+/* 16030 */ MCD_OPC_CheckPredicate, 0, 51, 37, // Skip to: 25557
+/* 16034 */ MCD_OPC_CheckField, 13, 1, 0, 45, 37, // Skip to: 25557
+/* 16040 */ MCD_OPC_Decode, 166, 12, 64, // Opcode: UQSHRNvvi_2S
+/* 16044 */ MCD_OPC_FilterValue, 1, 37, 37, // Skip to: 25557
+/* 16048 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 16051 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16069
+/* 16055 */ MCD_OPC_CheckPredicate, 0, 26, 37, // Skip to: 25557
+/* 16059 */ MCD_OPC_CheckField, 19, 3, 0, 20, 37, // Skip to: 25557
+/* 16065 */ MCD_OPC_Decode, 142, 7, 67, // Opcode: MVNIvi_msl_2S
+/* 16069 */ MCD_OPC_FilterValue, 1, 12, 37, // Skip to: 25557
+/* 16073 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16076 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 16100
+/* 16080 */ MCD_OPC_CheckPredicate, 0, 1, 37, // Skip to: 25557
+/* 16084 */ MCD_OPC_CheckField, 19, 2, 0, 251, 36, // Skip to: 25557
+/* 16090 */ MCD_OPC_CheckField, 12, 1, 0, 245, 36, // Skip to: 25557
+/* 16096 */ MCD_OPC_Decode, 239, 6, 68, // Opcode: MOVIdi
+/* 16100 */ MCD_OPC_FilterValue, 1, 237, 36, // Skip to: 25557
+/* 16104 */ MCD_OPC_CheckPredicate, 0, 233, 36, // Skip to: 25557
+/* 16108 */ MCD_OPC_CheckField, 12, 1, 0, 227, 36, // Skip to: 25557
+/* 16114 */ MCD_OPC_Decode, 136, 13, 51, // Opcode: VCVTxu2f_2S
+/* 16118 */ MCD_OPC_FilterValue, 3, 219, 36, // Skip to: 25557
+/* 16122 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 16125 */ MCD_OPC_FilterValue, 8, 52, 0, // Skip to: 16181
+/* 16129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16132 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16169
+/* 16136 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16139 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16157
+/* 16143 */ MCD_OPC_CheckPredicate, 0, 194, 36, // Skip to: 25557
+/* 16147 */ MCD_OPC_CheckField, 19, 1, 1, 188, 36, // Skip to: 25557
+/* 16153 */ MCD_OPC_Decode, 191, 7, 60, // Opcode: QRSHRUNvvi_8B
+/* 16157 */ MCD_OPC_FilterValue, 1, 180, 36, // Skip to: 25557
+/* 16161 */ MCD_OPC_CheckPredicate, 0, 176, 36, // Skip to: 25557
+/* 16165 */ MCD_OPC_Decode, 189, 7, 62, // Opcode: QRSHRUNvvi_4H
+/* 16169 */ MCD_OPC_FilterValue, 1, 168, 36, // Skip to: 25557
+/* 16173 */ MCD_OPC_CheckPredicate, 0, 164, 36, // Skip to: 25557
+/* 16177 */ MCD_OPC_Decode, 188, 7, 64, // Opcode: QRSHRUNvvi_2S
+/* 16181 */ MCD_OPC_FilterValue, 9, 52, 0, // Skip to: 16237
+/* 16185 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16188 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16225
+/* 16192 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16195 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16213
+/* 16199 */ MCD_OPC_CheckPredicate, 0, 138, 36, // Skip to: 25557
+/* 16203 */ MCD_OPC_CheckField, 19, 1, 1, 132, 36, // Skip to: 25557
+/* 16209 */ MCD_OPC_Decode, 145, 12, 60, // Opcode: UQRSHRNvvi_8B
+/* 16213 */ MCD_OPC_FilterValue, 1, 124, 36, // Skip to: 25557
+/* 16217 */ MCD_OPC_CheckPredicate, 0, 120, 36, // Skip to: 25557
+/* 16221 */ MCD_OPC_Decode, 143, 12, 62, // Opcode: UQRSHRNvvi_4H
+/* 16225 */ MCD_OPC_FilterValue, 1, 112, 36, // Skip to: 25557
+/* 16229 */ MCD_OPC_CheckPredicate, 0, 108, 36, // Skip to: 25557
+/* 16233 */ MCD_OPC_Decode, 142, 12, 64, // Opcode: UQRSHRNvvi_2S
+/* 16237 */ MCD_OPC_FilterValue, 15, 100, 36, // Skip to: 25557
+/* 16241 */ MCD_OPC_CheckPredicate, 0, 96, 36, // Skip to: 25557
+/* 16245 */ MCD_OPC_CheckField, 21, 1, 1, 90, 36, // Skip to: 25557
+/* 16251 */ MCD_OPC_Decode, 130, 13, 51, // Opcode: VCVTf2xu_2S
+/* 16255 */ MCD_OPC_FilterValue, 2, 24, 3, // Skip to: 17051
+/* 16259 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 16262 */ MCD_OPC_FilterValue, 1, 136, 2, // Skip to: 16914
+/* 16266 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 16269 */ MCD_OPC_FilterValue, 0, 71, 1, // Skip to: 16600
+/* 16273 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 16276 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 16402
+/* 16280 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16283 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 16371
+/* 16287 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16290 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 16340
+/* 16294 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 16297 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16309
+/* 16301 */ MCD_OPC_CheckPredicate, 0, 36, 36, // Skip to: 25557
+/* 16305 */ MCD_OPC_Decode, 245, 6, 72, // Opcode: MOVIvi_lsl_4S
+/* 16309 */ MCD_OPC_FilterValue, 1, 28, 36, // Skip to: 25557
+/* 16313 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16316 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16328
+/* 16320 */ MCD_OPC_CheckPredicate, 0, 17, 36, // Skip to: 25557
+/* 16324 */ MCD_OPC_Decode, 250, 9, 73, // Opcode: SSHRvvi_16B
+/* 16328 */ MCD_OPC_FilterValue, 1, 9, 36, // Skip to: 25557
+/* 16332 */ MCD_OPC_CheckPredicate, 0, 5, 36, // Skip to: 25557
+/* 16336 */ MCD_OPC_Decode, 222, 9, 73, // Opcode: SRSHRvvi_16B
+/* 16340 */ MCD_OPC_FilterValue, 1, 253, 35, // Skip to: 25557
+/* 16344 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16347 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16359
+/* 16351 */ MCD_OPC_CheckPredicate, 0, 242, 35, // Skip to: 25557
+/* 16355 */ MCD_OPC_Decode, 128, 10, 74, // Opcode: SSHRvvi_8H
+/* 16359 */ MCD_OPC_FilterValue, 1, 234, 35, // Skip to: 25557
+/* 16363 */ MCD_OPC_CheckPredicate, 0, 230, 35, // Skip to: 25557
+/* 16367 */ MCD_OPC_Decode, 228, 9, 74, // Opcode: SRSHRvvi_8H
+/* 16371 */ MCD_OPC_FilterValue, 1, 222, 35, // Skip to: 25557
+/* 16375 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16378 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16390
+/* 16382 */ MCD_OPC_CheckPredicate, 0, 211, 35, // Skip to: 25557
+/* 16386 */ MCD_OPC_Decode, 254, 9, 75, // Opcode: SSHRvvi_4S
+/* 16390 */ MCD_OPC_FilterValue, 1, 203, 35, // Skip to: 25557
+/* 16394 */ MCD_OPC_CheckPredicate, 0, 199, 35, // Skip to: 25557
+/* 16398 */ MCD_OPC_Decode, 226, 9, 75, // Opcode: SRSHRvvi_4S
+/* 16402 */ MCD_OPC_FilterValue, 1, 191, 35, // Skip to: 25557
+/* 16406 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16409 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 16545
+/* 16413 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16416 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 16490
+/* 16420 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 16423 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16435
+/* 16427 */ MCD_OPC_CheckPredicate, 0, 166, 35, // Skip to: 25557
+/* 16431 */ MCD_OPC_Decode, 164, 7, 76, // Opcode: ORRvi_lsl_4S
+/* 16435 */ MCD_OPC_FilterValue, 1, 158, 35, // Skip to: 25557
+/* 16439 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16442 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16454
+/* 16446 */ MCD_OPC_CheckPredicate, 0, 147, 35, // Skip to: 25557
+/* 16450 */ MCD_OPC_Decode, 129, 10, 77, // Opcode: SSRAvvi_16B
+/* 16454 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16466
+/* 16458 */ MCD_OPC_CheckPredicate, 0, 135, 35, // Skip to: 25557
+/* 16462 */ MCD_OPC_Decode, 229, 9, 77, // Opcode: SRSRAvvi_16B
+/* 16466 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16478
+/* 16470 */ MCD_OPC_CheckPredicate, 0, 123, 35, // Skip to: 25557
+/* 16474 */ MCD_OPC_Decode, 162, 8, 78, // Opcode: SHLvvi_16B
+/* 16478 */ MCD_OPC_FilterValue, 3, 115, 35, // Skip to: 25557
+/* 16482 */ MCD_OPC_CheckPredicate, 0, 111, 35, // Skip to: 25557
+/* 16486 */ MCD_OPC_Decode, 170, 9, 78, // Opcode: SQSHLvvi_16B
+/* 16490 */ MCD_OPC_FilterValue, 1, 103, 35, // Skip to: 25557
+/* 16494 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16497 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16509
+/* 16501 */ MCD_OPC_CheckPredicate, 0, 92, 35, // Skip to: 25557
+/* 16505 */ MCD_OPC_Decode, 135, 10, 79, // Opcode: SSRAvvi_8H
+/* 16509 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16521
+/* 16513 */ MCD_OPC_CheckPredicate, 0, 80, 35, // Skip to: 25557
+/* 16517 */ MCD_OPC_Decode, 235, 9, 79, // Opcode: SRSRAvvi_8H
+/* 16521 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16533
+/* 16525 */ MCD_OPC_CheckPredicate, 0, 68, 35, // Skip to: 25557
+/* 16529 */ MCD_OPC_Decode, 168, 8, 80, // Opcode: SHLvvi_8H
+/* 16533 */ MCD_OPC_FilterValue, 3, 60, 35, // Skip to: 25557
+/* 16537 */ MCD_OPC_CheckPredicate, 0, 56, 35, // Skip to: 25557
+/* 16541 */ MCD_OPC_Decode, 176, 9, 80, // Opcode: SQSHLvvi_8H
+/* 16545 */ MCD_OPC_FilterValue, 1, 48, 35, // Skip to: 25557
+/* 16549 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 16552 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16564
+/* 16556 */ MCD_OPC_CheckPredicate, 0, 37, 35, // Skip to: 25557
+/* 16560 */ MCD_OPC_Decode, 133, 10, 81, // Opcode: SSRAvvi_4S
+/* 16564 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16576
+/* 16568 */ MCD_OPC_CheckPredicate, 0, 25, 35, // Skip to: 25557
+/* 16572 */ MCD_OPC_Decode, 233, 9, 81, // Opcode: SRSRAvvi_4S
+/* 16576 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16588
+/* 16580 */ MCD_OPC_CheckPredicate, 0, 13, 35, // Skip to: 25557
+/* 16584 */ MCD_OPC_Decode, 166, 8, 82, // Opcode: SHLvvi_4S
+/* 16588 */ MCD_OPC_FilterValue, 3, 5, 35, // Skip to: 25557
+/* 16592 */ MCD_OPC_CheckPredicate, 0, 1, 35, // Skip to: 25557
+/* 16596 */ MCD_OPC_Decode, 174, 9, 82, // Opcode: SQSHLvvi_4S
+/* 16600 */ MCD_OPC_FilterValue, 1, 249, 34, // Skip to: 25557
+/* 16604 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ...
+/* 16607 */ MCD_OPC_FilterValue, 0, 216, 0, // Skip to: 16827
+/* 16611 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 16614 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 16740
+/* 16618 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16621 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 16709
+/* 16625 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16628 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 16678
+/* 16632 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 16635 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16647
+/* 16639 */ MCD_OPC_CheckPredicate, 0, 210, 34, // Skip to: 25557
+/* 16643 */ MCD_OPC_Decode, 246, 6, 83, // Opcode: MOVIvi_lsl_8H
+/* 16647 */ MCD_OPC_FilterValue, 1, 202, 34, // Skip to: 25557
+/* 16651 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 16654 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16666
+/* 16658 */ MCD_OPC_CheckPredicate, 0, 191, 34, // Skip to: 25557
+/* 16662 */ MCD_OPC_Decode, 169, 8, 77, // Opcode: SHRNvvi_16B
+/* 16666 */ MCD_OPC_FilterValue, 1, 183, 34, // Skip to: 25557
+/* 16670 */ MCD_OPC_CheckPredicate, 0, 179, 34, // Skip to: 25557
+/* 16674 */ MCD_OPC_Decode, 236, 9, 78, // Opcode: SSHLLvvi_16B
+/* 16678 */ MCD_OPC_FilterValue, 1, 171, 34, // Skip to: 25557
+/* 16682 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 16685 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16697
+/* 16689 */ MCD_OPC_CheckPredicate, 0, 160, 34, // Skip to: 25557
+/* 16693 */ MCD_OPC_Decode, 174, 8, 79, // Opcode: SHRNvvi_8H
+/* 16697 */ MCD_OPC_FilterValue, 1, 152, 34, // Skip to: 25557
+/* 16701 */ MCD_OPC_CheckPredicate, 0, 148, 34, // Skip to: 25557
+/* 16705 */ MCD_OPC_Decode, 241, 9, 80, // Opcode: SSHLLvvi_8H
+/* 16709 */ MCD_OPC_FilterValue, 1, 140, 34, // Skip to: 25557
+/* 16713 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 16716 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16728
+/* 16720 */ MCD_OPC_CheckPredicate, 0, 129, 34, // Skip to: 25557
+/* 16724 */ MCD_OPC_Decode, 172, 8, 81, // Opcode: SHRNvvi_4S
+/* 16728 */ MCD_OPC_FilterValue, 1, 121, 34, // Skip to: 25557
+/* 16732 */ MCD_OPC_CheckPredicate, 0, 117, 34, // Skip to: 25557
+/* 16736 */ MCD_OPC_Decode, 239, 9, 82, // Opcode: SSHLLvvi_4S
+/* 16740 */ MCD_OPC_FilterValue, 1, 109, 34, // Skip to: 25557
+/* 16744 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16747 */ MCD_OPC_FilterValue, 0, 58, 0, // Skip to: 16809
+/* 16751 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16754 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16791
+/* 16758 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 16761 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16773
+/* 16765 */ MCD_OPC_CheckPredicate, 0, 84, 34, // Skip to: 25557
+/* 16769 */ MCD_OPC_Decode, 165, 7, 84, // Opcode: ORRvi_lsl_8H
+/* 16773 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 25557
+/* 16777 */ MCD_OPC_CheckPredicate, 0, 72, 34, // Skip to: 25557
+/* 16781 */ MCD_OPC_CheckField, 13, 1, 0, 66, 34, // Skip to: 25557
+/* 16787 */ MCD_OPC_Decode, 184, 9, 77, // Opcode: SQSHRNvvi_16B
+/* 16791 */ MCD_OPC_FilterValue, 1, 58, 34, // Skip to: 25557
+/* 16795 */ MCD_OPC_CheckPredicate, 0, 54, 34, // Skip to: 25557
+/* 16799 */ MCD_OPC_CheckField, 13, 1, 0, 48, 34, // Skip to: 25557
+/* 16805 */ MCD_OPC_Decode, 189, 9, 79, // Opcode: SQSHRNvvi_8H
+/* 16809 */ MCD_OPC_FilterValue, 1, 40, 34, // Skip to: 25557
+/* 16813 */ MCD_OPC_CheckPredicate, 0, 36, 34, // Skip to: 25557
+/* 16817 */ MCD_OPC_CheckField, 13, 1, 0, 30, 34, // Skip to: 25557
+/* 16823 */ MCD_OPC_Decode, 187, 9, 81, // Opcode: SQSHRNvvi_4S
+/* 16827 */ MCD_OPC_FilterValue, 1, 22, 34, // Skip to: 25557
+/* 16831 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 16834 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16852
+/* 16838 */ MCD_OPC_CheckPredicate, 0, 11, 34, // Skip to: 25557
+/* 16842 */ MCD_OPC_CheckField, 19, 3, 0, 5, 34, // Skip to: 25557
+/* 16848 */ MCD_OPC_Decode, 248, 6, 85, // Opcode: MOVIvi_msl_4S
+/* 16852 */ MCD_OPC_FilterValue, 1, 253, 33, // Skip to: 25557
+/* 16856 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 16859 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16896
+/* 16863 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16866 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16884
+/* 16870 */ MCD_OPC_CheckPredicate, 0, 235, 33, // Skip to: 25557
+/* 16874 */ MCD_OPC_CheckField, 19, 2, 0, 229, 33, // Skip to: 25557
+/* 16880 */ MCD_OPC_Decode, 240, 6, 86, // Opcode: MOVIvi_16B
+/* 16884 */ MCD_OPC_FilterValue, 1, 221, 33, // Skip to: 25557
+/* 16888 */ MCD_OPC_CheckPredicate, 0, 217, 33, // Skip to: 25557
+/* 16892 */ MCD_OPC_Decode, 134, 13, 75, // Opcode: VCVTxs2f_4S
+/* 16896 */ MCD_OPC_FilterValue, 1, 209, 33, // Skip to: 25557
+/* 16900 */ MCD_OPC_CheckPredicate, 0, 205, 33, // Skip to: 25557
+/* 16904 */ MCD_OPC_CheckField, 19, 3, 0, 199, 33, // Skip to: 25557
+/* 16910 */ MCD_OPC_Decode, 193, 4, 86, // Opcode: FMOVvi_4S
+/* 16914 */ MCD_OPC_FilterValue, 3, 191, 33, // Skip to: 25557
+/* 16918 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 16921 */ MCD_OPC_FilterValue, 8, 52, 0, // Skip to: 16977
+/* 16925 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16928 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 16965
+/* 16932 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16935 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16953
+/* 16939 */ MCD_OPC_CheckPredicate, 0, 166, 33, // Skip to: 25557
+/* 16943 */ MCD_OPC_CheckField, 19, 1, 1, 160, 33, // Skip to: 25557
+/* 16949 */ MCD_OPC_Decode, 216, 7, 77, // Opcode: RSHRNvvi_16B
+/* 16953 */ MCD_OPC_FilterValue, 1, 152, 33, // Skip to: 25557
+/* 16957 */ MCD_OPC_CheckPredicate, 0, 148, 33, // Skip to: 25557
+/* 16961 */ MCD_OPC_Decode, 221, 7, 79, // Opcode: RSHRNvvi_8H
+/* 16965 */ MCD_OPC_FilterValue, 1, 140, 33, // Skip to: 25557
+/* 16969 */ MCD_OPC_CheckPredicate, 0, 136, 33, // Skip to: 25557
+/* 16973 */ MCD_OPC_Decode, 219, 7, 81, // Opcode: RSHRNvvi_4S
+/* 16977 */ MCD_OPC_FilterValue, 9, 52, 0, // Skip to: 17033
+/* 16981 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 16984 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 17021
+/* 16988 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 16991 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17009
+/* 16995 */ MCD_OPC_CheckPredicate, 0, 110, 33, // Skip to: 25557
+/* 16999 */ MCD_OPC_CheckField, 19, 1, 1, 104, 33, // Skip to: 25557
+/* 17005 */ MCD_OPC_Decode, 153, 9, 77, // Opcode: SQRSHRNvvi_16B
+/* 17009 */ MCD_OPC_FilterValue, 1, 96, 33, // Skip to: 25557
+/* 17013 */ MCD_OPC_CheckPredicate, 0, 92, 33, // Skip to: 25557
+/* 17017 */ MCD_OPC_Decode, 158, 9, 79, // Opcode: SQRSHRNvvi_8H
+/* 17021 */ MCD_OPC_FilterValue, 1, 84, 33, // Skip to: 25557
+/* 17025 */ MCD_OPC_CheckPredicate, 0, 80, 33, // Skip to: 25557
+/* 17029 */ MCD_OPC_Decode, 156, 9, 81, // Opcode: SQRSHRNvvi_4S
+/* 17033 */ MCD_OPC_FilterValue, 15, 72, 33, // Skip to: 25557
+/* 17037 */ MCD_OPC_CheckPredicate, 0, 68, 33, // Skip to: 25557
+/* 17041 */ MCD_OPC_CheckField, 21, 1, 1, 62, 33, // Skip to: 25557
+/* 17047 */ MCD_OPC_Decode, 128, 13, 75, // Opcode: VCVTf2xs_4S
+/* 17051 */ MCD_OPC_FilterValue, 3, 54, 33, // Skip to: 25557
+/* 17055 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 17058 */ MCD_OPC_FilterValue, 1, 208, 2, // Skip to: 17782
+/* 17062 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 17065 */ MCD_OPC_FilterValue, 0, 143, 1, // Skip to: 17468
+/* 17069 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 17072 */ MCD_OPC_FilterValue, 0, 194, 0, // Skip to: 17270
+/* 17076 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17079 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 17215
+/* 17083 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17086 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 17160
+/* 17090 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 17093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17105
+/* 17097 */ MCD_OPC_CheckPredicate, 0, 8, 33, // Skip to: 25557
+/* 17101 */ MCD_OPC_Decode, 140, 7, 72, // Opcode: MVNIvi_lsl_4S
+/* 17105 */ MCD_OPC_FilterValue, 1, 0, 33, // Skip to: 25557
+/* 17109 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17112 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17124
+/* 17116 */ MCD_OPC_CheckPredicate, 0, 245, 32, // Skip to: 25557
+/* 17120 */ MCD_OPC_Decode, 224, 12, 73, // Opcode: USHRvvi_16B
+/* 17124 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17136
+/* 17128 */ MCD_OPC_CheckPredicate, 0, 233, 32, // Skip to: 25557
+/* 17132 */ MCD_OPC_Decode, 196, 12, 73, // Opcode: URSHRvvi_16B
+/* 17136 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17148
+/* 17140 */ MCD_OPC_CheckPredicate, 0, 221, 32, // Skip to: 25557
+/* 17144 */ MCD_OPC_Decode, 207, 9, 77, // Opcode: SRIvvi_16B
+/* 17148 */ MCD_OPC_FilterValue, 3, 213, 32, // Skip to: 25557
+/* 17152 */ MCD_OPC_CheckPredicate, 0, 209, 32, // Skip to: 25557
+/* 17156 */ MCD_OPC_Decode, 159, 9, 78, // Opcode: SQSHLUvvi_16B
+/* 17160 */ MCD_OPC_FilterValue, 1, 201, 32, // Skip to: 25557
+/* 17164 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17167 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17179
+/* 17171 */ MCD_OPC_CheckPredicate, 0, 190, 32, // Skip to: 25557
+/* 17175 */ MCD_OPC_Decode, 230, 12, 74, // Opcode: USHRvvi_8H
+/* 17179 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17191
+/* 17183 */ MCD_OPC_CheckPredicate, 0, 178, 32, // Skip to: 25557
+/* 17187 */ MCD_OPC_Decode, 202, 12, 74, // Opcode: URSHRvvi_8H
+/* 17191 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17203
+/* 17195 */ MCD_OPC_CheckPredicate, 0, 166, 32, // Skip to: 25557
+/* 17199 */ MCD_OPC_Decode, 213, 9, 79, // Opcode: SRIvvi_8H
+/* 17203 */ MCD_OPC_FilterValue, 3, 158, 32, // Skip to: 25557
+/* 17207 */ MCD_OPC_CheckPredicate, 0, 154, 32, // Skip to: 25557
+/* 17211 */ MCD_OPC_Decode, 165, 9, 80, // Opcode: SQSHLUvvi_8H
+/* 17215 */ MCD_OPC_FilterValue, 1, 146, 32, // Skip to: 25557
+/* 17219 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17222 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17234
+/* 17226 */ MCD_OPC_CheckPredicate, 0, 135, 32, // Skip to: 25557
+/* 17230 */ MCD_OPC_Decode, 228, 12, 75, // Opcode: USHRvvi_4S
+/* 17234 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17246
+/* 17238 */ MCD_OPC_CheckPredicate, 0, 123, 32, // Skip to: 25557
+/* 17242 */ MCD_OPC_Decode, 200, 12, 75, // Opcode: URSHRvvi_4S
+/* 17246 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17258
+/* 17250 */ MCD_OPC_CheckPredicate, 0, 111, 32, // Skip to: 25557
+/* 17254 */ MCD_OPC_Decode, 211, 9, 81, // Opcode: SRIvvi_4S
+/* 17258 */ MCD_OPC_FilterValue, 3, 103, 32, // Skip to: 25557
+/* 17262 */ MCD_OPC_CheckPredicate, 0, 99, 32, // Skip to: 25557
+/* 17266 */ MCD_OPC_Decode, 163, 9, 82, // Opcode: SQSHLUvvi_4S
+/* 17270 */ MCD_OPC_FilterValue, 1, 91, 32, // Skip to: 25557
+/* 17274 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17277 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 17413
+/* 17281 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17284 */ MCD_OPC_FilterValue, 0, 70, 0, // Skip to: 17358
+/* 17288 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 17291 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17303
+/* 17295 */ MCD_OPC_CheckPredicate, 0, 66, 32, // Skip to: 25557
+/* 17299 */ MCD_OPC_Decode, 194, 1, 76, // Opcode: BICvi_lsl_4S
+/* 17303 */ MCD_OPC_FilterValue, 1, 58, 32, // Skip to: 25557
+/* 17307 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17310 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17322
+/* 17314 */ MCD_OPC_CheckPredicate, 0, 47, 32, // Skip to: 25557
+/* 17318 */ MCD_OPC_Decode, 231, 12, 77, // Opcode: USRAvvi_16B
+/* 17322 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17334
+/* 17326 */ MCD_OPC_CheckPredicate, 0, 35, 32, // Skip to: 25557
+/* 17330 */ MCD_OPC_Decode, 203, 12, 77, // Opcode: URSRAvvi_16B
+/* 17334 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17346
+/* 17338 */ MCD_OPC_CheckPredicate, 0, 23, 32, // Skip to: 25557
+/* 17342 */ MCD_OPC_Decode, 181, 8, 87, // Opcode: SLIvvi_16B
+/* 17346 */ MCD_OPC_FilterValue, 3, 15, 32, // Skip to: 25557
+/* 17350 */ MCD_OPC_CheckPredicate, 0, 11, 32, // Skip to: 25557
+/* 17354 */ MCD_OPC_Decode, 151, 12, 78, // Opcode: UQSHLvvi_16B
+/* 17358 */ MCD_OPC_FilterValue, 1, 3, 32, // Skip to: 25557
+/* 17362 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17365 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17377
+/* 17369 */ MCD_OPC_CheckPredicate, 0, 248, 31, // Skip to: 25557
+/* 17373 */ MCD_OPC_Decode, 237, 12, 79, // Opcode: USRAvvi_8H
+/* 17377 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17389
+/* 17381 */ MCD_OPC_CheckPredicate, 0, 236, 31, // Skip to: 25557
+/* 17385 */ MCD_OPC_Decode, 209, 12, 79, // Opcode: URSRAvvi_8H
+/* 17389 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17401
+/* 17393 */ MCD_OPC_CheckPredicate, 0, 224, 31, // Skip to: 25557
+/* 17397 */ MCD_OPC_Decode, 187, 8, 88, // Opcode: SLIvvi_8H
+/* 17401 */ MCD_OPC_FilterValue, 3, 216, 31, // Skip to: 25557
+/* 17405 */ MCD_OPC_CheckPredicate, 0, 212, 31, // Skip to: 25557
+/* 17409 */ MCD_OPC_Decode, 157, 12, 80, // Opcode: UQSHLvvi_8H
+/* 17413 */ MCD_OPC_FilterValue, 1, 204, 31, // Skip to: 25557
+/* 17417 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ...
+/* 17420 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17432
+/* 17424 */ MCD_OPC_CheckPredicate, 0, 193, 31, // Skip to: 25557
+/* 17428 */ MCD_OPC_Decode, 235, 12, 81, // Opcode: USRAvvi_4S
+/* 17432 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 17444
+/* 17436 */ MCD_OPC_CheckPredicate, 0, 181, 31, // Skip to: 25557
+/* 17440 */ MCD_OPC_Decode, 207, 12, 81, // Opcode: URSRAvvi_4S
+/* 17444 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17456
+/* 17448 */ MCD_OPC_CheckPredicate, 0, 169, 31, // Skip to: 25557
+/* 17452 */ MCD_OPC_Decode, 185, 8, 89, // Opcode: SLIvvi_4S
+/* 17456 */ MCD_OPC_FilterValue, 3, 161, 31, // Skip to: 25557
+/* 17460 */ MCD_OPC_CheckPredicate, 0, 157, 31, // Skip to: 25557
+/* 17464 */ MCD_OPC_Decode, 155, 12, 82, // Opcode: UQSHLvvi_4S
+/* 17468 */ MCD_OPC_FilterValue, 1, 149, 31, // Skip to: 25557
+/* 17472 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ...
+/* 17475 */ MCD_OPC_FilterValue, 0, 216, 0, // Skip to: 17695
+/* 17479 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 17482 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 17608
+/* 17486 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17489 */ MCD_OPC_FilterValue, 0, 84, 0, // Skip to: 17577
+/* 17493 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17496 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 17546
+/* 17500 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 17503 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17515
+/* 17507 */ MCD_OPC_CheckPredicate, 0, 110, 31, // Skip to: 25557
+/* 17511 */ MCD_OPC_Decode, 141, 7, 83, // Opcode: MVNIvi_lsl_8H
+/* 17515 */ MCD_OPC_FilterValue, 1, 102, 31, // Skip to: 25557
+/* 17519 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 17522 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17534
+/* 17526 */ MCD_OPC_CheckPredicate, 0, 91, 31, // Skip to: 25557
+/* 17530 */ MCD_OPC_Decode, 193, 7, 77, // Opcode: QSHRUNvvi_16B
+/* 17534 */ MCD_OPC_FilterValue, 1, 83, 31, // Skip to: 25557
+/* 17538 */ MCD_OPC_CheckPredicate, 0, 79, 31, // Skip to: 25557
+/* 17542 */ MCD_OPC_Decode, 210, 12, 78, // Opcode: USHLLvvi_16B
+/* 17546 */ MCD_OPC_FilterValue, 1, 71, 31, // Skip to: 25557
+/* 17550 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 17553 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17565
+/* 17557 */ MCD_OPC_CheckPredicate, 0, 60, 31, // Skip to: 25557
+/* 17561 */ MCD_OPC_Decode, 198, 7, 79, // Opcode: QSHRUNvvi_8H
+/* 17565 */ MCD_OPC_FilterValue, 1, 52, 31, // Skip to: 25557
+/* 17569 */ MCD_OPC_CheckPredicate, 0, 48, 31, // Skip to: 25557
+/* 17573 */ MCD_OPC_Decode, 215, 12, 80, // Opcode: USHLLvvi_8H
+/* 17577 */ MCD_OPC_FilterValue, 1, 40, 31, // Skip to: 25557
+/* 17581 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 17584 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17596
+/* 17588 */ MCD_OPC_CheckPredicate, 0, 29, 31, // Skip to: 25557
+/* 17592 */ MCD_OPC_Decode, 196, 7, 81, // Opcode: QSHRUNvvi_4S
+/* 17596 */ MCD_OPC_FilterValue, 1, 21, 31, // Skip to: 25557
+/* 17600 */ MCD_OPC_CheckPredicate, 0, 17, 31, // Skip to: 25557
+/* 17604 */ MCD_OPC_Decode, 213, 12, 82, // Opcode: USHLLvvi_4S
+/* 17608 */ MCD_OPC_FilterValue, 1, 9, 31, // Skip to: 25557
+/* 17612 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17615 */ MCD_OPC_FilterValue, 0, 58, 0, // Skip to: 17677
+/* 17619 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17622 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 17659
+/* 17626 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ...
+/* 17629 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 17641
+/* 17633 */ MCD_OPC_CheckPredicate, 0, 240, 30, // Skip to: 25557
+/* 17637 */ MCD_OPC_Decode, 195, 1, 84, // Opcode: BICvi_lsl_8H
+/* 17641 */ MCD_OPC_FilterValue, 1, 232, 30, // Skip to: 25557
+/* 17645 */ MCD_OPC_CheckPredicate, 0, 228, 30, // Skip to: 25557
+/* 17649 */ MCD_OPC_CheckField, 13, 1, 0, 222, 30, // Skip to: 25557
+/* 17655 */ MCD_OPC_Decode, 165, 12, 77, // Opcode: UQSHRNvvi_16B
+/* 17659 */ MCD_OPC_FilterValue, 1, 214, 30, // Skip to: 25557
+/* 17663 */ MCD_OPC_CheckPredicate, 0, 210, 30, // Skip to: 25557
+/* 17667 */ MCD_OPC_CheckField, 13, 1, 0, 204, 30, // Skip to: 25557
+/* 17673 */ MCD_OPC_Decode, 170, 12, 79, // Opcode: UQSHRNvvi_8H
+/* 17677 */ MCD_OPC_FilterValue, 1, 196, 30, // Skip to: 25557
+/* 17681 */ MCD_OPC_CheckPredicate, 0, 192, 30, // Skip to: 25557
+/* 17685 */ MCD_OPC_CheckField, 13, 1, 0, 186, 30, // Skip to: 25557
+/* 17691 */ MCD_OPC_Decode, 168, 12, 81, // Opcode: UQSHRNvvi_4S
+/* 17695 */ MCD_OPC_FilterValue, 1, 178, 30, // Skip to: 25557
+/* 17699 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 17702 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17720
+/* 17706 */ MCD_OPC_CheckPredicate, 0, 167, 30, // Skip to: 25557
+/* 17710 */ MCD_OPC_CheckField, 19, 3, 0, 161, 30, // Skip to: 25557
+/* 17716 */ MCD_OPC_Decode, 143, 7, 85, // Opcode: MVNIvi_msl_4S
+/* 17720 */ MCD_OPC_FilterValue, 1, 153, 30, // Skip to: 25557
+/* 17724 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 17727 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 17764
+/* 17731 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17734 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17752
+/* 17738 */ MCD_OPC_CheckPredicate, 0, 135, 30, // Skip to: 25557
+/* 17742 */ MCD_OPC_CheckField, 19, 2, 0, 129, 30, // Skip to: 25557
+/* 17748 */ MCD_OPC_Decode, 241, 6, 86, // Opcode: MOVIvi_2D
+/* 17752 */ MCD_OPC_FilterValue, 1, 121, 30, // Skip to: 25557
+/* 17756 */ MCD_OPC_CheckPredicate, 0, 117, 30, // Skip to: 25557
+/* 17760 */ MCD_OPC_Decode, 137, 13, 75, // Opcode: VCVTxu2f_4S
+/* 17764 */ MCD_OPC_FilterValue, 1, 109, 30, // Skip to: 25557
+/* 17768 */ MCD_OPC_CheckPredicate, 0, 105, 30, // Skip to: 25557
+/* 17772 */ MCD_OPC_CheckField, 19, 3, 0, 99, 30, // Skip to: 25557
+/* 17778 */ MCD_OPC_Decode, 191, 4, 86, // Opcode: FMOVvi_2D
+/* 17782 */ MCD_OPC_FilterValue, 3, 91, 30, // Skip to: 25557
+/* 17786 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 17789 */ MCD_OPC_FilterValue, 8, 52, 0, // Skip to: 17845
+/* 17793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17796 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 17833
+/* 17800 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17803 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17821
+/* 17807 */ MCD_OPC_CheckPredicate, 0, 66, 30, // Skip to: 25557
+/* 17811 */ MCD_OPC_CheckField, 19, 1, 1, 60, 30, // Skip to: 25557
+/* 17817 */ MCD_OPC_Decode, 187, 7, 77, // Opcode: QRSHRUNvvi_16B
+/* 17821 */ MCD_OPC_FilterValue, 1, 52, 30, // Skip to: 25557
+/* 17825 */ MCD_OPC_CheckPredicate, 0, 48, 30, // Skip to: 25557
+/* 17829 */ MCD_OPC_Decode, 192, 7, 79, // Opcode: QRSHRUNvvi_8H
+/* 17833 */ MCD_OPC_FilterValue, 1, 40, 30, // Skip to: 25557
+/* 17837 */ MCD_OPC_CheckPredicate, 0, 36, 30, // Skip to: 25557
+/* 17841 */ MCD_OPC_Decode, 190, 7, 81, // Opcode: QRSHRUNvvi_4S
+/* 17845 */ MCD_OPC_FilterValue, 9, 52, 0, // Skip to: 17901
+/* 17849 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 17852 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 17889
+/* 17856 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 17859 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17877
+/* 17863 */ MCD_OPC_CheckPredicate, 0, 10, 30, // Skip to: 25557
+/* 17867 */ MCD_OPC_CheckField, 19, 1, 1, 4, 30, // Skip to: 25557
+/* 17873 */ MCD_OPC_Decode, 141, 12, 77, // Opcode: UQRSHRNvvi_16B
+/* 17877 */ MCD_OPC_FilterValue, 1, 252, 29, // Skip to: 25557
+/* 17881 */ MCD_OPC_CheckPredicate, 0, 248, 29, // Skip to: 25557
+/* 17885 */ MCD_OPC_Decode, 146, 12, 79, // Opcode: UQRSHRNvvi_8H
+/* 17889 */ MCD_OPC_FilterValue, 1, 240, 29, // Skip to: 25557
+/* 17893 */ MCD_OPC_CheckPredicate, 0, 236, 29, // Skip to: 25557
+/* 17897 */ MCD_OPC_Decode, 144, 12, 81, // Opcode: UQRSHRNvvi_4S
+/* 17901 */ MCD_OPC_FilterValue, 15, 228, 29, // Skip to: 25557
+/* 17905 */ MCD_OPC_CheckPredicate, 0, 224, 29, // Skip to: 25557
+/* 17909 */ MCD_OPC_CheckField, 21, 1, 1, 218, 29, // Skip to: 25557
+/* 17915 */ MCD_OPC_Decode, 131, 13, 75, // Opcode: VCVTf2xu_4S
+/* 17919 */ MCD_OPC_FilterValue, 13, 210, 29, // Skip to: 25557
+/* 17923 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 17926 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 17957
+/* 17930 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 17933 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17945
+/* 17937 */ MCD_OPC_CheckPredicate, 0, 192, 29, // Skip to: 25557
+/* 17941 */ MCD_OPC_Decode, 251, 9, 90, // Opcode: SSHRvvi_2D
+/* 17945 */ MCD_OPC_FilterValue, 3, 184, 29, // Skip to: 25557
+/* 17949 */ MCD_OPC_CheckPredicate, 0, 180, 29, // Skip to: 25557
+/* 17953 */ MCD_OPC_Decode, 225, 12, 90, // Opcode: USHRvvi_2D
+/* 17957 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 17988
+/* 17961 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 17964 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 17976
+/* 17968 */ MCD_OPC_CheckPredicate, 0, 161, 29, // Skip to: 25557
+/* 17972 */ MCD_OPC_Decode, 130, 10, 91, // Opcode: SSRAvvi_2D
+/* 17976 */ MCD_OPC_FilterValue, 3, 153, 29, // Skip to: 25557
+/* 17980 */ MCD_OPC_CheckPredicate, 0, 149, 29, // Skip to: 25557
+/* 17984 */ MCD_OPC_Decode, 232, 12, 91, // Opcode: USRAvvi_2D
+/* 17988 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 18019
+/* 17992 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 17995 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18007
+/* 17999 */ MCD_OPC_CheckPredicate, 0, 130, 29, // Skip to: 25557
+/* 18003 */ MCD_OPC_Decode, 223, 9, 90, // Opcode: SRSHRvvi_2D
+/* 18007 */ MCD_OPC_FilterValue, 3, 122, 29, // Skip to: 25557
+/* 18011 */ MCD_OPC_CheckPredicate, 0, 118, 29, // Skip to: 25557
+/* 18015 */ MCD_OPC_Decode, 197, 12, 90, // Opcode: URSHRvvi_2D
+/* 18019 */ MCD_OPC_FilterValue, 13, 27, 0, // Skip to: 18050
+/* 18023 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18026 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18038
+/* 18030 */ MCD_OPC_CheckPredicate, 0, 99, 29, // Skip to: 25557
+/* 18034 */ MCD_OPC_Decode, 230, 9, 91, // Opcode: SRSRAvvi_2D
+/* 18038 */ MCD_OPC_FilterValue, 3, 91, 29, // Skip to: 25557
+/* 18042 */ MCD_OPC_CheckPredicate, 0, 87, 29, // Skip to: 25557
+/* 18046 */ MCD_OPC_Decode, 204, 12, 91, // Opcode: URSRAvvi_2D
+/* 18050 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 18068
+/* 18054 */ MCD_OPC_CheckPredicate, 0, 75, 29, // Skip to: 25557
+/* 18058 */ MCD_OPC_CheckField, 29, 3, 3, 69, 29, // Skip to: 25557
+/* 18064 */ MCD_OPC_Decode, 208, 9, 91, // Opcode: SRIvvi_2D
+/* 18068 */ MCD_OPC_FilterValue, 21, 27, 0, // Skip to: 18099
+/* 18072 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18075 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18087
+/* 18079 */ MCD_OPC_CheckPredicate, 0, 50, 29, // Skip to: 25557
+/* 18083 */ MCD_OPC_Decode, 163, 8, 92, // Opcode: SHLvvi_2D
+/* 18087 */ MCD_OPC_FilterValue, 3, 42, 29, // Skip to: 25557
+/* 18091 */ MCD_OPC_CheckPredicate, 0, 38, 29, // Skip to: 25557
+/* 18095 */ MCD_OPC_Decode, 182, 8, 93, // Opcode: SLIvvi_2D
+/* 18099 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 18117
+/* 18103 */ MCD_OPC_CheckPredicate, 0, 26, 29, // Skip to: 25557
+/* 18107 */ MCD_OPC_CheckField, 29, 3, 3, 20, 29, // Skip to: 25557
+/* 18113 */ MCD_OPC_Decode, 160, 9, 92, // Opcode: SQSHLUvvi_2D
+/* 18117 */ MCD_OPC_FilterValue, 29, 27, 0, // Skip to: 18148
+/* 18121 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18124 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18136
+/* 18128 */ MCD_OPC_CheckPredicate, 0, 1, 29, // Skip to: 25557
+/* 18132 */ MCD_OPC_Decode, 171, 9, 92, // Opcode: SQSHLvvi_2D
+/* 18136 */ MCD_OPC_FilterValue, 3, 249, 28, // Skip to: 25557
+/* 18140 */ MCD_OPC_CheckPredicate, 0, 245, 28, // Skip to: 25557
+/* 18144 */ MCD_OPC_Decode, 152, 12, 92, // Opcode: UQSHLvvi_2D
+/* 18148 */ MCD_OPC_FilterValue, 57, 27, 0, // Skip to: 18179
+/* 18152 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18155 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18167
+/* 18159 */ MCD_OPC_CheckPredicate, 0, 226, 28, // Skip to: 25557
+/* 18163 */ MCD_OPC_Decode, 132, 13, 90, // Opcode: VCVTxs2f_2D
+/* 18167 */ MCD_OPC_FilterValue, 3, 218, 28, // Skip to: 25557
+/* 18171 */ MCD_OPC_CheckPredicate, 0, 214, 28, // Skip to: 25557
+/* 18175 */ MCD_OPC_Decode, 135, 13, 90, // Opcode: VCVTxu2f_2D
+/* 18179 */ MCD_OPC_FilterValue, 63, 206, 28, // Skip to: 25557
+/* 18183 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18186 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 18198
+/* 18190 */ MCD_OPC_CheckPredicate, 0, 195, 28, // Skip to: 25557
+/* 18194 */ MCD_OPC_Decode, 254, 12, 90, // Opcode: VCVTf2xs_2D
+/* 18198 */ MCD_OPC_FilterValue, 3, 187, 28, // Skip to: 25557
+/* 18202 */ MCD_OPC_CheckPredicate, 0, 183, 28, // Skip to: 25557
+/* 18206 */ MCD_OPC_Decode, 129, 13, 90, // Opcode: VCVTf2xu_2D
+/* 18210 */ MCD_OPC_FilterValue, 4, 167, 2, // Skip to: 18893
+/* 18214 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 18217 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 18238
+/* 18221 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 18224 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18231
+/* 18228 */ MCD_OPC_Decode, 102, 94, // Opcode: ADRxi
+/* 18231 */ MCD_OPC_FilterValue, 1, 154, 28, // Skip to: 25557
+/* 18235 */ MCD_OPC_Decode, 101, 94, // Opcode: ADRPxi
+/* 18238 */ MCD_OPC_FilterValue, 1, 255, 0, // Skip to: 18497
+/* 18242 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18245 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 18266
+/* 18249 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18252 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18259
+/* 18256 */ MCD_OPC_Decode, 67, 95, // Opcode: ADDwwi_lsl0_s
+/* 18259 */ MCD_OPC_FilterValue, 1, 126, 28, // Skip to: 25557
+/* 18263 */ MCD_OPC_Decode, 70, 95, // Opcode: ADDwwi_lsl12_s
+/* 18266 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 18305
+/* 18270 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18273 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 18289
+/* 18277 */ MCD_OPC_CheckField, 0, 5, 31, 3, 0, // Skip to: 18286
+/* 18283 */ MCD_OPC_Decode, 66, 96, // Opcode: ADDwwi_lsl0_cmp
+/* 18286 */ MCD_OPC_Decode, 65, 97, // Opcode: ADDwwi_lsl0_S
+/* 18289 */ MCD_OPC_FilterValue, 1, 96, 28, // Skip to: 25557
+/* 18293 */ MCD_OPC_CheckField, 0, 5, 31, 3, 0, // Skip to: 18302
+/* 18299 */ MCD_OPC_Decode, 69, 96, // Opcode: ADDwwi_lsl12_cmp
+/* 18302 */ MCD_OPC_Decode, 68, 97, // Opcode: ADDwwi_lsl12_S
+/* 18305 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 18328
+/* 18309 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18312 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18320
+/* 18316 */ MCD_OPC_Decode, 202, 10, 95, // Opcode: SUBwwi_lsl0_s
+/* 18320 */ MCD_OPC_FilterValue, 1, 65, 28, // Skip to: 25557
+/* 18324 */ MCD_OPC_Decode, 205, 10, 95, // Opcode: SUBwwi_lsl12_s
+/* 18328 */ MCD_OPC_FilterValue, 3, 39, 0, // Skip to: 18371
+/* 18332 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18335 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18353
+/* 18339 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 18349
+/* 18345 */ MCD_OPC_Decode, 201, 10, 96, // Opcode: SUBwwi_lsl0_cmp
+/* 18349 */ MCD_OPC_Decode, 200, 10, 97, // Opcode: SUBwwi_lsl0_S
+/* 18353 */ MCD_OPC_FilterValue, 1, 32, 28, // Skip to: 25557
+/* 18357 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 18367
+/* 18363 */ MCD_OPC_Decode, 204, 10, 96, // Opcode: SUBwwi_lsl12_cmp
+/* 18367 */ MCD_OPC_Decode, 203, 10, 97, // Opcode: SUBwwi_lsl12_S
+/* 18371 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 18392
+/* 18375 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18378 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18385
+/* 18382 */ MCD_OPC_Decode, 84, 98, // Opcode: ADDxxi_lsl0_s
+/* 18385 */ MCD_OPC_FilterValue, 1, 0, 28, // Skip to: 25557
+/* 18389 */ MCD_OPC_Decode, 87, 98, // Opcode: ADDxxi_lsl12_s
+/* 18392 */ MCD_OPC_FilterValue, 5, 35, 0, // Skip to: 18431
+/* 18396 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18399 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 18415
+/* 18403 */ MCD_OPC_CheckField, 0, 5, 31, 3, 0, // Skip to: 18412
+/* 18409 */ MCD_OPC_Decode, 83, 99, // Opcode: ADDxxi_lsl0_cmp
+/* 18412 */ MCD_OPC_Decode, 82, 100, // Opcode: ADDxxi_lsl0_S
+/* 18415 */ MCD_OPC_FilterValue, 1, 226, 27, // Skip to: 25557
+/* 18419 */ MCD_OPC_CheckField, 0, 5, 31, 3, 0, // Skip to: 18428
+/* 18425 */ MCD_OPC_Decode, 86, 99, // Opcode: ADDxxi_lsl12_cmp
+/* 18428 */ MCD_OPC_Decode, 85, 100, // Opcode: ADDxxi_lsl12_S
+/* 18431 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 18454
+/* 18435 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18438 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18446
+/* 18442 */ MCD_OPC_Decode, 219, 10, 98, // Opcode: SUBxxi_lsl0_s
+/* 18446 */ MCD_OPC_FilterValue, 1, 195, 27, // Skip to: 25557
+/* 18450 */ MCD_OPC_Decode, 222, 10, 98, // Opcode: SUBxxi_lsl12_s
+/* 18454 */ MCD_OPC_FilterValue, 7, 187, 27, // Skip to: 25557
+/* 18458 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18461 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18479
+/* 18465 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 18475
+/* 18471 */ MCD_OPC_Decode, 218, 10, 99, // Opcode: SUBxxi_lsl0_cmp
+/* 18475 */ MCD_OPC_Decode, 217, 10, 100, // Opcode: SUBxxi_lsl0_S
+/* 18479 */ MCD_OPC_FilterValue, 1, 162, 27, // Skip to: 25557
+/* 18483 */ MCD_OPC_CheckField, 0, 5, 31, 4, 0, // Skip to: 18493
+/* 18489 */ MCD_OPC_Decode, 221, 10, 99, // Opcode: SUBxxi_lsl12_cmp
+/* 18493 */ MCD_OPC_Decode, 220, 10, 100, // Opcode: SUBxxi_lsl12_S
+/* 18497 */ MCD_OPC_FilterValue, 2, 165, 0, // Skip to: 18666
+/* 18501 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18504 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 18526
+/* 18508 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18511 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18518
+/* 18515 */ MCD_OPC_Decode, 115, 101, // Opcode: ANDwwi
+/* 18518 */ MCD_OPC_FilterValue, 1, 123, 27, // Skip to: 25557
+/* 18522 */ MCD_OPC_Decode, 251, 6, 102, // Opcode: MOVNwii
+/* 18526 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 18540
+/* 18530 */ MCD_OPC_CheckField, 23, 1, 0, 109, 27, // Skip to: 25557
+/* 18536 */ MCD_OPC_Decode, 168, 7, 101, // Opcode: ORRwwi
+/* 18540 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 18563
+/* 18544 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18547 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18555
+/* 18551 */ MCD_OPC_Decode, 133, 3, 101, // Opcode: EORwwi
+/* 18555 */ MCD_OPC_FilterValue, 1, 86, 27, // Skip to: 25557
+/* 18559 */ MCD_OPC_Decode, 253, 6, 102, // Opcode: MOVZwii
+/* 18563 */ MCD_OPC_FilterValue, 3, 18, 0, // Skip to: 18585
+/* 18567 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18570 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18577
+/* 18574 */ MCD_OPC_Decode, 103, 103, // Opcode: ANDSwwi
+/* 18577 */ MCD_OPC_FilterValue, 1, 64, 27, // Skip to: 25557
+/* 18581 */ MCD_OPC_Decode, 249, 6, 104, // Opcode: MOVKwii
+/* 18585 */ MCD_OPC_FilterValue, 4, 18, 0, // Skip to: 18607
+/* 18589 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18592 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18599
+/* 18596 */ MCD_OPC_Decode, 120, 105, // Opcode: ANDxxi
+/* 18599 */ MCD_OPC_FilterValue, 1, 42, 27, // Skip to: 25557
+/* 18603 */ MCD_OPC_Decode, 252, 6, 106, // Opcode: MOVNxii
+/* 18607 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 18621
+/* 18611 */ MCD_OPC_CheckField, 23, 1, 0, 28, 27, // Skip to: 25557
+/* 18617 */ MCD_OPC_Decode, 173, 7, 105, // Opcode: ORRxxi
+/* 18621 */ MCD_OPC_FilterValue, 6, 19, 0, // Skip to: 18644
+/* 18625 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18628 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18636
+/* 18632 */ MCD_OPC_Decode, 138, 3, 105, // Opcode: EORxxi
+/* 18636 */ MCD_OPC_FilterValue, 1, 5, 27, // Skip to: 25557
+/* 18640 */ MCD_OPC_Decode, 254, 6, 106, // Opcode: MOVZxii
+/* 18644 */ MCD_OPC_FilterValue, 7, 253, 26, // Skip to: 25557
+/* 18648 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ...
+/* 18651 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 18658
+/* 18655 */ MCD_OPC_Decode, 108, 107, // Opcode: ANDSxxi
+/* 18658 */ MCD_OPC_FilterValue, 1, 239, 26, // Skip to: 25557
+/* 18662 */ MCD_OPC_Decode, 250, 6, 108, // Opcode: MOVKxii
+/* 18666 */ MCD_OPC_FilterValue, 3, 231, 26, // Skip to: 25557
+/* 18670 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 18673 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 18730
+/* 18677 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18680 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 18716
+/* 18684 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ...
+/* 18687 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 18695
+/* 18691 */ MCD_OPC_Decode, 235, 10, 109, // Opcode: SXTBww
+/* 18695 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 18703
+/* 18699 */ MCD_OPC_Decode, 237, 10, 109, // Opcode: SXTHww
+/* 18703 */ MCD_OPC_CheckField, 10, 6, 31, 3, 0, // Skip to: 18712
+/* 18709 */ MCD_OPC_Decode, 127, 110, // Opcode: ASRwwi
+/* 18712 */ MCD_OPC_Decode, 142, 8, 111, // Opcode: SBFMwwii
+/* 18716 */ MCD_OPC_FilterValue, 2, 181, 26, // Skip to: 25557
+/* 18720 */ MCD_OPC_CheckField, 21, 1, 0, 175, 26, // Skip to: 25557
+/* 18726 */ MCD_OPC_Decode, 144, 3, 112, // Opcode: EXTRwwwi
+/* 18730 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 18744
+/* 18734 */ MCD_OPC_CheckField, 22, 2, 0, 161, 26, // Skip to: 25557
+/* 18740 */ MCD_OPC_Decode, 180, 1, 111, // Opcode: BFMwwii
+/* 18744 */ MCD_OPC_FilterValue, 2, 40, 0, // Skip to: 18788
+/* 18748 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18751 */ MCD_OPC_FilterValue, 0, 146, 26, // Skip to: 25557
+/* 18755 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ...
+/* 18758 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 18766
+/* 18762 */ MCD_OPC_Decode, 250, 12, 109, // Opcode: UXTBww
+/* 18766 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 18774
+/* 18770 */ MCD_OPC_Decode, 252, 12, 109, // Opcode: UXTHww
+/* 18774 */ MCD_OPC_CheckField, 10, 6, 31, 4, 0, // Skip to: 18784
+/* 18780 */ MCD_OPC_Decode, 223, 6, 110, // Opcode: LSRwwi
+/* 18784 */ MCD_OPC_Decode, 172, 11, 111, // Opcode: UBFMwwii
+/* 18788 */ MCD_OPC_FilterValue, 4, 62, 0, // Skip to: 18854
+/* 18792 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18795 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 18840
+/* 18799 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ...
+/* 18802 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 18810
+/* 18806 */ MCD_OPC_Decode, 236, 10, 113, // Opcode: SXTBxw
+/* 18810 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 18818
+/* 18814 */ MCD_OPC_Decode, 238, 10, 113, // Opcode: SXTHxw
+/* 18818 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 18826
+/* 18822 */ MCD_OPC_Decode, 239, 10, 113, // Opcode: SXTWxw
+/* 18826 */ MCD_OPC_CheckField, 10, 6, 63, 4, 0, // Skip to: 18836
+/* 18832 */ MCD_OPC_Decode, 128, 1, 114, // Opcode: ASRxxi
+/* 18836 */ MCD_OPC_Decode, 143, 8, 111, // Opcode: SBFMxxii
+/* 18840 */ MCD_OPC_FilterValue, 3, 57, 26, // Skip to: 25557
+/* 18844 */ MCD_OPC_CheckField, 21, 1, 0, 51, 26, // Skip to: 25557
+/* 18850 */ MCD_OPC_Decode, 145, 3, 11, // Opcode: EXTRxxxi
+/* 18854 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 18868
+/* 18858 */ MCD_OPC_CheckField, 22, 2, 1, 37, 26, // Skip to: 25557
+/* 18864 */ MCD_OPC_Decode, 181, 1, 111, // Opcode: BFMxxii
+/* 18868 */ MCD_OPC_FilterValue, 6, 29, 26, // Skip to: 25557
+/* 18872 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ...
+/* 18875 */ MCD_OPC_FilterValue, 1, 22, 26, // Skip to: 25557
+/* 18879 */ MCD_OPC_CheckField, 10, 6, 63, 4, 0, // Skip to: 18889
+/* 18885 */ MCD_OPC_Decode, 224, 6, 114, // Opcode: LSRxxi
+/* 18889 */ MCD_OPC_Decode, 173, 11, 111, // Opcode: UBFMxxii
+/* 18893 */ MCD_OPC_FilterValue, 5, 9, 2, // Skip to: 19418
+/* 18897 */ MCD_OPC_ExtractField, 29, 2, // Inst{30-29} ...
+/* 18900 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 18923
+/* 18904 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 18907 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18915
+/* 18911 */ MCD_OPC_Decode, 217, 1, 115, // Opcode: Bimm
+/* 18915 */ MCD_OPC_FilterValue, 1, 238, 25, // Skip to: 25557
+/* 18919 */ MCD_OPC_Decode, 211, 1, 115, // Opcode: BLimm
+/* 18923 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 19012
+/* 18927 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 18930 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 18953
+/* 18934 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 18937 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18945
+/* 18941 */ MCD_OPC_Decode, 220, 1, 116, // Opcode: CBZw
+/* 18945 */ MCD_OPC_FilterValue, 1, 208, 25, // Skip to: 25557
+/* 18949 */ MCD_OPC_Decode, 221, 1, 117, // Opcode: CBZx
+/* 18953 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 18976
+/* 18957 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 18960 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 18968
+/* 18964 */ MCD_OPC_Decode, 218, 1, 116, // Opcode: CBNZw
+/* 18968 */ MCD_OPC_FilterValue, 1, 185, 25, // Skip to: 25557
+/* 18972 */ MCD_OPC_Decode, 219, 1, 117, // Opcode: CBNZx
+/* 18976 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18994
+/* 18980 */ MCD_OPC_CheckField, 31, 1, 0, 4, 0, // Skip to: 18990
+/* 18986 */ MCD_OPC_Decode, 246, 10, 118, // Opcode: TBZwii
+/* 18990 */ MCD_OPC_Decode, 247, 10, 119, // Opcode: TBZxii
+/* 18994 */ MCD_OPC_FilterValue, 3, 159, 25, // Skip to: 25557
+/* 18998 */ MCD_OPC_CheckField, 31, 1, 0, 4, 0, // Skip to: 19008
+/* 19004 */ MCD_OPC_Decode, 244, 10, 118, // Opcode: TBNZwii
+/* 19008 */ MCD_OPC_Decode, 245, 10, 119, // Opcode: TBNZxii
+/* 19012 */ MCD_OPC_FilterValue, 2, 141, 25, // Skip to: 25557
+/* 19016 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 19019 */ MCD_OPC_FilterValue, 0, 116, 0, // Skip to: 19139
+/* 19023 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 19026 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 19040
+/* 19030 */ MCD_OPC_CheckField, 4, 1, 0, 121, 25, // Skip to: 25557
+/* 19036 */ MCD_OPC_Decode, 216, 1, 120, // Opcode: Bcc
+/* 19040 */ MCD_OPC_FilterValue, 1, 113, 25, // Skip to: 25557
+/* 19044 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 19047 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 19070
+/* 19051 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19054 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 19062
+/* 19058 */ MCD_OPC_Decode, 212, 1, 121, // Opcode: BRKi
+/* 19062 */ MCD_OPC_FilterValue, 2, 91, 25, // Skip to: 25557
+/* 19066 */ MCD_OPC_Decode, 244, 4, 121, // Opcode: HLTi
+/* 19070 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 19093
+/* 19074 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19077 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 19085
+/* 19081 */ MCD_OPC_Decode, 234, 10, 121, // Opcode: SVCi
+/* 19085 */ MCD_OPC_FilterValue, 5, 68, 25, // Skip to: 25557
+/* 19089 */ MCD_OPC_Decode, 244, 2, 121, // Opcode: DCPS1i
+/* 19093 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 19116
+/* 19097 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19100 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 19108
+/* 19104 */ MCD_OPC_Decode, 245, 4, 121, // Opcode: HVCi
+/* 19108 */ MCD_OPC_FilterValue, 5, 45, 25, // Skip to: 25557
+/* 19112 */ MCD_OPC_Decode, 245, 2, 121, // Opcode: DCPS2i
+/* 19116 */ MCD_OPC_FilterValue, 3, 37, 25, // Skip to: 25557
+/* 19120 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19123 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 19131
+/* 19127 */ MCD_OPC_Decode, 201, 8, 121, // Opcode: SMCi
+/* 19131 */ MCD_OPC_FilterValue, 5, 22, 25, // Skip to: 25557
+/* 19135 */ MCD_OPC_Decode, 246, 2, 121, // Opcode: DCPS3i
+/* 19139 */ MCD_OPC_FilterValue, 1, 156, 0, // Skip to: 19299
+/* 19143 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19146 */ MCD_OPC_FilterValue, 0, 122, 0, // Skip to: 19272
+/* 19150 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 19153 */ MCD_OPC_FilterValue, 1, 0, 25, // Skip to: 25557
+/* 19157 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ...
+/* 19160 */ MCD_OPC_FilterValue, 95, 10, 0, // Skip to: 19174
+/* 19164 */ MCD_OPC_CheckField, 12, 9, 51, 49, 0, // Skip to: 19219
+/* 19170 */ MCD_OPC_Decode, 230, 1, 122, // Opcode: CLREXi
+/* 19174 */ MCD_OPC_FilterValue, 159, 1, 10, 0, // Skip to: 19189
+/* 19179 */ MCD_OPC_CheckField, 12, 9, 51, 34, 0, // Skip to: 19219
+/* 19185 */ MCD_OPC_Decode, 250, 2, 123, // Opcode: DSBi
+/* 19189 */ MCD_OPC_FilterValue, 191, 1, 10, 0, // Skip to: 19204
+/* 19194 */ MCD_OPC_CheckField, 12, 9, 51, 19, 0, // Skip to: 19219
+/* 19200 */ MCD_OPC_Decode, 248, 2, 123, // Opcode: DMBi
+/* 19204 */ MCD_OPC_FilterValue, 223, 1, 10, 0, // Skip to: 19219
+/* 19209 */ MCD_OPC_CheckField, 12, 9, 51, 4, 0, // Skip to: 19219
+/* 19215 */ MCD_OPC_Decode, 128, 5, 124, // Opcode: ISBi
+/* 19219 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 19222 */ MCD_OPC_FilterValue, 31, 31, 0, // Skip to: 19257
+/* 19226 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 19229 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 19243
+/* 19233 */ MCD_OPC_CheckField, 16, 5, 3, 18, 0, // Skip to: 19257
+/* 19239 */ MCD_OPC_Decode, 243, 4, 125, // Opcode: HINTi
+/* 19243 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 19257
+/* 19247 */ MCD_OPC_CheckField, 19, 2, 0, 4, 0, // Skip to: 19257
+/* 19253 */ MCD_OPC_Decode, 128, 7, 126, // Opcode: MSRii
+/* 19257 */ MCD_OPC_CheckField, 19, 2, 1, 4, 0, // Skip to: 19267
+/* 19263 */ MCD_OPC_Decode, 241, 10, 127, // Opcode: SYSiccix
+/* 19267 */ MCD_OPC_Decode, 129, 7, 128, 1, // Opcode: MSRix
+/* 19272 */ MCD_OPC_FilterValue, 1, 137, 24, // Skip to: 25557
+/* 19276 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ...
+/* 19279 */ MCD_OPC_FilterValue, 1, 130, 24, // Skip to: 25557
+/* 19283 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, // Skip to: 19294
+/* 19289 */ MCD_OPC_Decode, 240, 10, 129, 1, // Opcode: SYSLxicci
+/* 19294 */ MCD_OPC_Decode, 255, 6, 130, 1, // Opcode: MRSxi
+/* 19299 */ MCD_OPC_FilterValue, 2, 110, 24, // Skip to: 25557
+/* 19303 */ MCD_OPC_ExtractField, 10, 14, // Inst{23-10} ...
+/* 19306 */ MCD_OPC_FilterValue, 192, 15, 17, 0, // Skip to: 19328
+/* 19311 */ MCD_OPC_CheckField, 31, 1, 1, 96, 24, // Skip to: 25557
+/* 19317 */ MCD_OPC_CheckField, 0, 5, 0, 90, 24, // Skip to: 25557
+/* 19323 */ MCD_OPC_Decode, 213, 1, 131, 1, // Opcode: BRx
+/* 19328 */ MCD_OPC_FilterValue, 192, 31, 17, 0, // Skip to: 19350
+/* 19333 */ MCD_OPC_CheckField, 31, 1, 1, 74, 24, // Skip to: 25557
+/* 19339 */ MCD_OPC_CheckField, 0, 5, 0, 68, 24, // Skip to: 25557
+/* 19345 */ MCD_OPC_Decode, 210, 1, 131, 1, // Opcode: BLRx
+/* 19350 */ MCD_OPC_FilterValue, 192, 47, 17, 0, // Skip to: 19372
+/* 19355 */ MCD_OPC_CheckField, 31, 1, 1, 52, 24, // Skip to: 25557
+/* 19361 */ MCD_OPC_CheckField, 0, 5, 0, 46, 24, // Skip to: 25557
+/* 19367 */ MCD_OPC_Decode, 208, 7, 131, 1, // Opcode: RETx
+/* 19372 */ MCD_OPC_FilterValue, 192, 79, 18, 0, // Skip to: 19395
+/* 19377 */ MCD_OPC_CheckField, 31, 1, 1, 30, 24, // Skip to: 25557
+/* 19383 */ MCD_OPC_CheckField, 0, 10, 224, 7, 23, 24, // Skip to: 25557
+/* 19390 */ MCD_OPC_Decode, 143, 3, 132, 1, // Opcode: ERET
+/* 19395 */ MCD_OPC_FilterValue, 192, 95, 13, 24, // Skip to: 25557
+/* 19400 */ MCD_OPC_CheckField, 31, 1, 1, 7, 24, // Skip to: 25557
+/* 19406 */ MCD_OPC_CheckField, 0, 10, 224, 7, 0, 24, // Skip to: 25557
+/* 19413 */ MCD_OPC_Decode, 249, 2, 132, 1, // Opcode: DRPS
+/* 19418 */ MCD_OPC_FilterValue, 6, 9, 10, // Skip to: 21991
+/* 19422 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 19425 */ MCD_OPC_FilterValue, 0, 16, 1, // Skip to: 19701
+/* 19429 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 19432 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 19440
+/* 19436 */ MCD_OPC_Decode, 175, 5, 116, // Opcode: LDRw_lit
+/* 19440 */ MCD_OPC_FilterValue, 2, 220, 0, // Skip to: 19664
+/* 19444 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 19447 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 19511
+/* 19451 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19454 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 19468
+/* 19458 */ MCD_OPC_CheckField, 12, 4, 0, 205, 23, // Skip to: 25557
+/* 19464 */ MCD_OPC_Decode, 19, 133, 1, // Opcode: ADCwww
+/* 19468 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 19477
+/* 19472 */ MCD_OPC_Decode, 236, 2, 134, 1, // Opcode: CSELwwwc
+/* 19477 */ MCD_OPC_FilterValue, 6, 188, 23, // Skip to: 25557
+/* 19481 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 19484 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 19493
+/* 19488 */ MCD_OPC_Decode, 201, 6, 133, 1, // Opcode: LSLVwww
+/* 19493 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 19502
+/* 19497 */ MCD_OPC_Decode, 228, 2, 133, 1, // Opcode: CRC32B_www
+/* 19502 */ MCD_OPC_FilterValue, 5, 163, 23, // Skip to: 25557
+/* 19506 */ MCD_OPC_Decode, 229, 2, 133, 1, // Opcode: CRC32CB_www
+/* 19511 */ MCD_OPC_FilterValue, 1, 46, 0, // Skip to: 19561
+/* 19515 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 19518 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 19527
+/* 19522 */ MCD_OPC_Decode, 238, 2, 134, 1, // Opcode: CSINCwwwc
+/* 19527 */ MCD_OPC_FilterValue, 6, 138, 23, // Skip to: 25557
+/* 19531 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 19534 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 19543
+/* 19538 */ MCD_OPC_Decode, 221, 6, 133, 1, // Opcode: LSRVwww
+/* 19543 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 19552
+/* 19547 */ MCD_OPC_Decode, 233, 2, 133, 1, // Opcode: CRC32H_www
+/* 19552 */ MCD_OPC_FilterValue, 5, 113, 23, // Skip to: 25557
+/* 19556 */ MCD_OPC_Decode, 230, 2, 133, 1, // Opcode: CRC32CH_www
+/* 19561 */ MCD_OPC_FilterValue, 2, 62, 0, // Skip to: 19627
+/* 19565 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 19568 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19583
+/* 19572 */ MCD_OPC_CheckField, 21, 3, 6, 91, 23, // Skip to: 25557
+/* 19578 */ MCD_OPC_Decode, 184, 11, 133, 1, // Opcode: UDIVwww
+/* 19583 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 19597
+/* 19587 */ MCD_OPC_CheckField, 21, 3, 6, 76, 23, // Skip to: 25557
+/* 19593 */ MCD_OPC_Decode, 125, 133, 1, // Opcode: ASRVwww
+/* 19597 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 19612
+/* 19601 */ MCD_OPC_CheckField, 21, 3, 6, 62, 23, // Skip to: 25557
+/* 19607 */ MCD_OPC_Decode, 234, 2, 133, 1, // Opcode: CRC32W_www
+/* 19612 */ MCD_OPC_FilterValue, 5, 53, 23, // Skip to: 25557
+/* 19616 */ MCD_OPC_CheckField, 21, 3, 6, 47, 23, // Skip to: 25557
+/* 19622 */ MCD_OPC_Decode, 231, 2, 133, 1, // Opcode: CRC32CW_www
+/* 19627 */ MCD_OPC_FilterValue, 3, 38, 23, // Skip to: 25557
+/* 19631 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 19634 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19649
+/* 19638 */ MCD_OPC_CheckField, 21, 3, 6, 25, 23, // Skip to: 25557
+/* 19644 */ MCD_OPC_Decode, 154, 8, 133, 1, // Opcode: SDIVwww
+/* 19649 */ MCD_OPC_FilterValue, 2, 16, 23, // Skip to: 25557
+/* 19653 */ MCD_OPC_CheckField, 21, 3, 6, 10, 23, // Skip to: 25557
+/* 19659 */ MCD_OPC_Decode, 214, 7, 133, 1, // Opcode: RORVwww
+/* 19664 */ MCD_OPC_FilterValue, 3, 1, 23, // Skip to: 25557
+/* 19668 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 19671 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19686
+/* 19675 */ MCD_OPC_CheckField, 21, 3, 0, 244, 22, // Skip to: 25557
+/* 19681 */ MCD_OPC_Decode, 225, 6, 135, 1, // Opcode: MADDwwww
+/* 19686 */ MCD_OPC_FilterValue, 1, 235, 22, // Skip to: 25557
+/* 19690 */ MCD_OPC_CheckField, 21, 3, 0, 229, 22, // Skip to: 25557
+/* 19696 */ MCD_OPC_Decode, 130, 7, 135, 1, // Opcode: MSUBwwww
+/* 19701 */ MCD_OPC_FilterValue, 1, 223, 1, // Skip to: 20184
+/* 19705 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 19708 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 19801
+/* 19712 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 19715 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19730
+/* 19719 */ MCD_OPC_CheckField, 21, 1, 0, 200, 22, // Skip to: 25557
+/* 19725 */ MCD_OPC_Decode, 238, 5, 136, 1, // Opcode: LS8_STUR
+/* 19730 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 19745
+/* 19734 */ MCD_OPC_CheckField, 21, 1, 0, 185, 22, // Skip to: 25557
+/* 19740 */ MCD_OPC_Decode, 234, 5, 137, 1, // Opcode: LS8_PostInd_STR
+/* 19745 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 19786
+/* 19749 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 19752 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19761
+/* 19756 */ MCD_OPC_Decode, 240, 5, 136, 1, // Opcode: LS8_UnPriv_STR
+/* 19761 */ MCD_OPC_FilterValue, 1, 160, 22, // Skip to: 25557
+/* 19765 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 19768 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19777
+/* 19772 */ MCD_OPC_Decode, 242, 5, 138, 1, // Opcode: LS8_Wm_RegOffset_STR
+/* 19777 */ MCD_OPC_FilterValue, 1, 144, 22, // Skip to: 25557
+/* 19781 */ MCD_OPC_Decode, 244, 5, 139, 1, // Opcode: LS8_Xm_RegOffset_STR
+/* 19786 */ MCD_OPC_FilterValue, 3, 135, 22, // Skip to: 25557
+/* 19790 */ MCD_OPC_CheckField, 21, 1, 0, 129, 22, // Skip to: 25557
+/* 19796 */ MCD_OPC_Decode, 236, 5, 137, 1, // Opcode: LS8_PreInd_STR
+/* 19801 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 19894
+/* 19805 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 19808 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19823
+/* 19812 */ MCD_OPC_CheckField, 21, 1, 0, 107, 22, // Skip to: 25557
+/* 19818 */ MCD_OPC_Decode, 232, 5, 136, 1, // Opcode: LS8_LDUR
+/* 19823 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 19838
+/* 19827 */ MCD_OPC_CheckField, 21, 1, 0, 92, 22, // Skip to: 25557
+/* 19833 */ MCD_OPC_Decode, 233, 5, 137, 1, // Opcode: LS8_PostInd_LDR
+/* 19838 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 19879
+/* 19842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 19845 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19854
+/* 19849 */ MCD_OPC_Decode, 239, 5, 136, 1, // Opcode: LS8_UnPriv_LDR
+/* 19854 */ MCD_OPC_FilterValue, 1, 67, 22, // Skip to: 25557
+/* 19858 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 19861 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19870
+/* 19865 */ MCD_OPC_Decode, 241, 5, 138, 1, // Opcode: LS8_Wm_RegOffset_LDR
+/* 19870 */ MCD_OPC_FilterValue, 1, 51, 22, // Skip to: 25557
+/* 19874 */ MCD_OPC_Decode, 243, 5, 139, 1, // Opcode: LS8_Xm_RegOffset_LDR
+/* 19879 */ MCD_OPC_FilterValue, 3, 42, 22, // Skip to: 25557
+/* 19883 */ MCD_OPC_CheckField, 21, 1, 0, 36, 22, // Skip to: 25557
+/* 19889 */ MCD_OPC_Decode, 235, 5, 137, 1, // Opcode: LS8_PreInd_LDR
+/* 19894 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 19987
+/* 19898 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 19901 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 19916
+/* 19905 */ MCD_OPC_CheckField, 21, 1, 0, 14, 22, // Skip to: 25557
+/* 19911 */ MCD_OPC_Decode, 151, 5, 140, 1, // Opcode: LDRSBx_U
+/* 19916 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 19931
+/* 19920 */ MCD_OPC_CheckField, 21, 1, 0, 255, 21, // Skip to: 25557
+/* 19926 */ MCD_OPC_Decode, 149, 5, 137, 1, // Opcode: LDRSBx_PostInd
+/* 19931 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 19972
+/* 19935 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 19938 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19947
+/* 19942 */ MCD_OPC_Decode, 178, 5, 140, 1, // Opcode: LDTRSBx
+/* 19947 */ MCD_OPC_FilterValue, 1, 230, 21, // Skip to: 25557
+/* 19951 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 19954 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 19963
+/* 19958 */ MCD_OPC_Decode, 152, 5, 141, 1, // Opcode: LDRSBx_Wm_RegOffset
+/* 19963 */ MCD_OPC_FilterValue, 1, 214, 21, // Skip to: 25557
+/* 19967 */ MCD_OPC_Decode, 153, 5, 142, 1, // Opcode: LDRSBx_Xm_RegOffset
+/* 19972 */ MCD_OPC_FilterValue, 3, 205, 21, // Skip to: 25557
+/* 19976 */ MCD_OPC_CheckField, 21, 1, 0, 199, 21, // Skip to: 25557
+/* 19982 */ MCD_OPC_Decode, 150, 5, 137, 1, // Opcode: LDRSBx_PreInd
+/* 19987 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 20080
+/* 19991 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 19994 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20009
+/* 19998 */ MCD_OPC_CheckField, 21, 1, 0, 177, 21, // Skip to: 25557
+/* 20004 */ MCD_OPC_Decode, 145, 5, 136, 1, // Opcode: LDRSBw_U
+/* 20009 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 20024
+/* 20013 */ MCD_OPC_CheckField, 21, 1, 0, 162, 21, // Skip to: 25557
+/* 20019 */ MCD_OPC_Decode, 143, 5, 137, 1, // Opcode: LDRSBw_PostInd
+/* 20024 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 20065
+/* 20028 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 20031 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20040
+/* 20035 */ MCD_OPC_Decode, 177, 5, 136, 1, // Opcode: LDTRSBw
+/* 20040 */ MCD_OPC_FilterValue, 1, 137, 21, // Skip to: 25557
+/* 20044 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 20047 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20056
+/* 20051 */ MCD_OPC_Decode, 146, 5, 138, 1, // Opcode: LDRSBw_Wm_RegOffset
+/* 20056 */ MCD_OPC_FilterValue, 1, 121, 21, // Skip to: 25557
+/* 20060 */ MCD_OPC_Decode, 147, 5, 139, 1, // Opcode: LDRSBw_Xm_RegOffset
+/* 20065 */ MCD_OPC_FilterValue, 3, 112, 21, // Skip to: 25557
+/* 20069 */ MCD_OPC_CheckField, 21, 1, 0, 106, 21, // Skip to: 25557
+/* 20075 */ MCD_OPC_Decode, 144, 5, 137, 1, // Opcode: LDRSBw_PreInd
+/* 20080 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20089
+/* 20084 */ MCD_OPC_Decode, 237, 5, 143, 1, // Opcode: LS8_STR
+/* 20089 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 20098
+/* 20093 */ MCD_OPC_Decode, 231, 5, 143, 1, // Opcode: LS8_LDR
+/* 20098 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 20106
+/* 20102 */ MCD_OPC_Decode, 148, 5, 100, // Opcode: LDRSBx
+/* 20106 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 20115
+/* 20110 */ MCD_OPC_Decode, 142, 5, 143, 1, // Opcode: LDRSBw
+/* 20115 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 20135
+/* 20119 */ MCD_OPC_CheckField, 21, 1, 0, 56, 21, // Skip to: 25557
+/* 20125 */ MCD_OPC_CheckField, 10, 6, 0, 50, 21, // Skip to: 25557
+/* 20131 */ MCD_OPC_Decode, 17, 133, 1, // Opcode: ADCSwww
+/* 20135 */ MCD_OPC_FilterValue, 9, 42, 21, // Skip to: 25557
+/* 20139 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20142 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 20163
+/* 20146 */ MCD_OPC_CheckField, 21, 1, 0, 29, 21, // Skip to: 25557
+/* 20152 */ MCD_OPC_CheckField, 4, 1, 0, 23, 21, // Skip to: 25557
+/* 20158 */ MCD_OPC_Decode, 223, 1, 144, 1, // Opcode: CCMNww
+/* 20163 */ MCD_OPC_FilterValue, 2, 14, 21, // Skip to: 25557
+/* 20167 */ MCD_OPC_CheckField, 21, 1, 0, 8, 21, // Skip to: 25557
+/* 20173 */ MCD_OPC_CheckField, 4, 1, 0, 2, 21, // Skip to: 25557
+/* 20179 */ MCD_OPC_Decode, 222, 1, 145, 1, // Opcode: CCMNwi
+/* 20184 */ MCD_OPC_FilterValue, 2, 126, 0, // Skip to: 20314
+/* 20188 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 20191 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 20199
+/* 20195 */ MCD_OPC_Decode, 176, 5, 117, // Opcode: LDRx_lit
+/* 20199 */ MCD_OPC_FilterValue, 2, 234, 20, // Skip to: 25557
+/* 20203 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20206 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 20260
+/* 20210 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 20213 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20228
+/* 20217 */ MCD_OPC_CheckField, 12, 4, 0, 214, 20, // Skip to: 25557
+/* 20223 */ MCD_OPC_Decode, 138, 8, 133, 1, // Opcode: SBCwww
+/* 20228 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20237
+/* 20232 */ MCD_OPC_Decode, 240, 2, 134, 1, // Opcode: CSINVwwwc
+/* 20237 */ MCD_OPC_FilterValue, 6, 196, 20, // Skip to: 25557
+/* 20241 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ...
+/* 20244 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 20252
+/* 20248 */ MCD_OPC_Decode, 205, 7, 109, // Opcode: RBITww
+/* 20252 */ MCD_OPC_FilterValue, 1, 181, 20, // Skip to: 25557
+/* 20256 */ MCD_OPC_Decode, 233, 1, 109, // Opcode: CLZww
+/* 20260 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 20299
+/* 20264 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 20267 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20276
+/* 20271 */ MCD_OPC_Decode, 242, 2, 134, 1, // Opcode: CSNEGwwwc
+/* 20276 */ MCD_OPC_FilterValue, 6, 157, 20, // Skip to: 25557
+/* 20280 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ...
+/* 20283 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 20291
+/* 20287 */ MCD_OPC_Decode, 209, 7, 109, // Opcode: REV16ww
+/* 20291 */ MCD_OPC_FilterValue, 1, 142, 20, // Skip to: 25557
+/* 20295 */ MCD_OPC_Decode, 231, 1, 109, // Opcode: CLSww
+/* 20299 */ MCD_OPC_FilterValue, 2, 134, 20, // Skip to: 25557
+/* 20303 */ MCD_OPC_CheckField, 12, 12, 128, 24, 127, 20, // Skip to: 25557
+/* 20310 */ MCD_OPC_Decode, 212, 7, 109, // Opcode: REVww
+/* 20314 */ MCD_OPC_FilterValue, 3, 224, 1, // Skip to: 20798
+/* 20318 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 20321 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 20414
+/* 20325 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20328 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20343
+/* 20332 */ MCD_OPC_CheckField, 21, 1, 0, 99, 20, // Skip to: 25557
+/* 20338 */ MCD_OPC_Decode, 196, 5, 136, 1, // Opcode: LS16_STUR
+/* 20343 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 20358
+/* 20347 */ MCD_OPC_CheckField, 21, 1, 0, 84, 20, // Skip to: 25557
+/* 20353 */ MCD_OPC_Decode, 192, 5, 137, 1, // Opcode: LS16_PostInd_STR
+/* 20358 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 20399
+/* 20362 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 20365 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20374
+/* 20369 */ MCD_OPC_Decode, 198, 5, 136, 1, // Opcode: LS16_UnPriv_STR
+/* 20374 */ MCD_OPC_FilterValue, 1, 59, 20, // Skip to: 25557
+/* 20378 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 20381 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20390
+/* 20385 */ MCD_OPC_Decode, 200, 5, 138, 1, // Opcode: LS16_Wm_RegOffset_STR
+/* 20390 */ MCD_OPC_FilterValue, 1, 43, 20, // Skip to: 25557
+/* 20394 */ MCD_OPC_Decode, 202, 5, 139, 1, // Opcode: LS16_Xm_RegOffset_STR
+/* 20399 */ MCD_OPC_FilterValue, 3, 34, 20, // Skip to: 25557
+/* 20403 */ MCD_OPC_CheckField, 21, 1, 0, 28, 20, // Skip to: 25557
+/* 20409 */ MCD_OPC_Decode, 194, 5, 137, 1, // Opcode: LS16_PreInd_STR
+/* 20414 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 20507
+/* 20418 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20421 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20436
+/* 20425 */ MCD_OPC_CheckField, 21, 1, 0, 6, 20, // Skip to: 25557
+/* 20431 */ MCD_OPC_Decode, 190, 5, 136, 1, // Opcode: LS16_LDUR
+/* 20436 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 20451
+/* 20440 */ MCD_OPC_CheckField, 21, 1, 0, 247, 19, // Skip to: 25557
+/* 20446 */ MCD_OPC_Decode, 191, 5, 137, 1, // Opcode: LS16_PostInd_LDR
+/* 20451 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 20492
+/* 20455 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 20458 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20467
+/* 20462 */ MCD_OPC_Decode, 197, 5, 136, 1, // Opcode: LS16_UnPriv_LDR
+/* 20467 */ MCD_OPC_FilterValue, 1, 222, 19, // Skip to: 25557
+/* 20471 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 20474 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20483
+/* 20478 */ MCD_OPC_Decode, 199, 5, 138, 1, // Opcode: LS16_Wm_RegOffset_LDR
+/* 20483 */ MCD_OPC_FilterValue, 1, 206, 19, // Skip to: 25557
+/* 20487 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: LS16_Xm_RegOffset_LDR
+/* 20492 */ MCD_OPC_FilterValue, 3, 197, 19, // Skip to: 25557
+/* 20496 */ MCD_OPC_CheckField, 21, 1, 0, 191, 19, // Skip to: 25557
+/* 20502 */ MCD_OPC_Decode, 193, 5, 137, 1, // Opcode: LS16_PreInd_LDR
+/* 20507 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 20600
+/* 20511 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20514 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20529
+/* 20518 */ MCD_OPC_CheckField, 21, 1, 0, 169, 19, // Skip to: 25557
+/* 20524 */ MCD_OPC_Decode, 163, 5, 140, 1, // Opcode: LDRSHx_U
+/* 20529 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 20544
+/* 20533 */ MCD_OPC_CheckField, 21, 1, 0, 154, 19, // Skip to: 25557
+/* 20539 */ MCD_OPC_Decode, 161, 5, 137, 1, // Opcode: LDRSHx_PostInd
+/* 20544 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 20585
+/* 20548 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 20551 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20560
+/* 20555 */ MCD_OPC_Decode, 180, 5, 140, 1, // Opcode: LDTRSHx
+/* 20560 */ MCD_OPC_FilterValue, 1, 129, 19, // Skip to: 25557
+/* 20564 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 20567 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20576
+/* 20571 */ MCD_OPC_Decode, 164, 5, 141, 1, // Opcode: LDRSHx_Wm_RegOffset
+/* 20576 */ MCD_OPC_FilterValue, 1, 113, 19, // Skip to: 25557
+/* 20580 */ MCD_OPC_Decode, 165, 5, 142, 1, // Opcode: LDRSHx_Xm_RegOffset
+/* 20585 */ MCD_OPC_FilterValue, 3, 104, 19, // Skip to: 25557
+/* 20589 */ MCD_OPC_CheckField, 21, 1, 0, 98, 19, // Skip to: 25557
+/* 20595 */ MCD_OPC_Decode, 162, 5, 137, 1, // Opcode: LDRSHx_PreInd
+/* 20600 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 20693
+/* 20604 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20607 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20622
+/* 20611 */ MCD_OPC_CheckField, 21, 1, 0, 76, 19, // Skip to: 25557
+/* 20617 */ MCD_OPC_Decode, 157, 5, 136, 1, // Opcode: LDRSHw_U
+/* 20622 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 20637
+/* 20626 */ MCD_OPC_CheckField, 21, 1, 0, 61, 19, // Skip to: 25557
+/* 20632 */ MCD_OPC_Decode, 155, 5, 137, 1, // Opcode: LDRSHw_PostInd
+/* 20637 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 20678
+/* 20641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 20644 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20653
+/* 20648 */ MCD_OPC_Decode, 179, 5, 136, 1, // Opcode: LDTRSHw
+/* 20653 */ MCD_OPC_FilterValue, 1, 36, 19, // Skip to: 25557
+/* 20657 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 20660 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20669
+/* 20664 */ MCD_OPC_Decode, 158, 5, 138, 1, // Opcode: LDRSHw_Wm_RegOffset
+/* 20669 */ MCD_OPC_FilterValue, 1, 20, 19, // Skip to: 25557
+/* 20673 */ MCD_OPC_Decode, 159, 5, 139, 1, // Opcode: LDRSHw_Xm_RegOffset
+/* 20678 */ MCD_OPC_FilterValue, 3, 11, 19, // Skip to: 25557
+/* 20682 */ MCD_OPC_CheckField, 21, 1, 0, 5, 19, // Skip to: 25557
+/* 20688 */ MCD_OPC_Decode, 156, 5, 137, 1, // Opcode: LDRSHw_PreInd
+/* 20693 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20702
+/* 20697 */ MCD_OPC_Decode, 195, 5, 143, 1, // Opcode: LS16_STR
+/* 20702 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 20711
+/* 20706 */ MCD_OPC_Decode, 189, 5, 143, 1, // Opcode: LS16_LDR
+/* 20711 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 20719
+/* 20715 */ MCD_OPC_Decode, 160, 5, 100, // Opcode: LDRSHx
+/* 20719 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 20728
+/* 20723 */ MCD_OPC_Decode, 154, 5, 143, 1, // Opcode: LDRSHw
+/* 20728 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 20749
+/* 20732 */ MCD_OPC_CheckField, 21, 1, 0, 211, 18, // Skip to: 25557
+/* 20738 */ MCD_OPC_CheckField, 10, 6, 0, 205, 18, // Skip to: 25557
+/* 20744 */ MCD_OPC_Decode, 136, 8, 133, 1, // Opcode: SBCSwww
+/* 20749 */ MCD_OPC_FilterValue, 9, 196, 18, // Skip to: 25557
+/* 20753 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20756 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 20777
+/* 20760 */ MCD_OPC_CheckField, 21, 1, 0, 183, 18, // Skip to: 25557
+/* 20766 */ MCD_OPC_CheckField, 4, 1, 0, 177, 18, // Skip to: 25557
+/* 20772 */ MCD_OPC_Decode, 227, 1, 144, 1, // Opcode: CCMPww
+/* 20777 */ MCD_OPC_FilterValue, 2, 168, 18, // Skip to: 25557
+/* 20781 */ MCD_OPC_CheckField, 21, 1, 0, 162, 18, // Skip to: 25557
+/* 20787 */ MCD_OPC_CheckField, 4, 1, 0, 156, 18, // Skip to: 25557
+/* 20793 */ MCD_OPC_Decode, 226, 1, 145, 1, // Opcode: CCMPwi
+/* 20798 */ MCD_OPC_FilterValue, 4, 53, 1, // Skip to: 21111
+/* 20802 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 20805 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 20813
+/* 20809 */ MCD_OPC_Decode, 171, 5, 117, // Opcode: LDRSWx_lit
+/* 20813 */ MCD_OPC_FilterValue, 2, 182, 0, // Skip to: 20999
+/* 20817 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 20820 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 20865
+/* 20824 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 20827 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 20841
+/* 20831 */ MCD_OPC_CheckField, 12, 4, 0, 112, 18, // Skip to: 25557
+/* 20837 */ MCD_OPC_Decode, 20, 146, 1, // Opcode: ADCxxx
+/* 20841 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20850
+/* 20845 */ MCD_OPC_Decode, 237, 2, 147, 1, // Opcode: CSELxxxc
+/* 20850 */ MCD_OPC_FilterValue, 6, 95, 18, // Skip to: 25557
+/* 20854 */ MCD_OPC_CheckField, 12, 4, 2, 89, 18, // Skip to: 25557
+/* 20860 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: LSLVxxx
+/* 20865 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 20896
+/* 20869 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 20872 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 20881
+/* 20876 */ MCD_OPC_Decode, 239, 2, 147, 1, // Opcode: CSINCxxxc
+/* 20881 */ MCD_OPC_FilterValue, 6, 64, 18, // Skip to: 25557
+/* 20885 */ MCD_OPC_CheckField, 12, 4, 2, 58, 18, // Skip to: 25557
+/* 20891 */ MCD_OPC_Decode, 222, 6, 146, 1, // Opcode: LSRVxxx
+/* 20896 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 20932
+/* 20900 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 20903 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20918
+/* 20907 */ MCD_OPC_CheckField, 21, 3, 6, 36, 18, // Skip to: 25557
+/* 20913 */ MCD_OPC_Decode, 185, 11, 146, 1, // Opcode: UDIVxxx
+/* 20918 */ MCD_OPC_FilterValue, 2, 27, 18, // Skip to: 25557
+/* 20922 */ MCD_OPC_CheckField, 21, 3, 6, 21, 18, // Skip to: 25557
+/* 20928 */ MCD_OPC_Decode, 126, 146, 1, // Opcode: ASRVxxx
+/* 20932 */ MCD_OPC_FilterValue, 3, 13, 18, // Skip to: 25557
+/* 20936 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 20939 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 20954
+/* 20943 */ MCD_OPC_CheckField, 21, 3, 6, 0, 18, // Skip to: 25557
+/* 20949 */ MCD_OPC_Decode, 155, 8, 146, 1, // Opcode: SDIVxxx
+/* 20954 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 20969
+/* 20958 */ MCD_OPC_CheckField, 21, 3, 6, 241, 17, // Skip to: 25557
+/* 20964 */ MCD_OPC_Decode, 215, 7, 146, 1, // Opcode: RORVxxx
+/* 20969 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 20984
+/* 20973 */ MCD_OPC_CheckField, 21, 3, 6, 226, 17, // Skip to: 25557
+/* 20979 */ MCD_OPC_Decode, 235, 2, 148, 1, // Opcode: CRC32X_wwx
+/* 20984 */ MCD_OPC_FilterValue, 5, 217, 17, // Skip to: 25557
+/* 20988 */ MCD_OPC_CheckField, 21, 3, 6, 211, 17, // Skip to: 25557
+/* 20994 */ MCD_OPC_Decode, 232, 2, 148, 1, // Opcode: CRC32CX_wwx
+/* 20999 */ MCD_OPC_FilterValue, 3, 202, 17, // Skip to: 25557
+/* 21003 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 21006 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 21031
+/* 21010 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 21013 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21022
+/* 21017 */ MCD_OPC_Decode, 226, 6, 149, 1, // Opcode: MADDxxxx
+/* 21022 */ MCD_OPC_FilterValue, 1, 179, 17, // Skip to: 25557
+/* 21026 */ MCD_OPC_Decode, 131, 7, 149, 1, // Opcode: MSUBxxxx
+/* 21031 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 21056
+/* 21035 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 21038 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21047
+/* 21042 */ MCD_OPC_Decode, 188, 8, 150, 1, // Opcode: SMADDLxwwx
+/* 21047 */ MCD_OPC_FilterValue, 1, 154, 17, // Skip to: 25557
+/* 21051 */ MCD_OPC_Decode, 231, 8, 150, 1, // Opcode: SMSUBLxwwx
+/* 21056 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 21071
+/* 21060 */ MCD_OPC_CheckField, 15, 1, 0, 139, 17, // Skip to: 25557
+/* 21066 */ MCD_OPC_Decode, 232, 8, 146, 1, // Opcode: SMULHxxx
+/* 21071 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 21096
+/* 21075 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 21078 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21087
+/* 21082 */ MCD_OPC_Decode, 198, 11, 150, 1, // Opcode: UMADDLxwwx
+/* 21087 */ MCD_OPC_FilterValue, 1, 114, 17, // Skip to: 25557
+/* 21091 */ MCD_OPC_Decode, 239, 11, 150, 1, // Opcode: UMSUBLxwwx
+/* 21096 */ MCD_OPC_FilterValue, 6, 105, 17, // Skip to: 25557
+/* 21100 */ MCD_OPC_CheckField, 15, 1, 0, 99, 17, // Skip to: 25557
+/* 21106 */ MCD_OPC_Decode, 240, 11, 146, 1, // Opcode: UMULHxxx
+/* 21111 */ MCD_OPC_FilterValue, 5, 121, 1, // Skip to: 21492
+/* 21115 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 21118 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 21211
+/* 21122 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21125 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21140
+/* 21129 */ MCD_OPC_CheckField, 21, 1, 0, 70, 17, // Skip to: 25557
+/* 21135 */ MCD_OPC_Decode, 210, 5, 136, 1, // Opcode: LS32_STUR
+/* 21140 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 21155
+/* 21144 */ MCD_OPC_CheckField, 21, 1, 0, 55, 17, // Skip to: 25557
+/* 21150 */ MCD_OPC_Decode, 206, 5, 137, 1, // Opcode: LS32_PostInd_STR
+/* 21155 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 21196
+/* 21159 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 21162 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21171
+/* 21166 */ MCD_OPC_Decode, 212, 5, 136, 1, // Opcode: LS32_UnPriv_STR
+/* 21171 */ MCD_OPC_FilterValue, 1, 30, 17, // Skip to: 25557
+/* 21175 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21178 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21187
+/* 21182 */ MCD_OPC_Decode, 214, 5, 138, 1, // Opcode: LS32_Wm_RegOffset_STR
+/* 21187 */ MCD_OPC_FilterValue, 1, 14, 17, // Skip to: 25557
+/* 21191 */ MCD_OPC_Decode, 216, 5, 139, 1, // Opcode: LS32_Xm_RegOffset_STR
+/* 21196 */ MCD_OPC_FilterValue, 3, 5, 17, // Skip to: 25557
+/* 21200 */ MCD_OPC_CheckField, 21, 1, 0, 255, 16, // Skip to: 25557
+/* 21206 */ MCD_OPC_Decode, 208, 5, 137, 1, // Opcode: LS32_PreInd_STR
+/* 21211 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 21304
+/* 21215 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21218 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21233
+/* 21222 */ MCD_OPC_CheckField, 21, 1, 0, 233, 16, // Skip to: 25557
+/* 21228 */ MCD_OPC_Decode, 204, 5, 136, 1, // Opcode: LS32_LDUR
+/* 21233 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 21248
+/* 21237 */ MCD_OPC_CheckField, 21, 1, 0, 218, 16, // Skip to: 25557
+/* 21243 */ MCD_OPC_Decode, 205, 5, 137, 1, // Opcode: LS32_PostInd_LDR
+/* 21248 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 21289
+/* 21252 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 21255 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21264
+/* 21259 */ MCD_OPC_Decode, 211, 5, 136, 1, // Opcode: LS32_UnPriv_LDR
+/* 21264 */ MCD_OPC_FilterValue, 1, 193, 16, // Skip to: 25557
+/* 21268 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21271 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21280
+/* 21275 */ MCD_OPC_Decode, 213, 5, 138, 1, // Opcode: LS32_Wm_RegOffset_LDR
+/* 21280 */ MCD_OPC_FilterValue, 1, 177, 16, // Skip to: 25557
+/* 21284 */ MCD_OPC_Decode, 215, 5, 139, 1, // Opcode: LS32_Xm_RegOffset_LDR
+/* 21289 */ MCD_OPC_FilterValue, 3, 168, 16, // Skip to: 25557
+/* 21293 */ MCD_OPC_CheckField, 21, 1, 0, 162, 16, // Skip to: 25557
+/* 21299 */ MCD_OPC_Decode, 207, 5, 137, 1, // Opcode: LS32_PreInd_LDR
+/* 21304 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 21397
+/* 21308 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21311 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21326
+/* 21315 */ MCD_OPC_CheckField, 21, 1, 0, 140, 16, // Skip to: 25557
+/* 21321 */ MCD_OPC_Decode, 182, 5, 140, 1, // Opcode: LDURSWx
+/* 21326 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 21341
+/* 21330 */ MCD_OPC_CheckField, 21, 1, 0, 125, 16, // Skip to: 25557
+/* 21336 */ MCD_OPC_Decode, 167, 5, 137, 1, // Opcode: LDRSWx_PostInd
+/* 21341 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 21382
+/* 21345 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 21348 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21357
+/* 21352 */ MCD_OPC_Decode, 181, 5, 140, 1, // Opcode: LDTRSWx
+/* 21357 */ MCD_OPC_FilterValue, 1, 100, 16, // Skip to: 25557
+/* 21361 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21364 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21373
+/* 21368 */ MCD_OPC_Decode, 169, 5, 141, 1, // Opcode: LDRSWx_Wm_RegOffset
+/* 21373 */ MCD_OPC_FilterValue, 1, 84, 16, // Skip to: 25557
+/* 21377 */ MCD_OPC_Decode, 170, 5, 142, 1, // Opcode: LDRSWx_Xm_RegOffset
+/* 21382 */ MCD_OPC_FilterValue, 3, 75, 16, // Skip to: 25557
+/* 21386 */ MCD_OPC_CheckField, 21, 1, 0, 69, 16, // Skip to: 25557
+/* 21392 */ MCD_OPC_Decode, 168, 5, 137, 1, // Opcode: LDRSWx_PreInd
+/* 21397 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 21406
+/* 21401 */ MCD_OPC_Decode, 209, 5, 143, 1, // Opcode: LS32_STR
+/* 21406 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 21415
+/* 21410 */ MCD_OPC_Decode, 203, 5, 143, 1, // Opcode: LS32_LDR
+/* 21415 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 21423
+/* 21419 */ MCD_OPC_Decode, 166, 5, 100, // Opcode: LDRSWx
+/* 21423 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 21443
+/* 21427 */ MCD_OPC_CheckField, 21, 1, 0, 28, 16, // Skip to: 25557
+/* 21433 */ MCD_OPC_CheckField, 10, 6, 0, 22, 16, // Skip to: 25557
+/* 21439 */ MCD_OPC_Decode, 18, 146, 1, // Opcode: ADCSxxx
+/* 21443 */ MCD_OPC_FilterValue, 9, 14, 16, // Skip to: 25557
+/* 21447 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21450 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 21471
+/* 21454 */ MCD_OPC_CheckField, 21, 1, 0, 1, 16, // Skip to: 25557
+/* 21460 */ MCD_OPC_CheckField, 4, 1, 0, 251, 15, // Skip to: 25557
+/* 21466 */ MCD_OPC_Decode, 225, 1, 151, 1, // Opcode: CCMNxx
+/* 21471 */ MCD_OPC_FilterValue, 2, 242, 15, // Skip to: 25557
+/* 21475 */ MCD_OPC_CheckField, 21, 1, 0, 236, 15, // Skip to: 25557
+/* 21481 */ MCD_OPC_CheckField, 4, 1, 0, 230, 15, // Skip to: 25557
+/* 21487 */ MCD_OPC_Decode, 224, 1, 152, 1, // Opcode: CCMNxi
+/* 21492 */ MCD_OPC_FilterValue, 6, 148, 0, // Skip to: 21644
+/* 21496 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 21499 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21508
+/* 21503 */ MCD_OPC_Decode, 185, 7, 153, 1, // Opcode: PRFM_lit
+/* 21508 */ MCD_OPC_FilterValue, 2, 205, 15, // Skip to: 25557
+/* 21512 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21515 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 21571
+/* 21519 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 21522 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21537
+/* 21526 */ MCD_OPC_CheckField, 12, 4, 0, 185, 15, // Skip to: 25557
+/* 21532 */ MCD_OPC_Decode, 139, 8, 146, 1, // Opcode: SBCxxx
+/* 21537 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 21546
+/* 21541 */ MCD_OPC_Decode, 241, 2, 147, 1, // Opcode: CSINVxxxc
+/* 21546 */ MCD_OPC_FilterValue, 6, 167, 15, // Skip to: 25557
+/* 21550 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ...
+/* 21553 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21562
+/* 21557 */ MCD_OPC_Decode, 206, 7, 154, 1, // Opcode: RBITxx
+/* 21562 */ MCD_OPC_FilterValue, 1, 151, 15, // Skip to: 25557
+/* 21566 */ MCD_OPC_Decode, 234, 1, 154, 1, // Opcode: CLZxx
+/* 21571 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 21612
+/* 21575 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 21578 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 21587
+/* 21582 */ MCD_OPC_Decode, 243, 2, 147, 1, // Opcode: CSNEGxxxc
+/* 21587 */ MCD_OPC_FilterValue, 6, 126, 15, // Skip to: 25557
+/* 21591 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ...
+/* 21594 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21603
+/* 21598 */ MCD_OPC_Decode, 210, 7, 154, 1, // Opcode: REV16xx
+/* 21603 */ MCD_OPC_FilterValue, 1, 110, 15, // Skip to: 25557
+/* 21607 */ MCD_OPC_Decode, 232, 1, 154, 1, // Opcode: CLSxx
+/* 21612 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 21628
+/* 21616 */ MCD_OPC_CheckField, 12, 12, 128, 24, 94, 15, // Skip to: 25557
+/* 21623 */ MCD_OPC_Decode, 211, 7, 154, 1, // Opcode: REV32xx
+/* 21628 */ MCD_OPC_FilterValue, 3, 85, 15, // Skip to: 25557
+/* 21632 */ MCD_OPC_CheckField, 12, 12, 128, 24, 78, 15, // Skip to: 25557
+/* 21639 */ MCD_OPC_Decode, 213, 7, 154, 1, // Opcode: REVxx
+/* 21644 */ MCD_OPC_FilterValue, 7, 69, 15, // Skip to: 25557
+/* 21648 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 21651 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 21744
+/* 21655 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21658 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21673
+/* 21662 */ MCD_OPC_CheckField, 21, 1, 0, 49, 15, // Skip to: 25557
+/* 21668 */ MCD_OPC_Decode, 224, 5, 140, 1, // Opcode: LS64_STUR
+/* 21673 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 21688
+/* 21677 */ MCD_OPC_CheckField, 21, 1, 0, 34, 15, // Skip to: 25557
+/* 21683 */ MCD_OPC_Decode, 220, 5, 137, 1, // Opcode: LS64_PostInd_STR
+/* 21688 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 21729
+/* 21692 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 21695 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21704
+/* 21699 */ MCD_OPC_Decode, 226, 5, 140, 1, // Opcode: LS64_UnPriv_STR
+/* 21704 */ MCD_OPC_FilterValue, 1, 9, 15, // Skip to: 25557
+/* 21708 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21711 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21720
+/* 21715 */ MCD_OPC_Decode, 228, 5, 141, 1, // Opcode: LS64_Wm_RegOffset_STR
+/* 21720 */ MCD_OPC_FilterValue, 1, 249, 14, // Skip to: 25557
+/* 21724 */ MCD_OPC_Decode, 230, 5, 142, 1, // Opcode: LS64_Xm_RegOffset_STR
+/* 21729 */ MCD_OPC_FilterValue, 3, 240, 14, // Skip to: 25557
+/* 21733 */ MCD_OPC_CheckField, 21, 1, 0, 234, 14, // Skip to: 25557
+/* 21739 */ MCD_OPC_Decode, 222, 5, 137, 1, // Opcode: LS64_PreInd_STR
+/* 21744 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 21837
+/* 21748 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21751 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21766
+/* 21755 */ MCD_OPC_CheckField, 21, 1, 0, 212, 14, // Skip to: 25557
+/* 21761 */ MCD_OPC_Decode, 218, 5, 140, 1, // Opcode: LS64_LDUR
+/* 21766 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 21781
+/* 21770 */ MCD_OPC_CheckField, 21, 1, 0, 197, 14, // Skip to: 25557
+/* 21776 */ MCD_OPC_Decode, 219, 5, 137, 1, // Opcode: LS64_PostInd_LDR
+/* 21781 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 21822
+/* 21785 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 21788 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21797
+/* 21792 */ MCD_OPC_Decode, 225, 5, 140, 1, // Opcode: LS64_UnPriv_LDR
+/* 21797 */ MCD_OPC_FilterValue, 1, 172, 14, // Skip to: 25557
+/* 21801 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21804 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 21813
+/* 21808 */ MCD_OPC_Decode, 227, 5, 141, 1, // Opcode: LS64_Wm_RegOffset_LDR
+/* 21813 */ MCD_OPC_FilterValue, 1, 156, 14, // Skip to: 25557
+/* 21817 */ MCD_OPC_Decode, 229, 5, 142, 1, // Opcode: LS64_Xm_RegOffset_LDR
+/* 21822 */ MCD_OPC_FilterValue, 3, 147, 14, // Skip to: 25557
+/* 21826 */ MCD_OPC_CheckField, 21, 1, 0, 141, 14, // Skip to: 25557
+/* 21832 */ MCD_OPC_Decode, 221, 5, 137, 1, // Opcode: LS64_PreInd_LDR
+/* 21837 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 21896
+/* 21841 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21844 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21859
+/* 21848 */ MCD_OPC_CheckField, 21, 1, 0, 119, 14, // Skip to: 25557
+/* 21854 */ MCD_OPC_Decode, 186, 7, 155, 1, // Opcode: PRFUM
+/* 21859 */ MCD_OPC_FilterValue, 2, 110, 14, // Skip to: 25557
+/* 21863 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 21866 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 21881
+/* 21870 */ MCD_OPC_CheckField, 21, 1, 1, 97, 14, // Skip to: 25557
+/* 21876 */ MCD_OPC_Decode, 183, 7, 156, 1, // Opcode: PRFM_Wm_RegOffset
+/* 21881 */ MCD_OPC_FilterValue, 1, 88, 14, // Skip to: 25557
+/* 21885 */ MCD_OPC_CheckField, 21, 1, 1, 82, 14, // Skip to: 25557
+/* 21891 */ MCD_OPC_Decode, 184, 7, 157, 1, // Opcode: PRFM_Xm_RegOffset
+/* 21896 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 21904
+/* 21900 */ MCD_OPC_Decode, 223, 5, 100, // Opcode: LS64_STR
+/* 21904 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 21912
+/* 21908 */ MCD_OPC_Decode, 217, 5, 100, // Opcode: LS64_LDR
+/* 21912 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 21921
+/* 21916 */ MCD_OPC_Decode, 182, 7, 158, 1, // Opcode: PRFM
+/* 21921 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 21942
+/* 21925 */ MCD_OPC_CheckField, 21, 1, 0, 42, 14, // Skip to: 25557
+/* 21931 */ MCD_OPC_CheckField, 10, 6, 0, 36, 14, // Skip to: 25557
+/* 21937 */ MCD_OPC_Decode, 137, 8, 146, 1, // Opcode: SBCSxxx
+/* 21942 */ MCD_OPC_FilterValue, 9, 27, 14, // Skip to: 25557
+/* 21946 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 21949 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 21970
+/* 21953 */ MCD_OPC_CheckField, 21, 1, 0, 14, 14, // Skip to: 25557
+/* 21959 */ MCD_OPC_CheckField, 4, 1, 0, 8, 14, // Skip to: 25557
+/* 21965 */ MCD_OPC_Decode, 229, 1, 151, 1, // Opcode: CCMPxx
+/* 21970 */ MCD_OPC_FilterValue, 2, 255, 13, // Skip to: 25557
+/* 21974 */ MCD_OPC_CheckField, 21, 1, 0, 249, 13, // Skip to: 25557
+/* 21980 */ MCD_OPC_CheckField, 4, 1, 0, 243, 13, // Skip to: 25557
+/* 21986 */ MCD_OPC_Decode, 228, 1, 152, 1, // Opcode: CCMPxi
+/* 21991 */ MCD_OPC_FilterValue, 7, 234, 13, // Skip to: 25557
+/* 21995 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
+/* 21998 */ MCD_OPC_FilterValue, 0, 107, 4, // Skip to: 23133
+/* 22002 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 22005 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22014
+/* 22009 */ MCD_OPC_Decode, 174, 5, 159, 1, // Opcode: LDRs_lit
+/* 22014 */ MCD_OPC_FilterValue, 2, 240, 3, // Skip to: 23026
+/* 22018 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 22021 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 22064
+/* 22025 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22028 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22037
+/* 22032 */ MCD_OPC_Decode, 151, 8, 160, 1, // Opcode: SCVTFswi
+/* 22037 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22046
+/* 22041 */ MCD_OPC_Decode, 181, 11, 160, 1, // Opcode: UCVTFswi
+/* 22046 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 22055
+/* 22050 */ MCD_OPC_Decode, 241, 3, 161, 1, // Opcode: FCVTZSwsi
+/* 22055 */ MCD_OPC_FilterValue, 25, 170, 13, // Skip to: 25557
+/* 22059 */ MCD_OPC_Decode, 249, 3, 161, 1, // Opcode: FCVTZUwsi
+/* 22064 */ MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 22529
+/* 22068 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 22071 */ MCD_OPC_FilterValue, 0, 76, 1, // Skip to: 22407
+/* 22075 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 22078 */ MCD_OPC_FilterValue, 0, 54, 1, // Skip to: 22392
+/* 22082 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 22085 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 22218
+/* 22089 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22092 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22101
+/* 22096 */ MCD_OPC_Decode, 223, 3, 162, 1, // Opcode: FCVTNSws
+/* 22101 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 22110
+/* 22105 */ MCD_OPC_Decode, 227, 3, 162, 1, // Opcode: FCVTNUws
+/* 22110 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22119
+/* 22114 */ MCD_OPC_Decode, 150, 8, 163, 1, // Opcode: SCVTFsw
+/* 22119 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22128
+/* 22123 */ MCD_OPC_Decode, 180, 11, 163, 1, // Opcode: UCVTFsw
+/* 22128 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 22137
+/* 22132 */ MCD_OPC_Decode, 207, 3, 162, 1, // Opcode: FCVTASws
+/* 22137 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 22146
+/* 22141 */ MCD_OPC_Decode, 211, 3, 162, 1, // Opcode: FCVTAUws
+/* 22146 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 22155
+/* 22150 */ MCD_OPC_Decode, 195, 4, 162, 1, // Opcode: FMOVws
+/* 22155 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 22164
+/* 22159 */ MCD_OPC_Decode, 190, 4, 163, 1, // Opcode: FMOVsw
+/* 22164 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 22173
+/* 22168 */ MCD_OPC_Decode, 231, 3, 162, 1, // Opcode: FCVTPSws
+/* 22173 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 22182
+/* 22177 */ MCD_OPC_Decode, 235, 3, 162, 1, // Opcode: FCVTPUws
+/* 22182 */ MCD_OPC_FilterValue, 16, 5, 0, // Skip to: 22191
+/* 22186 */ MCD_OPC_Decode, 215, 3, 162, 1, // Opcode: FCVTMSws
+/* 22191 */ MCD_OPC_FilterValue, 17, 5, 0, // Skip to: 22200
+/* 22195 */ MCD_OPC_Decode, 219, 3, 162, 1, // Opcode: FCVTMUws
+/* 22200 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 22209
+/* 22204 */ MCD_OPC_Decode, 240, 3, 162, 1, // Opcode: FCVTZSws
+/* 22209 */ MCD_OPC_FilterValue, 25, 16, 13, // Skip to: 25557
+/* 22213 */ MCD_OPC_Decode, 248, 3, 162, 1, // Opcode: FCVTZUws
+/* 22218 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 22261
+/* 22222 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 22225 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22234
+/* 22229 */ MCD_OPC_Decode, 202, 3, 164, 1, // Opcode: FCMPss_quiet
+/* 22234 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 22243
+/* 22238 */ MCD_OPC_Decode, 200, 3, 165, 1, // Opcode: FCMPsi_quiet
+/* 22243 */ MCD_OPC_FilterValue, 16, 5, 0, // Skip to: 22252
+/* 22247 */ MCD_OPC_Decode, 203, 3, 164, 1, // Opcode: FCMPss_sig
+/* 22252 */ MCD_OPC_FilterValue, 24, 229, 12, // Skip to: 25557
+/* 22256 */ MCD_OPC_Decode, 201, 3, 165, 1, // Opcode: FCMPsi_sig
+/* 22261 */ MCD_OPC_FilterValue, 2, 57, 0, // Skip to: 22322
+/* 22265 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22268 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22277
+/* 22272 */ MCD_OPC_Decode, 189, 4, 166, 1, // Opcode: FMOVss
+/* 22277 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 22286
+/* 22281 */ MCD_OPC_Decode, 209, 4, 166, 1, // Opcode: FNEGss
+/* 22286 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 22295
+/* 22290 */ MCD_OPC_Decode, 226, 4, 166, 1, // Opcode: FRINTNss
+/* 22295 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 22304
+/* 22299 */ MCD_OPC_Decode, 224, 4, 166, 1, // Opcode: FRINTMss
+/* 22304 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 22313
+/* 22308 */ MCD_OPC_Decode, 220, 4, 166, 1, // Opcode: FRINTAss
+/* 22313 */ MCD_OPC_FilterValue, 7, 168, 12, // Skip to: 25557
+/* 22317 */ MCD_OPC_Decode, 230, 4, 166, 1, // Opcode: FRINTXss
+/* 22322 */ MCD_OPC_FilterValue, 6, 159, 12, // Skip to: 25557
+/* 22326 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22329 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22338
+/* 22333 */ MCD_OPC_Decode, 151, 3, 166, 1, // Opcode: FABSss
+/* 22338 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 22347
+/* 22342 */ MCD_OPC_Decode, 237, 4, 166, 1, // Opcode: FSQRTss
+/* 22347 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22356
+/* 22351 */ MCD_OPC_Decode, 255, 3, 167, 1, // Opcode: FCVTds
+/* 22356 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22365
+/* 22360 */ MCD_OPC_Decode, 129, 4, 168, 1, // Opcode: FCVThs
+/* 22365 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 22374
+/* 22369 */ MCD_OPC_Decode, 228, 4, 166, 1, // Opcode: FRINTPss
+/* 22374 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 22383
+/* 22378 */ MCD_OPC_Decode, 232, 4, 166, 1, // Opcode: FRINTZss
+/* 22383 */ MCD_OPC_FilterValue, 7, 98, 12, // Skip to: 25557
+/* 22387 */ MCD_OPC_Decode, 222, 4, 166, 1, // Opcode: FRINTIss
+/* 22392 */ MCD_OPC_FilterValue, 1, 89, 12, // Skip to: 25557
+/* 22396 */ MCD_OPC_CheckField, 5, 5, 0, 83, 12, // Skip to: 25557
+/* 22402 */ MCD_OPC_Decode, 188, 4, 169, 1, // Opcode: FMOVsi
+/* 22407 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 22432
+/* 22411 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 22414 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22423
+/* 22418 */ MCD_OPC_Decode, 171, 3, 170, 1, // Opcode: FCCMPss
+/* 22423 */ MCD_OPC_FilterValue, 1, 58, 12, // Skip to: 25557
+/* 22427 */ MCD_OPC_Decode, 169, 3, 170, 1, // Opcode: FCCMPEss
+/* 22432 */ MCD_OPC_FilterValue, 2, 84, 0, // Skip to: 22520
+/* 22436 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 22439 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22448
+/* 22443 */ MCD_OPC_Decode, 204, 4, 171, 1, // Opcode: FMULsss
+/* 22448 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 22457
+/* 22452 */ MCD_OPC_Decode, 133, 4, 171, 1, // Opcode: FDIVsss
+/* 22457 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22466
+/* 22461 */ MCD_OPC_Decode, 164, 3, 171, 1, // Opcode: FADDsss
+/* 22466 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22475
+/* 22470 */ MCD_OPC_Decode, 239, 4, 171, 1, // Opcode: FSUBsss
+/* 22475 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 22484
+/* 22479 */ MCD_OPC_Decode, 155, 4, 171, 1, // Opcode: FMAXsss
+/* 22484 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 22493
+/* 22488 */ MCD_OPC_Decode, 175, 4, 171, 1, // Opcode: FMINsss
+/* 22493 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 22502
+/* 22497 */ MCD_OPC_Decode, 145, 4, 171, 1, // Opcode: FMAXNMsss
+/* 22502 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 22511
+/* 22506 */ MCD_OPC_Decode, 165, 4, 171, 1, // Opcode: FMINNMsss
+/* 22511 */ MCD_OPC_FilterValue, 8, 226, 11, // Skip to: 25557
+/* 22515 */ MCD_OPC_Decode, 215, 4, 171, 1, // Opcode: FNMULsss
+/* 22520 */ MCD_OPC_FilterValue, 3, 217, 11, // Skip to: 25557
+/* 22524 */ MCD_OPC_Decode, 205, 3, 172, 1, // Opcode: FCSELsssc
+/* 22529 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 22572
+/* 22533 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22536 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22545
+/* 22540 */ MCD_OPC_Decode, 147, 8, 173, 1, // Opcode: SCVTFdwi
+/* 22545 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22554
+/* 22549 */ MCD_OPC_Decode, 177, 11, 173, 1, // Opcode: UCVTFdwi
+/* 22554 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 22563
+/* 22558 */ MCD_OPC_Decode, 239, 3, 174, 1, // Opcode: FCVTZSwdi
+/* 22563 */ MCD_OPC_FilterValue, 25, 174, 11, // Skip to: 25557
+/* 22567 */ MCD_OPC_Decode, 247, 3, 174, 1, // Opcode: FCVTZUwdi
+/* 22572 */ MCD_OPC_FilterValue, 3, 167, 1, // Skip to: 22999
+/* 22576 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 22579 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 22886
+/* 22583 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 22586 */ MCD_OPC_FilterValue, 0, 25, 1, // Skip to: 22871
+/* 22590 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 22593 */ MCD_OPC_FilterValue, 0, 111, 0, // Skip to: 22708
+/* 22597 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22600 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22609
+/* 22604 */ MCD_OPC_Decode, 222, 3, 175, 1, // Opcode: FCVTNSwd
+/* 22609 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 22618
+/* 22613 */ MCD_OPC_Decode, 226, 3, 175, 1, // Opcode: FCVTNUwd
+/* 22618 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22627
+/* 22622 */ MCD_OPC_Decode, 146, 8, 176, 1, // Opcode: SCVTFdw
+/* 22627 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22636
+/* 22631 */ MCD_OPC_Decode, 176, 11, 176, 1, // Opcode: UCVTFdw
+/* 22636 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 22645
+/* 22640 */ MCD_OPC_Decode, 206, 3, 175, 1, // Opcode: FCVTASwd
+/* 22645 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 22654
+/* 22649 */ MCD_OPC_Decode, 210, 3, 175, 1, // Opcode: FCVTAUwd
+/* 22654 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 22663
+/* 22658 */ MCD_OPC_Decode, 230, 3, 175, 1, // Opcode: FCVTPSwd
+/* 22663 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 22672
+/* 22667 */ MCD_OPC_Decode, 234, 3, 175, 1, // Opcode: FCVTPUwd
+/* 22672 */ MCD_OPC_FilterValue, 16, 5, 0, // Skip to: 22681
+/* 22676 */ MCD_OPC_Decode, 214, 3, 175, 1, // Opcode: FCVTMSwd
+/* 22681 */ MCD_OPC_FilterValue, 17, 5, 0, // Skip to: 22690
+/* 22685 */ MCD_OPC_Decode, 218, 3, 175, 1, // Opcode: FCVTMUwd
+/* 22690 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 22699
+/* 22694 */ MCD_OPC_Decode, 238, 3, 175, 1, // Opcode: FCVTZSwd
+/* 22699 */ MCD_OPC_FilterValue, 25, 38, 11, // Skip to: 25557
+/* 22703 */ MCD_OPC_Decode, 246, 3, 175, 1, // Opcode: FCVTZUwd
+/* 22708 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 22751
+/* 22712 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 22715 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22724
+/* 22719 */ MCD_OPC_Decode, 196, 3, 177, 1, // Opcode: FCMPdd_quiet
+/* 22724 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 22733
+/* 22728 */ MCD_OPC_Decode, 198, 3, 178, 1, // Opcode: FCMPdi_quiet
+/* 22733 */ MCD_OPC_FilterValue, 16, 5, 0, // Skip to: 22742
+/* 22737 */ MCD_OPC_Decode, 197, 3, 177, 1, // Opcode: FCMPdd_sig
+/* 22742 */ MCD_OPC_FilterValue, 24, 251, 10, // Skip to: 25557
+/* 22746 */ MCD_OPC_Decode, 199, 3, 178, 1, // Opcode: FCMPdi_sig
+/* 22751 */ MCD_OPC_FilterValue, 2, 60, 0, // Skip to: 22815
+/* 22755 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22758 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 22766
+/* 22762 */ MCD_OPC_Decode, 185, 4, 32, // Opcode: FMOVdd
+/* 22766 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 22774
+/* 22770 */ MCD_OPC_Decode, 208, 4, 32, // Opcode: FNEGdd
+/* 22774 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 22783
+/* 22778 */ MCD_OPC_Decode, 130, 4, 179, 1, // Opcode: FCVTsd
+/* 22783 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 22791
+/* 22787 */ MCD_OPC_Decode, 225, 4, 32, // Opcode: FRINTNdd
+/* 22791 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 22799
+/* 22795 */ MCD_OPC_Decode, 223, 4, 32, // Opcode: FRINTMdd
+/* 22799 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 22807
+/* 22803 */ MCD_OPC_Decode, 219, 4, 32, // Opcode: FRINTAdd
+/* 22807 */ MCD_OPC_FilterValue, 7, 186, 10, // Skip to: 25557
+/* 22811 */ MCD_OPC_Decode, 229, 4, 32, // Opcode: FRINTXdd
+/* 22815 */ MCD_OPC_FilterValue, 6, 178, 10, // Skip to: 25557
+/* 22819 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 22822 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 22830
+/* 22826 */ MCD_OPC_Decode, 150, 3, 32, // Opcode: FABSdd
+/* 22830 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 22838
+/* 22834 */ MCD_OPC_Decode, 236, 4, 32, // Opcode: FSQRTdd
+/* 22838 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 22847
+/* 22842 */ MCD_OPC_Decode, 128, 4, 180, 1, // Opcode: FCVThd
+/* 22847 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 22855
+/* 22851 */ MCD_OPC_Decode, 227, 4, 32, // Opcode: FRINTPdd
+/* 22855 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 22863
+/* 22859 */ MCD_OPC_Decode, 231, 4, 32, // Opcode: FRINTZdd
+/* 22863 */ MCD_OPC_FilterValue, 7, 130, 10, // Skip to: 25557
+/* 22867 */ MCD_OPC_Decode, 221, 4, 32, // Opcode: FRINTIdd
+/* 22871 */ MCD_OPC_FilterValue, 1, 122, 10, // Skip to: 25557
+/* 22875 */ MCD_OPC_CheckField, 5, 5, 0, 116, 10, // Skip to: 25557
+/* 22881 */ MCD_OPC_Decode, 186, 4, 181, 1, // Opcode: FMOVdi
+/* 22886 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 22911
+/* 22890 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 22893 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 22902
+/* 22897 */ MCD_OPC_Decode, 170, 3, 182, 1, // Opcode: FCCMPdd
+/* 22902 */ MCD_OPC_FilterValue, 1, 91, 10, // Skip to: 25557
+/* 22906 */ MCD_OPC_Decode, 168, 3, 182, 1, // Opcode: FCCMPEdd
+/* 22911 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 22990
+/* 22915 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 22918 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 22926
+/* 22922 */ MCD_OPC_Decode, 203, 4, 24, // Opcode: FMULddd
+/* 22926 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 22934
+/* 22930 */ MCD_OPC_Decode, 132, 4, 24, // Opcode: FDIVddd
+/* 22934 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 22942
+/* 22938 */ MCD_OPC_Decode, 163, 3, 24, // Opcode: FADDddd
+/* 22942 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 22950
+/* 22946 */ MCD_OPC_Decode, 238, 4, 24, // Opcode: FSUBddd
+/* 22950 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 22958
+/* 22954 */ MCD_OPC_Decode, 154, 4, 24, // Opcode: FMAXddd
+/* 22958 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 22966
+/* 22962 */ MCD_OPC_Decode, 174, 4, 24, // Opcode: FMINddd
+/* 22966 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 22974
+/* 22970 */ MCD_OPC_Decode, 144, 4, 24, // Opcode: FMAXNMddd
+/* 22974 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 22982
+/* 22978 */ MCD_OPC_Decode, 164, 4, 24, // Opcode: FMINNMddd
+/* 22982 */ MCD_OPC_FilterValue, 8, 11, 10, // Skip to: 25557
+/* 22986 */ MCD_OPC_Decode, 214, 4, 24, // Opcode: FNMULddd
+/* 22990 */ MCD_OPC_FilterValue, 3, 3, 10, // Skip to: 25557
+/* 22994 */ MCD_OPC_Decode, 204, 3, 183, 1, // Opcode: FCSELdddc
+/* 22999 */ MCD_OPC_FilterValue, 7, 250, 9, // Skip to: 25557
+/* 23003 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ...
+/* 23006 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 23016
+/* 23011 */ MCD_OPC_Decode, 131, 4, 184, 1, // Opcode: FCVTsh
+/* 23016 */ MCD_OPC_FilterValue, 176, 1, 232, 9, // Skip to: 25557
+/* 23021 */ MCD_OPC_Decode, 254, 3, 185, 1, // Opcode: FCVTdh
+/* 23026 */ MCD_OPC_FilterValue, 3, 223, 9, // Skip to: 25557
+/* 23030 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 23033 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 23058
+/* 23037 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 23040 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 23049
+/* 23044 */ MCD_OPC_Decode, 138, 4, 186, 1, // Opcode: FMADDssss
+/* 23049 */ MCD_OPC_FilterValue, 1, 200, 9, // Skip to: 25557
+/* 23053 */ MCD_OPC_Decode, 199, 4, 186, 1, // Opcode: FMSUBssss
+/* 23058 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 23083
+/* 23062 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 23065 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 23074
+/* 23069 */ MCD_OPC_Decode, 211, 4, 186, 1, // Opcode: FNMADDssss
+/* 23074 */ MCD_OPC_FilterValue, 1, 175, 9, // Skip to: 25557
+/* 23078 */ MCD_OPC_Decode, 213, 4, 186, 1, // Opcode: FNMSUBssss
+/* 23083 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 23108
+/* 23087 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 23090 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 23099
+/* 23094 */ MCD_OPC_Decode, 137, 4, 187, 1, // Opcode: FMADDdddd
+/* 23099 */ MCD_OPC_FilterValue, 1, 150, 9, // Skip to: 25557
+/* 23103 */ MCD_OPC_Decode, 198, 4, 187, 1, // Opcode: FMSUBdddd
+/* 23108 */ MCD_OPC_FilterValue, 3, 141, 9, // Skip to: 25557
+/* 23112 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ...
+/* 23115 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 23124
+/* 23119 */ MCD_OPC_Decode, 210, 4, 187, 1, // Opcode: FNMADDdddd
+/* 23124 */ MCD_OPC_FilterValue, 1, 125, 9, // Skip to: 25557
+/* 23128 */ MCD_OPC_Decode, 212, 4, 187, 1, // Opcode: FNMSUBdddd
+/* 23133 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 23532
+/* 23137 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 23140 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 23229
+/* 23144 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23147 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23162
+/* 23151 */ MCD_OPC_CheckField, 21, 1, 0, 96, 9, // Skip to: 25557
+/* 23157 */ MCD_OPC_Decode, 172, 6, 188, 1, // Opcode: LSFP8_STUR
+/* 23162 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23177
+/* 23166 */ MCD_OPC_CheckField, 21, 1, 0, 81, 9, // Skip to: 25557
+/* 23172 */ MCD_OPC_Decode, 168, 6, 137, 1, // Opcode: LSFP8_PostInd_STR
+/* 23177 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 23214
+/* 23181 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23184 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23199
+/* 23188 */ MCD_OPC_CheckField, 21, 1, 1, 59, 9, // Skip to: 25557
+/* 23194 */ MCD_OPC_Decode, 174, 6, 189, 1, // Opcode: LSFP8_Wm_RegOffset_STR
+/* 23199 */ MCD_OPC_FilterValue, 1, 50, 9, // Skip to: 25557
+/* 23203 */ MCD_OPC_CheckField, 21, 1, 1, 44, 9, // Skip to: 25557
+/* 23209 */ MCD_OPC_Decode, 176, 6, 190, 1, // Opcode: LSFP8_Xm_RegOffset_STR
+/* 23214 */ MCD_OPC_FilterValue, 3, 35, 9, // Skip to: 25557
+/* 23218 */ MCD_OPC_CheckField, 21, 1, 0, 29, 9, // Skip to: 25557
+/* 23224 */ MCD_OPC_Decode, 170, 6, 137, 1, // Opcode: LSFP8_PreInd_STR
+/* 23229 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 23318
+/* 23233 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23236 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23251
+/* 23240 */ MCD_OPC_CheckField, 21, 1, 0, 7, 9, // Skip to: 25557
+/* 23246 */ MCD_OPC_Decode, 166, 6, 188, 1, // Opcode: LSFP8_LDUR
+/* 23251 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23266
+/* 23255 */ MCD_OPC_CheckField, 21, 1, 0, 248, 8, // Skip to: 25557
+/* 23261 */ MCD_OPC_Decode, 167, 6, 137, 1, // Opcode: LSFP8_PostInd_LDR
+/* 23266 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 23303
+/* 23270 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23273 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23288
+/* 23277 */ MCD_OPC_CheckField, 21, 1, 1, 226, 8, // Skip to: 25557
+/* 23283 */ MCD_OPC_Decode, 173, 6, 189, 1, // Opcode: LSFP8_Wm_RegOffset_LDR
+/* 23288 */ MCD_OPC_FilterValue, 1, 217, 8, // Skip to: 25557
+/* 23292 */ MCD_OPC_CheckField, 21, 1, 1, 211, 8, // Skip to: 25557
+/* 23298 */ MCD_OPC_Decode, 175, 6, 190, 1, // Opcode: LSFP8_Xm_RegOffset_LDR
+/* 23303 */ MCD_OPC_FilterValue, 3, 202, 8, // Skip to: 25557
+/* 23307 */ MCD_OPC_CheckField, 21, 1, 0, 196, 8, // Skip to: 25557
+/* 23313 */ MCD_OPC_Decode, 169, 6, 137, 1, // Opcode: LSFP8_PreInd_LDR
+/* 23318 */ MCD_OPC_FilterValue, 2, 85, 0, // Skip to: 23407
+/* 23322 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23325 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23340
+/* 23329 */ MCD_OPC_CheckField, 21, 1, 0, 174, 8, // Skip to: 25557
+/* 23335 */ MCD_OPC_Decode, 252, 5, 191, 1, // Opcode: LSFP128_STUR
+/* 23340 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23355
+/* 23344 */ MCD_OPC_CheckField, 21, 1, 0, 159, 8, // Skip to: 25557
+/* 23350 */ MCD_OPC_Decode, 248, 5, 137, 1, // Opcode: LSFP128_PostInd_STR
+/* 23355 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 23392
+/* 23359 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23362 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23377
+/* 23366 */ MCD_OPC_CheckField, 21, 1, 1, 137, 8, // Skip to: 25557
+/* 23372 */ MCD_OPC_Decode, 254, 5, 192, 1, // Opcode: LSFP128_Wm_RegOffset_STR
+/* 23377 */ MCD_OPC_FilterValue, 1, 128, 8, // Skip to: 25557
+/* 23381 */ MCD_OPC_CheckField, 21, 1, 1, 122, 8, // Skip to: 25557
+/* 23387 */ MCD_OPC_Decode, 128, 6, 193, 1, // Opcode: LSFP128_Xm_RegOffset_STR
+/* 23392 */ MCD_OPC_FilterValue, 3, 113, 8, // Skip to: 25557
+/* 23396 */ MCD_OPC_CheckField, 21, 1, 0, 107, 8, // Skip to: 25557
+/* 23402 */ MCD_OPC_Decode, 250, 5, 137, 1, // Opcode: LSFP128_PreInd_STR
+/* 23407 */ MCD_OPC_FilterValue, 3, 85, 0, // Skip to: 23496
+/* 23411 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23414 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23429
+/* 23418 */ MCD_OPC_CheckField, 21, 1, 0, 85, 8, // Skip to: 25557
+/* 23424 */ MCD_OPC_Decode, 246, 5, 191, 1, // Opcode: LSFP128_LDUR
+/* 23429 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23444
+/* 23433 */ MCD_OPC_CheckField, 21, 1, 0, 70, 8, // Skip to: 25557
+/* 23439 */ MCD_OPC_Decode, 247, 5, 137, 1, // Opcode: LSFP128_PostInd_LDR
+/* 23444 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 23481
+/* 23448 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23451 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23466
+/* 23455 */ MCD_OPC_CheckField, 21, 1, 1, 48, 8, // Skip to: 25557
+/* 23461 */ MCD_OPC_Decode, 253, 5, 192, 1, // Opcode: LSFP128_Wm_RegOffset_LDR
+/* 23466 */ MCD_OPC_FilterValue, 1, 39, 8, // Skip to: 25557
+/* 23470 */ MCD_OPC_CheckField, 21, 1, 1, 33, 8, // Skip to: 25557
+/* 23476 */ MCD_OPC_Decode, 255, 5, 193, 1, // Opcode: LSFP128_Xm_RegOffset_LDR
+/* 23481 */ MCD_OPC_FilterValue, 3, 24, 8, // Skip to: 25557
+/* 23485 */ MCD_OPC_CheckField, 21, 1, 0, 18, 8, // Skip to: 25557
+/* 23491 */ MCD_OPC_Decode, 249, 5, 137, 1, // Opcode: LSFP128_PreInd_LDR
+/* 23496 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 23505
+/* 23500 */ MCD_OPC_Decode, 171, 6, 194, 1, // Opcode: LSFP8_STR
+/* 23505 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 23514
+/* 23509 */ MCD_OPC_Decode, 165, 6, 194, 1, // Opcode: LSFP8_LDR
+/* 23514 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 23523
+/* 23518 */ MCD_OPC_Decode, 251, 5, 195, 1, // Opcode: LSFP128_STR
+/* 23523 */ MCD_OPC_FilterValue, 7, 238, 7, // Skip to: 25557
+/* 23527 */ MCD_OPC_Decode, 245, 5, 195, 1, // Opcode: LSFP128_LDR
+/* 23532 */ MCD_OPC_FilterValue, 2, 67, 1, // Skip to: 23859
+/* 23536 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 23539 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 23548
+/* 23543 */ MCD_OPC_Decode, 172, 5, 196, 1, // Opcode: LDRd_lit
+/* 23548 */ MCD_OPC_FilterValue, 2, 213, 7, // Skip to: 25557
+/* 23552 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 23555 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 23613
+/* 23559 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 23562 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 23575
+/* 23566 */ MCD_OPC_CheckPredicate, 0, 195, 7, // Skip to: 25557
+/* 23570 */ MCD_OPC_Decode, 239, 8, 197, 1, // Opcode: SQADDbbb
+/* 23575 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 23588
+/* 23579 */ MCD_OPC_CheckPredicate, 0, 182, 7, // Skip to: 25557
+/* 23583 */ MCD_OPC_Decode, 241, 8, 198, 1, // Opcode: SQADDhhh
+/* 23588 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 23601
+/* 23592 */ MCD_OPC_CheckPredicate, 0, 169, 7, // Skip to: 25557
+/* 23596 */ MCD_OPC_Decode, 242, 8, 171, 1, // Opcode: SQADDsss
+/* 23601 */ MCD_OPC_FilterValue, 7, 160, 7, // Skip to: 25557
+/* 23605 */ MCD_OPC_CheckPredicate, 0, 156, 7, // Skip to: 25557
+/* 23609 */ MCD_OPC_Decode, 240, 8, 24, // Opcode: SQADDddd
+/* 23613 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 23671
+/* 23617 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 23620 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 23633
+/* 23624 */ MCD_OPC_CheckPredicate, 0, 137, 7, // Skip to: 25557
+/* 23628 */ MCD_OPC_Decode, 190, 9, 197, 1, // Opcode: SQSUBbbb
+/* 23633 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 23646
+/* 23637 */ MCD_OPC_CheckPredicate, 0, 124, 7, // Skip to: 25557
+/* 23641 */ MCD_OPC_Decode, 192, 9, 198, 1, // Opcode: SQSUBhhh
+/* 23646 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 23659
+/* 23650 */ MCD_OPC_CheckPredicate, 0, 111, 7, // Skip to: 25557
+/* 23654 */ MCD_OPC_Decode, 193, 9, 171, 1, // Opcode: SQSUBsss
+/* 23659 */ MCD_OPC_FilterValue, 7, 102, 7, // Skip to: 25557
+/* 23663 */ MCD_OPC_CheckPredicate, 0, 98, 7, // Skip to: 25557
+/* 23667 */ MCD_OPC_Decode, 191, 9, 24, // Opcode: SQSUBddd
+/* 23671 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 23689
+/* 23675 */ MCD_OPC_CheckPredicate, 0, 86, 7, // Skip to: 25557
+/* 23679 */ MCD_OPC_CheckField, 21, 3, 7, 80, 7, // Skip to: 25557
+/* 23685 */ MCD_OPC_Decode, 242, 9, 24, // Opcode: SSHLddd
+/* 23689 */ MCD_OPC_FilterValue, 19, 54, 0, // Skip to: 23747
+/* 23693 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 23696 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 23709
+/* 23700 */ MCD_OPC_CheckPredicate, 0, 61, 7, // Skip to: 25557
+/* 23704 */ MCD_OPC_Decode, 166, 9, 197, 1, // Opcode: SQSHLbbb
+/* 23709 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 23722
+/* 23713 */ MCD_OPC_CheckPredicate, 0, 48, 7, // Skip to: 25557
+/* 23717 */ MCD_OPC_Decode, 168, 9, 198, 1, // Opcode: SQSHLhhh
+/* 23722 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 23735
+/* 23726 */ MCD_OPC_CheckPredicate, 0, 35, 7, // Skip to: 25557
+/* 23730 */ MCD_OPC_Decode, 169, 9, 171, 1, // Opcode: SQSHLsss
+/* 23735 */ MCD_OPC_FilterValue, 7, 26, 7, // Skip to: 25557
+/* 23739 */ MCD_OPC_CheckPredicate, 0, 22, 7, // Skip to: 25557
+/* 23743 */ MCD_OPC_Decode, 167, 9, 24, // Opcode: SQSHLddd
+/* 23747 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 23765
+/* 23751 */ MCD_OPC_CheckPredicate, 0, 10, 7, // Skip to: 25557
+/* 23755 */ MCD_OPC_CheckField, 21, 3, 7, 4, 7, // Skip to: 25557
+/* 23761 */ MCD_OPC_Decode, 214, 9, 24, // Opcode: SRSHLddd
+/* 23765 */ MCD_OPC_FilterValue, 23, 54, 0, // Skip to: 23823
+/* 23769 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ...
+/* 23772 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 23785
+/* 23776 */ MCD_OPC_CheckPredicate, 0, 241, 6, // Skip to: 25557
+/* 23780 */ MCD_OPC_Decode, 142, 9, 197, 1, // Opcode: SQRSHLbbb
+/* 23785 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 23798
+/* 23789 */ MCD_OPC_CheckPredicate, 0, 228, 6, // Skip to: 25557
+/* 23793 */ MCD_OPC_Decode, 144, 9, 198, 1, // Opcode: SQRSHLhhh
+/* 23798 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 23811
+/* 23802 */ MCD_OPC_CheckPredicate, 0, 215, 6, // Skip to: 25557
+/* 23806 */ MCD_OPC_Decode, 145, 9, 171, 1, // Opcode: SQRSHLsss
+/* 23811 */ MCD_OPC_FilterValue, 7, 206, 6, // Skip to: 25557
+/* 23815 */ MCD_OPC_CheckPredicate, 0, 202, 6, // Skip to: 25557
+/* 23819 */ MCD_OPC_Decode, 143, 9, 24, // Opcode: SQRSHLddd
+/* 23823 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 23840
+/* 23827 */ MCD_OPC_CheckPredicate, 0, 190, 6, // Skip to: 25557
+/* 23831 */ MCD_OPC_CheckField, 21, 3, 7, 184, 6, // Skip to: 25557
+/* 23837 */ MCD_OPC_Decode, 57, 24, // Opcode: ADDddd
+/* 23840 */ MCD_OPC_FilterValue, 46, 177, 6, // Skip to: 25557
+/* 23844 */ MCD_OPC_CheckPredicate, 0, 173, 6, // Skip to: 25557
+/* 23848 */ MCD_OPC_CheckField, 16, 8, 241, 1, 166, 6, // Skip to: 25557
+/* 23855 */ MCD_OPC_Decode, 34, 199, 1, // Opcode: ADDPvv_D_2D
+/* 23859 */ MCD_OPC_FilterValue, 3, 3, 3, // Skip to: 24634
+/* 23863 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 23866 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 23955
+/* 23870 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23873 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23888
+/* 23877 */ MCD_OPC_CheckField, 21, 1, 0, 138, 6, // Skip to: 25557
+/* 23883 */ MCD_OPC_Decode, 136, 6, 200, 1, // Opcode: LSFP16_STUR
+/* 23888 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23903
+/* 23892 */ MCD_OPC_CheckField, 21, 1, 0, 123, 6, // Skip to: 25557
+/* 23898 */ MCD_OPC_Decode, 132, 6, 137, 1, // Opcode: LSFP16_PostInd_STR
+/* 23903 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 23940
+/* 23907 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23910 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23925
+/* 23914 */ MCD_OPC_CheckField, 21, 1, 1, 101, 6, // Skip to: 25557
+/* 23920 */ MCD_OPC_Decode, 138, 6, 201, 1, // Opcode: LSFP16_Wm_RegOffset_STR
+/* 23925 */ MCD_OPC_FilterValue, 1, 92, 6, // Skip to: 25557
+/* 23929 */ MCD_OPC_CheckField, 21, 1, 1, 86, 6, // Skip to: 25557
+/* 23935 */ MCD_OPC_Decode, 140, 6, 202, 1, // Opcode: LSFP16_Xm_RegOffset_STR
+/* 23940 */ MCD_OPC_FilterValue, 3, 77, 6, // Skip to: 25557
+/* 23944 */ MCD_OPC_CheckField, 21, 1, 0, 71, 6, // Skip to: 25557
+/* 23950 */ MCD_OPC_Decode, 134, 6, 137, 1, // Opcode: LSFP16_PreInd_STR
+/* 23955 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 24044
+/* 23959 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 23962 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 23977
+/* 23966 */ MCD_OPC_CheckField, 21, 1, 0, 49, 6, // Skip to: 25557
+/* 23972 */ MCD_OPC_Decode, 130, 6, 200, 1, // Opcode: LSFP16_LDUR
+/* 23977 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 23992
+/* 23981 */ MCD_OPC_CheckField, 21, 1, 0, 34, 6, // Skip to: 25557
+/* 23987 */ MCD_OPC_Decode, 131, 6, 137, 1, // Opcode: LSFP16_PostInd_LDR
+/* 23992 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 24029
+/* 23996 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 23999 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 24014
+/* 24003 */ MCD_OPC_CheckField, 21, 1, 1, 12, 6, // Skip to: 25557
+/* 24009 */ MCD_OPC_Decode, 137, 6, 201, 1, // Opcode: LSFP16_Wm_RegOffset_LDR
+/* 24014 */ MCD_OPC_FilterValue, 1, 3, 6, // Skip to: 25557
+/* 24018 */ MCD_OPC_CheckField, 21, 1, 1, 253, 5, // Skip to: 25557
+/* 24024 */ MCD_OPC_Decode, 139, 6, 202, 1, // Opcode: LSFP16_Xm_RegOffset_LDR
+/* 24029 */ MCD_OPC_FilterValue, 3, 244, 5, // Skip to: 25557
+/* 24033 */ MCD_OPC_CheckField, 21, 1, 0, 238, 5, // Skip to: 25557
+/* 24039 */ MCD_OPC_Decode, 133, 6, 137, 1, // Opcode: LSFP16_PreInd_LDR
+/* 24044 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 24053
+/* 24048 */ MCD_OPC_Decode, 135, 6, 203, 1, // Opcode: LSFP16_STR
+/* 24053 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 24062
+/* 24057 */ MCD_OPC_Decode, 129, 6, 203, 1, // Opcode: LSFP16_LDR
+/* 24062 */ MCD_OPC_FilterValue, 8, 136, 0, // Skip to: 24202
+/* 24066 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 24069 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 24088
+/* 24073 */ MCD_OPC_CheckPredicate, 0, 200, 5, // Skip to: 25557
+/* 24077 */ MCD_OPC_CheckField, 21, 1, 1, 194, 5, // Skip to: 25557
+/* 24083 */ MCD_OPC_Decode, 247, 11, 197, 1, // Opcode: UQADDbbb
+/* 24088 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 24107
+/* 24092 */ MCD_OPC_CheckPredicate, 0, 181, 5, // Skip to: 25557
+/* 24096 */ MCD_OPC_CheckField, 21, 1, 1, 175, 5, // Skip to: 25557
+/* 24102 */ MCD_OPC_Decode, 171, 12, 197, 1, // Opcode: UQSUBbbb
+/* 24107 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 24126
+/* 24111 */ MCD_OPC_CheckPredicate, 0, 162, 5, // Skip to: 25557
+/* 24115 */ MCD_OPC_CheckField, 21, 1, 1, 156, 5, // Skip to: 25557
+/* 24121 */ MCD_OPC_Decode, 147, 12, 197, 1, // Opcode: UQSHLbbb
+/* 24126 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 24145
+/* 24130 */ MCD_OPC_CheckPredicate, 0, 143, 5, // Skip to: 25557
+/* 24134 */ MCD_OPC_CheckField, 21, 1, 1, 137, 5, // Skip to: 25557
+/* 24140 */ MCD_OPC_Decode, 130, 12, 197, 1, // Opcode: UQRSHLbbb
+/* 24145 */ MCD_OPC_FilterValue, 50, 15, 0, // Skip to: 24164
+/* 24149 */ MCD_OPC_CheckPredicate, 0, 124, 5, // Skip to: 25557
+/* 24153 */ MCD_OPC_CheckField, 16, 6, 48, 118, 5, // Skip to: 25557
+/* 24159 */ MCD_OPC_Decode, 140, 4, 179, 1, // Opcode: FMAXNMPvv_S_2S
+/* 24164 */ MCD_OPC_FilterValue, 54, 15, 0, // Skip to: 24183
+/* 24168 */ MCD_OPC_CheckPredicate, 0, 105, 5, // Skip to: 25557
+/* 24172 */ MCD_OPC_CheckField, 16, 6, 48, 99, 5, // Skip to: 25557
+/* 24178 */ MCD_OPC_Decode, 162, 3, 179, 1, // Opcode: FADDPvv_S_2S
+/* 24183 */ MCD_OPC_FilterValue, 62, 90, 5, // Skip to: 25557
+/* 24187 */ MCD_OPC_CheckPredicate, 0, 86, 5, // Skip to: 25557
+/* 24191 */ MCD_OPC_CheckField, 16, 6, 48, 80, 5, // Skip to: 25557
+/* 24197 */ MCD_OPC_Decode, 150, 4, 179, 1, // Opcode: FMAXPvv_S_2S
+/* 24202 */ MCD_OPC_FilterValue, 9, 136, 0, // Skip to: 24342
+/* 24206 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 24209 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 24228
+/* 24213 */ MCD_OPC_CheckPredicate, 0, 60, 5, // Skip to: 25557
+/* 24217 */ MCD_OPC_CheckField, 21, 1, 1, 54, 5, // Skip to: 25557
+/* 24223 */ MCD_OPC_Decode, 249, 11, 198, 1, // Opcode: UQADDhhh
+/* 24228 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 24247
+/* 24232 */ MCD_OPC_CheckPredicate, 0, 41, 5, // Skip to: 25557
+/* 24236 */ MCD_OPC_CheckField, 21, 1, 1, 35, 5, // Skip to: 25557
+/* 24242 */ MCD_OPC_Decode, 173, 12, 198, 1, // Opcode: UQSUBhhh
+/* 24247 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 24266
+/* 24251 */ MCD_OPC_CheckPredicate, 0, 22, 5, // Skip to: 25557
+/* 24255 */ MCD_OPC_CheckField, 21, 1, 1, 16, 5, // Skip to: 25557
+/* 24261 */ MCD_OPC_Decode, 149, 12, 198, 1, // Opcode: UQSHLhhh
+/* 24266 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 24285
+/* 24270 */ MCD_OPC_CheckPredicate, 0, 3, 5, // Skip to: 25557
+/* 24274 */ MCD_OPC_CheckField, 21, 1, 1, 253, 4, // Skip to: 25557
+/* 24280 */ MCD_OPC_Decode, 132, 12, 198, 1, // Opcode: UQRSHLhhh
+/* 24285 */ MCD_OPC_FilterValue, 50, 15, 0, // Skip to: 24304
+/* 24289 */ MCD_OPC_CheckPredicate, 0, 240, 4, // Skip to: 25557
+/* 24293 */ MCD_OPC_CheckField, 16, 6, 48, 234, 4, // Skip to: 25557
+/* 24299 */ MCD_OPC_Decode, 139, 4, 199, 1, // Opcode: FMAXNMPvv_D_2D
+/* 24304 */ MCD_OPC_FilterValue, 54, 15, 0, // Skip to: 24323
+/* 24308 */ MCD_OPC_CheckPredicate, 0, 221, 4, // Skip to: 25557
+/* 24312 */ MCD_OPC_CheckField, 16, 6, 48, 215, 4, // Skip to: 25557
+/* 24318 */ MCD_OPC_Decode, 161, 3, 199, 1, // Opcode: FADDPvv_D_2D
+/* 24323 */ MCD_OPC_FilterValue, 62, 206, 4, // Skip to: 25557
+/* 24327 */ MCD_OPC_CheckPredicate, 0, 202, 4, // Skip to: 25557
+/* 24331 */ MCD_OPC_CheckField, 16, 6, 48, 196, 4, // Skip to: 25557
+/* 24337 */ MCD_OPC_Decode, 149, 4, 199, 1, // Opcode: FMAXPvv_D_2D
+/* 24342 */ MCD_OPC_FilterValue, 10, 117, 0, // Skip to: 24463
+/* 24346 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 24349 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 24368
+/* 24353 */ MCD_OPC_CheckPredicate, 0, 176, 4, // Skip to: 25557
+/* 24357 */ MCD_OPC_CheckField, 21, 1, 1, 170, 4, // Skip to: 25557
+/* 24363 */ MCD_OPC_Decode, 250, 11, 171, 1, // Opcode: UQADDsss
+/* 24368 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 24387
+/* 24372 */ MCD_OPC_CheckPredicate, 0, 157, 4, // Skip to: 25557
+/* 24376 */ MCD_OPC_CheckField, 21, 1, 1, 151, 4, // Skip to: 25557
+/* 24382 */ MCD_OPC_Decode, 174, 12, 171, 1, // Opcode: UQSUBsss
+/* 24387 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 24406
+/* 24391 */ MCD_OPC_CheckPredicate, 0, 138, 4, // Skip to: 25557
+/* 24395 */ MCD_OPC_CheckField, 21, 1, 1, 132, 4, // Skip to: 25557
+/* 24401 */ MCD_OPC_Decode, 150, 12, 171, 1, // Opcode: UQSHLsss
+/* 24406 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 24425
+/* 24410 */ MCD_OPC_CheckPredicate, 0, 119, 4, // Skip to: 25557
+/* 24414 */ MCD_OPC_CheckField, 21, 1, 1, 113, 4, // Skip to: 25557
+/* 24420 */ MCD_OPC_Decode, 133, 12, 171, 1, // Opcode: UQRSHLsss
+/* 24425 */ MCD_OPC_FilterValue, 50, 15, 0, // Skip to: 24444
+/* 24429 */ MCD_OPC_CheckPredicate, 0, 100, 4, // Skip to: 25557
+/* 24433 */ MCD_OPC_CheckField, 16, 6, 48, 94, 4, // Skip to: 25557
+/* 24439 */ MCD_OPC_Decode, 160, 4, 179, 1, // Opcode: FMINNMPvv_S_2S
+/* 24444 */ MCD_OPC_FilterValue, 62, 85, 4, // Skip to: 25557
+/* 24448 */ MCD_OPC_CheckPredicate, 0, 81, 4, // Skip to: 25557
+/* 24452 */ MCD_OPC_CheckField, 16, 6, 48, 75, 4, // Skip to: 25557
+/* 24458 */ MCD_OPC_Decode, 170, 4, 179, 1, // Opcode: FMINPvv_S_2S
+/* 24463 */ MCD_OPC_FilterValue, 11, 66, 4, // Skip to: 25557
+/* 24467 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 24470 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 24488
+/* 24474 */ MCD_OPC_CheckPredicate, 0, 55, 4, // Skip to: 25557
+/* 24478 */ MCD_OPC_CheckField, 21, 1, 1, 49, 4, // Skip to: 25557
+/* 24484 */ MCD_OPC_Decode, 248, 11, 24, // Opcode: UQADDddd
+/* 24488 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 24506
+/* 24492 */ MCD_OPC_CheckPredicate, 0, 37, 4, // Skip to: 25557
+/* 24496 */ MCD_OPC_CheckField, 21, 1, 1, 31, 4, // Skip to: 25557
+/* 24502 */ MCD_OPC_Decode, 172, 12, 24, // Opcode: UQSUBddd
+/* 24506 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 24524
+/* 24510 */ MCD_OPC_CheckPredicate, 0, 19, 4, // Skip to: 25557
+/* 24514 */ MCD_OPC_CheckField, 21, 1, 1, 13, 4, // Skip to: 25557
+/* 24520 */ MCD_OPC_Decode, 216, 12, 24, // Opcode: USHLddd
+/* 24524 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 24542
+/* 24528 */ MCD_OPC_CheckPredicate, 0, 1, 4, // Skip to: 25557
+/* 24532 */ MCD_OPC_CheckField, 21, 1, 1, 251, 3, // Skip to: 25557
+/* 24538 */ MCD_OPC_Decode, 148, 12, 24, // Opcode: UQSHLddd
+/* 24542 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 24560
+/* 24546 */ MCD_OPC_CheckPredicate, 0, 239, 3, // Skip to: 25557
+/* 24550 */ MCD_OPC_CheckField, 21, 1, 1, 233, 3, // Skip to: 25557
+/* 24556 */ MCD_OPC_Decode, 188, 12, 24, // Opcode: URSHLddd
+/* 24560 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 24578
+/* 24564 */ MCD_OPC_CheckPredicate, 0, 221, 3, // Skip to: 25557
+/* 24568 */ MCD_OPC_CheckField, 21, 1, 1, 215, 3, // Skip to: 25557
+/* 24574 */ MCD_OPC_Decode, 131, 12, 24, // Opcode: UQRSHLddd
+/* 24578 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 24596
+/* 24582 */ MCD_OPC_CheckPredicate, 0, 203, 3, // Skip to: 25557
+/* 24586 */ MCD_OPC_CheckField, 21, 1, 1, 197, 3, // Skip to: 25557
+/* 24592 */ MCD_OPC_Decode, 192, 10, 24, // Opcode: SUBddd
+/* 24596 */ MCD_OPC_FilterValue, 50, 15, 0, // Skip to: 24615
+/* 24600 */ MCD_OPC_CheckPredicate, 0, 185, 3, // Skip to: 25557
+/* 24604 */ MCD_OPC_CheckField, 16, 6, 48, 179, 3, // Skip to: 25557
+/* 24610 */ MCD_OPC_Decode, 159, 4, 199, 1, // Opcode: FMINNMPvv_D_2D
+/* 24615 */ MCD_OPC_FilterValue, 62, 170, 3, // Skip to: 25557
+/* 24619 */ MCD_OPC_CheckPredicate, 0, 166, 3, // Skip to: 25557
+/* 24623 */ MCD_OPC_CheckField, 16, 6, 48, 160, 3, // Skip to: 25557
+/* 24629 */ MCD_OPC_Decode, 169, 4, 199, 1, // Opcode: FMINPvv_D_2D
+/* 24634 */ MCD_OPC_FilterValue, 4, 1, 2, // Skip to: 25151
+/* 24638 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 24641 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 24650
+/* 24645 */ MCD_OPC_Decode, 173, 5, 204, 1, // Opcode: LDRq_lit
+/* 24650 */ MCD_OPC_FilterValue, 2, 135, 3, // Skip to: 25557
+/* 24654 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ...
+/* 24657 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 24666
+/* 24661 */ MCD_OPC_Decode, 153, 8, 205, 1, // Opcode: SCVTFsxi
+/* 24666 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 24675
+/* 24670 */ MCD_OPC_Decode, 183, 11, 205, 1, // Opcode: UCVTFsxi
+/* 24675 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 24684
+/* 24679 */ MCD_OPC_Decode, 245, 3, 206, 1, // Opcode: FCVTZSxsi
+/* 24684 */ MCD_OPC_FilterValue, 25, 5, 0, // Skip to: 24693
+/* 24688 */ MCD_OPC_Decode, 253, 3, 206, 1, // Opcode: FCVTZUxsi
+/* 24693 */ MCD_OPC_FilterValue, 32, 11, 0, // Skip to: 24708
+/* 24697 */ MCD_OPC_CheckField, 10, 6, 0, 86, 3, // Skip to: 25557
+/* 24703 */ MCD_OPC_Decode, 225, 3, 207, 1, // Opcode: FCVTNSxs
+/* 24708 */ MCD_OPC_FilterValue, 33, 11, 0, // Skip to: 24723
+/* 24712 */ MCD_OPC_CheckField, 10, 6, 0, 71, 3, // Skip to: 25557
+/* 24718 */ MCD_OPC_Decode, 229, 3, 207, 1, // Opcode: FCVTNUxs
+/* 24723 */ MCD_OPC_FilterValue, 34, 11, 0, // Skip to: 24738
+/* 24727 */ MCD_OPC_CheckField, 10, 6, 0, 56, 3, // Skip to: 25557
+/* 24733 */ MCD_OPC_Decode, 152, 8, 208, 1, // Opcode: SCVTFsx
+/* 24738 */ MCD_OPC_FilterValue, 35, 11, 0, // Skip to: 24753
+/* 24742 */ MCD_OPC_CheckField, 10, 6, 0, 41, 3, // Skip to: 25557
+/* 24748 */ MCD_OPC_Decode, 182, 11, 208, 1, // Opcode: UCVTFsx
+/* 24753 */ MCD_OPC_FilterValue, 36, 11, 0, // Skip to: 24768
+/* 24757 */ MCD_OPC_CheckField, 10, 6, 0, 26, 3, // Skip to: 25557
+/* 24763 */ MCD_OPC_Decode, 209, 3, 207, 1, // Opcode: FCVTASxs
+/* 24768 */ MCD_OPC_FilterValue, 37, 11, 0, // Skip to: 24783
+/* 24772 */ MCD_OPC_CheckField, 10, 6, 0, 11, 3, // Skip to: 25557
+/* 24778 */ MCD_OPC_Decode, 213, 3, 207, 1, // Opcode: FCVTAUxs
+/* 24783 */ MCD_OPC_FilterValue, 40, 11, 0, // Skip to: 24798
+/* 24787 */ MCD_OPC_CheckField, 10, 6, 0, 252, 2, // Skip to: 25557
+/* 24793 */ MCD_OPC_Decode, 233, 3, 207, 1, // Opcode: FCVTPSxs
+/* 24798 */ MCD_OPC_FilterValue, 41, 11, 0, // Skip to: 24813
+/* 24802 */ MCD_OPC_CheckField, 10, 6, 0, 237, 2, // Skip to: 25557
+/* 24808 */ MCD_OPC_Decode, 237, 3, 207, 1, // Opcode: FCVTPUxs
+/* 24813 */ MCD_OPC_FilterValue, 48, 11, 0, // Skip to: 24828
+/* 24817 */ MCD_OPC_CheckField, 10, 6, 0, 222, 2, // Skip to: 25557
+/* 24823 */ MCD_OPC_Decode, 217, 3, 207, 1, // Opcode: FCVTMSxs
+/* 24828 */ MCD_OPC_FilterValue, 49, 11, 0, // Skip to: 24843
+/* 24832 */ MCD_OPC_CheckField, 10, 6, 0, 207, 2, // Skip to: 25557
+/* 24838 */ MCD_OPC_Decode, 221, 3, 207, 1, // Opcode: FCVTMUxs
+/* 24843 */ MCD_OPC_FilterValue, 56, 11, 0, // Skip to: 24858
+/* 24847 */ MCD_OPC_CheckField, 10, 6, 0, 192, 2, // Skip to: 25557
+/* 24853 */ MCD_OPC_Decode, 244, 3, 207, 1, // Opcode: FCVTZSxs
+/* 24858 */ MCD_OPC_FilterValue, 57, 11, 0, // Skip to: 24873
+/* 24862 */ MCD_OPC_CheckField, 10, 6, 0, 177, 2, // Skip to: 25557
+/* 24868 */ MCD_OPC_Decode, 252, 3, 207, 1, // Opcode: FCVTZUxs
+/* 24873 */ MCD_OPC_FilterValue, 66, 5, 0, // Skip to: 24882
+/* 24877 */ MCD_OPC_Decode, 149, 8, 209, 1, // Opcode: SCVTFdxi
+/* 24882 */ MCD_OPC_FilterValue, 67, 5, 0, // Skip to: 24891
+/* 24886 */ MCD_OPC_Decode, 179, 11, 209, 1, // Opcode: UCVTFdxi
+/* 24891 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 24900
+/* 24895 */ MCD_OPC_Decode, 243, 3, 210, 1, // Opcode: FCVTZSxdi
+/* 24900 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 24909
+/* 24904 */ MCD_OPC_Decode, 251, 3, 210, 1, // Opcode: FCVTZUxdi
+/* 24909 */ MCD_OPC_FilterValue, 96, 11, 0, // Skip to: 24924
+/* 24913 */ MCD_OPC_CheckField, 10, 6, 0, 126, 2, // Skip to: 25557
+/* 24919 */ MCD_OPC_Decode, 224, 3, 211, 1, // Opcode: FCVTNSxd
+/* 24924 */ MCD_OPC_FilterValue, 97, 11, 0, // Skip to: 24939
+/* 24928 */ MCD_OPC_CheckField, 10, 6, 0, 111, 2, // Skip to: 25557
+/* 24934 */ MCD_OPC_Decode, 228, 3, 211, 1, // Opcode: FCVTNUxd
+/* 24939 */ MCD_OPC_FilterValue, 98, 11, 0, // Skip to: 24954
+/* 24943 */ MCD_OPC_CheckField, 10, 6, 0, 96, 2, // Skip to: 25557
+/* 24949 */ MCD_OPC_Decode, 148, 8, 212, 1, // Opcode: SCVTFdx
+/* 24954 */ MCD_OPC_FilterValue, 99, 11, 0, // Skip to: 24969
+/* 24958 */ MCD_OPC_CheckField, 10, 6, 0, 81, 2, // Skip to: 25557
+/* 24964 */ MCD_OPC_Decode, 178, 11, 212, 1, // Opcode: UCVTFdx
+/* 24969 */ MCD_OPC_FilterValue, 100, 11, 0, // Skip to: 24984
+/* 24973 */ MCD_OPC_CheckField, 10, 6, 0, 66, 2, // Skip to: 25557
+/* 24979 */ MCD_OPC_Decode, 208, 3, 211, 1, // Opcode: FCVTASxd
+/* 24984 */ MCD_OPC_FilterValue, 101, 11, 0, // Skip to: 24999
+/* 24988 */ MCD_OPC_CheckField, 10, 6, 0, 51, 2, // Skip to: 25557
+/* 24994 */ MCD_OPC_Decode, 212, 3, 211, 1, // Opcode: FCVTAUxd
+/* 24999 */ MCD_OPC_FilterValue, 102, 11, 0, // Skip to: 25014
+/* 25003 */ MCD_OPC_CheckField, 10, 6, 0, 36, 2, // Skip to: 25557
+/* 25009 */ MCD_OPC_Decode, 196, 4, 211, 1, // Opcode: FMOVxd
+/* 25014 */ MCD_OPC_FilterValue, 103, 11, 0, // Skip to: 25029
+/* 25018 */ MCD_OPC_CheckField, 10, 6, 0, 21, 2, // Skip to: 25557
+/* 25024 */ MCD_OPC_Decode, 187, 4, 212, 1, // Opcode: FMOVdx
+/* 25029 */ MCD_OPC_FilterValue, 104, 11, 0, // Skip to: 25044
+/* 25033 */ MCD_OPC_CheckField, 10, 6, 0, 6, 2, // Skip to: 25557
+/* 25039 */ MCD_OPC_Decode, 232, 3, 211, 1, // Opcode: FCVTPSxd
+/* 25044 */ MCD_OPC_FilterValue, 105, 11, 0, // Skip to: 25059
+/* 25048 */ MCD_OPC_CheckField, 10, 6, 0, 247, 1, // Skip to: 25557
+/* 25054 */ MCD_OPC_Decode, 236, 3, 211, 1, // Opcode: FCVTPUxd
+/* 25059 */ MCD_OPC_FilterValue, 112, 11, 0, // Skip to: 25074
+/* 25063 */ MCD_OPC_CheckField, 10, 6, 0, 232, 1, // Skip to: 25557
+/* 25069 */ MCD_OPC_Decode, 216, 3, 211, 1, // Opcode: FCVTMSxd
+/* 25074 */ MCD_OPC_FilterValue, 113, 11, 0, // Skip to: 25089
+/* 25078 */ MCD_OPC_CheckField, 10, 6, 0, 217, 1, // Skip to: 25557
+/* 25084 */ MCD_OPC_Decode, 220, 3, 211, 1, // Opcode: FCVTMUxd
+/* 25089 */ MCD_OPC_FilterValue, 120, 11, 0, // Skip to: 25104
+/* 25093 */ MCD_OPC_CheckField, 10, 6, 0, 202, 1, // Skip to: 25557
+/* 25099 */ MCD_OPC_Decode, 242, 3, 211, 1, // Opcode: FCVTZSxd
+/* 25104 */ MCD_OPC_FilterValue, 121, 11, 0, // Skip to: 25119
+/* 25108 */ MCD_OPC_CheckField, 10, 6, 0, 187, 1, // Skip to: 25557
+/* 25114 */ MCD_OPC_Decode, 250, 3, 211, 1, // Opcode: FCVTZUxd
+/* 25119 */ MCD_OPC_FilterValue, 174, 1, 11, 0, // Skip to: 25135
+/* 25124 */ MCD_OPC_CheckField, 10, 6, 0, 171, 1, // Skip to: 25557
+/* 25130 */ MCD_OPC_Decode, 197, 4, 213, 1, // Opcode: FMOVxv
+/* 25135 */ MCD_OPC_FilterValue, 175, 1, 161, 1, // Skip to: 25557
+/* 25140 */ MCD_OPC_CheckField, 10, 6, 0, 155, 1, // Skip to: 25557
+/* 25146 */ MCD_OPC_Decode, 194, 4, 213, 1, // Opcode: FMOVvx
+/* 25151 */ MCD_OPC_FilterValue, 5, 199, 0, // Skip to: 25354
+/* 25155 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 25158 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 25247
+/* 25162 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 25165 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25180
+/* 25169 */ MCD_OPC_CheckField, 21, 1, 0, 126, 1, // Skip to: 25557
+/* 25175 */ MCD_OPC_Decode, 148, 6, 214, 1, // Opcode: LSFP32_STUR
+/* 25180 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 25195
+/* 25184 */ MCD_OPC_CheckField, 21, 1, 0, 111, 1, // Skip to: 25557
+/* 25190 */ MCD_OPC_Decode, 144, 6, 137, 1, // Opcode: LSFP32_PostInd_STR
+/* 25195 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 25232
+/* 25199 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 25202 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25217
+/* 25206 */ MCD_OPC_CheckField, 21, 1, 1, 89, 1, // Skip to: 25557
+/* 25212 */ MCD_OPC_Decode, 150, 6, 215, 1, // Opcode: LSFP32_Wm_RegOffset_STR
+/* 25217 */ MCD_OPC_FilterValue, 1, 80, 1, // Skip to: 25557
+/* 25221 */ MCD_OPC_CheckField, 21, 1, 1, 74, 1, // Skip to: 25557
+/* 25227 */ MCD_OPC_Decode, 152, 6, 216, 1, // Opcode: LSFP32_Xm_RegOffset_STR
+/* 25232 */ MCD_OPC_FilterValue, 3, 65, 1, // Skip to: 25557
+/* 25236 */ MCD_OPC_CheckField, 21, 1, 0, 59, 1, // Skip to: 25557
+/* 25242 */ MCD_OPC_Decode, 146, 6, 137, 1, // Opcode: LSFP32_PreInd_STR
+/* 25247 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 25336
+/* 25251 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 25254 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25269
+/* 25258 */ MCD_OPC_CheckField, 21, 1, 0, 37, 1, // Skip to: 25557
+/* 25264 */ MCD_OPC_Decode, 142, 6, 214, 1, // Opcode: LSFP32_LDUR
+/* 25269 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 25284
+/* 25273 */ MCD_OPC_CheckField, 21, 1, 0, 22, 1, // Skip to: 25557
+/* 25279 */ MCD_OPC_Decode, 143, 6, 137, 1, // Opcode: LSFP32_PostInd_LDR
+/* 25284 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 25321
+/* 25288 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 25291 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25306
+/* 25295 */ MCD_OPC_CheckField, 21, 1, 1, 0, 1, // Skip to: 25557
+/* 25301 */ MCD_OPC_Decode, 149, 6, 215, 1, // Opcode: LSFP32_Wm_RegOffset_LDR
+/* 25306 */ MCD_OPC_FilterValue, 1, 247, 0, // Skip to: 25557
+/* 25310 */ MCD_OPC_CheckField, 21, 1, 1, 241, 0, // Skip to: 25557
+/* 25316 */ MCD_OPC_Decode, 151, 6, 216, 1, // Opcode: LSFP32_Xm_RegOffset_LDR
+/* 25321 */ MCD_OPC_FilterValue, 3, 232, 0, // Skip to: 25557
+/* 25325 */ MCD_OPC_CheckField, 21, 1, 0, 226, 0, // Skip to: 25557
+/* 25331 */ MCD_OPC_Decode, 145, 6, 137, 1, // Opcode: LSFP32_PreInd_LDR
+/* 25336 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 25345
+/* 25340 */ MCD_OPC_Decode, 147, 6, 217, 1, // Opcode: LSFP32_STR
+/* 25345 */ MCD_OPC_FilterValue, 5, 208, 0, // Skip to: 25557
+/* 25349 */ MCD_OPC_Decode, 141, 6, 217, 1, // Opcode: LSFP32_LDR
+/* 25354 */ MCD_OPC_FilterValue, 7, 199, 0, // Skip to: 25557
+/* 25358 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 25361 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 25450
+/* 25365 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 25368 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25383
+/* 25372 */ MCD_OPC_CheckField, 21, 1, 0, 179, 0, // Skip to: 25557
+/* 25378 */ MCD_OPC_Decode, 160, 6, 218, 1, // Opcode: LSFP64_STUR
+/* 25383 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 25398
+/* 25387 */ MCD_OPC_CheckField, 21, 1, 0, 164, 0, // Skip to: 25557
+/* 25393 */ MCD_OPC_Decode, 156, 6, 137, 1, // Opcode: LSFP64_PostInd_STR
+/* 25398 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 25435
+/* 25402 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 25405 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25420
+/* 25409 */ MCD_OPC_CheckField, 21, 1, 1, 142, 0, // Skip to: 25557
+/* 25415 */ MCD_OPC_Decode, 162, 6, 219, 1, // Opcode: LSFP64_Wm_RegOffset_STR
+/* 25420 */ MCD_OPC_FilterValue, 1, 133, 0, // Skip to: 25557
+/* 25424 */ MCD_OPC_CheckField, 21, 1, 1, 127, 0, // Skip to: 25557
+/* 25430 */ MCD_OPC_Decode, 164, 6, 220, 1, // Opcode: LSFP64_Xm_RegOffset_STR
+/* 25435 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 25557
+/* 25439 */ MCD_OPC_CheckField, 21, 1, 0, 112, 0, // Skip to: 25557
+/* 25445 */ MCD_OPC_Decode, 158, 6, 137, 1, // Opcode: LSFP64_PreInd_STR
+/* 25450 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 25539
+/* 25454 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 25457 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25472
+/* 25461 */ MCD_OPC_CheckField, 21, 1, 0, 90, 0, // Skip to: 25557
+/* 25467 */ MCD_OPC_Decode, 154, 6, 218, 1, // Opcode: LSFP64_LDUR
+/* 25472 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 25487
+/* 25476 */ MCD_OPC_CheckField, 21, 1, 0, 75, 0, // Skip to: 25557
+/* 25482 */ MCD_OPC_Decode, 155, 6, 137, 1, // Opcode: LSFP64_PostInd_LDR
+/* 25487 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 25524
+/* 25491 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 25494 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 25509
+/* 25498 */ MCD_OPC_CheckField, 21, 1, 1, 53, 0, // Skip to: 25557
+/* 25504 */ MCD_OPC_Decode, 161, 6, 219, 1, // Opcode: LSFP64_Wm_RegOffset_LDR
+/* 25509 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 25557
+/* 25513 */ MCD_OPC_CheckField, 21, 1, 1, 38, 0, // Skip to: 25557
+/* 25519 */ MCD_OPC_Decode, 163, 6, 220, 1, // Opcode: LSFP64_Xm_RegOffset_LDR
+/* 25524 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 25557
+/* 25528 */ MCD_OPC_CheckField, 21, 1, 0, 23, 0, // Skip to: 25557
+/* 25534 */ MCD_OPC_Decode, 157, 6, 137, 1, // Opcode: LSFP64_PreInd_LDR
+/* 25539 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 25548
+/* 25543 */ MCD_OPC_Decode, 159, 6, 221, 1, // Opcode: LSFP64_STR
+/* 25548 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 25557
+/* 25552 */ MCD_OPC_Decode, 153, 6, 221, 1, // Opcode: LSFP64_LDR
+/* 25557 */ MCD_OPC_Fail,
+ 0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
+{
+ switch (Idx) {
+ default: return false; // never reach
+ case 0:
+ return ((Bits & AArch64_FeatureNEON));
+ }
+}
+
+static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, uint32_t insn, MCInst *MI,
+ uint64_t Address, void *Decoder)
+{
+ uint32_t tmp;
+ switch (Idx) {
+ default: return S; // never reach
+ case 0:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 1:
+ if (!Check(&S, DecodeLDSTPairInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 2:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 3:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 4:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 5:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 6:
+ if (!Check(&S, DecodeLoadPairExclusiveInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 7:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 8:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, Decode32BitShiftOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 9:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, Decode32BitShiftOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 10:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, Decode32BitShiftOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 11:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 12:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 13:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 14:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 15:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 16:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 17:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 18:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 19:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 20:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 21:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 22:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 3);
+ if (!Check(&S, DecodeRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 23:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 24:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 25:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 26:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 18, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 27:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 17, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 28:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 19, 2);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 29:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 30:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 31:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 32:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 33:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 34:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 20, 1);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 35:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 19, 2);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 36:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 18, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 37:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 17, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 38:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 19, 2);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 39:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 18, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 40:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 17, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 41:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 20, 1);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 42:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 43:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 44:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 20, 1);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 14, 1);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 45:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 19, 2);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 2);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 46:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 18, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 47:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 17, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 48:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 2);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 49:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ if (!Check(&S, DecodeShiftRightImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 50:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ if (!Check(&S, DecodeShiftRightImm16(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 51:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeShiftRightImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 52:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 2);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 53:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ if (!Check(&S, DecodeShiftRightImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 54:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 55:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ if (!Check(&S, DecodeShiftRightImm16(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 56:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 57:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeShiftRightImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 58:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 59:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, true))) return MCDisassembler_Fail;
+ return S;
+ case 60:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ if (!Check(&S, DecodeShiftRightImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 61:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 62:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ if (!Check(&S, DecodeShiftRightImm16(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 63:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 64:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeShiftRightImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 65:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 66:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, true))) return MCDisassembler_Fail;
+ return S;
+ case 67:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_MSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 68:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 69:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 70:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 71:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 72:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 2);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 73:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ if (!Check(&S, DecodeShiftRightImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 74:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ if (!Check(&S, DecodeShiftRightImm16(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 75:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeShiftRightImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 76:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 2);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 77:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ if (!Check(&S, DecodeShiftRightImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 78:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 79:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ if (!Check(&S, DecodeShiftRightImm16(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 80:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 81:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeShiftRightImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 82:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 83:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, true))) return MCDisassembler_Fail;
+ return S;
+ case 84:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 13, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_LSL, true))) return MCDisassembler_Fail;
+ return S;
+ case 85:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 1);
+ if (!Check(&S, DecodeNeonMovImmShiftOperand(MI, tmp, Address, Decoder, A64SE_MSL, false))) return MCDisassembler_Fail;
+ return S;
+ case 86:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 87:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 88:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 89:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 90:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ if (!Check(&S, DecodeShiftRightImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 91:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ if (!Check(&S, DecodeShiftRightImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 92:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 93:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 94:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 19) << 2);
+ tmp |= (fieldFromInstruction(insn, 29, 2) << 0);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 95:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 96:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 97:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 98:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 99:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 100:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 101:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32wspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 13);
+ if (!Check(&S, DecodeLogicalImmOperand(MI, tmp, Address, Decoder, 32))) return MCDisassembler_Fail;
+ return S;
+ case 102:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 18);
+ if (!Check(&S, DecodeMoveWideImmOperand(MI, tmp, Address, Decoder, 32))) return MCDisassembler_Fail;
+ return S;
+ case 103:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 13);
+ if (!Check(&S, DecodeLogicalImmOperand(MI, tmp, Address, Decoder, 32))) return MCDisassembler_Fail;
+ return S;
+ case 104:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 18);
+ if (!Check(&S, DecodeMoveWideImmOperand(MI, tmp, Address, Decoder, 32))) return MCDisassembler_Fail;
+ return S;
+ case 105:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 13);
+ if (!Check(&S, DecodeLogicalImmOperand(MI, tmp, Address, Decoder, 64))) return MCDisassembler_Fail;
+ return S;
+ case 106:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 18);
+ if (!Check(&S, DecodeMoveWideImmOperand(MI, tmp, Address, Decoder, 64))) return MCDisassembler_Fail;
+ return S;
+ case 107:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 13);
+ if (!Check(&S, DecodeLogicalImmOperand(MI, tmp, Address, Decoder, 64))) return MCDisassembler_Fail;
+ return S;
+ case 108:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 18);
+ if (!Check(&S, DecodeMoveWideImmOperand(MI, tmp, Address, Decoder, 64))) return MCDisassembler_Fail;
+ return S;
+ case 109:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 110:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ if (!Check(&S, DecodeBitfield32ImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 111:
+ if (!Check(&S, DecodeBitfieldInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 112:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, DecodeBitfield32ImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 113:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 114:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 115:
+ tmp = fieldFromInstruction(insn, 0, 26);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 116:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 117:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 118:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 19, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 14);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 119:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 19, 5) << 0);
+ tmp |= (fieldFromInstruction(insn, 31, 1) << 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 14);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 120:
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 121:
+ tmp = fieldFromInstruction(insn, 5, 16);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 122:
+ tmp = fieldFromInstruction(insn, 8, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 123:
+ tmp = fieldFromInstruction(insn, 8, 4);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_DBarrierMapper))) return MCDisassembler_Fail;
+ return S;
+ case 124:
+ tmp = fieldFromInstruction(insn, 8, 4);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_ISBMapper))) return MCDisassembler_Fail;
+ return S;
+ case 125:
+ tmp = fieldFromInstruction(insn, 5, 7);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 126:
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 5, 3) << 0);
+ tmp |= (fieldFromInstruction(insn, 16, 3) << 3);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PStateMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 8, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 127:
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 8, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 128:
+ tmp = fieldFromInstruction(insn, 5, 16);
+ if (!Check(&S, DecodeMSROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 129:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 8, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 5, 3);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 130:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 16);
+ if (!Check(&S, DecodeMRSOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 131:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 132:
+ return S;
+ case 133:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 134:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 135:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 136:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 137:
+ if (!Check(&S, DecodeSingleIndexedInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 138:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 139:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 140:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 141:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 142:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 143:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 144:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 145:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 146:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 147:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 148:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 149:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 150:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 151:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 152:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 153:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PRFMMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 154:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 155:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PRFMMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 156:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PRFMMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 157:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PRFMMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 158:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeNamedImmOperand(MI, tmp, Address, Decoder, &AArch64_PRFMMapper))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 159:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 160:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, DecodeCVT32FixedPosOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 161:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, DecodeCVT32FixedPosOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 162:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 163:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 164:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 165:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPZeroOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 166:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 167:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 168:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 169:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 13, 8);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 170:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 171:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 172:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 173:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, DecodeCVT32FixedPosOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 174:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ if (!Check(&S, DecodeCVT32FixedPosOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 175:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 176:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 177:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 178:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPZeroOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 179:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 180:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 181:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 13, 8);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 182:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 183:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 184:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 185:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 186:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 187:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 188:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 189:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 190:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 191:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 192:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 193:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 194:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 195:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 196:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 197:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 198:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 199:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 200:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 201:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 202:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 203:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 204:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 19);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 205:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 206:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 207:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 208:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 209:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 210:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 6);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 211:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 212:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 213:
+ if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 214:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 215:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 216:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 217:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 218:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 12, 9);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ case 219:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 220:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = 0;
+ tmp |= (fieldFromInstruction(insn, 12, 1) << 0);
+ tmp |= (fieldFromInstruction(insn, 14, 2) << 1);
+ if (!Check(&S, DecodeAddrRegExtendOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ return S;
+ case 221:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (!Check(&S, DecodeGPR64xspRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail;
+ tmp = fieldFromInstruction(insn, 10, 12);
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp));
+ return S;
+ }
+}
+
+static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst *MI,
+ uint32_t insn, uint64_t Address,
+ MCRegisterInfo *MRI)
+{
+ //uint64_t Bits = 0;
+ uint64_t Bits = AArch64_getFeatureBits();
+
+ const uint8_t *Ptr = DecodeTable;
+ uint32_t CurFieldValue = 0;
+ DecodeStatus S = MCDisassembler_Success;
+ for (;;) {
+ //ptrdiff_t Loc = Ptr - DecodeTable;
+ // printf(">> Loc: %lu\n", Ptr - DecodeTable);
+ switch (*Ptr) {
+ default:
+ //errs() << Loc << ": Unexpected decode table opcode!\n";
+ return MCDisassembler_Fail;
+ case MCD_OPC_ExtractField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ ++Ptr;
+ CurFieldValue = fieldFromInstruction(insn, Start, Len);
+ //DEBUG(dbgs() << Loc << ": OPC_ExtractField(" << Start << ", "
+ // << Len << "): " << CurFieldValue << "\n");
+ break;
+ }
+ case MCD_OPC_FilterValue: {
+ // Decode the field value.
+ unsigned Len;
+ uint32_t Val = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 16-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+
+ // Perform the filter operation.
+ if (Val != CurFieldValue)
+ Ptr += NumToSkip;
+ //DEBUG(dbgs() << Loc << ": OPC_FilterValue(" << Val << ", " << NumToSkip
+ // << "): " << ((Val != CurFieldValue) ? "FAIL:" : "PASS:")
+ // << " continuing at " << (Ptr - DecodeTable) << "\n");
+
+ break;
+ }
+ case MCD_OPC_CheckField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ uint32_t FieldValue = fieldFromInstruction(insn, Start, Len);
+ // Decode the field value.
+ uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 16-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+
+ // If the actual and expected values don't match, skip.
+ if (ExpectedValue != FieldValue)
+ Ptr += NumToSkip;
+ //DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", "
+ // << Len << ", " << ExpectedValue << ", " << NumToSkip
+ // << "): FieldValue = " << FieldValue << ", ExpectedValue = "
+ // << ExpectedValue << ": "
+ // << ((ExpectedValue == FieldValue) ? "PASS\n" : "FAIL\n"));
+ break;
+ }
+ case MCD_OPC_CheckPredicate: {
+ unsigned Len;
+ // Decode the Predicate Index value.
+ unsigned PIdx = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 16-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ // Check the predicate.
+ bool Pred;
+ if (!(Pred = checkDecoderPredicate(PIdx, Bits)))
+ Ptr += NumToSkip;
+ (void)Pred;
+ //DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
+ // << (Pred ? "PASS\n" : "FAIL\n"));
+
+ break;
+ }
+ case MCD_OPC_Decode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ //DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
+ // << ", using decoder " << DecodeIdx << "\n" );
+ //DEBUG(dbgs() << "----- DECODE SUCCESSFUL -----\n");
+
+ MCInst_setOpcode(MI, Opc);
+ return decodeToMCInst(S, DecodeIdx, insn, MI, Address, MRI);
+ }
+ case MCD_OPC_SoftFail: {
+ // Decode the mask values.
+ unsigned Len;
+ uint32_t PositiveMask = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ uint32_t NegativeMask = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);
+ if (Fail)
+ S = MCDisassembler_SoftFail;
+ //DEBUG(dbgs() << Loc << ": OPC_SoftFail: " << (Fail ? "FAIL\n":"PASS\n"));
+ break;
+ }
+ case MCD_OPC_Fail: {
+ //DEBUG(dbgs() << Loc << ": OPC_Fail\n");
+ return MCDisassembler_Fail;
+ }
+ }
+ }
+}
+
diff --git a/arch/AArch64/AArch64GenInstrInfo.inc b/arch/AArch64/AArch64GenInstrInfo.inc
new file mode 100644
index 0000000..6141e1b
--- /dev/null
+++ b/arch/AArch64/AArch64GenInstrInfo.inc
@@ -0,0 +1,1692 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Instruction Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+enum {
+ AArch64_PHI = 0,
+ AArch64_INLINEASM = 1,
+ AArch64_PROLOG_LABEL = 2,
+ AArch64_EH_LABEL = 3,
+ AArch64_GC_LABEL = 4,
+ AArch64_KILL = 5,
+ AArch64_EXTRACT_SUBREG = 6,
+ AArch64_INSERT_SUBREG = 7,
+ AArch64_IMPLICIT_DEF = 8,
+ AArch64_SUBREG_TO_REG = 9,
+ AArch64_COPY_TO_REGCLASS = 10,
+ AArch64_DBG_VALUE = 11,
+ AArch64_REG_SEQUENCE = 12,
+ AArch64_COPY = 13,
+ AArch64_BUNDLE = 14,
+ AArch64_LIFETIME_START = 15,
+ AArch64_LIFETIME_END = 16,
+ AArch64_ADCSwww = 17,
+ AArch64_ADCSxxx = 18,
+ AArch64_ADCwww = 19,
+ AArch64_ADCxxx = 20,
+ AArch64_ADDHN2vvv_16b8h = 21,
+ AArch64_ADDHN2vvv_4s2d = 22,
+ AArch64_ADDHN2vvv_8h4s = 23,
+ AArch64_ADDHNvvv_2s2d = 24,
+ AArch64_ADDHNvvv_4h4s = 25,
+ AArch64_ADDHNvvv_8b8h = 26,
+ AArch64_ADDP_16B = 27,
+ AArch64_ADDP_2D = 28,
+ AArch64_ADDP_2S = 29,
+ AArch64_ADDP_4H = 30,
+ AArch64_ADDP_4S = 31,
+ AArch64_ADDP_8B = 32,
+ AArch64_ADDP_8H = 33,
+ AArch64_ADDPvv_D_2D = 34,
+ AArch64_ADDSwww_asr = 35,
+ AArch64_ADDSwww_lsl = 36,
+ AArch64_ADDSwww_lsr = 37,
+ AArch64_ADDSwww_sxtb = 38,
+ AArch64_ADDSwww_sxth = 39,
+ AArch64_ADDSwww_sxtw = 40,
+ AArch64_ADDSwww_sxtx = 41,
+ AArch64_ADDSwww_uxtb = 42,
+ AArch64_ADDSwww_uxth = 43,
+ AArch64_ADDSwww_uxtw = 44,
+ AArch64_ADDSwww_uxtx = 45,
+ AArch64_ADDSxxw_sxtb = 46,
+ AArch64_ADDSxxw_sxth = 47,
+ AArch64_ADDSxxw_sxtw = 48,
+ AArch64_ADDSxxw_uxtb = 49,
+ AArch64_ADDSxxw_uxth = 50,
+ AArch64_ADDSxxw_uxtw = 51,
+ AArch64_ADDSxxx_asr = 52,
+ AArch64_ADDSxxx_lsl = 53,
+ AArch64_ADDSxxx_lsr = 54,
+ AArch64_ADDSxxx_sxtx = 55,
+ AArch64_ADDSxxx_uxtx = 56,
+ AArch64_ADDddd = 57,
+ AArch64_ADDvvv_16B = 58,
+ AArch64_ADDvvv_2D = 59,
+ AArch64_ADDvvv_2S = 60,
+ AArch64_ADDvvv_4H = 61,
+ AArch64_ADDvvv_4S = 62,
+ AArch64_ADDvvv_8B = 63,
+ AArch64_ADDvvv_8H = 64,
+ AArch64_ADDwwi_lsl0_S = 65,
+ AArch64_ADDwwi_lsl0_cmp = 66,
+ AArch64_ADDwwi_lsl0_s = 67,
+ AArch64_ADDwwi_lsl12_S = 68,
+ AArch64_ADDwwi_lsl12_cmp = 69,
+ AArch64_ADDwwi_lsl12_s = 70,
+ AArch64_ADDwww_asr = 71,
+ AArch64_ADDwww_lsl = 72,
+ AArch64_ADDwww_lsr = 73,
+ AArch64_ADDwww_sxtb = 74,
+ AArch64_ADDwww_sxth = 75,
+ AArch64_ADDwww_sxtw = 76,
+ AArch64_ADDwww_sxtx = 77,
+ AArch64_ADDwww_uxtb = 78,
+ AArch64_ADDwww_uxth = 79,
+ AArch64_ADDwww_uxtw = 80,
+ AArch64_ADDwww_uxtx = 81,
+ AArch64_ADDxxi_lsl0_S = 82,
+ AArch64_ADDxxi_lsl0_cmp = 83,
+ AArch64_ADDxxi_lsl0_s = 84,
+ AArch64_ADDxxi_lsl12_S = 85,
+ AArch64_ADDxxi_lsl12_cmp = 86,
+ AArch64_ADDxxi_lsl12_s = 87,
+ AArch64_ADDxxw_sxtb = 88,
+ AArch64_ADDxxw_sxth = 89,
+ AArch64_ADDxxw_sxtw = 90,
+ AArch64_ADDxxw_uxtb = 91,
+ AArch64_ADDxxw_uxth = 92,
+ AArch64_ADDxxw_uxtw = 93,
+ AArch64_ADDxxx_asr = 94,
+ AArch64_ADDxxx_lsl = 95,
+ AArch64_ADDxxx_lsr = 96,
+ AArch64_ADDxxx_sxtx = 97,
+ AArch64_ADDxxx_uxtx = 98,
+ AArch64_ADJCALLSTACKDOWN = 99,
+ AArch64_ADJCALLSTACKUP = 100,
+ AArch64_ADRPxi = 101,
+ AArch64_ADRxi = 102,
+ AArch64_ANDSwwi = 103,
+ AArch64_ANDSwww_asr = 104,
+ AArch64_ANDSwww_lsl = 105,
+ AArch64_ANDSwww_lsr = 106,
+ AArch64_ANDSwww_ror = 107,
+ AArch64_ANDSxxi = 108,
+ AArch64_ANDSxxx_asr = 109,
+ AArch64_ANDSxxx_lsl = 110,
+ AArch64_ANDSxxx_lsr = 111,
+ AArch64_ANDSxxx_ror = 112,
+ AArch64_ANDvvv_16B = 113,
+ AArch64_ANDvvv_8B = 114,
+ AArch64_ANDwwi = 115,
+ AArch64_ANDwww_asr = 116,
+ AArch64_ANDwww_lsl = 117,
+ AArch64_ANDwww_lsr = 118,
+ AArch64_ANDwww_ror = 119,
+ AArch64_ANDxxi = 120,
+ AArch64_ANDxxx_asr = 121,
+ AArch64_ANDxxx_lsl = 122,
+ AArch64_ANDxxx_lsr = 123,
+ AArch64_ANDxxx_ror = 124,
+ AArch64_ASRVwww = 125,
+ AArch64_ASRVxxx = 126,
+ AArch64_ASRwwi = 127,
+ AArch64_ASRxxi = 128,
+ AArch64_ATOMIC_CMP_SWAP_I16 = 129,
+ AArch64_ATOMIC_CMP_SWAP_I32 = 130,
+ AArch64_ATOMIC_CMP_SWAP_I64 = 131,
+ AArch64_ATOMIC_CMP_SWAP_I8 = 132,
+ AArch64_ATOMIC_LOAD_ADD_I16 = 133,
+ AArch64_ATOMIC_LOAD_ADD_I32 = 134,
+ AArch64_ATOMIC_LOAD_ADD_I64 = 135,
+ AArch64_ATOMIC_LOAD_ADD_I8 = 136,
+ AArch64_ATOMIC_LOAD_AND_I16 = 137,
+ AArch64_ATOMIC_LOAD_AND_I32 = 138,
+ AArch64_ATOMIC_LOAD_AND_I64 = 139,
+ AArch64_ATOMIC_LOAD_AND_I8 = 140,
+ AArch64_ATOMIC_LOAD_MAX_I16 = 141,
+ AArch64_ATOMIC_LOAD_MAX_I32 = 142,
+ AArch64_ATOMIC_LOAD_MAX_I64 = 143,
+ AArch64_ATOMIC_LOAD_MAX_I8 = 144,
+ AArch64_ATOMIC_LOAD_MIN_I16 = 145,
+ AArch64_ATOMIC_LOAD_MIN_I32 = 146,
+ AArch64_ATOMIC_LOAD_MIN_I64 = 147,
+ AArch64_ATOMIC_LOAD_MIN_I8 = 148,
+ AArch64_ATOMIC_LOAD_NAND_I16 = 149,
+ AArch64_ATOMIC_LOAD_NAND_I32 = 150,
+ AArch64_ATOMIC_LOAD_NAND_I64 = 151,
+ AArch64_ATOMIC_LOAD_NAND_I8 = 152,
+ AArch64_ATOMIC_LOAD_OR_I16 = 153,
+ AArch64_ATOMIC_LOAD_OR_I32 = 154,
+ AArch64_ATOMIC_LOAD_OR_I64 = 155,
+ AArch64_ATOMIC_LOAD_OR_I8 = 156,
+ AArch64_ATOMIC_LOAD_SUB_I16 = 157,
+ AArch64_ATOMIC_LOAD_SUB_I32 = 158,
+ AArch64_ATOMIC_LOAD_SUB_I64 = 159,
+ AArch64_ATOMIC_LOAD_SUB_I8 = 160,
+ AArch64_ATOMIC_LOAD_UMAX_I16 = 161,
+ AArch64_ATOMIC_LOAD_UMAX_I32 = 162,
+ AArch64_ATOMIC_LOAD_UMAX_I64 = 163,
+ AArch64_ATOMIC_LOAD_UMAX_I8 = 164,
+ AArch64_ATOMIC_LOAD_UMIN_I16 = 165,
+ AArch64_ATOMIC_LOAD_UMIN_I32 = 166,
+ AArch64_ATOMIC_LOAD_UMIN_I64 = 167,
+ AArch64_ATOMIC_LOAD_UMIN_I8 = 168,
+ AArch64_ATOMIC_LOAD_XOR_I16 = 169,
+ AArch64_ATOMIC_LOAD_XOR_I32 = 170,
+ AArch64_ATOMIC_LOAD_XOR_I64 = 171,
+ AArch64_ATOMIC_LOAD_XOR_I8 = 172,
+ AArch64_ATOMIC_SWAP_I16 = 173,
+ AArch64_ATOMIC_SWAP_I32 = 174,
+ AArch64_ATOMIC_SWAP_I64 = 175,
+ AArch64_ATOMIC_SWAP_I8 = 176,
+ AArch64_ATix = 177,
+ AArch64_BFIwwii = 178,
+ AArch64_BFIxxii = 179,
+ AArch64_BFMwwii = 180,
+ AArch64_BFMxxii = 181,
+ AArch64_BFXILwwii = 182,
+ AArch64_BFXILxxii = 183,
+ AArch64_BICSwww_asr = 184,
+ AArch64_BICSwww_lsl = 185,
+ AArch64_BICSwww_lsr = 186,
+ AArch64_BICSwww_ror = 187,
+ AArch64_BICSxxx_asr = 188,
+ AArch64_BICSxxx_lsl = 189,
+ AArch64_BICSxxx_lsr = 190,
+ AArch64_BICSxxx_ror = 191,
+ AArch64_BICvi_lsl_2S = 192,
+ AArch64_BICvi_lsl_4H = 193,
+ AArch64_BICvi_lsl_4S = 194,
+ AArch64_BICvi_lsl_8H = 195,
+ AArch64_BICvvv_16B = 196,
+ AArch64_BICvvv_8B = 197,
+ AArch64_BICwww_asr = 198,
+ AArch64_BICwww_lsl = 199,
+ AArch64_BICwww_lsr = 200,
+ AArch64_BICwww_ror = 201,
+ AArch64_BICxxx_asr = 202,
+ AArch64_BICxxx_lsl = 203,
+ AArch64_BICxxx_lsr = 204,
+ AArch64_BICxxx_ror = 205,
+ AArch64_BIFvvv_16B = 206,
+ AArch64_BIFvvv_8B = 207,
+ AArch64_BITvvv_16B = 208,
+ AArch64_BITvvv_8B = 209,
+ AArch64_BLRx = 210,
+ AArch64_BLimm = 211,
+ AArch64_BRKi = 212,
+ AArch64_BRx = 213,
+ AArch64_BSLvvv_16B = 214,
+ AArch64_BSLvvv_8B = 215,
+ AArch64_Bcc = 216,
+ AArch64_Bimm = 217,
+ AArch64_CBNZw = 218,
+ AArch64_CBNZx = 219,
+ AArch64_CBZw = 220,
+ AArch64_CBZx = 221,
+ AArch64_CCMNwi = 222,
+ AArch64_CCMNww = 223,
+ AArch64_CCMNxi = 224,
+ AArch64_CCMNxx = 225,
+ AArch64_CCMPwi = 226,
+ AArch64_CCMPww = 227,
+ AArch64_CCMPxi = 228,
+ AArch64_CCMPxx = 229,
+ AArch64_CLREXi = 230,
+ AArch64_CLSww = 231,
+ AArch64_CLSxx = 232,
+ AArch64_CLZww = 233,
+ AArch64_CLZxx = 234,
+ AArch64_CMEQvvi_16B = 235,
+ AArch64_CMEQvvi_2D = 236,
+ AArch64_CMEQvvi_2S = 237,
+ AArch64_CMEQvvi_4H = 238,
+ AArch64_CMEQvvi_4S = 239,
+ AArch64_CMEQvvi_8B = 240,
+ AArch64_CMEQvvi_8H = 241,
+ AArch64_CMEQvvv_16B = 242,
+ AArch64_CMEQvvv_2D = 243,
+ AArch64_CMEQvvv_2S = 244,
+ AArch64_CMEQvvv_4H = 245,
+ AArch64_CMEQvvv_4S = 246,
+ AArch64_CMEQvvv_8B = 247,
+ AArch64_CMEQvvv_8H = 248,
+ AArch64_CMGEvvi_16B = 249,
+ AArch64_CMGEvvi_2D = 250,
+ AArch64_CMGEvvi_2S = 251,
+ AArch64_CMGEvvi_4H = 252,
+ AArch64_CMGEvvi_4S = 253,
+ AArch64_CMGEvvi_8B = 254,
+ AArch64_CMGEvvi_8H = 255,
+ AArch64_CMGEvvv_16B = 256,
+ AArch64_CMGEvvv_2D = 257,
+ AArch64_CMGEvvv_2S = 258,
+ AArch64_CMGEvvv_4H = 259,
+ AArch64_CMGEvvv_4S = 260,
+ AArch64_CMGEvvv_8B = 261,
+ AArch64_CMGEvvv_8H = 262,
+ AArch64_CMGTvvi_16B = 263,
+ AArch64_CMGTvvi_2D = 264,
+ AArch64_CMGTvvi_2S = 265,
+ AArch64_CMGTvvi_4H = 266,
+ AArch64_CMGTvvi_4S = 267,
+ AArch64_CMGTvvi_8B = 268,
+ AArch64_CMGTvvi_8H = 269,
+ AArch64_CMGTvvv_16B = 270,
+ AArch64_CMGTvvv_2D = 271,
+ AArch64_CMGTvvv_2S = 272,
+ AArch64_CMGTvvv_4H = 273,
+ AArch64_CMGTvvv_4S = 274,
+ AArch64_CMGTvvv_8B = 275,
+ AArch64_CMGTvvv_8H = 276,
+ AArch64_CMHIvvv_16B = 277,
+ AArch64_CMHIvvv_2D = 278,
+ AArch64_CMHIvvv_2S = 279,
+ AArch64_CMHIvvv_4H = 280,
+ AArch64_CMHIvvv_4S = 281,
+ AArch64_CMHIvvv_8B = 282,
+ AArch64_CMHIvvv_8H = 283,
+ AArch64_CMHSvvv_16B = 284,
+ AArch64_CMHSvvv_2D = 285,
+ AArch64_CMHSvvv_2S = 286,
+ AArch64_CMHSvvv_4H = 287,
+ AArch64_CMHSvvv_4S = 288,
+ AArch64_CMHSvvv_8B = 289,
+ AArch64_CMHSvvv_8H = 290,
+ AArch64_CMLEvvi_16B = 291,
+ AArch64_CMLEvvi_2D = 292,
+ AArch64_CMLEvvi_2S = 293,
+ AArch64_CMLEvvi_4H = 294,
+ AArch64_CMLEvvi_4S = 295,
+ AArch64_CMLEvvi_8B = 296,
+ AArch64_CMLEvvi_8H = 297,
+ AArch64_CMLTvvi_16B = 298,
+ AArch64_CMLTvvi_2D = 299,
+ AArch64_CMLTvvi_2S = 300,
+ AArch64_CMLTvvi_4H = 301,
+ AArch64_CMLTvvi_4S = 302,
+ AArch64_CMLTvvi_8B = 303,
+ AArch64_CMLTvvi_8H = 304,
+ AArch64_CMNww_asr = 305,
+ AArch64_CMNww_lsl = 306,
+ AArch64_CMNww_lsr = 307,
+ AArch64_CMNww_sxtb = 308,
+ AArch64_CMNww_sxth = 309,
+ AArch64_CMNww_sxtw = 310,
+ AArch64_CMNww_sxtx = 311,
+ AArch64_CMNww_uxtb = 312,
+ AArch64_CMNww_uxth = 313,
+ AArch64_CMNww_uxtw = 314,
+ AArch64_CMNww_uxtx = 315,
+ AArch64_CMNxw_sxtb = 316,
+ AArch64_CMNxw_sxth = 317,
+ AArch64_CMNxw_sxtw = 318,
+ AArch64_CMNxw_uxtb = 319,
+ AArch64_CMNxw_uxth = 320,
+ AArch64_CMNxw_uxtw = 321,
+ AArch64_CMNxx_asr = 322,
+ AArch64_CMNxx_lsl = 323,
+ AArch64_CMNxx_lsr = 324,
+ AArch64_CMNxx_sxtx = 325,
+ AArch64_CMNxx_uxtx = 326,
+ AArch64_CMPww_asr = 327,
+ AArch64_CMPww_lsl = 328,
+ AArch64_CMPww_lsr = 329,
+ AArch64_CMPww_sxtb = 330,
+ AArch64_CMPww_sxth = 331,
+ AArch64_CMPww_sxtw = 332,
+ AArch64_CMPww_sxtx = 333,
+ AArch64_CMPww_uxtb = 334,
+ AArch64_CMPww_uxth = 335,
+ AArch64_CMPww_uxtw = 336,
+ AArch64_CMPww_uxtx = 337,
+ AArch64_CMPxw_sxtb = 338,
+ AArch64_CMPxw_sxth = 339,
+ AArch64_CMPxw_sxtw = 340,
+ AArch64_CMPxw_uxtb = 341,
+ AArch64_CMPxw_uxth = 342,
+ AArch64_CMPxw_uxtw = 343,
+ AArch64_CMPxx_asr = 344,
+ AArch64_CMPxx_lsl = 345,
+ AArch64_CMPxx_lsr = 346,
+ AArch64_CMPxx_sxtx = 347,
+ AArch64_CMPxx_uxtx = 348,
+ AArch64_CMTSTvvv_16B = 349,
+ AArch64_CMTSTvvv_2D = 350,
+ AArch64_CMTSTvvv_2S = 351,
+ AArch64_CMTSTvvv_4H = 352,
+ AArch64_CMTSTvvv_4S = 353,
+ AArch64_CMTSTvvv_8B = 354,
+ AArch64_CMTSTvvv_8H = 355,
+ AArch64_CRC32B_www = 356,
+ AArch64_CRC32CB_www = 357,
+ AArch64_CRC32CH_www = 358,
+ AArch64_CRC32CW_www = 359,
+ AArch64_CRC32CX_wwx = 360,
+ AArch64_CRC32H_www = 361,
+ AArch64_CRC32W_www = 362,
+ AArch64_CRC32X_wwx = 363,
+ AArch64_CSELwwwc = 364,
+ AArch64_CSELxxxc = 365,
+ AArch64_CSINCwwwc = 366,
+ AArch64_CSINCxxxc = 367,
+ AArch64_CSINVwwwc = 368,
+ AArch64_CSINVxxxc = 369,
+ AArch64_CSNEGwwwc = 370,
+ AArch64_CSNEGxxxc = 371,
+ AArch64_DCPS1i = 372,
+ AArch64_DCPS2i = 373,
+ AArch64_DCPS3i = 374,
+ AArch64_DCix = 375,
+ AArch64_DMBi = 376,
+ AArch64_DRPS = 377,
+ AArch64_DSBi = 378,
+ AArch64_EONwww_asr = 379,
+ AArch64_EONwww_lsl = 380,
+ AArch64_EONwww_lsr = 381,
+ AArch64_EONwww_ror = 382,
+ AArch64_EONxxx_asr = 383,
+ AArch64_EONxxx_lsl = 384,
+ AArch64_EONxxx_lsr = 385,
+ AArch64_EONxxx_ror = 386,
+ AArch64_EORvvv_16B = 387,
+ AArch64_EORvvv_8B = 388,
+ AArch64_EORwwi = 389,
+ AArch64_EORwww_asr = 390,
+ AArch64_EORwww_lsl = 391,
+ AArch64_EORwww_lsr = 392,
+ AArch64_EORwww_ror = 393,
+ AArch64_EORxxi = 394,
+ AArch64_EORxxx_asr = 395,
+ AArch64_EORxxx_lsl = 396,
+ AArch64_EORxxx_lsr = 397,
+ AArch64_EORxxx_ror = 398,
+ AArch64_ERET = 399,
+ AArch64_EXTRwwwi = 400,
+ AArch64_EXTRxxxi = 401,
+ AArch64_F128CSEL = 402,
+ AArch64_FABDvvv_2D = 403,
+ AArch64_FABDvvv_2S = 404,
+ AArch64_FABDvvv_4S = 405,
+ AArch64_FABSdd = 406,
+ AArch64_FABSss = 407,
+ AArch64_FACGEvvv_2D = 408,
+ AArch64_FACGEvvv_2S = 409,
+ AArch64_FACGEvvv_4S = 410,
+ AArch64_FACGTvvv_2D = 411,
+ AArch64_FACGTvvv_2S = 412,
+ AArch64_FACGTvvv_4S = 413,
+ AArch64_FADDP_2D = 414,
+ AArch64_FADDP_2S = 415,
+ AArch64_FADDP_4S = 416,
+ AArch64_FADDPvv_D_2D = 417,
+ AArch64_FADDPvv_S_2S = 418,
+ AArch64_FADDddd = 419,
+ AArch64_FADDsss = 420,
+ AArch64_FADDvvv_2D = 421,
+ AArch64_FADDvvv_2S = 422,
+ AArch64_FADDvvv_4S = 423,
+ AArch64_FCCMPEdd = 424,
+ AArch64_FCCMPEss = 425,
+ AArch64_FCCMPdd = 426,
+ AArch64_FCCMPss = 427,
+ AArch64_FCMEQvvi_2D = 428,
+ AArch64_FCMEQvvi_2S = 429,
+ AArch64_FCMEQvvi_4S = 430,
+ AArch64_FCMEQvvv_2D = 431,
+ AArch64_FCMEQvvv_2S = 432,
+ AArch64_FCMEQvvv_4S = 433,
+ AArch64_FCMGEvvi_2D = 434,
+ AArch64_FCMGEvvi_2S = 435,
+ AArch64_FCMGEvvi_4S = 436,
+ AArch64_FCMGEvvv_2D = 437,
+ AArch64_FCMGEvvv_2S = 438,
+ AArch64_FCMGEvvv_4S = 439,
+ AArch64_FCMGTvvi_2D = 440,
+ AArch64_FCMGTvvi_2S = 441,
+ AArch64_FCMGTvvi_4S = 442,
+ AArch64_FCMGTvvv_2D = 443,
+ AArch64_FCMGTvvv_2S = 444,
+ AArch64_FCMGTvvv_4S = 445,
+ AArch64_FCMLEvvi_2D = 446,
+ AArch64_FCMLEvvi_2S = 447,
+ AArch64_FCMLEvvi_4S = 448,
+ AArch64_FCMLTvvi_2D = 449,
+ AArch64_FCMLTvvi_2S = 450,
+ AArch64_FCMLTvvi_4S = 451,
+ AArch64_FCMPdd_quiet = 452,
+ AArch64_FCMPdd_sig = 453,
+ AArch64_FCMPdi_quiet = 454,
+ AArch64_FCMPdi_sig = 455,
+ AArch64_FCMPsi_quiet = 456,
+ AArch64_FCMPsi_sig = 457,
+ AArch64_FCMPss_quiet = 458,
+ AArch64_FCMPss_sig = 459,
+ AArch64_FCSELdddc = 460,
+ AArch64_FCSELsssc = 461,
+ AArch64_FCVTASwd = 462,
+ AArch64_FCVTASws = 463,
+ AArch64_FCVTASxd = 464,
+ AArch64_FCVTASxs = 465,
+ AArch64_FCVTAUwd = 466,
+ AArch64_FCVTAUws = 467,
+ AArch64_FCVTAUxd = 468,
+ AArch64_FCVTAUxs = 469,
+ AArch64_FCVTMSwd = 470,
+ AArch64_FCVTMSws = 471,
+ AArch64_FCVTMSxd = 472,
+ AArch64_FCVTMSxs = 473,
+ AArch64_FCVTMUwd = 474,
+ AArch64_FCVTMUws = 475,
+ AArch64_FCVTMUxd = 476,
+ AArch64_FCVTMUxs = 477,
+ AArch64_FCVTNSwd = 478,
+ AArch64_FCVTNSws = 479,
+ AArch64_FCVTNSxd = 480,
+ AArch64_FCVTNSxs = 481,
+ AArch64_FCVTNUwd = 482,
+ AArch64_FCVTNUws = 483,
+ AArch64_FCVTNUxd = 484,
+ AArch64_FCVTNUxs = 485,
+ AArch64_FCVTPSwd = 486,
+ AArch64_FCVTPSws = 487,
+ AArch64_FCVTPSxd = 488,
+ AArch64_FCVTPSxs = 489,
+ AArch64_FCVTPUwd = 490,
+ AArch64_FCVTPUws = 491,
+ AArch64_FCVTPUxd = 492,
+ AArch64_FCVTPUxs = 493,
+ AArch64_FCVTZSwd = 494,
+ AArch64_FCVTZSwdi = 495,
+ AArch64_FCVTZSws = 496,
+ AArch64_FCVTZSwsi = 497,
+ AArch64_FCVTZSxd = 498,
+ AArch64_FCVTZSxdi = 499,
+ AArch64_FCVTZSxs = 500,
+ AArch64_FCVTZSxsi = 501,
+ AArch64_FCVTZUwd = 502,
+ AArch64_FCVTZUwdi = 503,
+ AArch64_FCVTZUws = 504,
+ AArch64_FCVTZUwsi = 505,
+ AArch64_FCVTZUxd = 506,
+ AArch64_FCVTZUxdi = 507,
+ AArch64_FCVTZUxs = 508,
+ AArch64_FCVTZUxsi = 509,
+ AArch64_FCVTdh = 510,
+ AArch64_FCVTds = 511,
+ AArch64_FCVThd = 512,
+ AArch64_FCVThs = 513,
+ AArch64_FCVTsd = 514,
+ AArch64_FCVTsh = 515,
+ AArch64_FDIVddd = 516,
+ AArch64_FDIVsss = 517,
+ AArch64_FDIVvvv_2D = 518,
+ AArch64_FDIVvvv_2S = 519,
+ AArch64_FDIVvvv_4S = 520,
+ AArch64_FMADDdddd = 521,
+ AArch64_FMADDssss = 522,
+ AArch64_FMAXNMPvv_D_2D = 523,
+ AArch64_FMAXNMPvv_S_2S = 524,
+ AArch64_FMAXNMPvvv_2D = 525,
+ AArch64_FMAXNMPvvv_2S = 526,
+ AArch64_FMAXNMPvvv_4S = 527,
+ AArch64_FMAXNMddd = 528,
+ AArch64_FMAXNMsss = 529,
+ AArch64_FMAXNMvvv_2D = 530,
+ AArch64_FMAXNMvvv_2S = 531,
+ AArch64_FMAXNMvvv_4S = 532,
+ AArch64_FMAXPvv_D_2D = 533,
+ AArch64_FMAXPvv_S_2S = 534,
+ AArch64_FMAXPvvv_2D = 535,
+ AArch64_FMAXPvvv_2S = 536,
+ AArch64_FMAXPvvv_4S = 537,
+ AArch64_FMAXddd = 538,
+ AArch64_FMAXsss = 539,
+ AArch64_FMAXvvv_2D = 540,
+ AArch64_FMAXvvv_2S = 541,
+ AArch64_FMAXvvv_4S = 542,
+ AArch64_FMINNMPvv_D_2D = 543,
+ AArch64_FMINNMPvv_S_2S = 544,
+ AArch64_FMINNMPvvv_2D = 545,
+ AArch64_FMINNMPvvv_2S = 546,
+ AArch64_FMINNMPvvv_4S = 547,
+ AArch64_FMINNMddd = 548,
+ AArch64_FMINNMsss = 549,
+ AArch64_FMINNMvvv_2D = 550,
+ AArch64_FMINNMvvv_2S = 551,
+ AArch64_FMINNMvvv_4S = 552,
+ AArch64_FMINPvv_D_2D = 553,
+ AArch64_FMINPvv_S_2S = 554,
+ AArch64_FMINPvvv_2D = 555,
+ AArch64_FMINPvvv_2S = 556,
+ AArch64_FMINPvvv_4S = 557,
+ AArch64_FMINddd = 558,
+ AArch64_FMINsss = 559,
+ AArch64_FMINvvv_2D = 560,
+ AArch64_FMINvvv_2S = 561,
+ AArch64_FMINvvv_4S = 562,
+ AArch64_FMLAvvv_2D = 563,
+ AArch64_FMLAvvv_2S = 564,
+ AArch64_FMLAvvv_4S = 565,
+ AArch64_FMLSvvv_2D = 566,
+ AArch64_FMLSvvv_2S = 567,
+ AArch64_FMLSvvv_4S = 568,
+ AArch64_FMOVdd = 569,
+ AArch64_FMOVdi = 570,
+ AArch64_FMOVdx = 571,
+ AArch64_FMOVsi = 572,
+ AArch64_FMOVss = 573,
+ AArch64_FMOVsw = 574,
+ AArch64_FMOVvi_2D = 575,
+ AArch64_FMOVvi_2S = 576,
+ AArch64_FMOVvi_4S = 577,
+ AArch64_FMOVvx = 578,
+ AArch64_FMOVws = 579,
+ AArch64_FMOVxd = 580,
+ AArch64_FMOVxv = 581,
+ AArch64_FMSUBdddd = 582,
+ AArch64_FMSUBssss = 583,
+ AArch64_FMULXvvv_2D = 584,
+ AArch64_FMULXvvv_2S = 585,
+ AArch64_FMULXvvv_4S = 586,
+ AArch64_FMULddd = 587,
+ AArch64_FMULsss = 588,
+ AArch64_FMULvvv_2D = 589,
+ AArch64_FMULvvv_2S = 590,
+ AArch64_FMULvvv_4S = 591,
+ AArch64_FNEGdd = 592,
+ AArch64_FNEGss = 593,
+ AArch64_FNMADDdddd = 594,
+ AArch64_FNMADDssss = 595,
+ AArch64_FNMSUBdddd = 596,
+ AArch64_FNMSUBssss = 597,
+ AArch64_FNMULddd = 598,
+ AArch64_FNMULsss = 599,
+ AArch64_FRECPSvvv_2D = 600,
+ AArch64_FRECPSvvv_2S = 601,
+ AArch64_FRECPSvvv_4S = 602,
+ AArch64_FRINTAdd = 603,
+ AArch64_FRINTAss = 604,
+ AArch64_FRINTIdd = 605,
+ AArch64_FRINTIss = 606,
+ AArch64_FRINTMdd = 607,
+ AArch64_FRINTMss = 608,
+ AArch64_FRINTNdd = 609,
+ AArch64_FRINTNss = 610,
+ AArch64_FRINTPdd = 611,
+ AArch64_FRINTPss = 612,
+ AArch64_FRINTXdd = 613,
+ AArch64_FRINTXss = 614,
+ AArch64_FRINTZdd = 615,
+ AArch64_FRINTZss = 616,
+ AArch64_FRSQRTSvvv_2D = 617,
+ AArch64_FRSQRTSvvv_2S = 618,
+ AArch64_FRSQRTSvvv_4S = 619,
+ AArch64_FSQRTdd = 620,
+ AArch64_FSQRTss = 621,
+ AArch64_FSUBddd = 622,
+ AArch64_FSUBsss = 623,
+ AArch64_FSUBvvv_2D = 624,
+ AArch64_FSUBvvv_2S = 625,
+ AArch64_FSUBvvv_4S = 626,
+ AArch64_HINTi = 627,
+ AArch64_HLTi = 628,
+ AArch64_HVCi = 629,
+ AArch64_ICi = 630,
+ AArch64_ICix = 631,
+ AArch64_INSELb = 632,
+ AArch64_INSELd = 633,
+ AArch64_INSELh = 634,
+ AArch64_INSELs = 635,
+ AArch64_INSbw = 636,
+ AArch64_INSdx = 637,
+ AArch64_INShw = 638,
+ AArch64_INSsw = 639,
+ AArch64_ISBi = 640,
+ AArch64_LDAR_byte = 641,
+ AArch64_LDAR_dword = 642,
+ AArch64_LDAR_hword = 643,
+ AArch64_LDAR_word = 644,
+ AArch64_LDAXP_dword = 645,
+ AArch64_LDAXP_word = 646,
+ AArch64_LDAXR_byte = 647,
+ AArch64_LDAXR_dword = 648,
+ AArch64_LDAXR_hword = 649,
+ AArch64_LDAXR_word = 650,
+ AArch64_LDPSWx = 651,
+ AArch64_LDPSWx_PostInd = 652,
+ AArch64_LDPSWx_PreInd = 653,
+ AArch64_LDRSBw = 654,
+ AArch64_LDRSBw_PostInd = 655,
+ AArch64_LDRSBw_PreInd = 656,
+ AArch64_LDRSBw_U = 657,
+ AArch64_LDRSBw_Wm_RegOffset = 658,
+ AArch64_LDRSBw_Xm_RegOffset = 659,
+ AArch64_LDRSBx = 660,
+ AArch64_LDRSBx_PostInd = 661,
+ AArch64_LDRSBx_PreInd = 662,
+ AArch64_LDRSBx_U = 663,
+ AArch64_LDRSBx_Wm_RegOffset = 664,
+ AArch64_LDRSBx_Xm_RegOffset = 665,
+ AArch64_LDRSHw = 666,
+ AArch64_LDRSHw_PostInd = 667,
+ AArch64_LDRSHw_PreInd = 668,
+ AArch64_LDRSHw_U = 669,
+ AArch64_LDRSHw_Wm_RegOffset = 670,
+ AArch64_LDRSHw_Xm_RegOffset = 671,
+ AArch64_LDRSHx = 672,
+ AArch64_LDRSHx_PostInd = 673,
+ AArch64_LDRSHx_PreInd = 674,
+ AArch64_LDRSHx_U = 675,
+ AArch64_LDRSHx_Wm_RegOffset = 676,
+ AArch64_LDRSHx_Xm_RegOffset = 677,
+ AArch64_LDRSWx = 678,
+ AArch64_LDRSWx_PostInd = 679,
+ AArch64_LDRSWx_PreInd = 680,
+ AArch64_LDRSWx_Wm_RegOffset = 681,
+ AArch64_LDRSWx_Xm_RegOffset = 682,
+ AArch64_LDRSWx_lit = 683,
+ AArch64_LDRd_lit = 684,
+ AArch64_LDRq_lit = 685,
+ AArch64_LDRs_lit = 686,
+ AArch64_LDRw_lit = 687,
+ AArch64_LDRx_lit = 688,
+ AArch64_LDTRSBw = 689,
+ AArch64_LDTRSBx = 690,
+ AArch64_LDTRSHw = 691,
+ AArch64_LDTRSHx = 692,
+ AArch64_LDTRSWx = 693,
+ AArch64_LDURSWx = 694,
+ AArch64_LDXP_dword = 695,
+ AArch64_LDXP_word = 696,
+ AArch64_LDXR_byte = 697,
+ AArch64_LDXR_dword = 698,
+ AArch64_LDXR_hword = 699,
+ AArch64_LDXR_word = 700,
+ AArch64_LS16_LDR = 701,
+ AArch64_LS16_LDUR = 702,
+ AArch64_LS16_PostInd_LDR = 703,
+ AArch64_LS16_PostInd_STR = 704,
+ AArch64_LS16_PreInd_LDR = 705,
+ AArch64_LS16_PreInd_STR = 706,
+ AArch64_LS16_STR = 707,
+ AArch64_LS16_STUR = 708,
+ AArch64_LS16_UnPriv_LDR = 709,
+ AArch64_LS16_UnPriv_STR = 710,
+ AArch64_LS16_Wm_RegOffset_LDR = 711,
+ AArch64_LS16_Wm_RegOffset_STR = 712,
+ AArch64_LS16_Xm_RegOffset_LDR = 713,
+ AArch64_LS16_Xm_RegOffset_STR = 714,
+ AArch64_LS32_LDR = 715,
+ AArch64_LS32_LDUR = 716,
+ AArch64_LS32_PostInd_LDR = 717,
+ AArch64_LS32_PostInd_STR = 718,
+ AArch64_LS32_PreInd_LDR = 719,
+ AArch64_LS32_PreInd_STR = 720,
+ AArch64_LS32_STR = 721,
+ AArch64_LS32_STUR = 722,
+ AArch64_LS32_UnPriv_LDR = 723,
+ AArch64_LS32_UnPriv_STR = 724,
+ AArch64_LS32_Wm_RegOffset_LDR = 725,
+ AArch64_LS32_Wm_RegOffset_STR = 726,
+ AArch64_LS32_Xm_RegOffset_LDR = 727,
+ AArch64_LS32_Xm_RegOffset_STR = 728,
+ AArch64_LS64_LDR = 729,
+ AArch64_LS64_LDUR = 730,
+ AArch64_LS64_PostInd_LDR = 731,
+ AArch64_LS64_PostInd_STR = 732,
+ AArch64_LS64_PreInd_LDR = 733,
+ AArch64_LS64_PreInd_STR = 734,
+ AArch64_LS64_STR = 735,
+ AArch64_LS64_STUR = 736,
+ AArch64_LS64_UnPriv_LDR = 737,
+ AArch64_LS64_UnPriv_STR = 738,
+ AArch64_LS64_Wm_RegOffset_LDR = 739,
+ AArch64_LS64_Wm_RegOffset_STR = 740,
+ AArch64_LS64_Xm_RegOffset_LDR = 741,
+ AArch64_LS64_Xm_RegOffset_STR = 742,
+ AArch64_LS8_LDR = 743,
+ AArch64_LS8_LDUR = 744,
+ AArch64_LS8_PostInd_LDR = 745,
+ AArch64_LS8_PostInd_STR = 746,
+ AArch64_LS8_PreInd_LDR = 747,
+ AArch64_LS8_PreInd_STR = 748,
+ AArch64_LS8_STR = 749,
+ AArch64_LS8_STUR = 750,
+ AArch64_LS8_UnPriv_LDR = 751,
+ AArch64_LS8_UnPriv_STR = 752,
+ AArch64_LS8_Wm_RegOffset_LDR = 753,
+ AArch64_LS8_Wm_RegOffset_STR = 754,
+ AArch64_LS8_Xm_RegOffset_LDR = 755,
+ AArch64_LS8_Xm_RegOffset_STR = 756,
+ AArch64_LSFP128_LDR = 757,
+ AArch64_LSFP128_LDUR = 758,
+ AArch64_LSFP128_PostInd_LDR = 759,
+ AArch64_LSFP128_PostInd_STR = 760,
+ AArch64_LSFP128_PreInd_LDR = 761,
+ AArch64_LSFP128_PreInd_STR = 762,
+ AArch64_LSFP128_STR = 763,
+ AArch64_LSFP128_STUR = 764,
+ AArch64_LSFP128_Wm_RegOffset_LDR = 765,
+ AArch64_LSFP128_Wm_RegOffset_STR = 766,
+ AArch64_LSFP128_Xm_RegOffset_LDR = 767,
+ AArch64_LSFP128_Xm_RegOffset_STR = 768,
+ AArch64_LSFP16_LDR = 769,
+ AArch64_LSFP16_LDUR = 770,
+ AArch64_LSFP16_PostInd_LDR = 771,
+ AArch64_LSFP16_PostInd_STR = 772,
+ AArch64_LSFP16_PreInd_LDR = 773,
+ AArch64_LSFP16_PreInd_STR = 774,
+ AArch64_LSFP16_STR = 775,
+ AArch64_LSFP16_STUR = 776,
+ AArch64_LSFP16_Wm_RegOffset_LDR = 777,
+ AArch64_LSFP16_Wm_RegOffset_STR = 778,
+ AArch64_LSFP16_Xm_RegOffset_LDR = 779,
+ AArch64_LSFP16_Xm_RegOffset_STR = 780,
+ AArch64_LSFP32_LDR = 781,
+ AArch64_LSFP32_LDUR = 782,
+ AArch64_LSFP32_PostInd_LDR = 783,
+ AArch64_LSFP32_PostInd_STR = 784,
+ AArch64_LSFP32_PreInd_LDR = 785,
+ AArch64_LSFP32_PreInd_STR = 786,
+ AArch64_LSFP32_STR = 787,
+ AArch64_LSFP32_STUR = 788,
+ AArch64_LSFP32_Wm_RegOffset_LDR = 789,
+ AArch64_LSFP32_Wm_RegOffset_STR = 790,
+ AArch64_LSFP32_Xm_RegOffset_LDR = 791,
+ AArch64_LSFP32_Xm_RegOffset_STR = 792,
+ AArch64_LSFP64_LDR = 793,
+ AArch64_LSFP64_LDUR = 794,
+ AArch64_LSFP64_PostInd_LDR = 795,
+ AArch64_LSFP64_PostInd_STR = 796,
+ AArch64_LSFP64_PreInd_LDR = 797,
+ AArch64_LSFP64_PreInd_STR = 798,
+ AArch64_LSFP64_STR = 799,
+ AArch64_LSFP64_STUR = 800,
+ AArch64_LSFP64_Wm_RegOffset_LDR = 801,
+ AArch64_LSFP64_Wm_RegOffset_STR = 802,
+ AArch64_LSFP64_Xm_RegOffset_LDR = 803,
+ AArch64_LSFP64_Xm_RegOffset_STR = 804,
+ AArch64_LSFP8_LDR = 805,
+ AArch64_LSFP8_LDUR = 806,
+ AArch64_LSFP8_PostInd_LDR = 807,
+ AArch64_LSFP8_PostInd_STR = 808,
+ AArch64_LSFP8_PreInd_LDR = 809,
+ AArch64_LSFP8_PreInd_STR = 810,
+ AArch64_LSFP8_STR = 811,
+ AArch64_LSFP8_STUR = 812,
+ AArch64_LSFP8_Wm_RegOffset_LDR = 813,
+ AArch64_LSFP8_Wm_RegOffset_STR = 814,
+ AArch64_LSFP8_Xm_RegOffset_LDR = 815,
+ AArch64_LSFP8_Xm_RegOffset_STR = 816,
+ AArch64_LSFPPair128_LDR = 817,
+ AArch64_LSFPPair128_NonTemp_LDR = 818,
+ AArch64_LSFPPair128_NonTemp_STR = 819,
+ AArch64_LSFPPair128_PostInd_LDR = 820,
+ AArch64_LSFPPair128_PostInd_STR = 821,
+ AArch64_LSFPPair128_PreInd_LDR = 822,
+ AArch64_LSFPPair128_PreInd_STR = 823,
+ AArch64_LSFPPair128_STR = 824,
+ AArch64_LSFPPair32_LDR = 825,
+ AArch64_LSFPPair32_NonTemp_LDR = 826,
+ AArch64_LSFPPair32_NonTemp_STR = 827,
+ AArch64_LSFPPair32_PostInd_LDR = 828,
+ AArch64_LSFPPair32_PostInd_STR = 829,
+ AArch64_LSFPPair32_PreInd_LDR = 830,
+ AArch64_LSFPPair32_PreInd_STR = 831,
+ AArch64_LSFPPair32_STR = 832,
+ AArch64_LSFPPair64_LDR = 833,
+ AArch64_LSFPPair64_NonTemp_LDR = 834,
+ AArch64_LSFPPair64_NonTemp_STR = 835,
+ AArch64_LSFPPair64_PostInd_LDR = 836,
+ AArch64_LSFPPair64_PostInd_STR = 837,
+ AArch64_LSFPPair64_PreInd_LDR = 838,
+ AArch64_LSFPPair64_PreInd_STR = 839,
+ AArch64_LSFPPair64_STR = 840,
+ AArch64_LSLVwww = 841,
+ AArch64_LSLVxxx = 842,
+ AArch64_LSLwwi = 843,
+ AArch64_LSLxxi = 844,
+ AArch64_LSPair32_LDR = 845,
+ AArch64_LSPair32_NonTemp_LDR = 846,
+ AArch64_LSPair32_NonTemp_STR = 847,
+ AArch64_LSPair32_PostInd_LDR = 848,
+ AArch64_LSPair32_PostInd_STR = 849,
+ AArch64_LSPair32_PreInd_LDR = 850,
+ AArch64_LSPair32_PreInd_STR = 851,
+ AArch64_LSPair32_STR = 852,
+ AArch64_LSPair64_LDR = 853,
+ AArch64_LSPair64_NonTemp_LDR = 854,
+ AArch64_LSPair64_NonTemp_STR = 855,
+ AArch64_LSPair64_PostInd_LDR = 856,
+ AArch64_LSPair64_PostInd_STR = 857,
+ AArch64_LSPair64_PreInd_LDR = 858,
+ AArch64_LSPair64_PreInd_STR = 859,
+ AArch64_LSPair64_STR = 860,
+ AArch64_LSRVwww = 861,
+ AArch64_LSRVxxx = 862,
+ AArch64_LSRwwi = 863,
+ AArch64_LSRxxi = 864,
+ AArch64_MADDwwww = 865,
+ AArch64_MADDxxxx = 866,
+ AArch64_MLAvvv_16B = 867,
+ AArch64_MLAvvv_2S = 868,
+ AArch64_MLAvvv_4H = 869,
+ AArch64_MLAvvv_4S = 870,
+ AArch64_MLAvvv_8B = 871,
+ AArch64_MLAvvv_8H = 872,
+ AArch64_MLSvvv_16B = 873,
+ AArch64_MLSvvv_2S = 874,
+ AArch64_MLSvvv_4H = 875,
+ AArch64_MLSvvv_4S = 876,
+ AArch64_MLSvvv_8B = 877,
+ AArch64_MLSvvv_8H = 878,
+ AArch64_MOVIdi = 879,
+ AArch64_MOVIvi_16B = 880,
+ AArch64_MOVIvi_2D = 881,
+ AArch64_MOVIvi_8B = 882,
+ AArch64_MOVIvi_lsl_2S = 883,
+ AArch64_MOVIvi_lsl_4H = 884,
+ AArch64_MOVIvi_lsl_4S = 885,
+ AArch64_MOVIvi_lsl_8H = 886,
+ AArch64_MOVIvi_msl_2S = 887,
+ AArch64_MOVIvi_msl_4S = 888,
+ AArch64_MOVKwii = 889,
+ AArch64_MOVKxii = 890,
+ AArch64_MOVNwii = 891,
+ AArch64_MOVNxii = 892,
+ AArch64_MOVZwii = 893,
+ AArch64_MOVZxii = 894,
+ AArch64_MRSxi = 895,
+ AArch64_MSRii = 896,
+ AArch64_MSRix = 897,
+ AArch64_MSUBwwww = 898,
+ AArch64_MSUBxxxx = 899,
+ AArch64_MULvvv_16B = 900,
+ AArch64_MULvvv_2S = 901,
+ AArch64_MULvvv_4H = 902,
+ AArch64_MULvvv_4S = 903,
+ AArch64_MULvvv_8B = 904,
+ AArch64_MULvvv_8H = 905,
+ AArch64_MVNIvi_lsl_2S = 906,
+ AArch64_MVNIvi_lsl_4H = 907,
+ AArch64_MVNIvi_lsl_4S = 908,
+ AArch64_MVNIvi_lsl_8H = 909,
+ AArch64_MVNIvi_msl_2S = 910,
+ AArch64_MVNIvi_msl_4S = 911,
+ AArch64_MVNww_asr = 912,
+ AArch64_MVNww_lsl = 913,
+ AArch64_MVNww_lsr = 914,
+ AArch64_MVNww_ror = 915,
+ AArch64_MVNxx_asr = 916,
+ AArch64_MVNxx_lsl = 917,
+ AArch64_MVNxx_lsr = 918,
+ AArch64_MVNxx_ror = 919,
+ AArch64_ORNvvv_16B = 920,
+ AArch64_ORNvvv_8B = 921,
+ AArch64_ORNwww_asr = 922,
+ AArch64_ORNwww_lsl = 923,
+ AArch64_ORNwww_lsr = 924,
+ AArch64_ORNwww_ror = 925,
+ AArch64_ORNxxx_asr = 926,
+ AArch64_ORNxxx_lsl = 927,
+ AArch64_ORNxxx_lsr = 928,
+ AArch64_ORNxxx_ror = 929,
+ AArch64_ORRvi_lsl_2S = 930,
+ AArch64_ORRvi_lsl_4H = 931,
+ AArch64_ORRvi_lsl_4S = 932,
+ AArch64_ORRvi_lsl_8H = 933,
+ AArch64_ORRvvv_16B = 934,
+ AArch64_ORRvvv_8B = 935,
+ AArch64_ORRwwi = 936,
+ AArch64_ORRwww_asr = 937,
+ AArch64_ORRwww_lsl = 938,
+ AArch64_ORRwww_lsr = 939,
+ AArch64_ORRwww_ror = 940,
+ AArch64_ORRxxi = 941,
+ AArch64_ORRxxx_asr = 942,
+ AArch64_ORRxxx_lsl = 943,
+ AArch64_ORRxxx_lsr = 944,
+ AArch64_ORRxxx_ror = 945,
+ AArch64_PMULL2vvv_8h16b = 946,
+ AArch64_PMULLvvv_8h8b = 947,
+ AArch64_PMULvvv_16B = 948,
+ AArch64_PMULvvv_8B = 949,
+ AArch64_PRFM = 950,
+ AArch64_PRFM_Wm_RegOffset = 951,
+ AArch64_PRFM_Xm_RegOffset = 952,
+ AArch64_PRFM_lit = 953,
+ AArch64_PRFUM = 954,
+ AArch64_QRSHRUNvvi_16B = 955,
+ AArch64_QRSHRUNvvi_2S = 956,
+ AArch64_QRSHRUNvvi_4H = 957,
+ AArch64_QRSHRUNvvi_4S = 958,
+ AArch64_QRSHRUNvvi_8B = 959,
+ AArch64_QRSHRUNvvi_8H = 960,
+ AArch64_QSHRUNvvi_16B = 961,
+ AArch64_QSHRUNvvi_2S = 962,
+ AArch64_QSHRUNvvi_4H = 963,
+ AArch64_QSHRUNvvi_4S = 964,
+ AArch64_QSHRUNvvi_8B = 965,
+ AArch64_QSHRUNvvi_8H = 966,
+ AArch64_RADDHN2vvv_16b8h = 967,
+ AArch64_RADDHN2vvv_4s2d = 968,
+ AArch64_RADDHN2vvv_8h4s = 969,
+ AArch64_RADDHNvvv_2s2d = 970,
+ AArch64_RADDHNvvv_4h4s = 971,
+ AArch64_RADDHNvvv_8b8h = 972,
+ AArch64_RBITww = 973,
+ AArch64_RBITxx = 974,
+ AArch64_RET = 975,
+ AArch64_RETx = 976,
+ AArch64_REV16ww = 977,
+ AArch64_REV16xx = 978,
+ AArch64_REV32xx = 979,
+ AArch64_REVww = 980,
+ AArch64_REVxx = 981,
+ AArch64_RORVwww = 982,
+ AArch64_RORVxxx = 983,
+ AArch64_RSHRNvvi_16B = 984,
+ AArch64_RSHRNvvi_2S = 985,
+ AArch64_RSHRNvvi_4H = 986,
+ AArch64_RSHRNvvi_4S = 987,
+ AArch64_RSHRNvvi_8B = 988,
+ AArch64_RSHRNvvi_8H = 989,
+ AArch64_RSUBHN2vvv_16b8h = 990,
+ AArch64_RSUBHN2vvv_4s2d = 991,
+ AArch64_RSUBHN2vvv_8h4s = 992,
+ AArch64_RSUBHNvvv_2s2d = 993,
+ AArch64_RSUBHNvvv_4h4s = 994,
+ AArch64_RSUBHNvvv_8b8h = 995,
+ AArch64_SABAL2vvv_2d2s = 996,
+ AArch64_SABAL2vvv_4s4h = 997,
+ AArch64_SABAL2vvv_8h8b = 998,
+ AArch64_SABALvvv_2d2s = 999,
+ AArch64_SABALvvv_4s4h = 1000,
+ AArch64_SABALvvv_8h8b = 1001,
+ AArch64_SABAvvv_16B = 1002,
+ AArch64_SABAvvv_2S = 1003,
+ AArch64_SABAvvv_4H = 1004,
+ AArch64_SABAvvv_4S = 1005,
+ AArch64_SABAvvv_8B = 1006,
+ AArch64_SABAvvv_8H = 1007,
+ AArch64_SABDL2vvv_2d2s = 1008,
+ AArch64_SABDL2vvv_4s4h = 1009,
+ AArch64_SABDL2vvv_8h8b = 1010,
+ AArch64_SABDLvvv_2d2s = 1011,
+ AArch64_SABDLvvv_4s4h = 1012,
+ AArch64_SABDLvvv_8h8b = 1013,
+ AArch64_SABDvvv_16B = 1014,
+ AArch64_SABDvvv_2S = 1015,
+ AArch64_SABDvvv_4H = 1016,
+ AArch64_SABDvvv_4S = 1017,
+ AArch64_SABDvvv_8B = 1018,
+ AArch64_SABDvvv_8H = 1019,
+ AArch64_SADDL2vvv_2d4s = 1020,
+ AArch64_SADDL2vvv_4s8h = 1021,
+ AArch64_SADDL2vvv_8h16b = 1022,
+ AArch64_SADDLvvv_2d2s = 1023,
+ AArch64_SADDLvvv_4s4h = 1024,
+ AArch64_SADDLvvv_8h8b = 1025,
+ AArch64_SADDW2vvv_2d4s = 1026,
+ AArch64_SADDW2vvv_4s8h = 1027,
+ AArch64_SADDW2vvv_8h16b = 1028,
+ AArch64_SADDWvvv_2d2s = 1029,
+ AArch64_SADDWvvv_4s4h = 1030,
+ AArch64_SADDWvvv_8h8b = 1031,
+ AArch64_SBCSwww = 1032,
+ AArch64_SBCSxxx = 1033,
+ AArch64_SBCwww = 1034,
+ AArch64_SBCxxx = 1035,
+ AArch64_SBFIZwwii = 1036,
+ AArch64_SBFIZxxii = 1037,
+ AArch64_SBFMwwii = 1038,
+ AArch64_SBFMxxii = 1039,
+ AArch64_SBFXwwii = 1040,
+ AArch64_SBFXxxii = 1041,
+ AArch64_SCVTFdw = 1042,
+ AArch64_SCVTFdwi = 1043,
+ AArch64_SCVTFdx = 1044,
+ AArch64_SCVTFdxi = 1045,
+ AArch64_SCVTFsw = 1046,
+ AArch64_SCVTFswi = 1047,
+ AArch64_SCVTFsx = 1048,
+ AArch64_SCVTFsxi = 1049,
+ AArch64_SDIVwww = 1050,
+ AArch64_SDIVxxx = 1051,
+ AArch64_SHADDvvv_16B = 1052,
+ AArch64_SHADDvvv_2S = 1053,
+ AArch64_SHADDvvv_4H = 1054,
+ AArch64_SHADDvvv_4S = 1055,
+ AArch64_SHADDvvv_8B = 1056,
+ AArch64_SHADDvvv_8H = 1057,
+ AArch64_SHLvvi_16B = 1058,
+ AArch64_SHLvvi_2D = 1059,
+ AArch64_SHLvvi_2S = 1060,
+ AArch64_SHLvvi_4H = 1061,
+ AArch64_SHLvvi_4S = 1062,
+ AArch64_SHLvvi_8B = 1063,
+ AArch64_SHLvvi_8H = 1064,
+ AArch64_SHRNvvi_16B = 1065,
+ AArch64_SHRNvvi_2S = 1066,
+ AArch64_SHRNvvi_4H = 1067,
+ AArch64_SHRNvvi_4S = 1068,
+ AArch64_SHRNvvi_8B = 1069,
+ AArch64_SHRNvvi_8H = 1070,
+ AArch64_SHSUBvvv_16B = 1071,
+ AArch64_SHSUBvvv_2S = 1072,
+ AArch64_SHSUBvvv_4H = 1073,
+ AArch64_SHSUBvvv_4S = 1074,
+ AArch64_SHSUBvvv_8B = 1075,
+ AArch64_SHSUBvvv_8H = 1076,
+ AArch64_SLIvvi_16B = 1077,
+ AArch64_SLIvvi_2D = 1078,
+ AArch64_SLIvvi_2S = 1079,
+ AArch64_SLIvvi_4H = 1080,
+ AArch64_SLIvvi_4S = 1081,
+ AArch64_SLIvvi_8B = 1082,
+ AArch64_SLIvvi_8H = 1083,
+ AArch64_SMADDLxwwx = 1084,
+ AArch64_SMAXPvvv_16B = 1085,
+ AArch64_SMAXPvvv_2S = 1086,
+ AArch64_SMAXPvvv_4H = 1087,
+ AArch64_SMAXPvvv_4S = 1088,
+ AArch64_SMAXPvvv_8B = 1089,
+ AArch64_SMAXPvvv_8H = 1090,
+ AArch64_SMAXvvv_16B = 1091,
+ AArch64_SMAXvvv_2S = 1092,
+ AArch64_SMAXvvv_4H = 1093,
+ AArch64_SMAXvvv_4S = 1094,
+ AArch64_SMAXvvv_8B = 1095,
+ AArch64_SMAXvvv_8H = 1096,
+ AArch64_SMCi = 1097,
+ AArch64_SMINPvvv_16B = 1098,
+ AArch64_SMINPvvv_2S = 1099,
+ AArch64_SMINPvvv_4H = 1100,
+ AArch64_SMINPvvv_4S = 1101,
+ AArch64_SMINPvvv_8B = 1102,
+ AArch64_SMINPvvv_8H = 1103,
+ AArch64_SMINvvv_16B = 1104,
+ AArch64_SMINvvv_2S = 1105,
+ AArch64_SMINvvv_4H = 1106,
+ AArch64_SMINvvv_4S = 1107,
+ AArch64_SMINvvv_8B = 1108,
+ AArch64_SMINvvv_8H = 1109,
+ AArch64_SMLAL2vvv_2d4s = 1110,
+ AArch64_SMLAL2vvv_4s8h = 1111,
+ AArch64_SMLAL2vvv_8h16b = 1112,
+ AArch64_SMLALvvv_2d2s = 1113,
+ AArch64_SMLALvvv_4s4h = 1114,
+ AArch64_SMLALvvv_8h8b = 1115,
+ AArch64_SMLSL2vvv_2d4s = 1116,
+ AArch64_SMLSL2vvv_4s8h = 1117,
+ AArch64_SMLSL2vvv_8h16b = 1118,
+ AArch64_SMLSLvvv_2d2s = 1119,
+ AArch64_SMLSLvvv_4s4h = 1120,
+ AArch64_SMLSLvvv_8h8b = 1121,
+ AArch64_SMOVwb = 1122,
+ AArch64_SMOVwh = 1123,
+ AArch64_SMOVxb = 1124,
+ AArch64_SMOVxh = 1125,
+ AArch64_SMOVxs = 1126,
+ AArch64_SMSUBLxwwx = 1127,
+ AArch64_SMULHxxx = 1128,
+ AArch64_SMULL2vvv_2d4s = 1129,
+ AArch64_SMULL2vvv_4s8h = 1130,
+ AArch64_SMULL2vvv_8h16b = 1131,
+ AArch64_SMULLvvv_2d2s = 1132,
+ AArch64_SMULLvvv_4s4h = 1133,
+ AArch64_SMULLvvv_8h8b = 1134,
+ AArch64_SQADDbbb = 1135,
+ AArch64_SQADDddd = 1136,
+ AArch64_SQADDhhh = 1137,
+ AArch64_SQADDsss = 1138,
+ AArch64_SQADDvvv_16B = 1139,
+ AArch64_SQADDvvv_2D = 1140,
+ AArch64_SQADDvvv_2S = 1141,
+ AArch64_SQADDvvv_4H = 1142,
+ AArch64_SQADDvvv_4S = 1143,
+ AArch64_SQADDvvv_8B = 1144,
+ AArch64_SQADDvvv_8H = 1145,
+ AArch64_SQDMLAL2vvv_2d4s = 1146,
+ AArch64_SQDMLAL2vvv_4s8h = 1147,
+ AArch64_SQDMLALvvv_2d2s = 1148,
+ AArch64_SQDMLALvvv_4s4h = 1149,
+ AArch64_SQDMLSL2vvv_2d4s = 1150,
+ AArch64_SQDMLSL2vvv_4s8h = 1151,
+ AArch64_SQDMLSLvvv_2d2s = 1152,
+ AArch64_SQDMLSLvvv_4s4h = 1153,
+ AArch64_SQDMULHvvv_2S = 1154,
+ AArch64_SQDMULHvvv_4H = 1155,
+ AArch64_SQDMULHvvv_4S = 1156,
+ AArch64_SQDMULHvvv_8H = 1157,
+ AArch64_SQDMULL2vvv_2d4s = 1158,
+ AArch64_SQDMULL2vvv_4s8h = 1159,
+ AArch64_SQDMULLvvv_2d2s = 1160,
+ AArch64_SQDMULLvvv_4s4h = 1161,
+ AArch64_SQRDMULHvvv_2S = 1162,
+ AArch64_SQRDMULHvvv_4H = 1163,
+ AArch64_SQRDMULHvvv_4S = 1164,
+ AArch64_SQRDMULHvvv_8H = 1165,
+ AArch64_SQRSHLbbb = 1166,
+ AArch64_SQRSHLddd = 1167,
+ AArch64_SQRSHLhhh = 1168,
+ AArch64_SQRSHLsss = 1169,
+ AArch64_SQRSHLvvv_16B = 1170,
+ AArch64_SQRSHLvvv_2D = 1171,
+ AArch64_SQRSHLvvv_2S = 1172,
+ AArch64_SQRSHLvvv_4H = 1173,
+ AArch64_SQRSHLvvv_4S = 1174,
+ AArch64_SQRSHLvvv_8B = 1175,
+ AArch64_SQRSHLvvv_8H = 1176,
+ AArch64_SQRSHRNvvi_16B = 1177,
+ AArch64_SQRSHRNvvi_2S = 1178,
+ AArch64_SQRSHRNvvi_4H = 1179,
+ AArch64_SQRSHRNvvi_4S = 1180,
+ AArch64_SQRSHRNvvi_8B = 1181,
+ AArch64_SQRSHRNvvi_8H = 1182,
+ AArch64_SQSHLUvvi_16B = 1183,
+ AArch64_SQSHLUvvi_2D = 1184,
+ AArch64_SQSHLUvvi_2S = 1185,
+ AArch64_SQSHLUvvi_4H = 1186,
+ AArch64_SQSHLUvvi_4S = 1187,
+ AArch64_SQSHLUvvi_8B = 1188,
+ AArch64_SQSHLUvvi_8H = 1189,
+ AArch64_SQSHLbbb = 1190,
+ AArch64_SQSHLddd = 1191,
+ AArch64_SQSHLhhh = 1192,
+ AArch64_SQSHLsss = 1193,
+ AArch64_SQSHLvvi_16B = 1194,
+ AArch64_SQSHLvvi_2D = 1195,
+ AArch64_SQSHLvvi_2S = 1196,
+ AArch64_SQSHLvvi_4H = 1197,
+ AArch64_SQSHLvvi_4S = 1198,
+ AArch64_SQSHLvvi_8B = 1199,
+ AArch64_SQSHLvvi_8H = 1200,
+ AArch64_SQSHLvvv_16B = 1201,
+ AArch64_SQSHLvvv_2D = 1202,
+ AArch64_SQSHLvvv_2S = 1203,
+ AArch64_SQSHLvvv_4H = 1204,
+ AArch64_SQSHLvvv_4S = 1205,
+ AArch64_SQSHLvvv_8B = 1206,
+ AArch64_SQSHLvvv_8H = 1207,
+ AArch64_SQSHRNvvi_16B = 1208,
+ AArch64_SQSHRNvvi_2S = 1209,
+ AArch64_SQSHRNvvi_4H = 1210,
+ AArch64_SQSHRNvvi_4S = 1211,
+ AArch64_SQSHRNvvi_8B = 1212,
+ AArch64_SQSHRNvvi_8H = 1213,
+ AArch64_SQSUBbbb = 1214,
+ AArch64_SQSUBddd = 1215,
+ AArch64_SQSUBhhh = 1216,
+ AArch64_SQSUBsss = 1217,
+ AArch64_SQSUBvvv_16B = 1218,
+ AArch64_SQSUBvvv_2D = 1219,
+ AArch64_SQSUBvvv_2S = 1220,
+ AArch64_SQSUBvvv_4H = 1221,
+ AArch64_SQSUBvvv_4S = 1222,
+ AArch64_SQSUBvvv_8B = 1223,
+ AArch64_SQSUBvvv_8H = 1224,
+ AArch64_SRHADDvvv_16B = 1225,
+ AArch64_SRHADDvvv_2S = 1226,
+ AArch64_SRHADDvvv_4H = 1227,
+ AArch64_SRHADDvvv_4S = 1228,
+ AArch64_SRHADDvvv_8B = 1229,
+ AArch64_SRHADDvvv_8H = 1230,
+ AArch64_SRIvvi_16B = 1231,
+ AArch64_SRIvvi_2D = 1232,
+ AArch64_SRIvvi_2S = 1233,
+ AArch64_SRIvvi_4H = 1234,
+ AArch64_SRIvvi_4S = 1235,
+ AArch64_SRIvvi_8B = 1236,
+ AArch64_SRIvvi_8H = 1237,
+ AArch64_SRSHLddd = 1238,
+ AArch64_SRSHLvvv_16B = 1239,
+ AArch64_SRSHLvvv_2D = 1240,
+ AArch64_SRSHLvvv_2S = 1241,
+ AArch64_SRSHLvvv_4H = 1242,
+ AArch64_SRSHLvvv_4S = 1243,
+ AArch64_SRSHLvvv_8B = 1244,
+ AArch64_SRSHLvvv_8H = 1245,
+ AArch64_SRSHRvvi_16B = 1246,
+ AArch64_SRSHRvvi_2D = 1247,
+ AArch64_SRSHRvvi_2S = 1248,
+ AArch64_SRSHRvvi_4H = 1249,
+ AArch64_SRSHRvvi_4S = 1250,
+ AArch64_SRSHRvvi_8B = 1251,
+ AArch64_SRSHRvvi_8H = 1252,
+ AArch64_SRSRAvvi_16B = 1253,
+ AArch64_SRSRAvvi_2D = 1254,
+ AArch64_SRSRAvvi_2S = 1255,
+ AArch64_SRSRAvvi_4H = 1256,
+ AArch64_SRSRAvvi_4S = 1257,
+ AArch64_SRSRAvvi_8B = 1258,
+ AArch64_SRSRAvvi_8H = 1259,
+ AArch64_SSHLLvvi_16B = 1260,
+ AArch64_SSHLLvvi_2S = 1261,
+ AArch64_SSHLLvvi_4H = 1262,
+ AArch64_SSHLLvvi_4S = 1263,
+ AArch64_SSHLLvvi_8B = 1264,
+ AArch64_SSHLLvvi_8H = 1265,
+ AArch64_SSHLddd = 1266,
+ AArch64_SSHLvvv_16B = 1267,
+ AArch64_SSHLvvv_2D = 1268,
+ AArch64_SSHLvvv_2S = 1269,
+ AArch64_SSHLvvv_4H = 1270,
+ AArch64_SSHLvvv_4S = 1271,
+ AArch64_SSHLvvv_8B = 1272,
+ AArch64_SSHLvvv_8H = 1273,
+ AArch64_SSHRvvi_16B = 1274,
+ AArch64_SSHRvvi_2D = 1275,
+ AArch64_SSHRvvi_2S = 1276,
+ AArch64_SSHRvvi_4H = 1277,
+ AArch64_SSHRvvi_4S = 1278,
+ AArch64_SSHRvvi_8B = 1279,
+ AArch64_SSHRvvi_8H = 1280,
+ AArch64_SSRAvvi_16B = 1281,
+ AArch64_SSRAvvi_2D = 1282,
+ AArch64_SSRAvvi_2S = 1283,
+ AArch64_SSRAvvi_4H = 1284,
+ AArch64_SSRAvvi_4S = 1285,
+ AArch64_SSRAvvi_8B = 1286,
+ AArch64_SSRAvvi_8H = 1287,
+ AArch64_SSUBL2vvv_2d4s = 1288,
+ AArch64_SSUBL2vvv_4s8h = 1289,
+ AArch64_SSUBL2vvv_8h16b = 1290,
+ AArch64_SSUBLvvv_2d2s = 1291,
+ AArch64_SSUBLvvv_4s4h = 1292,
+ AArch64_SSUBLvvv_8h8b = 1293,
+ AArch64_SSUBW2vvv_2d4s = 1294,
+ AArch64_SSUBW2vvv_4s8h = 1295,
+ AArch64_SSUBW2vvv_8h16b = 1296,
+ AArch64_SSUBWvvv_2d2s = 1297,
+ AArch64_SSUBWvvv_4s4h = 1298,
+ AArch64_SSUBWvvv_8h8b = 1299,
+ AArch64_STLR_byte = 1300,
+ AArch64_STLR_dword = 1301,
+ AArch64_STLR_hword = 1302,
+ AArch64_STLR_word = 1303,
+ AArch64_STLXP_dword = 1304,
+ AArch64_STLXP_word = 1305,
+ AArch64_STLXR_byte = 1306,
+ AArch64_STLXR_dword = 1307,
+ AArch64_STLXR_hword = 1308,
+ AArch64_STLXR_word = 1309,
+ AArch64_STXP_dword = 1310,
+ AArch64_STXP_word = 1311,
+ AArch64_STXR_byte = 1312,
+ AArch64_STXR_dword = 1313,
+ AArch64_STXR_hword = 1314,
+ AArch64_STXR_word = 1315,
+ AArch64_SUBHN2vvv_16b8h = 1316,
+ AArch64_SUBHN2vvv_4s2d = 1317,
+ AArch64_SUBHN2vvv_8h4s = 1318,
+ AArch64_SUBHNvvv_2s2d = 1319,
+ AArch64_SUBHNvvv_4h4s = 1320,
+ AArch64_SUBHNvvv_8b8h = 1321,
+ AArch64_SUBSwww_asr = 1322,
+ AArch64_SUBSwww_lsl = 1323,
+ AArch64_SUBSwww_lsr = 1324,
+ AArch64_SUBSwww_sxtb = 1325,
+ AArch64_SUBSwww_sxth = 1326,
+ AArch64_SUBSwww_sxtw = 1327,
+ AArch64_SUBSwww_sxtx = 1328,
+ AArch64_SUBSwww_uxtb = 1329,
+ AArch64_SUBSwww_uxth = 1330,
+ AArch64_SUBSwww_uxtw = 1331,
+ AArch64_SUBSwww_uxtx = 1332,
+ AArch64_SUBSxxw_sxtb = 1333,
+ AArch64_SUBSxxw_sxth = 1334,
+ AArch64_SUBSxxw_sxtw = 1335,
+ AArch64_SUBSxxw_uxtb = 1336,
+ AArch64_SUBSxxw_uxth = 1337,
+ AArch64_SUBSxxw_uxtw = 1338,
+ AArch64_SUBSxxx_asr = 1339,
+ AArch64_SUBSxxx_lsl = 1340,
+ AArch64_SUBSxxx_lsr = 1341,
+ AArch64_SUBSxxx_sxtx = 1342,
+ AArch64_SUBSxxx_uxtx = 1343,
+ AArch64_SUBddd = 1344,
+ AArch64_SUBvvv_16B = 1345,
+ AArch64_SUBvvv_2D = 1346,
+ AArch64_SUBvvv_2S = 1347,
+ AArch64_SUBvvv_4H = 1348,
+ AArch64_SUBvvv_4S = 1349,
+ AArch64_SUBvvv_8B = 1350,
+ AArch64_SUBvvv_8H = 1351,
+ AArch64_SUBwwi_lsl0_S = 1352,
+ AArch64_SUBwwi_lsl0_cmp = 1353,
+ AArch64_SUBwwi_lsl0_s = 1354,
+ AArch64_SUBwwi_lsl12_S = 1355,
+ AArch64_SUBwwi_lsl12_cmp = 1356,
+ AArch64_SUBwwi_lsl12_s = 1357,
+ AArch64_SUBwww_asr = 1358,
+ AArch64_SUBwww_lsl = 1359,
+ AArch64_SUBwww_lsr = 1360,
+ AArch64_SUBwww_sxtb = 1361,
+ AArch64_SUBwww_sxth = 1362,
+ AArch64_SUBwww_sxtw = 1363,
+ AArch64_SUBwww_sxtx = 1364,
+ AArch64_SUBwww_uxtb = 1365,
+ AArch64_SUBwww_uxth = 1366,
+ AArch64_SUBwww_uxtw = 1367,
+ AArch64_SUBwww_uxtx = 1368,
+ AArch64_SUBxxi_lsl0_S = 1369,
+ AArch64_SUBxxi_lsl0_cmp = 1370,
+ AArch64_SUBxxi_lsl0_s = 1371,
+ AArch64_SUBxxi_lsl12_S = 1372,
+ AArch64_SUBxxi_lsl12_cmp = 1373,
+ AArch64_SUBxxi_lsl12_s = 1374,
+ AArch64_SUBxxw_sxtb = 1375,
+ AArch64_SUBxxw_sxth = 1376,
+ AArch64_SUBxxw_sxtw = 1377,
+ AArch64_SUBxxw_uxtb = 1378,
+ AArch64_SUBxxw_uxth = 1379,
+ AArch64_SUBxxw_uxtw = 1380,
+ AArch64_SUBxxx_asr = 1381,
+ AArch64_SUBxxx_lsl = 1382,
+ AArch64_SUBxxx_lsr = 1383,
+ AArch64_SUBxxx_sxtx = 1384,
+ AArch64_SUBxxx_uxtx = 1385,
+ AArch64_SVCi = 1386,
+ AArch64_SXTBww = 1387,
+ AArch64_SXTBxw = 1388,
+ AArch64_SXTHww = 1389,
+ AArch64_SXTHxw = 1390,
+ AArch64_SXTWxw = 1391,
+ AArch64_SYSLxicci = 1392,
+ AArch64_SYSiccix = 1393,
+ AArch64_TAIL_BRx = 1394,
+ AArch64_TAIL_Bimm = 1395,
+ AArch64_TBNZwii = 1396,
+ AArch64_TBNZxii = 1397,
+ AArch64_TBZwii = 1398,
+ AArch64_TBZxii = 1399,
+ AArch64_TC_RETURNdi = 1400,
+ AArch64_TC_RETURNxi = 1401,
+ AArch64_TLBIi = 1402,
+ AArch64_TLBIix = 1403,
+ AArch64_TLSDESCCALL = 1404,
+ AArch64_TLSDESC_BLRx = 1405,
+ AArch64_TSTww_asr = 1406,
+ AArch64_TSTww_lsl = 1407,
+ AArch64_TSTww_lsr = 1408,
+ AArch64_TSTww_ror = 1409,
+ AArch64_TSTxx_asr = 1410,
+ AArch64_TSTxx_lsl = 1411,
+ AArch64_TSTxx_lsr = 1412,
+ AArch64_TSTxx_ror = 1413,
+ AArch64_UABAL2vvv_2d2s = 1414,
+ AArch64_UABAL2vvv_4s4h = 1415,
+ AArch64_UABAL2vvv_8h8b = 1416,
+ AArch64_UABALvvv_2d2s = 1417,
+ AArch64_UABALvvv_4s4h = 1418,
+ AArch64_UABALvvv_8h8b = 1419,
+ AArch64_UABAvvv_16B = 1420,
+ AArch64_UABAvvv_2S = 1421,
+ AArch64_UABAvvv_4H = 1422,
+ AArch64_UABAvvv_4S = 1423,
+ AArch64_UABAvvv_8B = 1424,
+ AArch64_UABAvvv_8H = 1425,
+ AArch64_UABDL2vvv_2d2s = 1426,
+ AArch64_UABDL2vvv_4s4h = 1427,
+ AArch64_UABDL2vvv_8h8b = 1428,
+ AArch64_UABDLvvv_2d2s = 1429,
+ AArch64_UABDLvvv_4s4h = 1430,
+ AArch64_UABDLvvv_8h8b = 1431,
+ AArch64_UABDvvv_16B = 1432,
+ AArch64_UABDvvv_2S = 1433,
+ AArch64_UABDvvv_4H = 1434,
+ AArch64_UABDvvv_4S = 1435,
+ AArch64_UABDvvv_8B = 1436,
+ AArch64_UABDvvv_8H = 1437,
+ AArch64_UADDL2vvv_2d4s = 1438,
+ AArch64_UADDL2vvv_4s8h = 1439,
+ AArch64_UADDL2vvv_8h16b = 1440,
+ AArch64_UADDLvvv_2d2s = 1441,
+ AArch64_UADDLvvv_4s4h = 1442,
+ AArch64_UADDLvvv_8h8b = 1443,
+ AArch64_UADDW2vvv_2d4s = 1444,
+ AArch64_UADDW2vvv_4s8h = 1445,
+ AArch64_UADDW2vvv_8h16b = 1446,
+ AArch64_UADDWvvv_2d2s = 1447,
+ AArch64_UADDWvvv_4s4h = 1448,
+ AArch64_UADDWvvv_8h8b = 1449,
+ AArch64_UBFIZwwii = 1450,
+ AArch64_UBFIZxxii = 1451,
+ AArch64_UBFMwwii = 1452,
+ AArch64_UBFMxxii = 1453,
+ AArch64_UBFXwwii = 1454,
+ AArch64_UBFXxxii = 1455,
+ AArch64_UCVTFdw = 1456,
+ AArch64_UCVTFdwi = 1457,
+ AArch64_UCVTFdx = 1458,
+ AArch64_UCVTFdxi = 1459,
+ AArch64_UCVTFsw = 1460,
+ AArch64_UCVTFswi = 1461,
+ AArch64_UCVTFsx = 1462,
+ AArch64_UCVTFsxi = 1463,
+ AArch64_UDIVwww = 1464,
+ AArch64_UDIVxxx = 1465,
+ AArch64_UHADDvvv_16B = 1466,
+ AArch64_UHADDvvv_2S = 1467,
+ AArch64_UHADDvvv_4H = 1468,
+ AArch64_UHADDvvv_4S = 1469,
+ AArch64_UHADDvvv_8B = 1470,
+ AArch64_UHADDvvv_8H = 1471,
+ AArch64_UHSUBvvv_16B = 1472,
+ AArch64_UHSUBvvv_2S = 1473,
+ AArch64_UHSUBvvv_4H = 1474,
+ AArch64_UHSUBvvv_4S = 1475,
+ AArch64_UHSUBvvv_8B = 1476,
+ AArch64_UHSUBvvv_8H = 1477,
+ AArch64_UMADDLxwwx = 1478,
+ AArch64_UMAXPvvv_16B = 1479,
+ AArch64_UMAXPvvv_2S = 1480,
+ AArch64_UMAXPvvv_4H = 1481,
+ AArch64_UMAXPvvv_4S = 1482,
+ AArch64_UMAXPvvv_8B = 1483,
+ AArch64_UMAXPvvv_8H = 1484,
+ AArch64_UMAXvvv_16B = 1485,
+ AArch64_UMAXvvv_2S = 1486,
+ AArch64_UMAXvvv_4H = 1487,
+ AArch64_UMAXvvv_4S = 1488,
+ AArch64_UMAXvvv_8B = 1489,
+ AArch64_UMAXvvv_8H = 1490,
+ AArch64_UMINPvvv_16B = 1491,
+ AArch64_UMINPvvv_2S = 1492,
+ AArch64_UMINPvvv_4H = 1493,
+ AArch64_UMINPvvv_4S = 1494,
+ AArch64_UMINPvvv_8B = 1495,
+ AArch64_UMINPvvv_8H = 1496,
+ AArch64_UMINvvv_16B = 1497,
+ AArch64_UMINvvv_2S = 1498,
+ AArch64_UMINvvv_4H = 1499,
+ AArch64_UMINvvv_4S = 1500,
+ AArch64_UMINvvv_8B = 1501,
+ AArch64_UMINvvv_8H = 1502,
+ AArch64_UMLAL2vvv_2d4s = 1503,
+ AArch64_UMLAL2vvv_4s8h = 1504,
+ AArch64_UMLAL2vvv_8h16b = 1505,
+ AArch64_UMLALvvv_2d2s = 1506,
+ AArch64_UMLALvvv_4s4h = 1507,
+ AArch64_UMLALvvv_8h8b = 1508,
+ AArch64_UMLSL2vvv_2d4s = 1509,
+ AArch64_UMLSL2vvv_4s8h = 1510,
+ AArch64_UMLSL2vvv_8h16b = 1511,
+ AArch64_UMLSLvvv_2d2s = 1512,
+ AArch64_UMLSLvvv_4s4h = 1513,
+ AArch64_UMLSLvvv_8h8b = 1514,
+ AArch64_UMOVwb = 1515,
+ AArch64_UMOVwh = 1516,
+ AArch64_UMOVws = 1517,
+ AArch64_UMOVxd = 1518,
+ AArch64_UMSUBLxwwx = 1519,
+ AArch64_UMULHxxx = 1520,
+ AArch64_UMULL2vvv_2d4s = 1521,
+ AArch64_UMULL2vvv_4s8h = 1522,
+ AArch64_UMULL2vvv_8h16b = 1523,
+ AArch64_UMULLvvv_2d2s = 1524,
+ AArch64_UMULLvvv_4s4h = 1525,
+ AArch64_UMULLvvv_8h8b = 1526,
+ AArch64_UQADDbbb = 1527,
+ AArch64_UQADDddd = 1528,
+ AArch64_UQADDhhh = 1529,
+ AArch64_UQADDsss = 1530,
+ AArch64_UQADDvvv_16B = 1531,
+ AArch64_UQADDvvv_2D = 1532,
+ AArch64_UQADDvvv_2S = 1533,
+ AArch64_UQADDvvv_4H = 1534,
+ AArch64_UQADDvvv_4S = 1535,
+ AArch64_UQADDvvv_8B = 1536,
+ AArch64_UQADDvvv_8H = 1537,
+ AArch64_UQRSHLbbb = 1538,
+ AArch64_UQRSHLddd = 1539,
+ AArch64_UQRSHLhhh = 1540,
+ AArch64_UQRSHLsss = 1541,
+ AArch64_UQRSHLvvv_16B = 1542,
+ AArch64_UQRSHLvvv_2D = 1543,
+ AArch64_UQRSHLvvv_2S = 1544,
+ AArch64_UQRSHLvvv_4H = 1545,
+ AArch64_UQRSHLvvv_4S = 1546,
+ AArch64_UQRSHLvvv_8B = 1547,
+ AArch64_UQRSHLvvv_8H = 1548,
+ AArch64_UQRSHRNvvi_16B = 1549,
+ AArch64_UQRSHRNvvi_2S = 1550,
+ AArch64_UQRSHRNvvi_4H = 1551,
+ AArch64_UQRSHRNvvi_4S = 1552,
+ AArch64_UQRSHRNvvi_8B = 1553,
+ AArch64_UQRSHRNvvi_8H = 1554,
+ AArch64_UQSHLbbb = 1555,
+ AArch64_UQSHLddd = 1556,
+ AArch64_UQSHLhhh = 1557,
+ AArch64_UQSHLsss = 1558,
+ AArch64_UQSHLvvi_16B = 1559,
+ AArch64_UQSHLvvi_2D = 1560,
+ AArch64_UQSHLvvi_2S = 1561,
+ AArch64_UQSHLvvi_4H = 1562,
+ AArch64_UQSHLvvi_4S = 1563,
+ AArch64_UQSHLvvi_8B = 1564,
+ AArch64_UQSHLvvi_8H = 1565,
+ AArch64_UQSHLvvv_16B = 1566,
+ AArch64_UQSHLvvv_2D = 1567,
+ AArch64_UQSHLvvv_2S = 1568,
+ AArch64_UQSHLvvv_4H = 1569,
+ AArch64_UQSHLvvv_4S = 1570,
+ AArch64_UQSHLvvv_8B = 1571,
+ AArch64_UQSHLvvv_8H = 1572,
+ AArch64_UQSHRNvvi_16B = 1573,
+ AArch64_UQSHRNvvi_2S = 1574,
+ AArch64_UQSHRNvvi_4H = 1575,
+ AArch64_UQSHRNvvi_4S = 1576,
+ AArch64_UQSHRNvvi_8B = 1577,
+ AArch64_UQSHRNvvi_8H = 1578,
+ AArch64_UQSUBbbb = 1579,
+ AArch64_UQSUBddd = 1580,
+ AArch64_UQSUBhhh = 1581,
+ AArch64_UQSUBsss = 1582,
+ AArch64_UQSUBvvv_16B = 1583,
+ AArch64_UQSUBvvv_2D = 1584,
+ AArch64_UQSUBvvv_2S = 1585,
+ AArch64_UQSUBvvv_4H = 1586,
+ AArch64_UQSUBvvv_4S = 1587,
+ AArch64_UQSUBvvv_8B = 1588,
+ AArch64_UQSUBvvv_8H = 1589,
+ AArch64_URHADDvvv_16B = 1590,
+ AArch64_URHADDvvv_2S = 1591,
+ AArch64_URHADDvvv_4H = 1592,
+ AArch64_URHADDvvv_4S = 1593,
+ AArch64_URHADDvvv_8B = 1594,
+ AArch64_URHADDvvv_8H = 1595,
+ AArch64_URSHLddd = 1596,
+ AArch64_URSHLvvv_16B = 1597,
+ AArch64_URSHLvvv_2D = 1598,
+ AArch64_URSHLvvv_2S = 1599,
+ AArch64_URSHLvvv_4H = 1600,
+ AArch64_URSHLvvv_4S = 1601,
+ AArch64_URSHLvvv_8B = 1602,
+ AArch64_URSHLvvv_8H = 1603,
+ AArch64_URSHRvvi_16B = 1604,
+ AArch64_URSHRvvi_2D = 1605,
+ AArch64_URSHRvvi_2S = 1606,
+ AArch64_URSHRvvi_4H = 1607,
+ AArch64_URSHRvvi_4S = 1608,
+ AArch64_URSHRvvi_8B = 1609,
+ AArch64_URSHRvvi_8H = 1610,
+ AArch64_URSRAvvi_16B = 1611,
+ AArch64_URSRAvvi_2D = 1612,
+ AArch64_URSRAvvi_2S = 1613,
+ AArch64_URSRAvvi_4H = 1614,
+ AArch64_URSRAvvi_4S = 1615,
+ AArch64_URSRAvvi_8B = 1616,
+ AArch64_URSRAvvi_8H = 1617,
+ AArch64_USHLLvvi_16B = 1618,
+ AArch64_USHLLvvi_2S = 1619,
+ AArch64_USHLLvvi_4H = 1620,
+ AArch64_USHLLvvi_4S = 1621,
+ AArch64_USHLLvvi_8B = 1622,
+ AArch64_USHLLvvi_8H = 1623,
+ AArch64_USHLddd = 1624,
+ AArch64_USHLvvv_16B = 1625,
+ AArch64_USHLvvv_2D = 1626,
+ AArch64_USHLvvv_2S = 1627,
+ AArch64_USHLvvv_4H = 1628,
+ AArch64_USHLvvv_4S = 1629,
+ AArch64_USHLvvv_8B = 1630,
+ AArch64_USHLvvv_8H = 1631,
+ AArch64_USHRvvi_16B = 1632,
+ AArch64_USHRvvi_2D = 1633,
+ AArch64_USHRvvi_2S = 1634,
+ AArch64_USHRvvi_4H = 1635,
+ AArch64_USHRvvi_4S = 1636,
+ AArch64_USHRvvi_8B = 1637,
+ AArch64_USHRvvi_8H = 1638,
+ AArch64_USRAvvi_16B = 1639,
+ AArch64_USRAvvi_2D = 1640,
+ AArch64_USRAvvi_2S = 1641,
+ AArch64_USRAvvi_4H = 1642,
+ AArch64_USRAvvi_4S = 1643,
+ AArch64_USRAvvi_8B = 1644,
+ AArch64_USRAvvi_8H = 1645,
+ AArch64_USUBL2vvv_2d4s = 1646,
+ AArch64_USUBL2vvv_4s8h = 1647,
+ AArch64_USUBL2vvv_8h16b = 1648,
+ AArch64_USUBLvvv_2d2s = 1649,
+ AArch64_USUBLvvv_4s4h = 1650,
+ AArch64_USUBLvvv_8h8b = 1651,
+ AArch64_USUBW2vvv_2d4s = 1652,
+ AArch64_USUBW2vvv_4s8h = 1653,
+ AArch64_USUBW2vvv_8h16b = 1654,
+ AArch64_USUBWvvv_2d2s = 1655,
+ AArch64_USUBWvvv_4s4h = 1656,
+ AArch64_USUBWvvv_8h8b = 1657,
+ AArch64_UXTBww = 1658,
+ AArch64_UXTBxw = 1659,
+ AArch64_UXTHww = 1660,
+ AArch64_UXTHxw = 1661,
+ AArch64_VCVTf2xs_2D = 1662,
+ AArch64_VCVTf2xs_2S = 1663,
+ AArch64_VCVTf2xs_4S = 1664,
+ AArch64_VCVTf2xu_2D = 1665,
+ AArch64_VCVTf2xu_2S = 1666,
+ AArch64_VCVTf2xu_4S = 1667,
+ AArch64_VCVTxs2f_2D = 1668,
+ AArch64_VCVTxs2f_2S = 1669,
+ AArch64_VCVTxs2f_4S = 1670,
+ AArch64_VCVTxu2f_2D = 1671,
+ AArch64_VCVTxu2f_2S = 1672,
+ AArch64_VCVTxu2f_4S = 1673,
+ AArch64_INSTRUCTION_LIST_END = 1674
+};
+
+#endif // GET_INSTRINFO_ENUM
diff --git a/arch/AArch64/AArch64GenRegisterInfo.inc b/arch/AArch64/AArch64GenRegisterInfo.inc
new file mode 100644
index 0000000..bf44030
--- /dev/null
+++ b/arch/AArch64/AArch64GenRegisterInfo.inc
@@ -0,0 +1,710 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+ AArch64_NoRegister,
+ AArch64_NZCV = 1,
+ AArch64_WSP = 2,
+ AArch64_WZR = 3,
+ AArch64_XSP = 4,
+ AArch64_XZR = 5,
+ AArch64_B0 = 6,
+ AArch64_B1 = 7,
+ AArch64_B2 = 8,
+ AArch64_B3 = 9,
+ AArch64_B4 = 10,
+ AArch64_B5 = 11,
+ AArch64_B6 = 12,
+ AArch64_B7 = 13,
+ AArch64_B8 = 14,
+ AArch64_B9 = 15,
+ AArch64_B10 = 16,
+ AArch64_B11 = 17,
+ AArch64_B12 = 18,
+ AArch64_B13 = 19,
+ AArch64_B14 = 20,
+ AArch64_B15 = 21,
+ AArch64_B16 = 22,
+ AArch64_B17 = 23,
+ AArch64_B18 = 24,
+ AArch64_B19 = 25,
+ AArch64_B20 = 26,
+ AArch64_B21 = 27,
+ AArch64_B22 = 28,
+ AArch64_B23 = 29,
+ AArch64_B24 = 30,
+ AArch64_B25 = 31,
+ AArch64_B26 = 32,
+ AArch64_B27 = 33,
+ AArch64_B28 = 34,
+ AArch64_B29 = 35,
+ AArch64_B30 = 36,
+ AArch64_B31 = 37,
+ AArch64_D0 = 38,
+ AArch64_D1 = 39,
+ AArch64_D2 = 40,
+ AArch64_D3 = 41,
+ AArch64_D4 = 42,
+ AArch64_D5 = 43,
+ AArch64_D6 = 44,
+ AArch64_D7 = 45,
+ AArch64_D8 = 46,
+ AArch64_D9 = 47,
+ AArch64_D10 = 48,
+ AArch64_D11 = 49,
+ AArch64_D12 = 50,
+ AArch64_D13 = 51,
+ AArch64_D14 = 52,
+ AArch64_D15 = 53,
+ AArch64_D16 = 54,
+ AArch64_D17 = 55,
+ AArch64_D18 = 56,
+ AArch64_D19 = 57,
+ AArch64_D20 = 58,
+ AArch64_D21 = 59,
+ AArch64_D22 = 60,
+ AArch64_D23 = 61,
+ AArch64_D24 = 62,
+ AArch64_D25 = 63,
+ AArch64_D26 = 64,
+ AArch64_D27 = 65,
+ AArch64_D28 = 66,
+ AArch64_D29 = 67,
+ AArch64_D30 = 68,
+ AArch64_D31 = 69,
+ AArch64_H0 = 70,
+ AArch64_H1 = 71,
+ AArch64_H2 = 72,
+ AArch64_H3 = 73,
+ AArch64_H4 = 74,
+ AArch64_H5 = 75,
+ AArch64_H6 = 76,
+ AArch64_H7 = 77,
+ AArch64_H8 = 78,
+ AArch64_H9 = 79,
+ AArch64_H10 = 80,
+ AArch64_H11 = 81,
+ AArch64_H12 = 82,
+ AArch64_H13 = 83,
+ AArch64_H14 = 84,
+ AArch64_H15 = 85,
+ AArch64_H16 = 86,
+ AArch64_H17 = 87,
+ AArch64_H18 = 88,
+ AArch64_H19 = 89,
+ AArch64_H20 = 90,
+ AArch64_H21 = 91,
+ AArch64_H22 = 92,
+ AArch64_H23 = 93,
+ AArch64_H24 = 94,
+ AArch64_H25 = 95,
+ AArch64_H26 = 96,
+ AArch64_H27 = 97,
+ AArch64_H28 = 98,
+ AArch64_H29 = 99,
+ AArch64_H30 = 100,
+ AArch64_H31 = 101,
+ AArch64_Q0 = 102,
+ AArch64_Q1 = 103,
+ AArch64_Q2 = 104,
+ AArch64_Q3 = 105,
+ AArch64_Q4 = 106,
+ AArch64_Q5 = 107,
+ AArch64_Q6 = 108,
+ AArch64_Q7 = 109,
+ AArch64_Q8 = 110,
+ AArch64_Q9 = 111,
+ AArch64_Q10 = 112,
+ AArch64_Q11 = 113,
+ AArch64_Q12 = 114,
+ AArch64_Q13 = 115,
+ AArch64_Q14 = 116,
+ AArch64_Q15 = 117,
+ AArch64_Q16 = 118,
+ AArch64_Q17 = 119,
+ AArch64_Q18 = 120,
+ AArch64_Q19 = 121,
+ AArch64_Q20 = 122,
+ AArch64_Q21 = 123,
+ AArch64_Q22 = 124,
+ AArch64_Q23 = 125,
+ AArch64_Q24 = 126,
+ AArch64_Q25 = 127,
+ AArch64_Q26 = 128,
+ AArch64_Q27 = 129,
+ AArch64_Q28 = 130,
+ AArch64_Q29 = 131,
+ AArch64_Q30 = 132,
+ AArch64_Q31 = 133,
+ AArch64_S0 = 134,
+ AArch64_S1 = 135,
+ AArch64_S2 = 136,
+ AArch64_S3 = 137,
+ AArch64_S4 = 138,
+ AArch64_S5 = 139,
+ AArch64_S6 = 140,
+ AArch64_S7 = 141,
+ AArch64_S8 = 142,
+ AArch64_S9 = 143,
+ AArch64_S10 = 144,
+ AArch64_S11 = 145,
+ AArch64_S12 = 146,
+ AArch64_S13 = 147,
+ AArch64_S14 = 148,
+ AArch64_S15 = 149,
+ AArch64_S16 = 150,
+ AArch64_S17 = 151,
+ AArch64_S18 = 152,
+ AArch64_S19 = 153,
+ AArch64_S20 = 154,
+ AArch64_S21 = 155,
+ AArch64_S22 = 156,
+ AArch64_S23 = 157,
+ AArch64_S24 = 158,
+ AArch64_S25 = 159,
+ AArch64_S26 = 160,
+ AArch64_S27 = 161,
+ AArch64_S28 = 162,
+ AArch64_S29 = 163,
+ AArch64_S30 = 164,
+ AArch64_S31 = 165,
+ AArch64_W0 = 166,
+ AArch64_W1 = 167,
+ AArch64_W2 = 168,
+ AArch64_W3 = 169,
+ AArch64_W4 = 170,
+ AArch64_W5 = 171,
+ AArch64_W6 = 172,
+ AArch64_W7 = 173,
+ AArch64_W8 = 174,
+ AArch64_W9 = 175,
+ AArch64_W10 = 176,
+ AArch64_W11 = 177,
+ AArch64_W12 = 178,
+ AArch64_W13 = 179,
+ AArch64_W14 = 180,
+ AArch64_W15 = 181,
+ AArch64_W16 = 182,
+ AArch64_W17 = 183,
+ AArch64_W18 = 184,
+ AArch64_W19 = 185,
+ AArch64_W20 = 186,
+ AArch64_W21 = 187,
+ AArch64_W22 = 188,
+ AArch64_W23 = 189,
+ AArch64_W24 = 190,
+ AArch64_W25 = 191,
+ AArch64_W26 = 192,
+ AArch64_W27 = 193,
+ AArch64_W28 = 194,
+ AArch64_W29 = 195,
+ AArch64_W30 = 196,
+ AArch64_X0 = 197,
+ AArch64_X1 = 198,
+ AArch64_X2 = 199,
+ AArch64_X3 = 200,
+ AArch64_X4 = 201,
+ AArch64_X5 = 202,
+ AArch64_X6 = 203,
+ AArch64_X7 = 204,
+ AArch64_X8 = 205,
+ AArch64_X9 = 206,
+ AArch64_X10 = 207,
+ AArch64_X11 = 208,
+ AArch64_X12 = 209,
+ AArch64_X13 = 210,
+ AArch64_X14 = 211,
+ AArch64_X15 = 212,
+ AArch64_X16 = 213,
+ AArch64_X17 = 214,
+ AArch64_X18 = 215,
+ AArch64_X19 = 216,
+ AArch64_X20 = 217,
+ AArch64_X21 = 218,
+ AArch64_X22 = 219,
+ AArch64_X23 = 220,
+ AArch64_X24 = 221,
+ AArch64_X25 = 222,
+ AArch64_X26 = 223,
+ AArch64_X27 = 224,
+ AArch64_X28 = 225,
+ AArch64_X29 = 226,
+ AArch64_X30 = 227,
+ AArch64_NUM_TARGET_REGS // 228
+};
+
+// Register classes
+enum {
+ AArch64_FPR8RegClassID = 0,
+ AArch64_FPR16RegClassID = 1,
+ AArch64_FPR32RegClassID = 2,
+ AArch64_GPR32RegClassID = 3,
+ AArch64_GPR32wspRegClassID = 4,
+ AArch64_GPR32nowzrRegClassID = 5,
+ AArch64_FlagClassRegClassID = 6,
+ AArch64_RwspRegClassID = 7,
+ AArch64_FPR64RegClassID = 8,
+ AArch64_GPR64RegClassID = 9,
+ AArch64_GPR64xspRegClassID = 10,
+ AArch64_GPR64noxzrRegClassID = 11,
+ AArch64_tcGPR64RegClassID = 12,
+ AArch64_RxspRegClassID = 13,
+ AArch64_FPR128RegClassID = 14
+};
+
+// Subregister indices
+enum {
+ AArch64_NoSubRegister,
+ AArch64_sub_8, // 1
+ AArch64_sub_16, // 2
+ AArch64_sub_32, // 3
+ AArch64_sub_64, // 4
+ AArch64_sub_128, // 5
+ AArch64_NUM_TARGET_SUBREGS
+};
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static MCPhysReg AArch64RegDiffLists[] = {
+ /* 0 */ 2, 0,
+ /* 2 */ 31, 0,
+ /* 4 */ 64, 64, 65440, 64, 0,
+ /* 9 */ 65374, 0,
+ /* 11 */ 65405, 0,
+ /* 13 */ 65437, 0,
+ /* 15 */ 65469, 0,
+ /* 17 */ 65472, 96, 65472, 65472, 0,
+ /* 22 */ 65501, 0,
+ /* 24 */ 65505, 0,
+ /* 26 */ 65533, 0,
+ /* 28 */ 65534, 0,
+ /* 30 */ 65535, 0,
+};
+
+static uint16_t AArch64SubRegIdxLists[] = {
+ /* 0 */ 4, 3, 2, 1, 0,
+ /* 5 */ 3, 0,
+};
+
+static MCRegisterDesc AArch64RegDesc[] = { // Descriptors
+ { 3, 0, 0, 0, 0 },
+ { 834, 1, 1, 4, 481 },
+ { 818, 1, 0, 4, 481 },
+ { 826, 1, 0, 4, 481 },
+ { 822, 28, 1, 5, 417 },
+ { 830, 28, 1, 5, 417 },
+ { 84, 1, 4, 4, 417 },
+ { 181, 1, 4, 4, 417 },
+ { 258, 1, 4, 4, 417 },
+ { 335, 1, 4, 4, 417 },
+ { 412, 1, 4, 4, 417 },
+ { 489, 1, 4, 4, 417 },
+ { 566, 1, 4, 4, 417 },
+ { 643, 1, 4, 4, 417 },
+ { 720, 1, 4, 4, 417 },
+ { 797, 1, 4, 4, 417 },
+ { 0, 1, 4, 4, 417 },
+ { 105, 1, 4, 4, 417 },
+ { 202, 1, 4, 4, 417 },
+ { 279, 1, 4, 4, 417 },
+ { 356, 1, 4, 4, 417 },
+ { 433, 1, 4, 4, 417 },
+ { 510, 1, 4, 4, 417 },
+ { 587, 1, 4, 4, 417 },
+ { 664, 1, 4, 4, 417 },
+ { 741, 1, 4, 4, 417 },
+ { 28, 1, 4, 4, 417 },
+ { 133, 1, 4, 4, 417 },
+ { 230, 1, 4, 4, 417 },
+ { 307, 1, 4, 4, 417 },
+ { 384, 1, 4, 4, 417 },
+ { 461, 1, 4, 4, 417 },
+ { 538, 1, 4, 4, 417 },
+ { 615, 1, 4, 4, 417 },
+ { 692, 1, 4, 4, 417 },
+ { 769, 1, 4, 4, 417 },
+ { 56, 1, 4, 4, 417 },
+ { 161, 1, 4, 4, 417 },
+ { 87, 18, 7, 1, 353 },
+ { 184, 18, 7, 1, 353 },
+ { 261, 18, 7, 1, 353 },
+ { 338, 18, 7, 1, 353 },
+ { 415, 18, 7, 1, 353 },
+ { 492, 18, 7, 1, 353 },
+ { 569, 18, 7, 1, 353 },
+ { 646, 18, 7, 1, 353 },
+ { 723, 18, 7, 1, 353 },
+ { 800, 18, 7, 1, 353 },
+ { 4, 18, 7, 1, 353 },
+ { 109, 18, 7, 1, 353 },
+ { 206, 18, 7, 1, 353 },
+ { 283, 18, 7, 1, 353 },
+ { 360, 18, 7, 1, 353 },
+ { 437, 18, 7, 1, 353 },
+ { 514, 18, 7, 1, 353 },
+ { 591, 18, 7, 1, 353 },
+ { 668, 18, 7, 1, 353 },
+ { 745, 18, 7, 1, 353 },
+ { 32, 18, 7, 1, 353 },
+ { 137, 18, 7, 1, 353 },
+ { 234, 18, 7, 1, 353 },
+ { 311, 18, 7, 1, 353 },
+ { 388, 18, 7, 1, 353 },
+ { 465, 18, 7, 1, 353 },
+ { 542, 18, 7, 1, 353 },
+ { 619, 18, 7, 1, 353 },
+ { 696, 18, 7, 1, 353 },
+ { 773, 18, 7, 1, 353 },
+ { 60, 18, 7, 1, 353 },
+ { 165, 18, 7, 1, 353 },
+ { 90, 20, 5, 3, 241 },
+ { 187, 20, 5, 3, 241 },
+ { 264, 20, 5, 3, 241 },
+ { 341, 20, 5, 3, 241 },
+ { 418, 20, 5, 3, 241 },
+ { 495, 20, 5, 3, 241 },
+ { 572, 20, 5, 3, 241 },
+ { 649, 20, 5, 3, 241 },
+ { 726, 20, 5, 3, 241 },
+ { 803, 20, 5, 3, 241 },
+ { 8, 20, 5, 3, 241 },
+ { 113, 20, 5, 3, 241 },
+ { 210, 20, 5, 3, 241 },
+ { 287, 20, 5, 3, 241 },
+ { 364, 20, 5, 3, 241 },
+ { 441, 20, 5, 3, 241 },
+ { 518, 20, 5, 3, 241 },
+ { 595, 20, 5, 3, 241 },
+ { 672, 20, 5, 3, 241 },
+ { 749, 20, 5, 3, 241 },
+ { 36, 20, 5, 3, 241 },
+ { 141, 20, 5, 3, 241 },
+ { 238, 20, 5, 3, 241 },
+ { 315, 20, 5, 3, 241 },
+ { 392, 20, 5, 3, 241 },
+ { 469, 20, 5, 3, 241 },
+ { 546, 20, 5, 3, 241 },
+ { 623, 20, 5, 3, 241 },
+ { 700, 20, 5, 3, 241 },
+ { 777, 20, 5, 3, 241 },
+ { 64, 20, 5, 3, 241 },
+ { 169, 20, 5, 3, 241 },
+ { 93, 17, 1, 0, 209 },
+ { 190, 17, 1, 0, 209 },
+ { 267, 17, 1, 0, 209 },
+ { 344, 17, 1, 0, 209 },
+ { 421, 17, 1, 0, 209 },
+ { 498, 17, 1, 0, 209 },
+ { 575, 17, 1, 0, 209 },
+ { 652, 17, 1, 0, 209 },
+ { 729, 17, 1, 0, 209 },
+ { 806, 17, 1, 0, 209 },
+ { 12, 17, 1, 0, 209 },
+ { 117, 17, 1, 0, 209 },
+ { 214, 17, 1, 0, 209 },
+ { 291, 17, 1, 0, 209 },
+ { 368, 17, 1, 0, 209 },
+ { 445, 17, 1, 0, 209 },
+ { 522, 17, 1, 0, 209 },
+ { 599, 17, 1, 0, 209 },
+ { 676, 17, 1, 0, 209 },
+ { 753, 17, 1, 0, 209 },
+ { 40, 17, 1, 0, 209 },
+ { 145, 17, 1, 0, 209 },
+ { 242, 17, 1, 0, 209 },
+ { 319, 17, 1, 0, 209 },
+ { 396, 17, 1, 0, 209 },
+ { 473, 17, 1, 0, 209 },
+ { 550, 17, 1, 0, 209 },
+ { 627, 17, 1, 0, 209 },
+ { 704, 17, 1, 0, 209 },
+ { 781, 17, 1, 0, 209 },
+ { 68, 17, 1, 0, 209 },
+ { 173, 17, 1, 0, 209 },
+ { 96, 19, 6, 2, 177 },
+ { 193, 19, 6, 2, 177 },
+ { 270, 19, 6, 2, 177 },
+ { 347, 19, 6, 2, 177 },
+ { 424, 19, 6, 2, 177 },
+ { 501, 19, 6, 2, 177 },
+ { 578, 19, 6, 2, 177 },
+ { 655, 19, 6, 2, 177 },
+ { 732, 19, 6, 2, 177 },
+ { 809, 19, 6, 2, 177 },
+ { 16, 19, 6, 2, 177 },
+ { 121, 19, 6, 2, 177 },
+ { 218, 19, 6, 2, 177 },
+ { 295, 19, 6, 2, 177 },
+ { 372, 19, 6, 2, 177 },
+ { 449, 19, 6, 2, 177 },
+ { 526, 19, 6, 2, 177 },
+ { 603, 19, 6, 2, 177 },
+ { 680, 19, 6, 2, 177 },
+ { 757, 19, 6, 2, 177 },
+ { 44, 19, 6, 2, 177 },
+ { 149, 19, 6, 2, 177 },
+ { 246, 19, 6, 2, 177 },
+ { 323, 19, 6, 2, 177 },
+ { 400, 19, 6, 2, 177 },
+ { 477, 19, 6, 2, 177 },
+ { 554, 19, 6, 2, 177 },
+ { 631, 19, 6, 2, 177 },
+ { 708, 19, 6, 2, 177 },
+ { 785, 19, 6, 2, 177 },
+ { 72, 19, 6, 2, 177 },
+ { 177, 19, 6, 2, 177 },
+ { 99, 1, 2, 4, 177 },
+ { 196, 1, 2, 4, 177 },
+ { 273, 1, 2, 4, 177 },
+ { 350, 1, 2, 4, 177 },
+ { 427, 1, 2, 4, 177 },
+ { 504, 1, 2, 4, 177 },
+ { 581, 1, 2, 4, 177 },
+ { 658, 1, 2, 4, 177 },
+ { 735, 1, 2, 4, 177 },
+ { 812, 1, 2, 4, 177 },
+ { 20, 1, 2, 4, 177 },
+ { 125, 1, 2, 4, 177 },
+ { 222, 1, 2, 4, 177 },
+ { 299, 1, 2, 4, 177 },
+ { 376, 1, 2, 4, 177 },
+ { 453, 1, 2, 4, 177 },
+ { 530, 1, 2, 4, 177 },
+ { 607, 1, 2, 4, 177 },
+ { 684, 1, 2, 4, 177 },
+ { 761, 1, 2, 4, 177 },
+ { 48, 1, 2, 4, 177 },
+ { 153, 1, 2, 4, 177 },
+ { 250, 1, 2, 4, 177 },
+ { 327, 1, 2, 4, 177 },
+ { 404, 1, 2, 4, 177 },
+ { 481, 1, 2, 4, 177 },
+ { 558, 1, 2, 4, 177 },
+ { 635, 1, 2, 4, 177 },
+ { 712, 1, 2, 4, 177 },
+ { 789, 1, 2, 4, 177 },
+ { 76, 1, 2, 4, 177 },
+ { 102, 24, 1, 5, 145 },
+ { 199, 24, 1, 5, 145 },
+ { 276, 24, 1, 5, 145 },
+ { 353, 24, 1, 5, 145 },
+ { 430, 24, 1, 5, 145 },
+ { 507, 24, 1, 5, 145 },
+ { 584, 24, 1, 5, 145 },
+ { 661, 24, 1, 5, 145 },
+ { 738, 24, 1, 5, 145 },
+ { 815, 24, 1, 5, 145 },
+ { 24, 24, 1, 5, 145 },
+ { 129, 24, 1, 5, 145 },
+ { 226, 24, 1, 5, 145 },
+ { 303, 24, 1, 5, 145 },
+ { 380, 24, 1, 5, 145 },
+ { 457, 24, 1, 5, 145 },
+ { 534, 24, 1, 5, 145 },
+ { 611, 24, 1, 5, 145 },
+ { 688, 24, 1, 5, 145 },
+ { 765, 24, 1, 5, 145 },
+ { 52, 24, 1, 5, 145 },
+ { 157, 24, 1, 5, 145 },
+ { 254, 24, 1, 5, 145 },
+ { 331, 24, 1, 5, 145 },
+ { 408, 24, 1, 5, 145 },
+ { 485, 24, 1, 5, 145 },
+ { 562, 24, 1, 5, 145 },
+ { 639, 24, 1, 5, 145 },
+ { 716, 24, 1, 5, 145 },
+ { 793, 24, 1, 5, 145 },
+ { 80, 24, 1, 5, 145 },
+};
+
+// FPR8 Register Class...
+static uint16_t FPR8[] = {
+ AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31,
+};
+
+ // FPR8 Bit set.
+static uint8_t FPR8Bits[] = {
+ 0xc0, 0xff, 0xff, 0xff, 0x3f,
+};
+
+ // FPR16 Register Class...
+static uint16_t FPR16[] = {
+ AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31,
+};
+
+// FPR16 Bit set.
+static uint8_t FPR16Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
+};
+
+// FPR32 Register Class...
+static uint16_t FPR32[] = {
+ AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31,
+ };
+
+// FPR32 Bit set.
+static uint8_t FPR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
+};
+
+// GPR32 Register Class...
+static uint16_t GPR32[] = {
+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR,
+};
+
+// GPR32 Bit set.
+static uint8_t GPR32Bits[] = {
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
+};
+
+// GPR32wsp Register Class...
+static uint16_t GPR32wsp[] = {
+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP,
+};
+
+// GPR32wsp Bit set.
+static uint8_t GPR32wspBits[] = {
+ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
+};
+
+// GPR32nowzr Register Class...
+static uint16_t GPR32nowzr[] = {
+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30,
+};
+
+// GPR32nowzr Bit set.
+static uint8_t GPR32nowzrBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
+};
+
+// FlagClass Register Class...
+static uint16_t FlagClass[] = {
+ AArch64_NZCV,
+};
+
+// FlagClass Bit set.
+static uint8_t FlagClassBits[] = {
+ 0x02,
+};
+
+// Rwsp Register Class...
+static uint16_t Rwsp[] = {
+ AArch64_WSP,
+};
+
+// Rwsp Bit set.
+static uint8_t RwspBits[] = {
+ 0x04,
+};
+
+// FPR64 Register Class...
+static uint16_t FPR64[] = {
+ AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31,
+};
+
+// FPR64 Bit set.
+static uint8_t FPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
+};
+
+// GPR64 Register Class...
+static uint16_t GPR64[] = {
+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_X29, AArch64_X30, AArch64_XZR,
+};
+
+// GPR64 Bit set.
+static uint8_t GPR64Bits[] = {
+ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f,
+};
+
+// GPR64xsp Register Class...
+static uint16_t GPR64xsp[] = {
+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_X29, AArch64_X30, AArch64_XSP,
+};
+
+// GPR64xsp Bit set.
+static uint8_t GPR64xspBits[] = {
+ 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f,
+};
+
+// GPR64noxzr Register Class...
+static uint16_t GPR64noxzr[] = {
+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_X29, AArch64_X30,
+};
+
+// GPR64noxzr Bit set.
+static uint8_t GPR64noxzrBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f,
+};
+
+// tcGPR64 Register Class...
+static uint16_t tcGPR64[] = {
+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18,
+};
+
+// tcGPR64 Bit set.
+static uint8_t tcGPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xdf, 0xff,
+};
+
+// Rxsp Register Class...
+static uint16_t Rxsp[] = {
+ AArch64_XSP,
+};
+
+// Rxsp Bit set.
+static uint8_t RxspBits[] = {
+ 0x10,
+};
+
+// FPR128 Register Class...
+static uint16_t FPR128[] = {
+ AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31,
+};
+
+// FPR128 Bit set.
+static uint8_t FPR128Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
+};
+
+static MCRegisterClass AArch64MCRegisterClasses[] = {
+ { "FPR8", FPR8, FPR8Bits, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 },
+ { "FPR16", FPR16, FPR16Bits, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 },
+ { "FPR32", FPR32, FPR32Bits, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 },
+ { "GPR32", GPR32, GPR32Bits, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 },
+ { "GPR32wsp", GPR32wsp, GPR32wspBits, 32, sizeof(GPR32wspBits), AArch64_GPR32wspRegClassID, 4, 4, 1, 1 },
+ { "GPR32nowzr", GPR32nowzr, GPR32nowzrBits, 31, sizeof(GPR32nowzrBits), AArch64_GPR32nowzrRegClassID, 4, 4, 1, 1 },
+ { "FlagClass", FlagClass, FlagClassBits, 1, sizeof(FlagClassBits), AArch64_FlagClassRegClassID, 4, 4, -1, 0 },
+ { "Rwsp", Rwsp, RwspBits, 1, sizeof(RwspBits), AArch64_RwspRegClassID, 4, 4, 1, 1 },
+ { "FPR64", FPR64, FPR64Bits, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 },
+ { "GPR64", GPR64, GPR64Bits, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 },
+ { "GPR64xsp", GPR64xsp, GPR64xspBits, 32, sizeof(GPR64xspBits), AArch64_GPR64xspRegClassID, 8, 8, 1, 1 },
+ { "GPR64noxzr", GPR64noxzr, GPR64noxzrBits, 31, sizeof(GPR64noxzrBits), AArch64_GPR64noxzrRegClassID, 8, 8, 1, 1 },
+ { "tcGPR64", tcGPR64, tcGPR64Bits, 18, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 },
+ { "Rxsp", Rxsp, RxspBits, 1, sizeof(RxspBits), AArch64_RxspRegClassID, 8, 8, 1, 1 },
+ { "FPR128", FPR128, FPR128Bits, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 },
+};
+
+#endif // GET_REGINFO_MC_DESC
diff --git a/arch/AArch64/AArch64GenSubtargetInfo.inc b/arch/AArch64/AArch64GenSubtargetInfo.inc
new file mode 100644
index 0000000..858ff92
--- /dev/null
+++ b/arch/AArch64/AArch64GenSubtargetInfo.inc
@@ -0,0 +1,30 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Subtarget Enumeration Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+enum {
+ AArch64_FeatureCrypto = 1ULL << 0,
+ AArch64_FeatureNEON = 1ULL << 1
+};
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+#ifdef GET_SUBTARGETINFO_MC_DESC
+#undef GET_SUBTARGETINFO_MC_DESC
+
+// Sorted (by key) array of values for CPU features.
+static SubtargetFeatureKV AArch64FeatureKV[] = {
+ { "crypto", "Enable cryptographic instructions", AArch64_FeatureCrypto, 0ULL },
+ { "neon", "Enable Advanced SIMD instructions", AArch64_FeatureNEON, 0ULL }
+};
+
+#endif // GET_SUBTARGETINFO_MC_DESC
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
new file mode 100644
index 0000000..1cfddfc
--- /dev/null
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -0,0 +1,647 @@
+//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <inttypes.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "AArch64InstPrinter.h"
+#include "AArch64BaseInfo.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../utils.h"
+
+#include "mapping.h"
+
+static char *getRegisterName(unsigned RegNo);
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+
+// FIXME: make this status session's specific, not global like this
+static bool doing_mem = false;
+static void set_mem_access(MCInst *MI, bool status)
+{
+ doing_mem = status;
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_MEM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.base = ARM64_REG_INVALID;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.index = ARM64_REG_INVALID;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.disp = 0;
+ } else {
+ // done, create the next operand slot
+ MI->pub_insn.arm64.op_count++;
+ }
+}
+
+static int64_t unpackSignedImm(int BitWidth, uint64_t Value)
+{
+ //assert(!(Value & ~((1ULL << BitWidth)-1)) && "immediate not n-bit");
+ if (Value & (1ULL << (BitWidth - 1)))
+ return (int64_t)Value - (1LL << BitWidth);
+ else
+ return Value;
+}
+
+static void printOffsetSImm9Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
+ int32_t Imm = unpackSignedImm(9, MCOperand_getImm(MOImm));
+
+ SStream_concat(O, "#0x%x", Imm);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, unsigned MemSize, unsigned RmSize)
+{
+ unsigned ExtImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned OptionHi = ExtImm >> 1;
+ unsigned S = ExtImm & 1;
+ bool IsLSL = OptionHi == 1 && RmSize == 64;
+
+ char *Ext = 0;
+ switch (OptionHi) {
+ case 1:
+ if (RmSize == 32) {
+ Ext = "uxtw";
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].ext = ARM64_EXT_UXTW;
+ } else {
+ Ext = "lsl";
+ }
+ break;
+ case 3:
+ if (RmSize == 32) {
+ Ext = "sxtw";
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTW;
+ } else {
+ Ext = "sxtx";
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTX;
+ }
+ break;
+ default:
+ break; //llvm_unreachable("Incorrect Option on load/store (reg offset)");
+ }
+ SStream_concat(O, Ext);
+
+ if (S) {
+ unsigned ShiftAmt = Log2_32(MemSize);
+ SStream_concat(O, " #0x%x", ShiftAmt);
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].shift.value = ShiftAmt;
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = ShiftAmt;
+ }
+ } else if (IsLSL) {
+ SStream_concat(O, " #0");
+ }
+}
+
+static void printAddSubImmLSL0Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *Imm12Op = MCInst_getOperand(MI, OpNum);
+
+ if (MCOperand_isImm(Imm12Op)) {
+ int64_t Imm12 = MCOperand_getImm(Imm12Op);
+ //assert(Imm12 >= 0 && "Invalid immediate for add/sub imm");
+ SStream_concat(O, "#0x%"PRIx64, Imm12);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm12;
+ MI->pub_insn.arm64.op_count++;
+ }
+}
+
+static void printAddSubImmLSL12Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ printAddSubImmLSL0Operand(MI, OpNum, O);
+
+ SStream_concat(O, ", lsl #12");
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = 12;
+}
+
+static void printBareImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ SStream_concat(O, "0x%"PRIx64, MCOperand_getImm(MO));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = MCOperand_getImm(MO);
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printBFILSBOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, unsigned RegWidth)
+{
+ MCOperand *ImmROp = MCInst_getOperand(MI, OpNum);
+ unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - MCOperand_getImm(ImmROp);
+
+ SStream_concat(O, "#0x%x", LSB);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = LSB;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printBFIWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
+ unsigned Width = MCOperand_getImm(ImmSOp) + 1;
+
+ SStream_concat(O, "#0x%x", Width);
+}
+
+static void printBFXWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
+ MCOperand *ImmROp = MCInst_getOperand(MI, OpNum - 1);
+
+ unsigned ImmR = MCOperand_getImm(ImmROp);
+ unsigned ImmS = MCOperand_getImm(ImmSOp);
+
+ //assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
+
+ SStream_concat(O, "#0x%x", (ImmS - ImmR + 1));
+
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = ImmS - ImmR + 1;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printCRxOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *CRx = MCInst_getOperand(MI, OpNum);
+ SStream_concat(O, "c%"PRIu64, MCOperand_getImm(CRx));
+
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_CIMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = MCOperand_getImm(CRx);
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printCVTFixedPosOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *ScaleOp = MCInst_getOperand(MI, OpNum);
+
+ SStream_concat(O, "#0x%"PRIx64, (64 - MCOperand_getImm(ScaleOp)));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = 64 - MCOperand_getImm(ScaleOp);
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MOImm8 = MCInst_getOperand(MI, OpNum);
+
+ //assert(MOImm8.isImm()
+ // && "Immediate operand required for floating-point immediate inst");
+
+ uint32_t Imm8 = MCOperand_getImm(MOImm8);
+ uint32_t Fraction = Imm8 & 0xf;
+ uint32_t Exponent = (Imm8 >> 4) & 0x7;
+ uint32_t Negative = (Imm8 >> 7) & 0x1;
+
+ float Val = 1.0f + Fraction / 16.0f;
+
+ // That is:
+ // 000 -> 2^1, 001 -> 2^2, 010 -> 2^3, 011 -> 2^4,
+ // 100 -> 2^-3, 101 -> 2^-2, 110 -> 2^-1, 111 -> 2^0
+ if (Exponent & 0x4) {
+ Val /= 1 << (7 - Exponent);
+ } else {
+ Val *= 1 << (Exponent + 1);
+ }
+
+ Val = Negative ? -Val : Val;
+
+ //o << '#' << format("%.8f", Val);
+ SStream_concat(O, "#%.8f", Val);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_FP;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].fp = Val;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printFPZeroOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ SStream_concat(O, "#0.0");
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_FP;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].fp = 0;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printCondCodeOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ SStream_concat(O, A64CondCodeToString((A64CC_CondCodes)(MCOperand_getImm(MO))));
+ MI->pub_insn.arm64.cc = MCOperand_getImm(MO) + 1;
+}
+
+static void printLabelOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, unsigned field_width, unsigned scale)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+ if (!MCOperand_isImm(MO)) {
+ printOperand(MI, OpNum, O);
+ return;
+ }
+
+ // The immediate of LDR (lit) instructions is a signed 19-bit immediate, which
+ // is multiplied by 4 (because all A64 instructions are 32-bits wide).
+ uint64_t UImm = MCOperand_getImm(MO);
+ uint64_t Sign = UImm & (1LL << (field_width - 1));
+ int64_t SImm = scale * ((UImm & ~Sign) - Sign);
+
+ // this is a relative address, so add with the offset
+ // of current instruction
+ SImm += MI->pub_insn.address;
+
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = SImm;
+ MI->pub_insn.arm64.op_count++;
+
+ SStream_concat(O, "#0x%"PRIx64, SImm);
+}
+
+static void printLogicalImmOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, unsigned RegWidth)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ uint64_t Val;
+ A64Imms_isLogicalImmBits(RegWidth, MCOperand_getImm(MO), &Val);
+ SStream_concat(O, "#0x%"PRIx64, Val);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Val;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printOffsetUImm12Operand(MCInst *MI, unsigned OpNum,
+ SStream *O, int MemSize)
+{
+ MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
+
+ if (MCOperand_isImm(MOImm)) {
+ uint32_t Imm = MCOperand_getImm(MOImm) * MemSize;
+
+ SStream_concat(O, "#0x%x", Imm);
+
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.disp = Imm;
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm;
+ MI->pub_insn.arm64.op_count++;
+ }
+ }
+}
+
+static void printShiftOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, A64SE_ShiftExtSpecifiers Shift)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+ // LSL #0 is not printed
+ if (Shift == A64SE_LSL && MCOperand_isImm(MO) && MCOperand_getImm(MO) == 0)
+ return;
+
+ switch (Shift) {
+ case A64SE_LSL: SStream_concat(O, "lsl"); break;
+ case A64SE_LSR: SStream_concat(O, "lsr"); break;
+ case A64SE_ASR: SStream_concat(O, "asr"); break;
+ case A64SE_ROR: SStream_concat(O, "ror"); break;
+ default: break; // llvm_unreachable("Invalid shift specifier in logical instruction");
+ }
+
+ SStream_concat(O, " #0x%"PRIx64, MCOperand_getImm(MO));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = Shift + 1;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = MCOperand_getImm(MO);
+}
+
+static void printMoveWideImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *UImm16MO = MCInst_getOperand(MI, OpNum);
+ MCOperand *ShiftMO = MCInst_getOperand(MI, OpNum + 1);
+
+ if (MCOperand_isImm(UImm16MO)) {
+ SStream_concat(O, "#0x%"PRIx64, MCOperand_getImm(UImm16MO));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = MCOperand_getImm(UImm16MO);
+ MI->pub_insn.arm64.op_count++;
+
+ if (MCOperand_getImm(ShiftMO) != 0) {
+ SStream_concat(O, ", lsl #0x%"PRIx64, (MCOperand_getImm(ShiftMO) * 16));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = MCOperand_getImm(ShiftMO) * 16;
+ }
+
+ return;
+ }
+}
+
+static void printNamedImmOperand(NamedImmMapper *Mapper,
+ MCInst *MI, unsigned OpNum, SStream *O)
+{
+ bool ValidName;
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ char *Name = NamedImmMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName);
+
+ if (ValidName)
+ SStream_concat(O, Name);
+ else
+ SStream_concat(O, "#0x%"PRIx64, MCOperand_getImm(MO));
+
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = MCOperand_getImm(MO);
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printSysRegOperand(SysRegMapper *Mapper,
+ MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+ bool ValidName;
+ char *Name = SysRegMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName);
+ if (ValidName) {
+ SStream_concat(O, Name);
+ }
+ free(Name);
+}
+
+#define GET_REGINFO_ENUM
+#include "AArch64GenRegisterInfo.inc"
+
+static inline bool isStackReg(unsigned RegNo)
+{
+ return RegNo == AArch64_XSP || RegNo == AArch64_WSP;
+}
+
+static void printRegExtendOperand(MCInst *MI, unsigned OpNum, SStream *O,
+ A64SE_ShiftExtSpecifiers Ext)
+{
+ // FIXME: In principle TableGen should be able to detect this itself far more
+ // easily. We will only accumulate more of these hacks.
+ unsigned Reg0 = MCOperand_getReg(MCInst_getOperand(MI, 0));
+ unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
+
+ if (isStackReg(Reg0) || isStackReg(Reg1)) {
+ A64SE_ShiftExtSpecifiers LSLEquiv;
+
+ if (Reg0 == AArch64_XSP || Reg1 == AArch64_XSP)
+ LSLEquiv = A64SE_UXTX;
+ else
+ LSLEquiv = A64SE_UXTW;
+
+ if (Ext == LSLEquiv) {
+ SStream_concat(O, "lsl #0x%"PRIx64, MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].ext = Ext - 4;
+ return;
+ }
+ }
+
+ switch (Ext) {
+ case A64SE_UXTB: SStream_concat(O, "uxtb"); break;
+ case A64SE_UXTH: SStream_concat(O, "uxth"); break;
+ case A64SE_UXTW: SStream_concat(O, "uxtw"); break;
+ case A64SE_UXTX: SStream_concat(O, "uxtx"); break;
+ case A64SE_SXTB: SStream_concat(O, "sxtb"); break;
+ case A64SE_SXTH: SStream_concat(O, "sxth"); break;
+ case A64SE_SXTW: SStream_concat(O, "sxtw"); break;
+ case A64SE_SXTX: SStream_concat(O, "sxtx"); break;
+ default: break; //llvm_unreachable("Unexpected shift type for printing");
+ }
+
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].ext = Ext - 4;
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ if (MCOperand_getImm(MO) != 0) {
+ SStream_concat(O, " #0x%"PRIx64, MCOperand_getImm(MO));
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = MCOperand_getImm(MO);
+ }
+}
+
+static void printSImm7ScaledOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, int MemScale)
+{
+ MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
+ int32_t Imm = unpackSignedImm(7, MCOperand_getImm(MOImm));
+
+ SStream_concat(O, "#0x%x", (Imm * MemScale));
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.disp = Imm * MemScale;
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm * MemScale;
+ MI->pub_insn.arm64.op_count++;
+ }
+}
+
+// TODO: handle this Vd register??
+static void printVPRRegister(MCInst *MI, unsigned OpNo, SStream *O)
+{
+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
+ char *Name = strdup(getRegisterName(Reg));
+ Name[0] = 'v';
+ SStream_concat(O, "%s", Name);
+ free(Name);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_REG;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].reg = Reg;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+ MCOperand *Op = MCInst_getOperand(MI, OpNo);
+ if (MCOperand_isReg(Op)) {
+ unsigned Reg = MCOperand_getReg(Op);
+ SStream_concat(O, getRegisterName(Reg));
+ if (doing_mem) {
+ if (MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.base == ARM64_REG_INVALID) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.base = Reg;
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.index = Reg;
+ }
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_REG;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].reg = Reg;
+ MI->pub_insn.arm64.op_count++;
+ }
+ } else if (MCOperand_isImm(Op)) {
+ int64_t imm = MCOperand_getImm(Op);
+ SStream_concat(O, "#0x%"PRIx64, imm);
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.disp = imm;
+ } else {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = imm;
+ MI->pub_insn.arm64.op_count++;
+ }
+ }
+}
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+static void printNeonMovImmShiftOperand(MCInst *MI, unsigned OpNum,
+ SStream *O, A64SE_ShiftExtSpecifiers Ext, bool isHalf)
+{
+ MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+ //assert(MO.isImm() &&
+ // "Immediate operand required for Neon vector immediate inst.");
+
+ bool IsLSL = false;
+ if (Ext == A64SE_LSL)
+ IsLSL = true;
+ else if (Ext != A64SE_MSL) {
+ //llvm_unreachable("Invalid shift specifier in movi instruction");
+ }
+
+ int64_t Imm = MCOperand_getImm(MO);
+
+ // MSL and LSLH accepts encoded shift amount 0 or 1.
+ if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1) {
+ // llvm_unreachable("Invalid shift amount in movi instruction");
+ }
+
+ // LSH accepts encoded shift amount 0, 1, 2 or 3.
+ if (IsLSL && (Imm < 0 || Imm > 3)) {
+ //llvm_unreachable("Invalid shift amount in movi instruction");
+ }
+
+ // Print shift amount as multiple of 8 with MSL encoded shift amount
+ // 0 and 1 printed as 8 and 16.
+ if (!IsLSL)
+ Imm++;
+ Imm *= 8;
+
+ // LSL #0 is not printed
+ if (IsLSL) {
+ if (Imm == 0)
+ return;
+ SStream_concat(O, ", lsl");
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ } else {
+ SStream_concat(O, ", msl");
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.type = ARM64_SFT_MSL;
+ }
+
+ SStream_concat(O, " #0x%"PRIx64, Imm);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count - 1].shift.value = Imm;
+}
+
+static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ SStream_concat(O, "#0x0");
+ // FIXME: vector ZERO
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = 0;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printNeonUImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MOUImm = MCInst_getOperand(MI, OpNum);
+
+ //assert(MOUImm.isImm() &&
+ // "Immediate operand required for Neon vector immediate inst.");
+
+ unsigned Imm = MCOperand_getImm(MOUImm);
+
+ SStream_concat(O, "#0x%"PRIx64, Imm);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printNeonUImm8OperandBare(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MOUImm = MCInst_getOperand(MI, OpNum);
+
+ //assert(MOUImm.isImm()
+ // && "Immediate operand required for Neon vector immediate inst.");
+
+ unsigned Imm = MCOperand_getImm(MOUImm);
+ SStream_concat(O, "0x%x", Imm);
+
+ if (doing_mem) {
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].mem.disp = Imm;
+ } else {
+ // FIXME: never has false branch??
+ }
+}
+
+static void printNeonUImm64MaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ MCOperand *MOUImm8 = MCInst_getOperand(MI, OpNum);
+
+ //assert(MOUImm8.isImm() &&
+ // "Immediate operand required for Neon vector immediate bytemask inst.");
+
+ uint32_t UImm8 = MCOperand_getImm(MOUImm8);
+ uint64_t Mask = 0;
+
+ // Replicates 0x00 or 0xff byte in a 64-bit vector
+ unsigned ByteNum;
+ for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+ if ((UImm8 >> ByteNum) & 1)
+ Mask |= (uint64_t)0xff << (8 * ByteNum);
+ }
+
+ SStream_concat(O, "#0x%"PRIx64, Mask);
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
+ MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Mask;
+ MI->pub_insn.arm64.op_count++;
+}
+
+static void printMRSOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ printSysRegOperand(&AArch64_MRSMapper, MI, OpNum, O);
+}
+
+static void printMSROperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+ printSysRegOperand(&AArch64_MSRMapper, MI, OpNum, O);
+}
+
+
+#define PRINT_ALIAS_INSTR
+#include "AArch64GenAsmWriter.inc"
+
+void AArch64_post_printer(unsigned int insn, cs_insn *pub_insn, char *insn_asm)
+{
+ // check if this insn requests write-back
+ if (strrchr(insn_asm, '!') != NULL)
+ pub_insn->arm64.writeback = true;
+}
+
+void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
+{
+ if (printAliasInstr(MI, O, Info)) {
+ char *mnem = strdup(O->buffer);
+ char *tab = strchr(mnem, '\t');
+ if (tab)
+ *tab = '\0';
+ // reflect the new insn name (alias) in the opcode
+ MCInst_setOpcode(MI, AArch64_get_insn_id2(AArch64_map_insn(mnem)));
+ free(mnem);
+ } else
+ AArch64InstPrinter_printInstruction(MI, O);
+}
+
diff --git a/arch/AArch64/AArch64InstPrinter.h b/arch/AArch64/AArch64InstPrinter.h
new file mode 100644
index 0000000..d70eecd
--- /dev/null
+++ b/arch/AArch64/AArch64InstPrinter.h
@@ -0,0 +1,28 @@
+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_LLVM_AARCH64INSTPRINTER_H
+#define CS_LLVM_AARCH64INSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void AArch64_printInst(MCInst *MI, SStream *O, void *);
+
+void AArch64_post_printer(unsigned int insn, cs_insn *pub_insn, char *insn_asm);
+
+#endif
diff --git a/arch/AArch64/mapping.c b/arch/AArch64/mapping.c
new file mode 100644
index 0000000..7354901
--- /dev/null
+++ b/arch/AArch64/mapping.c
@@ -0,0 +1,2248 @@
+/* Capstone Unified Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../include/arm64.h"
+#include "../../utils.h"
+
+#include "mapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "AArch64GenInstrInfo.inc"
+
+static name_map reg_name_maps[] = {
+ { ARM64_REG_INVALID, NULL },
+ { ARM64_REG_NZCV, "nzcv"},
+ { ARM64_REG_WSP, "wsp"},
+ { ARM64_REG_WZR, "wzr"},
+ { ARM64_REG_SP, "sp"},
+ { ARM64_REG_XZR, "xzr"},
+ { ARM64_REG_B0, "b0"},
+ { ARM64_REG_B1, "b1"},
+ { ARM64_REG_B2, "b2"},
+ { ARM64_REG_B3, "b3"},
+ { ARM64_REG_B4, "b4"},
+ { ARM64_REG_B5, "b5"},
+ { ARM64_REG_B6, "b6"},
+ { ARM64_REG_B7, "b7"},
+ { ARM64_REG_B8, "b8"},
+ { ARM64_REG_B9, "b9"},
+ { ARM64_REG_B10, "b10"},
+ { ARM64_REG_B11, "b11"},
+ { ARM64_REG_B12, "b12"},
+ { ARM64_REG_B13, "b13"},
+ { ARM64_REG_B14, "b14"},
+ { ARM64_REG_B15, "b15"},
+ { ARM64_REG_B16, "b16"},
+ { ARM64_REG_B17, "b17"},
+ { ARM64_REG_B18, "b18"},
+ { ARM64_REG_B19, "b19"},
+ { ARM64_REG_B20, "b20"},
+ { ARM64_REG_B21, "b21"},
+ { ARM64_REG_B22, "b22"},
+ { ARM64_REG_B23, "b23"},
+ { ARM64_REG_B24, "b24"},
+ { ARM64_REG_B25, "b25"},
+ { ARM64_REG_B26, "b26"},
+ { ARM64_REG_B27, "b27"},
+ { ARM64_REG_B28, "b28"},
+ { ARM64_REG_B29, "b29"},
+ { ARM64_REG_B30, "b30"},
+ { ARM64_REG_B31, "b31"},
+ { ARM64_REG_D0, "d0"},
+ { ARM64_REG_D1, "d1"},
+ { ARM64_REG_D2, "d2"},
+ { ARM64_REG_D3, "d3"},
+ { ARM64_REG_D4, "d4"},
+ { ARM64_REG_D5, "d5"},
+ { ARM64_REG_D6, "d6"},
+ { ARM64_REG_D7, "d7"},
+ { ARM64_REG_D8, "d8"},
+ { ARM64_REG_D9, "d9"},
+ { ARM64_REG_D10, "d10"},
+ { ARM64_REG_D11, "d11"},
+ { ARM64_REG_D12, "d12"},
+ { ARM64_REG_D13, "d13"},
+ { ARM64_REG_D14, "d14"},
+ { ARM64_REG_D15, "d15"},
+ { ARM64_REG_D16, "d16"},
+ { ARM64_REG_D17, "d17"},
+ { ARM64_REG_D18, "d18"},
+ { ARM64_REG_D19, "d19"},
+ { ARM64_REG_D20, "d20"},
+ { ARM64_REG_D21, "d21"},
+ { ARM64_REG_D22, "d22"},
+ { ARM64_REG_D23, "d23"},
+ { ARM64_REG_D24, "d24"},
+ { ARM64_REG_D25, "d25"},
+ { ARM64_REG_D26, "d26"},
+ { ARM64_REG_D27, "d27"},
+ { ARM64_REG_D28, "d28"},
+ { ARM64_REG_D29, "d29"},
+ { ARM64_REG_D30, "d30"},
+ { ARM64_REG_D31, "d31"},
+ { ARM64_REG_H0, "h0"},
+ { ARM64_REG_H1, "h1"},
+ { ARM64_REG_H2, "h2"},
+ { ARM64_REG_H3, "h3"},
+ { ARM64_REG_H4, "h4"},
+ { ARM64_REG_H5, "h5"},
+ { ARM64_REG_H6, "h6"},
+ { ARM64_REG_H7, "h7"},
+ { ARM64_REG_H8, "h8"},
+ { ARM64_REG_H9, "h9"},
+ { ARM64_REG_H10, "h10"},
+ { ARM64_REG_H11, "h11"},
+ { ARM64_REG_H12, "h12"},
+ { ARM64_REG_H13, "h13"},
+ { ARM64_REG_H14, "h14"},
+ { ARM64_REG_H15, "h15"},
+ { ARM64_REG_H16, "h16"},
+ { ARM64_REG_H17, "h17"},
+ { ARM64_REG_H18, "h18"},
+ { ARM64_REG_H19, "h19"},
+ { ARM64_REG_H20, "h20"},
+ { ARM64_REG_H21, "h21"},
+ { ARM64_REG_H22, "h22"},
+ { ARM64_REG_H23, "h23"},
+ { ARM64_REG_H24, "h24"},
+ { ARM64_REG_H25, "h25"},
+ { ARM64_REG_H26, "h26"},
+ { ARM64_REG_H27, "h27"},
+ { ARM64_REG_H28, "h28"},
+ { ARM64_REG_H29, "h29"},
+ { ARM64_REG_H30, "h30"},
+ { ARM64_REG_H31, "h31"},
+ { ARM64_REG_Q0, "q0"},
+ { ARM64_REG_Q1, "q1"},
+ { ARM64_REG_Q2, "q2"},
+ { ARM64_REG_Q3, "q3"},
+ { ARM64_REG_Q4, "q4"},
+ { ARM64_REG_Q5, "q5"},
+ { ARM64_REG_Q6, "q6"},
+ { ARM64_REG_Q7, "q7"},
+ { ARM64_REG_Q8, "q8"},
+ { ARM64_REG_Q9, "q9"},
+ { ARM64_REG_Q10, "q10"},
+ { ARM64_REG_Q11, "q11"},
+ { ARM64_REG_Q12, "q12"},
+ { ARM64_REG_Q13, "q13"},
+ { ARM64_REG_Q14, "q14"},
+ { ARM64_REG_Q15, "q15"},
+ { ARM64_REG_Q16, "q16"},
+ { ARM64_REG_Q17, "q17"},
+ { ARM64_REG_Q18, "q18"},
+ { ARM64_REG_Q19, "q19"},
+ { ARM64_REG_Q20, "q20"},
+ { ARM64_REG_Q21, "q21"},
+ { ARM64_REG_Q22, "q22"},
+ { ARM64_REG_Q23, "q23"},
+ { ARM64_REG_Q24, "q24"},
+ { ARM64_REG_Q25, "q25"},
+ { ARM64_REG_Q26, "q26"},
+ { ARM64_REG_Q27, "q27"},
+ { ARM64_REG_Q28, "q28"},
+ { ARM64_REG_Q29, "q29"},
+ { ARM64_REG_Q30, "q30"},
+ { ARM64_REG_Q31, "q31"},
+ { ARM64_REG_S0, "s0"},
+ { ARM64_REG_S1, "s1"},
+ { ARM64_REG_S2, "s2"},
+ { ARM64_REG_S3, "s3"},
+ { ARM64_REG_S4, "s4"},
+ { ARM64_REG_S5, "s5"},
+ { ARM64_REG_S6, "s6"},
+ { ARM64_REG_S7, "s7"},
+ { ARM64_REG_S8, "s8"},
+ { ARM64_REG_S9, "s9"},
+ { ARM64_REG_S10, "s10"},
+ { ARM64_REG_S11, "s11"},
+ { ARM64_REG_S12, "s12"},
+ { ARM64_REG_S13, "s13"},
+ { ARM64_REG_S14, "s14"},
+ { ARM64_REG_S15, "s15"},
+ { ARM64_REG_S16, "s16"},
+ { ARM64_REG_S17, "s17"},
+ { ARM64_REG_S18, "s18"},
+ { ARM64_REG_S19, "s19"},
+ { ARM64_REG_S20, "s20"},
+ { ARM64_REG_S21, "s21"},
+ { ARM64_REG_S22, "s22"},
+ { ARM64_REG_S23, "s23"},
+ { ARM64_REG_S24, "s24"},
+ { ARM64_REG_S25, "s25"},
+ { ARM64_REG_S26, "s26"},
+ { ARM64_REG_S27, "s27"},
+ { ARM64_REG_S28, "s28"},
+ { ARM64_REG_S29, "s29"},
+ { ARM64_REG_S30, "s30"},
+ { ARM64_REG_S31, "s31"},
+ { ARM64_REG_W0, "w0"},
+ { ARM64_REG_W1, "w1"},
+ { ARM64_REG_W2, "w2"},
+ { ARM64_REG_W3, "w3"},
+ { ARM64_REG_W4, "w4"},
+ { ARM64_REG_W5, "w5"},
+ { ARM64_REG_W6, "w6"},
+ { ARM64_REG_W7, "w7"},
+ { ARM64_REG_W8, "w8"},
+ { ARM64_REG_W9, "w9"},
+ { ARM64_REG_W10, "w10"},
+ { ARM64_REG_W11, "w11"},
+ { ARM64_REG_W12, "w12"},
+ { ARM64_REG_W13, "w13"},
+ { ARM64_REG_W14, "w14"},
+ { ARM64_REG_W15, "w15"},
+ { ARM64_REG_W16, "w16"},
+ { ARM64_REG_W17, "w17"},
+ { ARM64_REG_W18, "w18"},
+ { ARM64_REG_W19, "w19"},
+ { ARM64_REG_W20, "w20"},
+ { ARM64_REG_W21, "w21"},
+ { ARM64_REG_W22, "w22"},
+ { ARM64_REG_W23, "w23"},
+ { ARM64_REG_W24, "w24"},
+ { ARM64_REG_W25, "w25"},
+ { ARM64_REG_W26, "w26"},
+ { ARM64_REG_W27, "w27"},
+ { ARM64_REG_W28, "w28"},
+ { ARM64_REG_W29, "w29"},
+ { ARM64_REG_W30, "w30"},
+ { ARM64_REG_X0, "x0"},
+ { ARM64_REG_X1, "x1"},
+ { ARM64_REG_X2, "x2"},
+ { ARM64_REG_X3, "x3"},
+ { ARM64_REG_X4, "x4"},
+ { ARM64_REG_X5, "x5"},
+ { ARM64_REG_X6, "x6"},
+ { ARM64_REG_X7, "x7"},
+ { ARM64_REG_X8, "x8"},
+ { ARM64_REG_X9, "x9"},
+ { ARM64_REG_X10, "x10"},
+ { ARM64_REG_X11, "x11"},
+ { ARM64_REG_X12, "x12"},
+ { ARM64_REG_X13, "x13"},
+ { ARM64_REG_X14, "x14"},
+ { ARM64_REG_X15, "x15"},
+ { ARM64_REG_X16, "x16"},
+ { ARM64_REG_X17, "x17"},
+ { ARM64_REG_X18, "x18"},
+ { ARM64_REG_X19, "x19"},
+ { ARM64_REG_X20, "x20"},
+ { ARM64_REG_X21, "x21"},
+ { ARM64_REG_X22, "x22"},
+ { ARM64_REG_X23, "x23"},
+ { ARM64_REG_X24, "x24"},
+ { ARM64_REG_X25, "x25"},
+ { ARM64_REG_X26, "x26"},
+ { ARM64_REG_X27, "x27"},
+ { ARM64_REG_X28, "x28"},
+ { ARM64_REG_X29, "x29"},
+ { ARM64_REG_X30, "x30"},
+};
+
+char *AArch64_reg_name(unsigned int reg)
+{
+ if (reg >= ARM64_REG_MAX)
+ return NULL;
+
+ return reg_name_maps[reg].name;
+}
+
+static insn_map insns[] = {
+ { AArch64_ADCSwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADCSxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADCwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_ADCxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_16B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_2S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_4H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_4S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_8B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDP_8H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDSwww_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSwww_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxx_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxx_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxx_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDddd, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_16B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_2D, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_2S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_4H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_4S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_8B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDvvv_8H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDwww_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxw_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxx_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxx_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxx_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxx_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADDxxx_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADRPxi, ARM64_INS_ADRP, { 0 }, { 0 }, { 0 } },
+ { AArch64_ADRxi, ARM64_INS_ADR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDSwwi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSwww_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSwww_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSwww_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSwww_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSxxi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSxxx_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSxxx_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSxxx_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDSxxx_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_ANDvvv_16B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ANDvvv_8B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ANDwwi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDwww_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDwww_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDwww_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDwww_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDxxi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDxxx_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDxxx_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDxxx_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ANDxxx_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
+ { AArch64_ASRVwww, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ASRVxxx, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ASRwwi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ASRxxi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ATix, ARM64_INS_AT, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFIwwii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFIxxii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFMwwii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFMxxii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFXILwwii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } },
+ { AArch64_BFXILxxii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICSwww_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSwww_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSwww_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSwww_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSxxx_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSxxx_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSxxx_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICSxxx_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_BICvi_lsl_2S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICvi_lsl_4H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICvi_lsl_4S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICvi_lsl_8H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICvvv_16B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICvvv_8B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BICwww_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICwww_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICwww_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICwww_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICxxx_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICxxx_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICxxx_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BICxxx_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
+ { AArch64_BIFvvv_16B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BIFvvv_8B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BITvvv_16B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BITvvv_8B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BLRx, ARM64_INS_BLR, { 0 }, { ARM64_REG_X30, 0 }, { 0 } },
+ { AArch64_BLimm, ARM64_INS_BL, { 0 }, { ARM64_REG_X30, 0 }, { 0 } },
+ { AArch64_BRKi, ARM64_INS_BRK, { 0 }, { 0 }, { 0 } },
+ { AArch64_BRx, ARM64_INS_BR, { 0 }, { 0 }, { 0 } },
+ { AArch64_BSLvvv_16B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_BSLvvv_8B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_Bcc, ARM64_INS_B, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_Bimm, ARM64_INS_B, { 0 }, { 0 }, { 0 } },
+ { AArch64_CBNZw, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CBNZx, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CBZw, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CBZx, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CCMNwi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMNww, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMNxi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMNxx, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMPwi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMPww, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMPxi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CCMPxx, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CLREXi, ARM64_INS_CLREX, { 0 }, { 0 }, { 0 } },
+ { AArch64_CLSww, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } },
+ { AArch64_CLSxx, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } },
+ { AArch64_CLZww, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CLZxx, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvi_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGEvvv_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvi_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMGTvvv_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_16B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_2D, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_2S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_4H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_4S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_8B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHIvvv_8H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_16B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_2D, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_2S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_4H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_4S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_8B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMHSvvv_8H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_16B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_2D, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_2S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_4H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_4S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_8B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLEvvi_8H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_16B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_2D, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_2S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_4H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_4S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_8B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMLTvvi_8H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMNww_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNww_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxw_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxx_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxx_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxx_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxx_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMNxx_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPww_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxw_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxx_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxx_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxx_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxx_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMPxx_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_CRC32B_www, ARM64_INS_CRC32B, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32CB_www, ARM64_INS_CRC32CB, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32CH_www, ARM64_INS_CRC32CH, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32CW_www, ARM64_INS_CRC32CW, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32H_www, ARM64_INS_CRC32H, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32W_www, ARM64_INS_CRC32W, { 0 }, { 0 }, { 0 } },
+ { AArch64_CRC32X_wwx, ARM64_INS_CRC32X, { 0 }, { 0 }, { 0 } },
+ { AArch64_CSELwwwc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSELxxxc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSINCwwwc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSINCxxxc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSINVwwwc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSINVxxxc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSNEGwwwc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_CSNEGxxxc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_DCPS1i, ARM64_INS_DCPS1, { 0 }, { 0 }, { 0 } },
+ { AArch64_DCPS2i, ARM64_INS_DCPS2, { 0 }, { 0 }, { 0 } },
+ { AArch64_DCPS3i, ARM64_INS_DCPS3, { 0 }, { 0 }, { 0 } },
+ { AArch64_DCix, ARM64_INS_DC, { 0 }, { 0 }, { 0 } },
+ { AArch64_DMBi, ARM64_INS_DMB, { 0 }, { 0 }, { 0 } },
+ { AArch64_DRPS, ARM64_INS_DRPS, { 0 }, { 0 }, { 0 } },
+ { AArch64_DSBi, ARM64_INS_DSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONwww_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONwww_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONwww_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONwww_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONxxx_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONxxx_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONxxx_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EONxxx_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORvvv_16B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_EORvvv_8B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_EORwwi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORwww_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORwww_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORwww_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORwww_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORxxi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORxxx_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORxxx_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORxxx_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EORxxx_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ERET, ARM64_INS_ERET, { 0 }, { 0 }, { 0 } },
+ { AArch64_EXTRwwwi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_EXTRxxxi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_FABDvvv_2D, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FABDvvv_2S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FABDvvv_4S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FABSdd, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FABSss, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FACGEvvv_2D, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FACGEvvv_2S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FACGEvvv_4S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FACGTvvv_2D, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FACGTvvv_2S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FACGTvvv_4S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDP_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDP_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDP_4S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDddd, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FADDsss, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FADDvvv_2D, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDvvv_2S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FADDvvv_4S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCCMPEdd, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCCMPEss, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCCMPdd, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCCMPss, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FCMPdd_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPdd_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPdi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPdi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPsi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPsi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPss_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCMPss_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_FCSELdddc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_FCSELsssc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTASwd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTASws, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTASxd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTASxs, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTAUwd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTAUws, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTAUxd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTAUxs, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMSwd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMSws, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMSxd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMSxs, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMUwd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMUws, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMUxd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTMUxs, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNSwd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNSws, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNSxd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNSxs, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNUwd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNUws, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNUxd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTNUxs, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPSwd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPSws, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPSxd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPSxs, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPUwd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPUws, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPUxd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTPUxs, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSwd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSws, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSxd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSxs, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUwd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUws, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUxd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUxs, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTdh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTds, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVThd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVThs, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTsd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FCVTsh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FDIVddd, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FDIVsss, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FDIVvvv_2D, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FDIVvvv_2S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FDIVvvv_4S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMADDdddd, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMADDssss, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXNMddd, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMAXNMsss, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXddd, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMAXsss, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMAXvvv_2D, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXvvv_2S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMAXvvv_4S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMddd, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMINNMsss, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINPvvv_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINPvvv_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINPvvv_4S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINddd, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMINsss, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMINvvv_2D, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINvvv_2S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMINvvv_4S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLAvvv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLAvvv_2S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLAvvv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLSvvv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLSvvv_2S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMLSvvv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMOVdd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVdi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVdx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVsi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVss, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVsw, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVvi_2D, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMOVvi_2S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMOVvi_4S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMOVvx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVws, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVxd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMOVxv, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMSUBdddd, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMSUBssss, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMULXvvv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMULXvvv_2S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMULXvvv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMULddd, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMULsss, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } },
+ { AArch64_FMULvvv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMULvvv_2S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FMULvvv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FNEGdd, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNEGss, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMADDdddd, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMADDssss, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMSUBssss, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMULddd, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } },
+ { AArch64_FNMULsss, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FRINTAdd, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTAss, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTIdd, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTIss, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTMdd, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTMss, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTNdd, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTNss, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTPdd, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTPss, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTXdd, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTXss, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTZdd, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRINTZss, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FSQRTdd, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FSQRTss, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } },
+ { AArch64_FSUBddd, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FSUBsss, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_FSUBvvv_2D, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FSUBvvv_2S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_FSUBvvv_4S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_HINTi, ARM64_INS_HINT, { 0 }, { 0 }, { 0 } },
+ { AArch64_HLTi, ARM64_INS_HLT, { 0 }, { 0 }, { 0 } },
+ { AArch64_HVCi, ARM64_INS_HVC, { 0 }, { 0 }, { 0 } },
+ { AArch64_ICi, ARM64_INS_IC, { 0 }, { 0 }, { 0 } },
+ { AArch64_ICix, ARM64_INS_IC, { 0 }, { 0 }, { 0 } },
+ { AArch64_INSELb, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSELd, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSELh, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSELs, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSbw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSdx, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INShw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_INSsw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ISBi, ARM64_INS_ISB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAR_byte, ARM64_INS_LDARB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAR_dword, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAR_hword, ARM64_INS_LDARH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAR_word, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXP_dword, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXP_word, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXR_byte, ARM64_INS_LDAXRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXR_dword, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXR_hword, ARM64_INS_LDAXRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDAXR_word, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDPSWx, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRSWx_lit, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRd_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRq_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRs_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRw_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDRx_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDTRSBw, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDTRSBx, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDTRSHw, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDTRSHx, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDTRSWx, ARM64_INS_LDTRSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDURSWx, ARM64_INS_LDURSW, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXP_dword, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXP_word, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXR_byte, ARM64_INS_LDXRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXR_dword, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXR_hword, ARM64_INS_LDXRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LDXR_word, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_LDUR, ARM64_INS_LDURH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_PostInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_PreInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_STUR, ARM64_INS_STURH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_LDUR, ARM64_INS_LDURB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_PostInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_PreInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_STUR, ARM64_INS_STURB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair128_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSFPPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSLVwww, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSLVxxx, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSLwwi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSLxxi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSRVwww, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSRVxxx, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSRwwi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_LSRxxi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_MADDwwww, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_MADDxxxx, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } },
+ { AArch64_MLAvvv_16B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLAvvv_2S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLAvvv_4H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLAvvv_4S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLAvvv_8B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLAvvv_8H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_16B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_2S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_4H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_4S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_8B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MLSvvv_8H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIdi, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_16B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_2D, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_8B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MOVKwii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } },
+ { AArch64_MOVKxii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } },
+ { AArch64_MOVNwii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MOVNxii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MOVZwii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_MOVZxii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_MRSxi, ARM64_INS_MRS, { 0 }, { 0 }, { 0 } },
+ { AArch64_MSRii, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_MSRix, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } },
+ { AArch64_MSUBwwww, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_MSUBxxxx, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_MULvvv_16B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MULvvv_2S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MULvvv_4H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MULvvv_4S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MULvvv_8B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MULvvv_8H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_MVNww_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNww_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNww_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNww_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNxx_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNxx_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNxx_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_MVNxx_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNvvv_16B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORNvvv_8B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORNwww_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNwww_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNwww_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNwww_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNxxx_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNxxx_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNxxx_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORNxxx_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRvvv_16B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRvvv_8B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_ORRwwi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRwww_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRwww_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRwww_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRwww_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRxxi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRxxx_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRxxx_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRxxx_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_ORRxxx_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
+ { AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_PMULvvv_16B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_PMULvvv_8B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_PRFM, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_PRFM_lit, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_PRFUM, ARM64_INS_PRFUM, { 0 }, { 0 }, { 0 } },
+ { AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RBITww, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } },
+ { AArch64_RBITxx, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } },
+ { AArch64_RETx, ARM64_INS_RET, { 0 }, { 0 }, { 0 } },
+ { AArch64_REV16ww, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } },
+ { AArch64_REV16xx, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } },
+ { AArch64_REV32xx, ARM64_INS_REV32, { 0 }, { 0 }, { 0 } },
+ { AArch64_REVww, ARM64_INS_REV, { 0 }, { 0 }, { 0 } },
+ { AArch64_REVxx, ARM64_INS_REV, { 0 }, { 0 }, { 0 } },
+ { AArch64_RORVwww, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } },
+ { AArch64_RORVxxx, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } },
+ { AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_16B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_2S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_4H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_4S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_8B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABAvvv_8H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_16B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_2S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_4H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_4S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_8B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SABDvvv_8H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SBCSwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SBCSxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SBCwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_SBCxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
+ { AArch64_SBFIZwwii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_SBFIZxxii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_SBFMwwii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_SBFMxxii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_SBFXwwii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } },
+ { AArch64_SBFXxxii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFdw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFdwi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFdx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFdxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFsw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFswi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFsx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SCVTFsxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_SDIVwww, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_SDIVxxx, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_SHADDvvv_16B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHADDvvv_2S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHADDvvv_4H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHADDvvv_4S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHADDvvv_8B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHADDvvv_8H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_16B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_2D, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_2S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_4H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_4S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_8B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHLvvi_8H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_2S, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_4H, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_8B, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_16B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_2D, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_2S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_4H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_4S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_8B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SLIvvi_8H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMADDLxwwx, ARM64_INS_SMADDL, { 0 }, { 0 }, { 0 } },
+ { AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_16B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_2S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_4H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_4S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_8B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMAXvvv_8H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMCi, ARM64_INS_SMC, { 0 }, { 0 }, { 0 } },
+ { AArch64_SMINPvvv_16B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINPvvv_2S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINPvvv_4H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINPvvv_4S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINPvvv_8B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINPvvv_8H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_16B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_2S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_4H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_4S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_8B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMINvvv_8H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMOVwb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMOVwh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMOVxb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMOVxh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMOVxs, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, { 0 }, { 0 }, { 0 } },
+ { AArch64_SMULHxxx, ARM64_INS_SMULH, { 0 }, { 0 }, { 0 } },
+ { AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDbbb, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDddd, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDhhh, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDsss, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_16B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_2D, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_2S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_4H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_4S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_8B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQADDvvv_8H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLddd, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLsss, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLbbb, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLddd, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLhhh, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLsss, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBbbb, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBddd, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBhhh, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBsss, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_16B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_2D, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_2S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_4H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_4S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_8B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRIvvi_8H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLddd, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLddd, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_16B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_2D, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_2S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_4H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_4S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_8B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHLvvv_8H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_16B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_2D, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_2S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_4H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_4S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_8B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSHRvvi_8H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_16B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_2D, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_2S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_4H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_4S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_8B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSRAvvi_8H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_STLR_byte, ARM64_INS_STLRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLR_dword, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLR_hword, ARM64_INS_STLRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLR_word, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXP_dword, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXP_word, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXR_byte, ARM64_INS_STLXRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXR_dword, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXR_hword, ARM64_INS_STLXRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_STLXR_word, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXP_dword, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXP_word, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXR_byte, ARM64_INS_STXRB, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXR_dword, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXR_hword, ARM64_INS_STXRH, { 0 }, { 0 }, { 0 } },
+ { AArch64_STXR_word, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBSwww_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSwww_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxx_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxx_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxx_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBddd, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_16B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_2D, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_2S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_4H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_4S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_8B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBvvv_8H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBwww_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxw_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxx_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxx_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxx_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxx_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SUBxxx_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SVCi, ARM64_INS_SVC, { 0 }, { 0 }, { 0 } },
+ { AArch64_SXTBww, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SXTBxw, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } },
+ { AArch64_SXTHww, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } },
+ { AArch64_SXTHxw, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } },
+ { AArch64_SXTWxw, ARM64_INS_SXTW, { 0 }, { 0 }, { 0 } },
+ { AArch64_SYSLxicci, ARM64_INS_SYSL, { 0 }, { 0 }, { 0 } },
+ { AArch64_SYSiccix, ARM64_INS_SYS, { 0 }, { 0 }, { 0 } },
+ { AArch64_TBNZwii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_TBNZxii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_TBZwii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_TBZxii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_TLBIi, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } },
+ { AArch64_TLBIix, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } },
+ { AArch64_TSTww_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTww_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTww_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTww_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTxx_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTxx_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTxx_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_TSTxx_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
+ { AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_16B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_2S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_4H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_4S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_8B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABAvvv_8H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_16B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_2S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_4H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_4S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_8B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UABDvvv_8H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UBFIZwwii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_UBFIZxxii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } },
+ { AArch64_UBFMwwii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_UBFMxxii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } },
+ { AArch64_UBFXwwii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } },
+ { AArch64_UBFXxxii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFdw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFdwi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFdx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFdxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFsw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFswi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFsx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UCVTFsxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
+ { AArch64_UDIVwww, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_UDIVxxx, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } },
+ { AArch64_UHADDvvv_16B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHADDvvv_2S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHADDvvv_4H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHADDvvv_4S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHADDvvv_8B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHADDvvv_8H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMADDLxwwx, ARM64_INS_UMADDL, { 0 }, { 0 }, { 0 } },
+ { AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_16B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_2S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_4H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_4S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_8B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMAXvvv_8H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_16B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_2S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_4H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_4S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_8B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINPvvv_8H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_16B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_2S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_4H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_4S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_8B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMINvvv_8H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMOVwb, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMOVwh, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMOVws, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMOVxd, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, { 0 }, { 0 }, { 0 } },
+ { AArch64_UMULHxxx, ARM64_INS_UMULH, { 0 }, { 0 }, { 0 } },
+ { AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDbbb, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDddd, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDhhh, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDsss, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_16B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_2D, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_2S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_4H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_4S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_8B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQADDvvv_8H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLddd, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLsss, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLbbb, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLddd, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLhhh, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLsss, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBbbb, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBddd, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBhhh, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBsss, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_16B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_2S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_4H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_4S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_8B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URHADDvvv_8H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLddd, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_16B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_2D, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_2S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_4H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_4S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_8B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHLvvv_8H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_16B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_2D, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_2S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_4H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_4S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_8B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSHRvvi_8H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_16B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_2D, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_2S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_4H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_4S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_8B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_URSRAvvi_8H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_2S, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_4H, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_8B, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLddd, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_16B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_2D, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_2S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_4H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_4S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_8B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHLvvv_8H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_16B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_2D, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_2S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_4H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_4S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_8B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USHRvvi_8H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_16B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_2D, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_2S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_4H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_4S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_8B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USRAvvi_8H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_UXTBww, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } },
+ { AArch64_UXTBxw, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } },
+ { AArch64_UXTHww, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } },
+ { AArch64_UXTHxw, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } },
+ { AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+ { AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
+};
+
+void AArch64_get_insn_id(cs_insn *insn, unsigned int id)
+{
+ int i = insn_find(insns, ARR_SIZE(insns), id);
+ if (i != -1) {
+ insn->id = insns[i].mapid;
+ memcpy(insn->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+ memcpy(insn->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+ memcpy(insn->groups, insns[i].groups, sizeof(insns[i].groups));
+ insn->arm64.update_flags = cs_reg_write(0, insn, ARM64_REG_NZCV);
+ }
+}
+
+unsigned int AArch64_get_insn_id2(unsigned int id)
+{
+ return insn_reverse_id(insns, ARR_SIZE(insns), id);
+}
+
+static name_map insn_name_maps[] = {
+ { ARM64_INS_INVALID, NULL },
+ { ARM64_INS_ADC, "ADC" },
+ { ARM64_INS_ADDHN2, "ADDHN2" },
+ { ARM64_INS_ADDHN, "ADDHN" },
+ { ARM64_INS_ADDP, "ADDP" },
+ { ARM64_INS_ADD, "ADD" },
+ { ARM64_INS_CMN, "CMN" },
+ { ARM64_INS_ADRP, "ADRP" },
+ { ARM64_INS_ADR, "ADR" },
+ { ARM64_INS_AND, "AND" },
+ { ARM64_INS_ASR, "ASR" },
+ { ARM64_INS_AT, "AT" },
+ { ARM64_INS_BFI, "BFI" },
+ { ARM64_INS_BFM, "BFM" },
+ { ARM64_INS_BFXIL, "BFXIL" },
+ { ARM64_INS_BIC, "BIC" },
+ { ARM64_INS_BIF, "BIF" },
+ { ARM64_INS_BIT, "BIT" },
+ { ARM64_INS_BLR, "BLR" },
+ { ARM64_INS_BL, "BL" },
+ { ARM64_INS_BRK, "BRK" },
+ { ARM64_INS_BR, "BR" },
+ { ARM64_INS_BSL, "BSL" },
+ { ARM64_INS_B, "B" },
+ { ARM64_INS_CBNZ, "CBNZ" },
+ { ARM64_INS_CBZ, "CBZ" },
+ { ARM64_INS_CCMN, "CCMN" },
+ { ARM64_INS_CCMP, "CCMP" },
+ { ARM64_INS_CLREX, "CLREX" },
+ { ARM64_INS_CLS, "CLS" },
+ { ARM64_INS_CLZ, "CLZ" },
+ { ARM64_INS_CMEQ, "CMEQ" },
+ { ARM64_INS_CMGE, "CMGE" },
+ { ARM64_INS_CMGT, "CMGT" },
+ { ARM64_INS_CMHI, "CMHI" },
+ { ARM64_INS_CMHS, "CMHS" },
+ { ARM64_INS_CMLE, "CMLE" },
+ { ARM64_INS_CMLT, "CMLT" },
+ { ARM64_INS_CMP, "CMP" },
+ { ARM64_INS_CMTST, "CMTST" },
+ { ARM64_INS_CRC32B, "CRC32B" },
+ { ARM64_INS_CRC32CB, "CRC32CB" },
+ { ARM64_INS_CRC32CH, "CRC32CH" },
+ { ARM64_INS_CRC32CW, "CRC32CW" },
+ { ARM64_INS_CRC32CX, "CRC32CX" },
+ { ARM64_INS_CRC32H, "CRC32H" },
+ { ARM64_INS_CRC32W, "CRC32W" },
+ { ARM64_INS_CRC32X, "CRC32X" },
+ { ARM64_INS_CSEL, "CSEL" },
+ { ARM64_INS_CSINC, "CSINC" },
+ { ARM64_INS_CSINV, "CSINV" },
+ { ARM64_INS_CSNEG, "CSNEG" },
+ { ARM64_INS_DCPS1, "DCPS1" },
+ { ARM64_INS_DCPS2, "DCPS2" },
+ { ARM64_INS_DCPS3, "DCPS3" },
+ { ARM64_INS_DC, "DC" },
+ { ARM64_INS_DMB, "DMB" },
+ { ARM64_INS_DRPS, "DRPS" },
+ { ARM64_INS_DSB, "DSB" },
+ { ARM64_INS_EON, "EON" },
+ { ARM64_INS_EOR, "EOR" },
+ { ARM64_INS_ERET, "ERET" },
+ { ARM64_INS_EXTR, "EXTR" },
+ { ARM64_INS_FABD, "FABD" },
+ { ARM64_INS_FABS, "FABS" },
+ { ARM64_INS_FACGE, "FACGE" },
+ { ARM64_INS_FACGT, "FACGT" },
+ { ARM64_INS_FADDP, "FADDP" },
+ { ARM64_INS_FADD, "FADD" },
+ { ARM64_INS_FCCMPE, "FCCMPE" },
+ { ARM64_INS_FCCMP, "FCCMP" },
+ { ARM64_INS_FCMEQ, "FCMEQ" },
+ { ARM64_INS_FCMGE, "FCMGE" },
+ { ARM64_INS_FCMGT, "FCMGT" },
+ { ARM64_INS_FCMLE, "FCMLE" },
+ { ARM64_INS_FCMLT, "FCMLT" },
+ { ARM64_INS_FCMP, "FCMP" },
+ { ARM64_INS_FCMPE, "FCMPE" },
+ { ARM64_INS_FCSEL, "FCSEL" },
+ { ARM64_INS_FCVTAS, "FCVTAS" },
+ { ARM64_INS_FCVTAU, "FCVTAU" },
+ { ARM64_INS_FCVTMS, "FCVTMS" },
+ { ARM64_INS_FCVTMU, "FCVTMU" },
+ { ARM64_INS_FCVTNS, "FCVTNS" },
+ { ARM64_INS_FCVTNU, "FCVTNU" },
+ { ARM64_INS_FCVTPS, "FCVTPS" },
+ { ARM64_INS_FCVTPU, "FCVTPU" },
+ { ARM64_INS_FCVTZS, "FCVTZS" },
+ { ARM64_INS_FCVTZU, "FCVTZU" },
+ { ARM64_INS_FCVT, "FCVT" },
+ { ARM64_INS_FDIV, "FDIV" },
+ { ARM64_INS_FMADD, "FMADD" },
+ { ARM64_INS_FMAXNMP, "FMAXNMP" },
+ { ARM64_INS_FMAXNM, "FMAXNM" },
+ { ARM64_INS_FMAXP, "FMAXP" },
+ { ARM64_INS_FMAX, "FMAX" },
+ { ARM64_INS_FMINNMP, "FMINNMP" },
+ { ARM64_INS_FMINNM, "FMINNM" },
+ { ARM64_INS_FMINP, "FMINP" },
+ { ARM64_INS_FMIN, "FMIN" },
+ { ARM64_INS_FMLA, "FMLA" },
+ { ARM64_INS_FMLS, "FMLS" },
+ { ARM64_INS_FMOV, "FMOV" },
+ { ARM64_INS_FMSUB, "FMSUB" },
+ { ARM64_INS_FMULX, "FMULX" },
+ { ARM64_INS_FMUL, "FMUL" },
+ { ARM64_INS_FNEG, "FNEG" },
+ { ARM64_INS_FNMADD, "FNMADD" },
+ { ARM64_INS_FNMSUB, "FNMSUB" },
+ { ARM64_INS_FNMUL, "FNMUL" },
+ { ARM64_INS_FRECPS, "FRECPS" },
+ { ARM64_INS_FRINTA, "FRINTA" },
+ { ARM64_INS_FRINTI, "FRINTI" },
+ { ARM64_INS_FRINTM, "FRINTM" },
+ { ARM64_INS_FRINTN, "FRINTN" },
+ { ARM64_INS_FRINTP, "FRINTP" },
+ { ARM64_INS_FRINTX, "FRINTX" },
+ { ARM64_INS_FRINTZ, "FRINTZ" },
+ { ARM64_INS_FRSQRTS, "FRSQRTS" },
+ { ARM64_INS_FSQRT, "FSQRT" },
+ { ARM64_INS_FSUB, "FSUB" },
+ { ARM64_INS_HINT, "HINT" },
+ { ARM64_INS_HLT, "HLT" },
+ { ARM64_INS_HVC, "HVC" },
+ { ARM64_INS_IC, "IC" },
+ { ARM64_INS_INS, "INS" },
+ { ARM64_INS_ISB, "ISB" },
+ { ARM64_INS_LDARB, "LDARB" },
+ { ARM64_INS_LDAR, "LDAR" },
+ { ARM64_INS_LDARH, "LDARH" },
+ { ARM64_INS_LDAXP, "LDAXP" },
+ { ARM64_INS_LDAXRB, "LDAXRB" },
+ { ARM64_INS_LDAXR, "LDAXR" },
+ { ARM64_INS_LDAXRH, "LDAXRH" },
+ { ARM64_INS_LDPSW, "LDPSW" },
+ { ARM64_INS_LDRSB, "LDRSB" },
+ { ARM64_INS_LDURSB, "LDURSB" },
+ { ARM64_INS_LDRSH, "LDRSH" },
+ { ARM64_INS_LDURSH, "LDURSH" },
+ { ARM64_INS_LDRSW, "LDRSW" },
+ { ARM64_INS_LDR, "LDR" },
+ { ARM64_INS_LDTRSB, "LDTRSB" },
+ { ARM64_INS_LDTRSH, "LDTRSH" },
+ { ARM64_INS_LDTRSW, "LDTRSW" },
+ { ARM64_INS_LDURSW, "LDURSW" },
+ { ARM64_INS_LDXP, "LDXP" },
+ { ARM64_INS_LDXRB, "LDXRB" },
+ { ARM64_INS_LDXR, "LDXR" },
+ { ARM64_INS_LDXRH, "LDXRH" },
+ { ARM64_INS_LDRH, "LDRH" },
+ { ARM64_INS_LDURH, "LDURH" },
+ { ARM64_INS_STRH, "STRH" },
+ { ARM64_INS_STURH, "STURH" },
+ { ARM64_INS_LDTRH, "LDTRH" },
+ { ARM64_INS_STTRH, "STTRH" },
+ { ARM64_INS_LDUR, "LDUR" },
+ { ARM64_INS_STR, "STR" },
+ { ARM64_INS_STUR, "STUR" },
+ { ARM64_INS_LDTR, "LDTR" },
+ { ARM64_INS_STTR, "STTR" },
+ { ARM64_INS_LDRB, "LDRB" },
+ { ARM64_INS_LDURB, "LDURB" },
+ { ARM64_INS_STRB, "STRB" },
+ { ARM64_INS_STURB, "STURB" },
+ { ARM64_INS_LDTRB, "LDTRB" },
+ { ARM64_INS_STTRB, "STTRB" },
+ { ARM64_INS_LDP, "LDP" },
+ { ARM64_INS_LDNP, "LDNP" },
+ { ARM64_INS_STNP, "STNP" },
+ { ARM64_INS_STP, "STP" },
+ { ARM64_INS_LSL, "LSL" },
+ { ARM64_INS_LSR, "LSR" },
+ { ARM64_INS_MADD, "MADD" },
+ { ARM64_INS_MLA, "MLA" },
+ { ARM64_INS_MLS, "MLS" },
+ { ARM64_INS_MOVI, "MOVI" },
+ { ARM64_INS_MOVK, "MOVK" },
+ { ARM64_INS_MOVN, "MOVN" },
+ { ARM64_INS_MOVZ, "MOVZ" },
+ { ARM64_INS_MRS, "MRS" },
+ { ARM64_INS_MSR, "MSR" },
+ { ARM64_INS_MSUB, "MSUB" },
+ { ARM64_INS_MUL, "MUL" },
+ { ARM64_INS_MVNI, "MVNI" },
+ { ARM64_INS_MVN, "MVN" },
+ { ARM64_INS_ORN, "ORN" },
+ { ARM64_INS_ORR, "ORR" },
+ { ARM64_INS_PMULL2, "PMULL2" },
+ { ARM64_INS_PMULL, "PMULL" },
+ { ARM64_INS_PMUL, "PMUL" },
+ { ARM64_INS_PRFM, "PRFM" },
+ { ARM64_INS_PRFUM, "PRFUM" },
+ { ARM64_INS_SQRSHRUN2, "SQRSHRUN2" },
+ { ARM64_INS_SQRSHRUN, "SQRSHRUN" },
+ { ARM64_INS_SQSHRUN2, "SQSHRUN2" },
+ { ARM64_INS_SQSHRUN, "SQSHRUN" },
+ { ARM64_INS_RADDHN2, "RADDHN2" },
+ { ARM64_INS_RADDHN, "RADDHN" },
+ { ARM64_INS_RBIT, "RBIT" },
+ { ARM64_INS_RET, "RET" },
+ { ARM64_INS_REV16, "REV16" },
+ { ARM64_INS_REV32, "REV32" },
+ { ARM64_INS_REV, "REV" },
+ { ARM64_INS_ROR, "ROR" },
+ { ARM64_INS_RSHRN2, "RSHRN2" },
+ { ARM64_INS_RSHRN, "RSHRN" },
+ { ARM64_INS_RSUBHN2, "RSUBHN2" },
+ { ARM64_INS_RSUBHN, "RSUBHN" },
+ { ARM64_INS_SABAL2, "SABAL2" },
+ { ARM64_INS_SABAL, "SABAL" },
+ { ARM64_INS_SABA, "SABA" },
+ { ARM64_INS_SABDL2, "SABDL2" },
+ { ARM64_INS_SABDL, "SABDL" },
+ { ARM64_INS_SABD, "SABD" },
+ { ARM64_INS_SADDL2, "SADDL2" },
+ { ARM64_INS_SADDL, "SADDL" },
+ { ARM64_INS_SADDW2, "SADDW2" },
+ { ARM64_INS_SADDW, "SADDW" },
+ { ARM64_INS_SBC, "SBC" },
+ { ARM64_INS_SBFIZ, "SBFIZ" },
+ { ARM64_INS_SBFM, "SBFM" },
+ { ARM64_INS_SBFX, "SBFX" },
+ { ARM64_INS_SCVTF, "SCVTF" },
+ { ARM64_INS_SDIV, "SDIV" },
+ { ARM64_INS_SHADD, "SHADD" },
+ { ARM64_INS_SHL, "SHL" },
+ { ARM64_INS_SHRN2, "SHRN2" },
+ { ARM64_INS_SHRN, "SHRN" },
+ { ARM64_INS_SHSUB, "SHSUB" },
+ { ARM64_INS_SLI, "SLI" },
+ { ARM64_INS_SMADDL, "SMADDL" },
+ { ARM64_INS_SMAXP, "SMAXP" },
+ { ARM64_INS_SMAX, "SMAX" },
+ { ARM64_INS_SMC, "SMC" },
+ { ARM64_INS_SMINP, "SMINP" },
+ { ARM64_INS_SMIN, "SMIN" },
+ { ARM64_INS_SMLAL2, "SMLAL2" },
+ { ARM64_INS_SMLAL, "SMLAL" },
+ { ARM64_INS_SMLSL2, "SMLSL2" },
+ { ARM64_INS_SMLSL, "SMLSL" },
+ { ARM64_INS_SMOV, "SMOV" },
+ { ARM64_INS_SMSUBL, "SMSUBL" },
+ { ARM64_INS_SMULH, "SMULH" },
+ { ARM64_INS_SMULL2, "SMULL2" },
+ { ARM64_INS_SMULL, "SMULL" },
+ { ARM64_INS_SQADD, "SQADD" },
+ { ARM64_INS_SQDMLAL2, "SQDMLAL2" },
+ { ARM64_INS_SQDMLAL, "SQDMLAL" },
+ { ARM64_INS_SQDMLSL2, "SQDMLSL2" },
+ { ARM64_INS_SQDMLSL, "SQDMLSL" },
+ { ARM64_INS_SQDMULH, "SQDMULH" },
+ { ARM64_INS_SQDMULL2, "SQDMULL2" },
+ { ARM64_INS_SQDMULL, "SQDMULL" },
+ { ARM64_INS_SQRDMULH, "SQRDMULH" },
+ { ARM64_INS_SQRSHL, "SQRSHL" },
+ { ARM64_INS_SQRSHRN2, "SQRSHRN2" },
+ { ARM64_INS_SQRSHRN, "SQRSHRN" },
+ { ARM64_INS_SQSHLU, "SQSHLU" },
+ { ARM64_INS_SQSHL, "SQSHL" },
+ { ARM64_INS_SQSHRN2, "SQSHRN2" },
+ { ARM64_INS_SQSHRN, "SQSHRN" },
+ { ARM64_INS_SQSUB, "SQSUB" },
+ { ARM64_INS_SRHADD, "SRHADD" },
+ { ARM64_INS_SRI, "SRI" },
+ { ARM64_INS_SRSHL, "SRSHL" },
+ { ARM64_INS_SRSHR, "SRSHR" },
+ { ARM64_INS_SRSRA, "SRSRA" },
+ { ARM64_INS_SSHLL2, "SSHLL2" },
+ { ARM64_INS_SSHLL, "SSHLL" },
+ { ARM64_INS_SSHL, "SSHL" },
+ { ARM64_INS_SSHR, "SSHR" },
+ { ARM64_INS_SSRA, "SSRA" },
+ { ARM64_INS_SSUBL2, "SSUBL2" },
+ { ARM64_INS_SSUBL, "SSUBL" },
+ { ARM64_INS_SSUBW2, "SSUBW2" },
+ { ARM64_INS_SSUBW, "SSUBW" },
+ { ARM64_INS_STLRB, "STLRB" },
+ { ARM64_INS_STLR, "STLR" },
+ { ARM64_INS_STLRH, "STLRH" },
+ { ARM64_INS_STLXP, "STLXP" },
+ { ARM64_INS_STLXRB, "STLXRB" },
+ { ARM64_INS_STLXR, "STLXR" },
+ { ARM64_INS_STLXRH, "STLXRH" },
+ { ARM64_INS_STXP, "STXP" },
+ { ARM64_INS_STXRB, "STXRB" },
+ { ARM64_INS_STXR, "STXR" },
+ { ARM64_INS_STXRH, "STXRH" },
+ { ARM64_INS_SUBHN2, "SUBHN2" },
+ { ARM64_INS_SUBHN, "SUBHN" },
+ { ARM64_INS_SUB, "SUB" },
+ { ARM64_INS_SVC, "SVC" },
+ { ARM64_INS_SXTB, "SXTB" },
+ { ARM64_INS_SXTH, "SXTH" },
+ { ARM64_INS_SXTW, "SXTW" },
+ { ARM64_INS_SYSL, "SYSL" },
+ { ARM64_INS_SYS, "SYS" },
+ { ARM64_INS_TBNZ, "TBNZ" },
+ { ARM64_INS_TBZ, "TBZ" },
+ { ARM64_INS_TLBI, "TLBI" },
+ { ARM64_INS_TST, "TST" },
+ { ARM64_INS_UABAL2, "UABAL2" },
+ { ARM64_INS_UABAL, "UABAL" },
+ { ARM64_INS_UABA, "UABA" },
+ { ARM64_INS_UABDL2, "UABDL2" },
+ { ARM64_INS_UABDL, "UABDL" },
+ { ARM64_INS_UABD, "UABD" },
+ { ARM64_INS_UADDL2, "UADDL2" },
+ { ARM64_INS_UADDL, "UADDL" },
+ { ARM64_INS_UADDW2, "UADDW2" },
+ { ARM64_INS_UADDW, "UADDW" },
+ { ARM64_INS_UBFIZ, "UBFIZ" },
+ { ARM64_INS_UBFM, "UBFM" },
+ { ARM64_INS_UBFX, "UBFX" },
+ { ARM64_INS_UCVTF, "UCVTF" },
+ { ARM64_INS_UDIV, "UDIV" },
+ { ARM64_INS_UHADD, "UHADD" },
+ { ARM64_INS_UHSUB, "UHSUB" },
+ { ARM64_INS_UMADDL, "UMADDL" },
+ { ARM64_INS_UMAXP, "UMAXP" },
+ { ARM64_INS_UMAX, "UMAX" },
+ { ARM64_INS_UMINP, "UMINP" },
+ { ARM64_INS_UMIN, "UMIN" },
+ { ARM64_INS_UMLAL2, "UMLAL2" },
+ { ARM64_INS_UMLAL, "UMLAL" },
+ { ARM64_INS_UMLSL2, "UMLSL2" },
+ { ARM64_INS_UMLSL, "UMLSL" },
+ { ARM64_INS_UMOV, "UMOV" },
+ { ARM64_INS_UMSUBL, "UMSUBL" },
+ { ARM64_INS_UMULH, "UMULH" },
+ { ARM64_INS_UMULL2, "UMULL2" },
+ { ARM64_INS_UMULL, "UMULL" },
+ { ARM64_INS_UQADD, "UQADD" },
+ { ARM64_INS_UQRSHL, "UQRSHL" },
+ { ARM64_INS_UQRSHRN2, "UQRSHRN2" },
+ { ARM64_INS_UQRSHRN, "UQRSHRN" },
+ { ARM64_INS_UQSHL, "UQSHL" },
+ { ARM64_INS_UQSHRN2, "UQSHRN2" },
+ { ARM64_INS_UQSHRN, "UQSHRN" },
+ { ARM64_INS_UQSUB, "UQSUB" },
+ { ARM64_INS_URHADD, "URHADD" },
+ { ARM64_INS_URSHL, "URSHL" },
+ { ARM64_INS_URSHR, "URSHR" },
+ { ARM64_INS_URSRA, "URSRA" },
+ { ARM64_INS_USHLL2, "USHLL2" },
+ { ARM64_INS_USHLL, "USHLL" },
+ { ARM64_INS_USHL, "USHL" },
+ { ARM64_INS_USHR, "USHR" },
+ { ARM64_INS_USRA, "USRA" },
+ { ARM64_INS_USUBL2, "USUBL2" },
+ { ARM64_INS_USUBL, "USUBL" },
+ { ARM64_INS_USUBW2, "USUBW2" },
+ { ARM64_INS_USUBW, "USUBW" },
+ { ARM64_INS_UXTB, "UXTB" },
+ { ARM64_INS_UXTH, "UXTH" },
+};
+
+char *AArch64_insn_name(unsigned int id)
+{
+ if (id >= ARM64_INS_MAX)
+ return NULL;
+
+ return insn_name_maps[id].name;
+}
+
+arm64_reg AArch64_map_insn(char *name)
+{
+ // map *S instructions back to original id
+ name_map insn_name_maps2[] = {
+ { ARM64_INS_ADC, "ADCS" },
+ { ARM64_INS_AND, "ANDS" },
+ { ARM64_INS_ADD, "ADDS" },
+ { ARM64_INS_BIC, "BICS" },
+ { ARM64_INS_SBC, "SBCS" },
+ { ARM64_INS_SUB, "SUBS" },
+ };
+
+ // NOTE: skip first NULL name in insn_name_maps
+ int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
+
+ if (i == -1)
+ // try again with 'special' insn that is not available in insn_name_maps
+ i = name2id(insn_name_maps2, ARR_SIZE(insn_name_maps2), name);
+
+ return (i != -1)? i : ARM64_REG_INVALID;
+}
+
diff --git a/arch/AArch64/mapping.h b/arch/AArch64/mapping.h
new file mode 100644
index 0000000..7cd316b
--- /dev/null
+++ b/arch/AArch64/mapping.h
@@ -0,0 +1,24 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#ifndef CS_ARM64_MAP_H
+#define CS_ARM64_MAP_H
+
+#include "../../include/capstone.h"
+#include "../../include/arm64.h"
+
+// return name of regiser in friendly string
+char *AArch64_reg_name(unsigned int reg);
+
+// given internal insn id, return public instruction info
+void AArch64_get_insn_id(cs_insn *insn, unsigned int id);
+
+// given public insn id, return internal instruction ID
+unsigned int AArch64_get_insn_id2(unsigned int id);
+
+char *AArch64_insn_name(unsigned int id);
+
+// map instruction name to instruction ID
+arm64_reg AArch64_map_insn(char *name);
+
+#endif