initial import
diff --git a/tests/Makefile b/tests/Makefile
new file mode 100644
index 0000000..56cb43f
--- /dev/null
+++ b/tests/Makefile
@@ -0,0 +1,44 @@
+# Capstone Disassembler Engine
+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013>
+
+INCDIR = ../include
+LIBDIR = ..
+
+CC = $(CROSS)gcc
+
+CFLAGS += -fPIC -O3 -Wall -I$(INCDIR) -L$(LIBDIR)
+
+LIBNAME = capstone
+
+.PHONY: all clean win_test
+
+all: test.o test_detail.o test_x86.o test_arm64.o test_arm.o test_mips.o
+ ${CC} $(CFLAGS) test.o -O3 -Wall -l$(LIBNAME) -o test
+ ${CC} $(CFLAGS) test_detail.o -O3 -Wall -l$(LIBNAME) -o test_detail
+ ${CC} $(CFLAGS) test_x86.o -O3 -Wall -l$(LIBNAME) -o test_x86
+ ${CC} $(CFLAGS) test_arm64.o -O3 -Wall -l$(LIBNAME) -o test_arm64
+ ${CC} $(CFLAGS) test_arm.o -O3 -Wall -l$(LIBNAME) -o test_arm
+ ${CC} $(CFLAGS) test_mips.o -O3 -Wall -l$(LIBNAME) -o test_mips
+
+# Mingw32
+windows: test.o test_detail.o test_x86.o test_arm64.o test_arm.o test_mips.o
+ ${CC} test.o -O3 -Wall $(LIBNAME).dll -o test.exe
+ ${CC} test_detail.o -O3 -Wall $(LIBNAME).dll -o test_detail.exe
+ ${CC} test_x86.o -O3 -Wall $(LIBNAME).dll -o test_x86.exe
+ ${CC} test_arm64.o -O3 -Wall $(LIBNAME).dll -o test_arm64.exe
+ ${CC} test_arm.o -O3 -Wall $(LIBNAME).dll -o test_arm.exe
+ ${CC} test_mips.o -O3 -Wall $(LIBNAME).dll -o test_mips.exe
+
+clean:
+ rm -rf test_x86 test_x86.exe test_x86.o
+ rm -rf test_arm64 test_arm64.exe test_arm64.o
+ rm -rf test_arm test_arm.exe test_arm.o
+ rm -rf test_mips test_mips.exe test_mips.o
+ rm -rf test test.exe test.o
+ rm -rf test_detail test_detail.exe test_detail.o
+ rm -rf *.dll
+ rm -rf *.so
+
+.c.o:
+ ${CC} ${CFLAGS} -c $< -o $@
+
diff --git a/tests/README b/tests/README
new file mode 100644
index 0000000..a26677a
--- /dev/null
+++ b/tests/README
@@ -0,0 +1,15 @@
+This directory contains some test code to show how to use Capstone API.
+
+- test.c
+ This code shows the most simple form of API where we only want to get basic
+ information out of disassembled instruction, such as address, mnemonic and
+ operand string.
+
+- test_detail.c:
+ This code shows how to access to architecture-neutral information in disassembled
+ instructions, such as implicit registers read/written, or groups of instructions
+ that this instruction belong to.
+
+- test_<arch>.c
+ These code show how to access architecture-specific information for each
+ architecture.
diff --git a/tests/test.c b/tests/test.c
new file mode 100644
index 0000000..65e55e4
--- /dev/null
+++ b/tests/test.c
@@ -0,0 +1,192 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static void print_string_hex(char *str, int len)
+{
+ char *c;
+
+ printf("Code: ");
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+ printf("\n");
+}
+
+static void test()
+{
+#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
+#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
+#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
+//#define ARM_CODE "\x04\xe0\x2d\xe5"
+#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
+#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
+#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
+#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
+#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
+#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
+//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
+//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
+//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
+//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
+#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_16,
+ .code = X86_CODE16,
+ .size = sizeof(X86_CODE16) - 1,
+ .comment = "X86 16bit (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32bit (ATT syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32 (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_64,
+ .code = X86_CODE64,
+ .size = sizeof(X86_CODE64) - 1,
+ .comment = "X86 64 (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_ARM,
+ .code = ARM_CODE,
+ .size = sizeof(ARM_CODE) - 1,
+ .comment = "ARM"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE2,
+ .size = sizeof(THUMB_CODE2) - 1,
+ .comment = "THUMB-2"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_ARM,
+ .code = ARM_CODE2,
+ .size = sizeof(ARM_CODE2) - 1,
+ .comment = "ARM: Cortex-A15 + NEON"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE,
+ .size = sizeof(THUMB_CODE) - 1,
+ .comment = "THUMB"
+ },
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_32 + CS_MODE_BIG_ENDIAN,
+ .code = MIPS_CODE,
+ .size = sizeof(MIPS_CODE) - 1,
+ .comment = "MIPS-32 (Big-endian)"
+ },
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_64+ CS_MODE_LITTLE_ENDIAN,
+ .code = MIPS_CODE2,
+ .size = sizeof(MIPS_CODE2) - 1,
+ .comment = "MIPS-64-EL (Little-endian)"
+ },
+ {
+ .arch = CS_ARCH_ARM64,
+ .mode = CS_MODE_ARM,
+ .code = ARM64_CODE,
+ .size = sizeof(ARM64_CODE) - 1,
+ .comment = "ARM-64"
+ },
+ };
+
+ csh handle;
+ uint64_t address = 0x1000;
+ //cs_insn insn[16];
+ cs_insn *insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
+ if (err) {
+ printf("Failed on cs_open() with error returned: %u\n", err);
+ return;
+ }
+
+ //uint64_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex(platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t\t%s\n",
+ insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ }
+
+ // print out the next offset, after the last insn
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex(platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+#if 0
+ #define offsetof(type, member) (int)(&((type *)0)->member)
+ cs_insn insn;
+ printf("size: %lu\n", sizeof(insn));
+ printf("@id: %u\n", offsetof(cs_insn, id));
+ printf("@address: %u\n", offsetof(cs_insn, address));
+ printf("@size: %u\n", offsetof(cs_insn, size));
+ printf("@mnemonic: %u\n", offsetof(cs_insn, mnemonic));
+ printf("@op_str: %u\n", offsetof(cs_insn, op_str));
+ printf("@regs_read: %u\n", offsetof(cs_insn, regs_read));
+ printf("@regs_write: %u\n", offsetof(cs_insn, regs_write));
+ printf("@groups: %u\n", offsetof(cs_insn, groups));
+ printf("@arch: %u\n", offsetof(cs_insn, x86));
+#endif
+
+ return 0;
+}
diff --git a/tests/test_arm.c b/tests/test_arm.c
new file mode 100644
index 0000000..21e1194
--- /dev/null
+++ b/tests/test_arm.c
@@ -0,0 +1,225 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+static csh handle;
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static void print_string_hex(char *comment, char *str, int len)
+{
+ char *c;
+
+ printf("%s", comment);
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+
+ printf("\n");
+}
+
+static void print_insn_detail(cs_arch mode, cs_insn *ins)
+{
+ cs_arm *arm = &(ins->arm);
+
+ if (arm->op_count)
+ printf("\top_count: %u\n", arm->op_count);
+
+ int i;
+ for (i = 0; i < arm->op_count; i++) {
+ cs_arm_op *op = &(arm->operands[i]);
+ switch((int)op->type) {
+ default:
+ break;
+ case ARM_OP_REG:
+ printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
+ break;
+ case ARM_OP_IMM:
+ printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
+ break;
+ case ARM_OP_FP:
+ printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
+ break;
+ case ARM_OP_MEM:
+ printf("\t\toperands[%u].type: MEM\n", i);
+ if (op->mem.base != X86_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+ i, cs_reg_name(handle, op->mem.base));
+ if (op->mem.index != X86_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.index: REG = %s\n",
+ i, cs_reg_name(handle, op->mem.index));
+ if (op->mem.scale != 1)
+ printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
+ if (op->mem.disp != 0)
+ printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
+
+ break;
+ case ARM_OP_PIMM:
+ printf("\t\toperands[%u].type: P-IMM = %"PRIu64 "\n", i, op->imm);
+ break;
+ case ARM_OP_CIMM:
+ printf("\t\toperands[%u].type: C-IMM = %"PRIu64 "\n", i, op->imm);
+ break;
+ }
+
+ if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
+ if (op->shift.type < ARM_SFT_ASR_REG)
+ // shift with constant value
+ printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value);
+ else
+ // shift with register
+ printf("\t\t\tShift: %u = %s\n", op->shift.type,
+ cs_reg_name(handle, op->shift.value));
+ }
+ }
+
+ if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
+ printf("\tCode condition: %u\n", ins->arm.cc);
+
+ if (arm->update_flags)
+ printf("\tUpdate-flags: True\n");
+
+ if (arm->writeback)
+ printf("\tWrite-back: True\n");
+
+ printf("\n");
+}
+
+static void test()
+{
+//#define ARM_CODE "\x04\xe0\x2d\xe5" // str lr, [sp, #-0x4]!
+//#define ARM_CODE "\xe0\x83\x22\xe5" // str r8, [r2, #-0x3e0]!
+//#define ARM_CODE "\xf1\x02\x03\x0e" // mcreq p0x2, #0x0, r0, c0x3, c0x1, #0x7
+//#define ARM_CODE "\x00\x00\xa0\xe3" // mov r0, #0x0
+//#define ARM_CODE "\x02\x30\xc1\xe7" // strb r3, [r1, r2]
+//#define ARM_CODE "\x00\x00\x53\xe3" // cmp r3, #0x0
+//#define ARM_CODE "\x02\x00\xa1\xe2" // adc r0, r1, r2
+//#define ARM_CODE "\x21\x01\xa0\xe0" // adc r0, r0, r1, lsr #2
+//#define ARM_CODE "\x21\x01\xb0\xe0" // adcs r0, r0, r1, lsr #2
+//#define ARM_CODE "\x32\x03\xa1\xe0" // adc r0, r1, r2, lsr r3
+//#define ARM_CODE "\x22\x01\xa1\xe0" // adc r0, r1, r2, lsr #2
+//#define ARM_CODE "\x65\x61\x4f\x50" // subpl r6, pc, r5, ror #2
+//#define ARM_CODE "\x30\x30\x53\xe5" // ldrb r3, [r3, #-0x30]
+//#define ARM_CODE "\xb6\x10\xdf\xe1" // ldrh r1, [pc, #0x6]
+//#define ARM_CODE "\x02\x00\x9f\xef" // svc #0x9f0002
+//#define ARM_CODE "\x00\xc0\x27\xea" // b 0x9F0002: FIXME: disasm as "b #0x9f0000"
+//#define ARM_CODE "\x12\x13\xa0\xe1" // lsl r1, r2, r3
+//#define ARM_CODE "\x82\x11\xa0\xe1" // lsl r1, r2, #0x3
+//#define ARM_CODE "\x00\xc0\xa0\xe1" // mov ip, r0
+//#define ARM_CODE "\x02\x00\x12\xe3" // tst r2, #2
+//#define ARM_CODE "\x51\x12\xa0\xe1" // asr r1, r2
+//#define ARM_CODE "\x72\x10\xef\xe6" // uxtb r1, r2
+//#define ARM_CODE "\xe0\x0a\xb7\xee" // vcvt.f64.f32 d0, s1
+//#define ARM_CODE "\x9f\x0f\x91\xe1" // ldrex r0, [r1]
+//#define ARM_CODE "\x0f\x06\x20\xf4" // vld1.8 {d0, d1, d2}, [r0]
+//#define ARM_CODE "\x72\x00\xa1\xe6" // sxtab r0, r1, r2
+//#define ARM_CODE "\x50\x06\x84\xf2" // vmov.i32 q0, #0x40000000
+//#define ARM_CODE "\x73\xe0\xb8\xee" // mrc p0, #5, lr, c8, c3, #3
+//#define ARM_CODE "\x12\x02\x81\xe6" // pkhbt r0, r1, r2, lsl #0x4
+//#define ARM_CODE "\x12\x00\xa0\xe6" // ssat r0, #0x1, r2
+//#define ARM_CODE "\x03\x60\x2d\xe9" // push {r0, r1, sp, lr}
+//#define ARM_CODE "\x8f\x40\x60\xf4" // vld4.32 {d20, d21, d22, d23}, [r0]
+//#define ARM_CODE "\xd0\x00\xc2\xe1" // ldrd r0, r1, [r2]
+//#define ARM_CODE "\x08\xf0\xd0\xf5" // pld [r0, #0x8]
+//#define ARM_CODE "\x10\x8b\xbc\xec" // ldc p11, c8, [r12], #64
+//#define ARM_CODE "\xd4\x30\xd2\xe1" // ldrsb r3, [r2, #0x4]
+//#define ARM_CODE "\x11\x0f\xbe\xf2" // vcvt.s32.f32 d0, d1, #2
+//#define ARM_CODE "\x01\x01\x70\xe1" // cmn r0, r1, lsl #2
+//#define ARM_CODE "\x06\x00\x91\xe2" // adds r0, r1, #6
+//#define ARM_CODE "\x5b\xf0\x7f\xf5" // dmb ish
+//#define ARM_CODE "\xf7\xff\xff\xfe"
+#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
+//#define ARM_CODE2 "\xf0\x24"
+//#define ARM_CODE2 "\x83\xb0"
+#define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
+//#define THUMB_CODE "\x70\x47" // bl 0x26
+//#define THUMB_CODE "\x07\xdd" // ble 0x1c
+#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1"
+#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_ARM,
+ .code = ARM_CODE,
+ .size = sizeof(ARM_CODE) - 1,
+ .comment = "ARM"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE,
+ .size = sizeof(THUMB_CODE) - 1,
+ .comment = "Thumb"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = ARM_CODE2,
+ .size = sizeof(ARM_CODE2) - 1,
+ .comment = "Thumb-mixed"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE2,
+ .size = sizeof(THUMB_CODE2) - 1,
+ .comment = "Thumb-2"
+ },
+ };
+
+ uint64_t address = 0x1000;
+ cs_insn *insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
+ return;
+
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ print_insn_detail(platforms[i].mode, &insn[j]);
+ }
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}
+
diff --git a/tests/test_arm64.c b/tests/test_arm64.c
new file mode 100644
index 0000000..80aa552
--- /dev/null
+++ b/tests/test_arm64.c
@@ -0,0 +1,191 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+static csh handle;
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static void print_string_hex(char *comment, char *str, int len)
+{
+ char *c;
+
+ printf("%s", comment);
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+
+ printf("\n");
+}
+
+static void print_insn_detail(cs_arch mode, cs_insn *ins)
+{
+ cs_arm64 *arm64 = &(ins->arm64);
+ int i;
+
+ if (arm64->op_count)
+ printf("\top_count: %u\n", arm64->op_count);
+
+ for (i = 0; i < arm64->op_count; i++) {
+ cs_arm64_op *op = &(arm64->operands[i]);
+ switch(op->type) {
+ default:
+ break;
+ case ARM64_OP_REG:
+ printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
+ break;
+ case ARM64_OP_IMM:
+ printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
+ break;
+ case ARM64_OP_FP:
+ printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
+ break;
+ case ARM64_OP_MEM:
+ printf("\t\toperands[%u].type: MEM\n", i);
+ if (op->mem.base != ARM64_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
+ if (op->mem.index != ARM64_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
+ if (op->mem.disp != 0)
+ printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
+
+ break;
+ case ARM64_OP_CIMM:
+ printf("\t\toperands[%u].type: C-IMM = %"PRIu64 "\n", i, op->imm);
+ break;
+ }
+
+ if (op->shift.type != ARM64_SFT_INVALID &&
+ op->shift.value)
+ printf("\t\t\tShift: type = %u, value = %u\n",
+ op->shift.type, op->shift.value);
+
+ if (op->ext != ARM64_EXT_INVALID)
+ printf("\t\t\tExt: %u\n", op->ext);
+ }
+
+ if (arm64->cc != ARM64_CC_INVALID)
+ printf("\tCode condition: %u\n", arm64->cc);
+
+ if (arm64->update_flags)
+ printf("\tUpdate-flags: True\n");
+
+ if (arm64->writeback)
+ printf("\tWrite-back: True\n");
+
+ printf("\n");
+}
+
+static void test()
+{
+//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
+//#define ARM64_CODE "\x21\x7c\x00\x53" // lsr w1, w1, #0x0
+//#define ARM64_CODE "\x21\x7c\x02\x9b"
+//#define ARM64_CODE "\x20\x04\x81\xda" // csneg x0, x1, x1, eq | cneg x0, x1, ne
+//#define ARM64_CODE "\x20\x08\x02\x8b" // add x0, x1, x2, lsl #2
+
+//#define ARM64_CODE "\x20\xcc\x20\x8b"
+//#define ARM64_CODE "\xe2\x8f\x40\xa9" // ldp x2, x3, [sp, #8]
+//#define ARM64_CODE "\x20\x40\x60\x1e" // fmov d0, d1
+//#define ARM64_CODE "\x20\x7c\x7d\x93" // sbfiz x0, x1, #3, #32
+
+//#define ARM64_CODE "\x20\x88\x43\xb3" // bfxil x0, x1, #3, #32
+//#define ARM64_CODE "\x01\x71\x08\xd5" // sys #0, c7, c1, #0, x1
+//#define ARM64_CODE "\x00\x71\x28\xd5" // sysl x0, #0, c7, c1, #0
+
+//#define ARM64_CODE "\x20\xf4\x18\x9e" // fcvtzs x0, s1, #3
+//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0: FIXME: handle as "sys" insn
+//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000
+//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
+//#define ARM64_CODE "\x20\x78\x62\xf8" // ldr x0, [x1, x2, lsl #3]
+//#define ARM64_CODE "\x41\x14\x44\xb3" // bfm x1, x2, #4, #5
+//#define ARM64_CODE "\x80\x23\x29\xd5" // sysl x0, #1, c2, c3, #4
+//#define ARM64_CODE "\x20\x00\x24\x1e" // fcvtas w0, s1
+//#define ARM64_CODE "\x41\x04\x40\xd2" // eor x1, x2, #0x3
+//#define ARM64_CODE "\x9f\x33\x03\xd5" // dsb osh
+//#define ARM64_CODE "\x41\x10\x23\x8a" // bic x1, x2, x3, lsl #4
+//#define ARM64_CODE "\x16\x41\x3c\xd5" // mrs x22, sp_el1
+//#define ARM64_CODE "\x41\x1c\x63\x0e" // bic v1.8b, v2.8b, v3.8b
+//#define ARM64_CODE "\x41\xd4\xe3\x6e" // fabd v1.2d, v2.2d, v3.2d
+//#define ARM64_CODE "\x20\x8c\x62\x2e" // cmeq v0.4h, v1.4h, v2.4h
+//#define ARM64_CODE "\x20\x98\x20\x4e" // cmeq v0.16b, v1.16b, #0
+//#define ARM64_CODE "\x20\x2c\x05\x4e" // smov x0, v1.b[2]
+//#define ARM64_CODE "\x21\xe4\x00\x2f" // movi d1, #0xff
+//#define ARM64_CODE "\x60\x78\x08\xd5" // at s1e0w, x0 // FIXME: same problem with dc ZVA
+//#define ARM64_CODE "\x20\x00\xa0\xf2" // movk x0, #1, lsl #16
+//#define ARM64_CODE "\x20\x08\x00\xb1" // adds x0, x1, #0x2
+//#define ARM64_CODE "\x41\x04\x00\x0f" // movi v1.2s, #0x2
+//#define ARM64_CODE "\x06\x00\x00\x14" // b 0x44
+//#define ARM64_CODE "\x00\x90\x24\x1e" // fmov s0, ##10.00000000
+//#define ARM64_CODE "\x5f\x3f\x03\xd5" // clrex
+//#define ARM64_CODE "\x5f\x3e\x03\xd5" // clrex #14
+//#define ARM64_CODE "\x20\x00\x02\xab" // adds x0, x1, x2 (alias of adds x0, x1, x2, lsl #0)
+#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_ARM64,
+ .mode = CS_MODE_ARM,
+ .code = ARM64_CODE,
+ .size = sizeof(ARM64_CODE) - 1,
+ .comment = "ARM-64"
+ },
+ };
+
+ uint64_t address = 0x2c;
+ //cs_insn insn[16];
+ cs_insn *insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
+ return;
+
+ //uint64_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ print_insn_detail(platforms[i].mode, &insn[j]);
+ }
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}
+
diff --git a/tests/test_detail.c b/tests/test_detail.c
new file mode 100644
index 0000000..0254f2e
--- /dev/null
+++ b/tests/test_detail.c
@@ -0,0 +1,212 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static void print_string_hex(char *str, int len)
+{
+ char *c;
+
+ printf("Code: ");
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+ printf("\n");
+}
+
+static void test()
+{
+#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
+#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
+#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
+//#define ARM_CODE "\x04\xe0\x2d\xe5"
+#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
+#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
+#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
+#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
+#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
+//#define MIPS_CODE "\x21\x38\x00\x01"
+//#define MIPS_CODE "\x21\x30\xe6\x70"
+#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
+//#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
+//#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
+//#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
+//#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
+#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_16,
+ .code = X86_CODE16,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 16bit (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32bit (ATT syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32 (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_64,
+ .code = X86_CODE64,
+ .size = sizeof(X86_CODE64) - 1,
+ .comment = "X86 64 (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_ARM,
+ .code = ARM_CODE,
+ .size = sizeof(ARM_CODE) - 1,
+ .comment = "ARM"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE2,
+ .size = sizeof(THUMB_CODE2) - 1,
+ .comment = "THUMB-2"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_ARM,
+ .code = ARM_CODE2,
+ .size = sizeof(ARM_CODE2) - 1,
+ .comment = "ARM: Cortex-A15 + NEON"
+ },
+ {
+ .arch = CS_ARCH_ARM,
+ .mode = CS_MODE_THUMB,
+ .code = THUMB_CODE,
+ .size = sizeof(THUMB_CODE) - 1,
+ .comment = "THUMB"
+ },
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_32 + CS_MODE_BIG_ENDIAN,
+ .code = MIPS_CODE,
+ .size = sizeof(MIPS_CODE) - 1,
+ .comment = "MIPS-32 (Big-endian)"
+ },
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_64+ CS_MODE_LITTLE_ENDIAN,
+ .code = MIPS_CODE2,
+ .size = sizeof(MIPS_CODE2) - 1,
+ .comment = "MIPS-64-EL (Little-endian)"
+ },
+ {
+ .arch = CS_ARCH_ARM64,
+ .mode = CS_MODE_ARM,
+ .code = ARM64_CODE,
+ .size = sizeof(ARM64_CODE) - 1,
+ .comment = "ARM-64"
+ },
+ };
+
+ csh handle;
+ uint64_t address = 0x1000;
+ //cs_insn all_insn[16];
+ cs_insn *all_insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
+ return;
+
+ //uint64_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, all_insn);
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex(platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ int n;
+ for (j = 0; j < count; j++) {
+ cs_insn *i = &(all_insn[j]);
+ printf("0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
+ i->address, i->mnemonic, i->op_str,
+ i->id, cs_insn_name(handle, i->id));
+
+ // print implicit registers used by this instruction
+ if (i->regs_read[0] != 0) {
+ printf("\tImplicit registers read: ");
+ for (n = 0; n < 32; n++) {
+ if (i->regs_read[n] == 0)
+ break;
+ printf("%s ", cs_reg_name(handle, i->regs_read[n]));
+ }
+ printf("\n");
+ }
+
+ // print implicit registers modified by this instruction
+ if (i->regs_write[0] != 0) {
+ printf("\tImplicit registers modified: ");
+ for (n = 0; n < 32; n++) {
+ if (i->regs_write[n] == 0)
+ break;
+ printf("%s ", cs_reg_name(handle, i->regs_write[n]));
+ }
+ printf("\n");
+ }
+
+ // print the groups this instruction belong to
+ if (i->groups[0] != 0) {
+ printf("\tThis instruction belongs to groups: ");
+ for (n = 0; n < 8; n++) {
+ if (i->groups[n] == 0)
+ break;
+ printf("%u ", i->groups[n]);
+ }
+ printf("\n");
+ }
+ }
+
+ // print out the next offset, after the last insn
+ printf("0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(all_insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex(platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}
diff --git a/tests/test_mips.c b/tests/test_mips.c
new file mode 100644
index 0000000..fbbd976
--- /dev/null
+++ b/tests/test_mips.c
@@ -0,0 +1,137 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static csh handle;
+
+static void print_string_hex(char *comment, char *str, int len)
+{
+ char *c;
+
+ printf("%s", comment);
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+
+ printf("\n");
+}
+
+static void print_insn_detail(cs_arch mode, cs_insn *ins)
+{
+ cs_mips *mips = &(ins->mips);
+
+ if (mips->op_count)
+ printf("\top_count: %u\n", mips->op_count);
+
+ int i;
+ for (i = 0; i < mips->op_count; i++) {
+ cs_mips_op *op = &(mips->operands[i]);
+ switch((int)op->type) {
+ default:
+ break;
+ case MIPS_OP_REG:
+ printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
+ break;
+ case MIPS_OP_IMM:
+ printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
+ break;
+ case MIPS_OP_MEM:
+ printf("\t\toperands[%u].type: MEM\n", i);
+ if (op->mem.base != X86_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+ i, cs_reg_name(handle, op->mem.base));
+ if (op->mem.disp != 0)
+ printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
+
+ break;
+ }
+
+ }
+
+ printf("\n");
+}
+
+static void test()
+{
+//#define MIPS_CODE "\x8f\xa2\x00\x00"
+//#define MIPS_CODE "\x00\x00\xa7\xac\x10\x00\xa2\x8f"
+//#define MIPS_CODE "\x21\x30\xe6\x70" // clo $6, $7
+//#define MIPS_CODE "\x00\x00\x00\x00" // nop
+//#define MIPS_CODE "\xc6\x23\xe9\xe4" // swc1 $f9, 0x23c6($7)
+//#define MIPS_CODE "\x21\x38\x00\x01" // move $7, $8
+#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
+#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_32 + CS_MODE_BIG_ENDIAN,
+ .code = MIPS_CODE,
+ .size = sizeof(MIPS_CODE) - 1,
+ .comment = "MIPS-32 (Big-endian)"
+ },
+ {
+ .arch = CS_ARCH_MIPS,
+ .mode = CS_MODE_64+ CS_MODE_LITTLE_ENDIAN,
+ .code = MIPS_CODE2,
+ .size = sizeof(MIPS_CODE2) - 1,
+ .comment = "MIPS-64-EL (Little-endian)"
+ },
+ };
+
+ uint64_t address = 0x1000;
+ cs_insn *insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
+ return;
+
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ print_insn_detail(platforms[i].mode, &insn[j]);
+ }
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}
diff --git a/tests/test_x86.c b/tests/test_x86.c
new file mode 100644
index 0000000..6453111
--- /dev/null
+++ b/tests/test_x86.c
@@ -0,0 +1,191 @@
+/* Second-Best Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+static csh handle;
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ char *code;
+ int size;
+ char *comment;
+};
+
+static void print_string_hex(char *comment, char *str, int len)
+{
+ char *c;
+
+ printf("%s", comment);
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+
+ printf("\n");
+}
+
+static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
+{
+ int i;
+ cs_x86 *x86 = &(ins->x86);
+
+ print_string_hex("\tPrefix:", (char *)x86->prefix, 5);
+
+ if (x86->segment != X86_REG_INVALID)
+ printf("\tSegment override: %s\n", cs_reg_name(handle, x86->segment));
+
+ print_string_hex("\tOpcode:", (char *)x86->opcode, 3);
+ printf("\top_size: %u, addr_size: %u, disp_size: %u, imm_size: %u\n", x86->op_size, x86->addr_size, x86->disp_size, x86->imm_size);
+ printf("\tmodrm: 0x%x\n", x86->modrm);
+ printf("\tdisp: 0x%x\n", x86->disp);
+
+ // SIB is not available in 16-bit mode
+ if ((mode & CS_MODE_16) == 0) {
+ printf("\tsib: 0x%x\n", x86->sib);
+ if (x86->sib_index != X86_REG_INVALID)
+ printf("\tsib_index: %s, sib_scale: %u, sib_base: %s\n",
+ cs_reg_name(handle, x86->sib_index),
+ x86->sib_scale,
+ cs_reg_name(handle, x86->sib_base));
+ }
+
+ int count = cs_op_count(ud, ins, X86_OP_IMM);
+ if (count) {
+ printf("\timm_count: %u\n", count);
+ for (i = 1; i < count + 1; i++) {
+ int index = cs_op_index(ud, ins, X86_OP_IMM, i);
+ printf("\t\timms[%u]: 0x%"PRIx64 "\n", i, x86->operands[index].imm);
+ }
+ }
+
+ if (x86->op_count)
+ printf("\top_count: %u\n", x86->op_count);
+ for (i = 0; i < x86->op_count; i++) {
+ cs_x86_op *op = &(x86->operands[i]);
+
+ switch((int)op->type) {
+ case X86_OP_REG:
+ printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
+ break;
+ case X86_OP_IMM:
+ printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
+ break;
+ case X86_OP_FP:
+ printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
+ break;
+ case X86_OP_MEM:
+ printf("\t\toperands[%u].type: MEM\n", i);
+ if (op->mem.base != 0)
+ printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
+ if (op->mem.index != 0)
+ printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
+ if (op->mem.scale != 1)
+ printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
+ if (op->mem.disp != 0)
+ printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
+ break;
+ default:
+ break;
+ }
+ }
+
+ printf("\n");
+}
+
+static void test()
+{
+//#define X86_CODE32 "\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x78\x56\x00\x00"
+//#define X86_CODE32 "\x05\x78\x56\x00\x00"
+//#define X86_CODE32 "\x01\xd8"
+//#define X86_CODE32 "\x05\x23\x01\x00\x00"
+//#define X86_CODE32 "\x8d\x87\x89\x67\x00\x00"
+//#define X86_CODE32 "\xa1\x13\x48\x6d\x3a\x8b\x81\x23\x01\x00\x00\x8b\x84\x39\x23\x01\x00\x00"
+//#define X86_CODE32 "\xb4\xc6" // mov ah, 0x6c
+//#define X86_CODE32 "\x77\x04" // ja +6
+#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
+
+#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
+//#define X86_CODE16 "\x67\x00\x18"
+#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
+
+ struct platform platforms[] = {
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_16,
+ .code = X86_CODE16,
+ .size = sizeof(X86_CODE16) - 1,
+ .comment = "X86 16bit (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32 (AT&T syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_32,
+ .code = X86_CODE32,
+ .size = sizeof(X86_CODE32) - 1,
+ .comment = "X86 32 (Intel syntax)"
+ },
+ {
+ .arch = CS_ARCH_X86,
+ .mode = CS_MODE_64,
+ .code = X86_CODE64,
+ .size = sizeof(X86_CODE64) - 1,
+ .comment = "X86 64 (Intel syntax)"
+ },
+ };
+
+ uint64_t address = 0x1000;
+ //cs_insn insn[16];
+ cs_insn *insn;
+ int i;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
+ return;
+
+ //uint64_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
+ uint64_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ uint64_t j;
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ print_insn_detail(handle, platforms[i].mode, &insn[j]);
+ }
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_dyn()
+ cs_free(insn);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}