commit 27f03c1b5dfbc219a4f6943411dc3fdee21c89e8
author Fotis Loukos <fotisl@users.noreply.github.com> Mon Jul 31 15:56:29 2017 +0300
committer Nguyen Anh Quynh <aquynh@gmail.com> Mon Jul 31 20:56:29 2017 +0800
tree f1e8f7b3e876142d5b0345bbc18b5e24854c085a
parent 26cb22a0ff99983c5e881b578eaadcd11c1fa408

Fixed bug in memory operand decoding. (#981)

Fixed bug #979. Decoding a memory operand with a register offset from
the B file would return an incorrect register.

arch/TMS320C64x/TMS320C64xDisassembler.c

diff --git a/arch/TMS320C64x/TMS320C64xDisassembler.c b/arch/TMS320C64x/TMS320C64xDisassembler.c
index 08e3651..836d513 100644
--- a/arch/TMS320C64x/TMS320C64xDisassembler.c
+++ b/arch/TMS320C64x/TMS320C64xDisassembler.c
@@ -289,7 +289,7 @@
 			if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31))
 				offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
 			else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31))
-				offset = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+				offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
 			offsetreg = getReg(GPRegsDecoderTable, offset);
 			MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit);
 			break;