fix all the code in other non-X86 archs after the change made by commit 5329a6ffd485ce4b06305c1b104df5a0adab57e6
diff --git a/MCInst.h b/MCInst.h
index a167982..7ba0aec 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -85,58 +85,6 @@
void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
-// NOTE: this structure is a flatten version of cs_insn struct
-// Detail information of disassembled instruction
-typedef struct cs_insn_flat {
- // Instruction ID
- // Find the instruction id from header file of corresponding architecture,
- // such as arm.h for ARM, x86.h for X86, etc...
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- unsigned int id;
-
- // Address (EIP) of this instruction
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- uint64_t address;
-
- // Size of this instruction
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- uint16_t size;
- // Machine bytes of this instruction, with number of bytes indicated by @size above
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- uint8_t bytes[16];
-
- // Ascii text of instruction mnemonic
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- char mnemonic[32];
-
- // Ascii text of instruction operands
- // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
- char op_str[160];
-
- // NOTE: All information below is not available when CS_OPT_DETAIL = CS_OPT_OFF
-
- uint8_t regs_read[12]; // list of implicit registers read by this insn
- uint8_t regs_read_count; // number of implicit registers read by this insn
-
- uint8_t regs_write[20]; // list of implicit registers modified by this insn
- uint8_t regs_write_count; // number of implicit registers modified by this insn
-
- uint8_t groups[8]; // list of group this instruction belong to
- uint8_t groups_count; // number of groups this insn belongs to
-
- // Architecture-specific instruction info
- union {
- cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
- cs_arm64 arm64; // ARM64 architecture (aka AArch64)
- cs_arm arm; // ARM architecture (including Thumb/Thumb2)
- cs_mips mips; // MIPS architecture
- cs_ppc ppc; // PowerPC architecture
- cs_sparc sparc; // Sparc architecture
- cs_sysz sysz; // SystemZ architecture
- cs_xcore xcore; // XCore architecture
- };
-} cs_insn_flat;
-
/// MCInst - Instances of this class represent a single low-level machine
/// instruction.
struct MCInst {
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index b9b6864..0beb147 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -41,13 +41,13 @@
MI->csh->doing_mem = status;
if (status) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_MEM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.base = ARM64_REG_INVALID;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.index = ARM64_REG_INVALID;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = 0;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -78,9 +78,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -98,7 +98,7 @@
if (RmSize == 32) {
Ext = "uxtw";
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_UXTW;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ARM64_EXT_UXTW;
} else {
Ext = "lsl";
}
@@ -107,11 +107,11 @@
if (RmSize == 32) {
Ext = "sxtw";
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTW;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ARM64_EXT_SXTW;
} else {
Ext = "sxtx";
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = ARM64_EXT_SXTX;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ARM64_EXT_SXTX;
}
break;
default:
@@ -127,11 +127,11 @@
SStream_concat(O, " #%u", ShiftAmt);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = ShiftAmt;
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = ShiftAmt;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftAmt;
}
}
} else if (IsLSL) {
@@ -151,9 +151,9 @@
else
SStream_concat(O, "#%u"PRIu64, Imm12);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Imm12;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)Imm12;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
}
@@ -164,8 +164,8 @@
SStream_concat(O, ", lsl #12");
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = 12;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = 12;
}
}
@@ -178,9 +178,9 @@
else
SStream_concat(O, "%"PRIu64, imm);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -195,9 +195,9 @@
else
SStream_concat(O, "#%u", LSB);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = LSB;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -228,9 +228,9 @@
SStream_concat(O, "#%u", (ImmS - ImmR + 1));
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = ImmS - ImmR + 1;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = ImmS - ImmR + 1;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -240,9 +240,9 @@
SStream_concat(O, "c%"PRIu64, MCOperand_getImm(CRx));
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_CIMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)MCOperand_getImm(CRx);
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)MCOperand_getImm(CRx);
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -255,9 +255,9 @@
else
SStream_concat(O, "#%u", 64 - MCOperand_getImm(ScaleOp));
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - (int32_t)MCOperand_getImm(ScaleOp);
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = 64 - (int32_t)MCOperand_getImm(ScaleOp);
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -289,9 +289,9 @@
//o << '#' << format("%.8f", Val);
SStream_concat(O, "#%.8f", Val);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_FP;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].fp = Val;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = Val;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -299,9 +299,9 @@
{
SStream_concat(O, "#0.0");
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_FP;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].fp = 0;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = 0;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -310,7 +310,7 @@
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SStream_concat(O, A64CondCodeToString((A64CC_CondCodes)(MCOperand_getImm(MO))));
if (MI->csh->detail)
- MI->flat_insn.arm64.cc = MCOperand_getImm(MO) + 1;
+ MI->flat_insn->detail->arm64.cc = MCOperand_getImm(MO) + 1;
}
static void printLabelOperand(MCInst *MI, unsigned OpNum,
@@ -336,9 +336,9 @@
SImm += MI->address;
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)SImm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)SImm;
+ MI->flat_insn->detail->arm64.op_count++;
}
if (SImm >= 0) {
@@ -366,9 +366,9 @@
else
SStream_concat(O, "#%"PRIu64, Val);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Val;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)Val;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -387,11 +387,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = Imm;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = Imm;
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
}
@@ -421,8 +421,8 @@
else
SStream_concat(O, " #%u", imm);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = Shift + 1;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = imm;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = Shift + 1;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = imm;
}
}
@@ -438,9 +438,9 @@
else
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
if (MCOperand_getImm(ShiftMO) != 0) {
@@ -450,8 +450,8 @@
else
SStream_concat(O, ", lsl #%u", shift);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = shift;
}
}
@@ -474,9 +474,9 @@
else
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
}
@@ -527,9 +527,9 @@
else
SStream_concat(O, "lsl #%u", shift);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = shift;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = Ext - 4;
}
return;
}
@@ -548,7 +548,7 @@
}
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = Ext - 4;
MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(MO) != 0) {
unsigned int shift = (unsigned int)MCOperand_getImm(MO);
@@ -557,8 +557,8 @@
else
SStream_concat(O, " #%u", shift);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = shift;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = shift;
}
}
}
@@ -585,11 +585,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)res;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)res;
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)res;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)res;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
}
@@ -605,9 +605,9 @@
cs_mem_free(Name);
#endif
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_REG;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].reg = Reg;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -619,15 +619,15 @@
SStream_concat(O, getRegisterName(Reg));
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- if (MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.base == ARM64_REG_INVALID) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.base = Reg;
+ if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.index = Reg;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
}
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_REG;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].reg = Reg;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
@@ -646,11 +646,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)imm;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
} else {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
}
@@ -698,11 +698,11 @@
return;
SStream_concat(O, ", lsl");
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
} else {
SStream_concat(O, ", msl");
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_MSL;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_MSL;
}
if (Imm >= 0) {
@@ -718,7 +718,7 @@
}
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = (unsigned int)Imm;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = (unsigned int)Imm;
}
static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
@@ -726,9 +726,9 @@
SStream_concat(O, "#0");
// FIXME: vector ZERO
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 0;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = 0;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -746,9 +746,9 @@
else
SStream_concat(O, "#%u", Imm);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
@@ -767,7 +767,7 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = Imm;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = Imm;
} else {
// FIXME: never has false branch??
}
@@ -796,9 +796,9 @@
else
SStream_concat(O, "#%"PRIu64, Mask);
if (MI->csh->detail) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Mask;
- MI->flat_insn.arm64.op_count++;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int32_t)Mask;
+ MI->flat_insn->detail->arm64.op_count++;
}
}
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index cfd9f4a..1d0c73f 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -127,14 +127,14 @@
MI->csh->doing_mem = status;
if (status) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_MEM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = ARM_REG_INVALID;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = ARM_REG_INVALID;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.scale = 1;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = 0;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -179,9 +179,9 @@
SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
if (MI->csh->detail) {
if (MI->csh->doing_mem)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)ShOpc;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
}
if (ShOpc != ARM_AM_rrx) {
@@ -193,9 +193,9 @@
SStream_concat(O, ">");
if (MI->csh->detail) {
if (MI->csh->doing_mem)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = translateShiftImm(ShImm);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = translateShiftImm(ShImm);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
}
}
}
@@ -345,26 +345,26 @@
SStream_concat(O, "\t");
printRegName(MI->csh, O, MCOperand_getReg(Dst));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.op_count++;
}
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
return;
@@ -383,17 +383,17 @@
SStream_concat(O, "\t");
printRegName(MI->csh, O, MCOperand_getReg(Dst));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.op_count++;
}
if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
@@ -409,9 +409,9 @@
SStream_concat(O, "#%u", tmp);
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type =
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
}
return;
}
@@ -440,9 +440,9 @@
SStream_concat(O, "\t{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
return;
@@ -473,9 +473,9 @@
SStream_concat(O, "\t{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
return;
@@ -521,9 +521,9 @@
SStream_concat(O, "\t");
printRegName(MI->csh, O, BaseReg);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = BaseReg;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
+ MI->flat_insn->detail->arm.op_count++;
}
if (Writeback)
SStream_concat(O, "!");
@@ -583,14 +583,14 @@
printRegName(MI->csh, O, Reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- if (MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base == ARM_REG_INVALID)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = Reg;
+ if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = Reg;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
} else {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
+ MI->flat_insn->detail->arm.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
@@ -635,11 +635,11 @@
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
if (MI->csh->doing_mem)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = imm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
else {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = imm;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
+ MI->flat_insn->detail->arm.op_count++;
}
}
}
@@ -670,12 +670,12 @@
SStream_concat(O, "]%s", markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_MEM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = ARM_REG_PC;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = ARM_REG_INVALID;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.scale = 1;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -694,11 +694,11 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
+ MI->flat_insn->detail->arm.op_count++;
}
// Print the shift opc.
@@ -711,7 +711,7 @@
SStream_concat(O, " ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
}
@@ -722,11 +722,11 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
+ MI->flat_insn->detail->arm.op_count++;
}
// Print the shift opc.
@@ -749,7 +749,7 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
}
if (!MCOperand_getReg(MO2)) {
@@ -761,8 +761,8 @@
else
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
}
SStream_concat(O, markup(">"));
}
@@ -775,7 +775,7 @@
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
}
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
@@ -792,11 +792,11 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@@ -809,15 +809,15 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, ", lsl %s #1%s]%s", markup("<imm:"), markup(">"), markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = ARM_SFT_LSL;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = 1;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
}
set_mem_access(MI, false);
}
@@ -850,9 +850,9 @@
ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
+ MI->flat_insn->detail->arm.op_count++;
}
return;
}
@@ -860,9 +860,9 @@
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.op_count++;
}
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
@@ -885,7 +885,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "], %s", markup(">"));
set_mem_access(MI, false);
@@ -893,9 +893,9 @@
SStream_concat(O, "%c", (char)op);
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.op_count++;
}
return;
}
@@ -911,14 +911,14 @@
markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
if (op)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -935,15 +935,15 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getReg(MO2)) {
SStream_concat(O, ", %s", ARM_AM_getAddrOpcStr(op));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
if (op)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.scale = -1;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
}
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -964,9 +964,9 @@
if (MI->csh->detail) {
if (op)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)MCOperand_getImm(MO3);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)MCOperand_getImm(MO3);
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)-MCOperand_getImm(MO3);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)-MCOperand_getImm(MO3);
}
SStream_concat(O, "]%s", markup(">"));
@@ -1006,9 +1006,9 @@
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getReg(MO1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.op_count++;
}
return;
}
@@ -1023,14 +1023,14 @@
ARM_AM_getAddrOpcStr(op), ImmOffs,
markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
if (op)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1045,9 +1045,9 @@
SStream_concat(O, "%s#%s%u%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
(Imm & 0xff), markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Imm & 0xff;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1059,9 +1059,9 @@
SStream_concat(O, (MCOperand_getImm(MO2) ? "" : "-"));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1092,11 +1092,11 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_MEM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = ARM_REG_INVALID;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.scale = 1;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = 0;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
}
ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
@@ -1111,13 +1111,13 @@
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
ImmOffs * 4, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = ImmOffs * 4;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
}
}
SStream_concat(O, "]%s", markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1131,7 +1131,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
tmp = (unsigned int)MCOperand_getImm(MO2);
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
@@ -1139,7 +1139,7 @@
else
SStream_concat(O, ":%u", (tmp << 3));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp << 3;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
}
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1152,7 +1152,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@@ -1166,9 +1166,9 @@
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
+ MI->flat_insn->detail->arm.op_count++;
}
}
}
@@ -1192,12 +1192,12 @@
SStream_concat(O, ", %s#%u%s", markup("<imm:"), width, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = lsb;
- MI->flat_insn.arm.op_count++;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = width;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
+ MI->flat_insn->detail->arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1228,8 +1228,8 @@
else
SStream_concat(O, ", asr %s#%u%s", markup("<imm:"), tmp, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ASR;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
}
} else if (Amt) {
if (Amt > HEX_THRESHOLD)
@@ -1237,8 +1237,8 @@
else
SStream_concat(O, ", lsl %s#%u%s", markup("<imm:"), Amt, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Amt;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
}
}
}
@@ -1254,8 +1254,8 @@
else
SStream_concat(O, ", lsl %s#%u%s", markup("<imm:"), Imm, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
}
}
@@ -1271,8 +1271,8 @@
else
SStream_concat(O, ", asr %s#%u%s", markup("<imm:"), Imm, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ASR;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
}
}
@@ -1285,9 +1285,9 @@
if (i != OpNum) SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
+ MI->flat_insn->detail->arm.op_count++;
}
}
SStream_concat(O, "}");
@@ -1299,16 +1299,16 @@
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1341,9 +1341,9 @@
SStream_concat(O, "none");
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = IFlags;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = IFlags;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1441,13 +1441,13 @@
if ((unsigned)CC == 15) {
SStream_concat(O, "<und>");
if (MI->csh->detail)
- MI->flat_insn.arm.cc = ARM_CC_INVALID;
+ MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
} else {
if (CC != ARMCC_AL) {
SStream_concat(O, ARMCC_ARMCondCodeToString(CC));
}
if (MI->csh->detail)
- MI->flat_insn.arm.cc = CC + 1;
+ MI->flat_insn->detail->arm.cc = CC + 1;
}
}
@@ -1457,7 +1457,7 @@
ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, ARMCC_ARMCondCodeToString(CC));
if (MI->csh->detail)
- MI->flat_insn.arm.cc = CC + 1;
+ MI->flat_insn->detail->arm.cc = CC + 1;
}
static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
@@ -1466,7 +1466,7 @@
//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
// "Expect ARM CPSR register!");
if (MI->csh->detail)
- MI->flat_insn.arm.update_flags = true;
+ MI->flat_insn->detail->arm.update_flags = true;
SStream_concat(O, "s");
}
}
@@ -1480,11 +1480,11 @@
SStream_concat(O, "%u", tmp);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
} else {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
}
}
@@ -1493,9 +1493,9 @@
{
SStream_concat(O, "p%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_PIMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1503,9 +1503,9 @@
{
SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_CIMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1517,9 +1517,9 @@
else
SStream_concat(O, "{%u}", tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1533,9 +1533,9 @@
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0");
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
+ MI->flat_insn->detail->arm.op_count++;
}
} else {
if (OffImm < 0)
@@ -1547,9 +1547,9 @@
SStream_concat(O, "#%u", OffImm);
}
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
+ MI->flat_insn->detail->arm.op_count++;
}
}
SStream_concat(O, markup(">"));
@@ -1563,9 +1563,9 @@
else
SStream_concat(O, "%s#%u", markup("<imm:"), tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, markup(">"));
}
@@ -1580,9 +1580,9 @@
SStream_concat(O, "%s#%u", markup("<imm:"), tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, markup(">"));
}
@@ -1622,13 +1622,13 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
RegNum = MCOperand_getReg(MO2);
if (RegNum) {
SStream_concat(O, ", ");
printRegName(MI->csh, O, RegNum);
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = RegNum;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
}
SStream_concat(O, "]");
set_mem_access(MI, false);
@@ -1652,7 +1652,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
ImmOffs = (unsigned int)MCOperand_getImm(MO2);
if (ImmOffs) {
tmp = ImmOffs * Scale;
@@ -1662,7 +1662,7 @@
else
SStream_concat(O, "#%u", tmp);
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
SStream_concat(O, markup(">"));
}
SStream_concat(O, "]");
@@ -1702,9 +1702,9 @@
unsigned Reg = MCOperand_getReg(MO1);
printRegName(MI->csh, O, Reg);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
+ MI->flat_insn->detail->arm.op_count++;
}
// Print the shift opc.
@@ -1732,7 +1732,7 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
@@ -1758,7 +1758,7 @@
}
}
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@@ -1776,7 +1776,7 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
@@ -1794,7 +1794,7 @@
}
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@@ -1817,7 +1817,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
@@ -1836,7 +1836,7 @@
SStream_concat(O, ", %s#%u%s", markup("<imm:"), OffImm, markup(">"));
}
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = OffImm;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1853,7 +1853,7 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getImm(MO2)) {
SStream_concat(O, ", ");
SStream_concat(O, markup("<imm:"));
@@ -1864,7 +1864,7 @@
SStream_concat(O, "#%u", tmp);
SStream_concat(O, markup(">"));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
}
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
@@ -1879,9 +1879,9 @@
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0%s", markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
+ MI->flat_insn->detail->arm.op_count++;
}
} else {
if (OffImm < 0) {
@@ -1896,9 +1896,9 @@
SStream_concat(O, "#%u%s", OffImm, markup(">"));
}
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
+ MI->flat_insn->detail->arm.op_count++;
}
}
}
@@ -1915,9 +1915,9 @@
if (OffImm == INT32_MIN) {
SStream_concat(O, "#-0%s", markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = 0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
+ MI->flat_insn->detail->arm.op_count++;
}
} else {
if (OffImm < 0) {
@@ -1932,9 +1932,9 @@
SStream_concat(O, "#%u%s", OffImm, markup(">"));
}
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = OffImm;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
+ MI->flat_insn->detail->arm.op_count++;
}
}
}
@@ -1951,13 +1951,13 @@
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
ShAmt = (unsigned int)MCOperand_getImm(MO3);
if (ShAmt) {
@@ -1967,8 +1967,8 @@
SStream_concat(O, "#%d", ShAmt);
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_LSL;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = ShAmt;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
}
}
@@ -1981,9 +1981,9 @@
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat((unsigned int)MCOperand_getImm(MO)), markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_FP;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -1997,9 +1997,9 @@
else
SStream_concat(O, "%s#%"PRIu64"%s", markup("<imm:"), Val, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)Val;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -2011,9 +2011,9 @@
else
SStream_concat(O, "%s#%u%s", markup("<imm:"), Imm + 1, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Imm + 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -2031,8 +2031,8 @@
}
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = ARM_SFT_ROR;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = Imm * 8;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
}
}
@@ -2047,9 +2047,9 @@
else
SStream_concat(O, "#%u", tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, markup(">"));
}
@@ -2065,9 +2065,9 @@
else
SStream_concat(O, "#%u", tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, markup(">"));
}
@@ -2080,9 +2080,9 @@
else
SStream_concat(O, "[%u]",tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
+ MI->flat_insn->detail->arm.op_count++;
}
}
@@ -2091,9 +2091,9 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2107,16 +2107,16 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2130,16 +2130,16 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2152,23 +2152,23 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2181,30 +2181,30 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2214,9 +2214,9 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2230,16 +2230,16 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2252,23 +2252,23 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2281,30 +2281,30 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2318,16 +2318,16 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2341,23 +2341,23 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2371,30 +2371,30 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "[]}");
}
@@ -2407,23 +2407,23 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
@@ -2436,30 +2436,30 @@
SStream_concat(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
- MI->flat_insn.arm.op_count++;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
+ MI->flat_insn->detail->arm.op_count++;
}
SStream_concat(O, "}");
}
diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c
index e27d2d3..1e7b07b 100644
--- a/arch/Mips/MipsInstPrinter.c
+++ b/arch/Mips/MipsInstPrinter.c
@@ -93,12 +93,12 @@
return;
if (status) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_MEM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = MIPS_REG_INVALID;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = 0;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn->detail->mips.op_count++;
}
}
@@ -230,11 +230,11 @@
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
} else {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_REG;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].reg = reg;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
+ MI->flat_insn->detail->mips.op_count++;
}
}
}
@@ -256,7 +256,7 @@
}
}
if (MI->csh->detail)
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
@@ -271,9 +271,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+ MI->flat_insn->detail->mips.op_count++;
}
}
}
@@ -296,9 +296,9 @@
SStream_concat(O, "-%u", (short int)-imm);
}
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = (unsigned short int)imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
+ MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
@@ -314,9 +314,9 @@
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
- MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
- MI->flat_insn.mips.op_count++;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+ MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index 8a1d542..0753f92 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -45,12 +45,12 @@
MI->csh->doing_mem = status;
if (status) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_MEM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.base = PPC_REG_INVALID;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = 0;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
@@ -139,7 +139,7 @@
{
unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
- MI->flat_insn.ppc.bc = (ppc_bc)Code;
+ MI->flat_insn->detail->ppc.bc = (ppc_bc)Code;
if (!strcmp(Modifier, "cc")) {
switch ((ppc_predicate)Code) {
@@ -247,9 +247,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
@@ -263,9 +263,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
@@ -279,9 +279,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Value;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
@@ -302,9 +302,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
+ MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
@@ -332,11 +332,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = Imm;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
} else {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
} else
@@ -353,9 +353,9 @@
SStream_concat(O, "%u", Imm);
if (MI->csh->detail) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = Imm;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
+ MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
@@ -504,11 +504,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.base = reg;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
} else {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_REG;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].reg = reg;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
@@ -531,11 +531,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].mem.disp = imm;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = imm;
} else {
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].type = PPC_OP_IMM;
- MI->flat_insn.ppc.operands[MI->flat_insn.ppc.op_count].imm = imm;
- MI->flat_insn.ppc.op_count++;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
+ MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
+ MI->flat_insn->detail->ppc.op_count++;
}
}
}
diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c
index 6f12086..4882826 100644
--- a/arch/Sparc/SparcInstPrinter.c
+++ b/arch/Sparc/SparcInstPrinter.c
@@ -43,12 +43,12 @@
MI->csh->doing_mem = status;
if (status) {
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_MEM;
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = SPARC_REG_INVALID;
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = 0;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
- MI->flat_insn.sparc.op_count++;
+ MI->flat_insn->detail->sparc.op_count++;
}
}
@@ -148,14 +148,14 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- if (MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base)
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.index = reg;
+ if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
else
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.base = reg;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
} else {
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_REG;
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].reg = reg;
- MI->flat_insn.sparc.op_count++;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
+ MI->flat_insn->detail->sparc.op_count++;
}
}
@@ -178,11 +178,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].mem.disp = Imm;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].type = SPARC_OP_IMM;
- MI->flat_insn.sparc.operands[MI->flat_insn.sparc.op_count].imm = Imm;
- MI->flat_insn.sparc.op_count++;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
+ MI->flat_insn->detail->sparc.op_count++;
}
}
}
@@ -248,7 +248,7 @@
SStream_concat(O, "%s", SPARCCondCodeToString((sparc_cc)CC));
if (MI->csh->detail)
- MI->flat_insn.sparc.cc = (sparc_cc)CC;
+ MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
}
diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c
index bc15f48..e39e67c 100644
--- a/arch/SystemZ/SystemZInstPrinter.c
+++ b/arch/SystemZ/SystemZInstPrinter.c
@@ -59,15 +59,15 @@
SStream_concat(O, "%%%s, ", getRegisterName(Index));
SStream_concat(O, "%%%s)", getRegisterName(Base));
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_MEM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.disp = Disp;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
+ MI->flat_insn->detail->sysz.op_count++;
} else if (!Index) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = Disp;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -81,9 +81,9 @@
reg = SystemZ_map_register(reg);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_REG;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].reg = reg;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg;
+ MI->flat_insn->detail->sysz.op_count++;
}
} else if (MCOperand_isImm(MO)) {
int64_t Imm = MCOperand_getImm(MO);
@@ -101,9 +101,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = Imm;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
}
@@ -125,9 +125,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -142,9 +142,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -166,9 +166,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -183,9 +183,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -207,9 +207,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -224,9 +224,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -248,9 +248,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -265,9 +265,9 @@
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -278,9 +278,9 @@
SStream_concat(O, "%%a%u", (unsigned int)Value);
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_ACREG;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].reg = (unsigned int)Value;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_ACREG;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = (unsigned int)Value;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
@@ -304,9 +304,9 @@
}
if (MI->csh->detail) {
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = (int64_t)imm;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)imm;
+ MI->flat_insn->detail->sysz.op_count++;
}
}
}
@@ -349,11 +349,11 @@
SStream_concat(O, ", %%%s", getRegisterName(Base));
SStream_concat(O, ")");
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_MEM;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.length = Length;
- MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.disp = (int64_t)Disp;
- MI->flat_insn.sysz.op_count++;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
+ MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
+ MI->flat_insn->detail->sysz.op_count++;
}
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
@@ -368,7 +368,7 @@
SStream_concat(O, CondNames[Imm - 1]);
if (MI->csh->detail)
- MI->flat_insn.sysz.cc = (sysz_cc)Imm;
+ MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm;
}
#define PRINT_ALIAS_INSTR
diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c
index 9f48623..aaf951a 100644
--- a/arch/XCore/XCoreInstPrinter.c
+++ b/arch/XCore/XCoreInstPrinter.c
@@ -67,9 +67,9 @@
id = XCore_reg_id(p);
if (id) {
// register
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_REG;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg = id;
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+ MI->flat_insn->detail->xcore.op_count++;
}
// next should be register, or memory?
// skip space
@@ -87,11 +87,11 @@
id = XCore_reg_id(p2);
if (id) {
// base register
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_MEM;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = id;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
p++;
p2 = p;
@@ -104,23 +104,23 @@
id = XCore_reg_id(p2);
if (id) {
// index register
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = id;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id;
} else {
// a number means disp
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = atoi(p2);
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
}
}
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.op_count++;
}
} else {
// a register?
id = XCore_reg_id(p2);
if (id) {
// register
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_REG;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg = id;
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+ MI->flat_insn->detail->xcore.op_count++;
}
}
}
@@ -128,9 +128,9 @@
id = XCore_reg_id(p);
if (id) {
// register
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_REG;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg = id;
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+ MI->flat_insn->detail->xcore.op_count++;
}
}
}
@@ -144,33 +144,33 @@
MI->csh->doing_mem = status;
if (status) {
if (reg != 0xffff && reg != -0xffff) {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_MEM;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
if (reg) {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
} else {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = XCORE_REG_INVALID;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID;
}
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
} else {
// the last op should be the memory base
- MI->flat_insn.xcore.op_count--;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_MEM;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
+ MI->flat_insn->detail->xcore.op_count--;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
if (reg > 0)
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
else
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = -1;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1;
}
} else {
if (reg) {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
}
// done, create the next operand slot
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.op_count++;
}
}
@@ -184,14 +184,14 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- if (MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base == ARM_REG_INVALID)
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = reg;
+ if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
else
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
} else {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_REG;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg = reg;
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;
+ MI->flat_insn->detail->xcore.op_count++;
}
}
} else if (MCOperand_isImm(MO)) {
@@ -211,11 +211,11 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = Imm;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm;
} else {
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_IMM;
- MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].imm = Imm;
- MI->flat_insn.xcore.op_count++;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm;
+ MI->flat_insn->detail->xcore.op_count++;
}
}
}