port Windows driver support
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index e2b3436..26eb786 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -629,7 +629,7 @@
Op2S = utostr(Op2, false);
//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
- dummy = sprintf(result, "s%s_%s_c%s_c%s_%s", Op0S, Op1S, CRnS, CRmS, Op2S);
+ dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
(void)dummy;
cs_mem_free(Op0S);
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 2d6e046..73859c1 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -21,7 +21,9 @@
#define CS_LLVM_AARCH64_BASEINFO_H
#include <ctype.h>
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include <string.h>
#ifndef __cplusplus
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index 87859a5..e1654e2 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -1165,9 +1165,9 @@
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
MCOperand_CreateImm0(Inst, offset);
- IsLoad = fieldFromInstruction(insn, 22, 1);
+ IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
- IsFP = fieldFromInstruction(insn, 26, 1);
+ IsFP = fieldFromInstruction(insn, 26, 1) != 0;
// Cannot write back to a transfer register (but xzr != sp).
if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
@@ -1260,7 +1260,7 @@
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
int32_t offset = fieldFromInstruction(insn, 15, 7);
- bool IsLoad = fieldFromInstruction(insn, 22, 1);
+ bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
unsigned Opcode = MCInst_getOpcode(Inst);
bool NeedsDisjointWritebackTransfer = false;
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
index a115140..c669f4e 100644
--- a/arch/AArch64/AArch64Disassembler.h
+++ b/arch/AArch64/AArch64Disassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_AARCH64_DISASSEMBLER_H
#define CS_AARCH64_DISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 1bb7ad0..7c5a26d 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -16,7 +16,7 @@
#ifdef CAPSTONE_HAS_ARM64
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
@@ -1656,7 +1656,7 @@
static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
{
- unsigned RawVal = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
SStream_concat(O, "#%#016llx", Val);
if (MI->csh->detail) {
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index 5b9746c..03d9eb4 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -1049,26 +1049,26 @@
switch((int)op->type) {
case ARM64_OP_REG:
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
- regs_read[read_count] = op->reg;
+ regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
- regs_write[write_count] = op->reg;
+ regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case ARM_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
- regs_read[read_count] = op->mem.base;
+ regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
- regs_read[read_count] = op->mem.index;
+ regs_read[read_count] = (uint16_t)op->mem.index;
read_count++;
}
if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
- regs_write[write_count] = op->mem.base;
+ regs_write[write_count] = (uint16_t)op->mem.base;
write_count++;
}
default:
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index 8e700b1..0390112 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -15,7 +15,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include "ARMAddressingModes.h"
#include "ARMBaseInfo.h"
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index 4f10cef..95ed9fb 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -19,7 +19,7 @@
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include "ARMInstPrinter.h"
#include "ARMAddressingModes.h"
@@ -1792,7 +1792,7 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm.op_count--;
- MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = tmp;
+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp;
MI->ac_idx--; // consecutive operands share the same access right
} else {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index 642330e..e6b27f2 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -915,26 +915,26 @@
switch((int)op->type) {
case ARM_OP_REG:
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
- regs_read[read_count] = op->reg;
+ regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
- regs_write[write_count] = op->reg;
+ regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case ARM_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
- regs_read[read_count] = op->mem.base;
+ regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
- regs_read[read_count] = op->mem.index;
+ regs_read[read_count] = (uint16_t)op->mem.index;
read_count++;
}
if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
- regs_write[write_count] = op->mem.base;
+ regs_write[write_count] = (uint16_t)op->mem.base;
write_count++;
}
default:
diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c
index a73a65b..faaabc0 100644
--- a/arch/M68K/M68KDisassembler.c
+++ b/arch/M68K/M68KDisassembler.c
@@ -48,8 +48,12 @@
#include "M68KDisassembler.h"
#ifndef DECL_SPEC
+#ifdef _MSC_VER
+#define DECL_SPEC __cdecl
+#else
#define DECL_SPEC
-#endif
+#endif // _MSC_VER
+#endif // DECL_SPEC
/* ======================================================================== */
/* ============================ GENERAL DEFINES =========================== */
@@ -458,7 +462,7 @@
/* address register indirect with displacement*/
op->address_mode = M68K_AM_REGI_ADDR_DISP;
op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
- op->mem.disp = read_imm_16(info);
+ op->mem.disp = (uint16_t)read_imm_16(info);
break;
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
@@ -481,7 +485,7 @@
case 0x3a:
/* program counter with displacement */
op->address_mode = M68K_AM_PCI_DISP;
- op->mem.disp = read_imm_16(info);
+ op->mem.disp = (uint16_t)read_imm_16(info);
break;
case 0x3b:
@@ -517,7 +521,7 @@
ext = &info->extension;
- ext->op_count = count;
+ ext->op_count = (uint8_t)count;
ext->op_size.type = M68K_SIZE_TYPE_CPU;
ext->op_size.cpu_size = size;
@@ -836,7 +840,7 @@
if (BIT_5(extension))
width = extension & 7;
else
- width = g_5bit_data_table[extension & 31];
+ width = (uint8_t)g_5bit_data_table[extension & 31];
if (has_d_arg) {
ext->op_count = 2;
@@ -1100,7 +1104,7 @@
op1->address_mode = M68K_AM_REGI_ADDR_DISP;
op1->type = M68K_OP_MEM;
op1->mem.base_reg = M68K_REG_A0 + (info->ir & 7);
- op1->mem.disp = read_imm_16(info);
+ op1->mem.disp = (uint16_t)read_imm_16(info);
}
static void build_movep_er(m68k_info *info, int size)
@@ -1115,7 +1119,7 @@
op0->address_mode = M68K_AM_REGI_ADDR_DISP;
op0->type = M68K_OP_MEM;
op0->mem.base_reg = M68K_REG_A0 + (info->ir & 7);
- op0->mem.disp = read_imm_16(info);
+ op0->mem.disp = (uint16_t)read_imm_16(info);
op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7);
}
diff --git a/arch/M68K/M68KDisassembler.h b/arch/M68K/M68KDisassembler.h
index a1cbc03..62f4c01 100644
--- a/arch/M68K/M68KDisassembler.h
+++ b/arch/M68K/M68KDisassembler.h
@@ -5,7 +5,10 @@
#define CS_M68KDISASSEMBLER_H
#include "../../MCInst.h"
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
/* Private, For internal use only */
typedef struct m68k_info {
diff --git a/arch/M68K/M68KInstPrinter.h b/arch/M68K/M68KInstPrinter.h
index 9cc4373..ac96afd 100644
--- a/arch/M68K/M68KInstPrinter.h
+++ b/arch/M68K/M68KInstPrinter.h
@@ -4,7 +4,9 @@
#ifndef CS_M68KINSTPRINTER_H
#define CS_M68KINSTPRINTER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 4f80934..846115f 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -19,7 +19,7 @@
#include <stdio.h>
#include <string.h>
-#include "../../myinttypes.h"
+#include "capstone/platform.h"
#include "../../utils.h"
diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c
index 844437a..e97bf4d 100644
--- a/arch/Mips/MipsInstPrinter.c
+++ b/arch/Mips/MipsInstPrinter.c
@@ -16,7 +16,7 @@
#ifdef CAPSTONE_HAS_MIPS
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include <stdlib.h>
#include <stdio.h> // debug
#include <string.h>
diff --git a/arch/PowerPC/PPCDisassembler.h b/arch/PowerPC/PPCDisassembler.h
index f71eb1f..946f3f7 100644
--- a/arch/PowerPC/PPCDisassembler.h
+++ b/arch/PowerPC/PPCDisassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_PPCDISASSEMBLER_H
#define CS_PPCDISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/PowerPC/PPCGenAsmWriter.inc b/arch/PowerPC/PPCGenAsmWriter.inc
index 16f5fd1..447bd04 100644
--- a/arch/PowerPC/PPCGenAsmWriter.inc
+++ b/arch/PowerPC/PPCGenAsmWriter.inc
@@ -10,7 +10,7 @@
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#include <stdio.h> // debug
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index a9fd936..45680ec 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -19,7 +19,6 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "../../myinttypes.h"
#include "PPCInstPrinter.h"
#include "PPCPredicates.h"
diff --git a/arch/Sparc/SparcDisassembler.c b/arch/Sparc/SparcDisassembler.c
index aa23fe8..78d9333 100644
--- a/arch/Sparc/SparcDisassembler.c
+++ b/arch/Sparc/SparcDisassembler.c
@@ -251,7 +251,7 @@
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
- bool isImm = fieldFromInstruction_4(insn, 13, 1);
+ bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
unsigned rs2 = 0;
unsigned simm13 = 0;
diff --git a/arch/Sparc/SparcDisassembler.h b/arch/Sparc/SparcDisassembler.h
index 353bd8d..49ac375 100644
--- a/arch/Sparc/SparcDisassembler.h
+++ b/arch/Sparc/SparcDisassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_SPARCDISASSEMBLER_H
#define CS_SPARCDISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/Sparc/SparcGenAsmWriter.inc b/arch/Sparc/SparcGenAsmWriter.inc
index 1b8562c..9ed9760 100644
--- a/arch/Sparc/SparcGenAsmWriter.inc
+++ b/arch/Sparc/SparcGenAsmWriter.inc
@@ -10,7 +10,7 @@
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#include <stdio.h> // debug
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
/// printInstruction - This method is automatically generated by tablegen
diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c
index 68826cf..ba2a315 100644
--- a/arch/Sparc/SparcInstPrinter.c
+++ b/arch/Sparc/SparcInstPrinter.c
@@ -81,7 +81,7 @@
if (insn->id == SPARC_INS_CASX) {
// first op is actually a memop, not regop
insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
- insn->detail->sparc.operands[0].mem.base = insn->detail->sparc.operands[0].reg;
+ insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
insn->detail->sparc.operands[0].mem.disp = 0;
}
}
@@ -172,9 +172,9 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
- MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
else
- MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
+ MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
diff --git a/arch/SystemZ/SystemZDisassembler.h b/arch/SystemZ/SystemZDisassembler.h
index 1f29929..6785d7c 100644
--- a/arch/SystemZ/SystemZDisassembler.h
+++ b/arch/SystemZ/SystemZDisassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_SYSZDISASSEMBLER_H
#define CS_SYSZDISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/SystemZ/SystemZGenAsmWriter.inc b/arch/SystemZ/SystemZGenAsmWriter.inc
index 0cec420..73baaaa 100644
--- a/arch/SystemZ/SystemZGenAsmWriter.inc
+++ b/arch/SystemZ/SystemZGenAsmWriter.inc
@@ -10,7 +10,7 @@
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#include <stdio.h> // debug
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
/// printInstruction - This method is automatically generated by tablegen
diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c
index 67680f1..5a8f019 100644
--- a/arch/SystemZ/SystemZInstPrinter.c
+++ b/arch/SystemZ/SystemZInstPrinter.c
@@ -19,7 +19,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include "SystemZInstPrinter.h"
#include "../../MCInst.h"
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 16be0c6..0e82273 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -21,7 +21,7 @@
#if !defined(CAPSTONE_HAS_OSXKERNEL)
#include <ctype.h>
#endif
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
@@ -708,7 +708,7 @@
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
if (opsize > 0)
- MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = (uint8_t)opsize;
else if (MI->op1_size > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size;
else
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index 7ff165e..cd02d94 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -19,7 +19,7 @@
#ifdef CAPSTONE_HAS_X86
-#include "../../myinttypes.h" // debug
+#include <capstone/platform.h>
#include <string.h>
#include "../../cs_priv.h"
diff --git a/arch/X86/X86Disassembler.h b/arch/X86/X86Disassembler.h
index eae2fa8..10bdeb8 100644
--- a/arch/X86/X86Disassembler.h
+++ b/arch/X86/X86Disassembler.h
@@ -77,7 +77,9 @@
#ifndef CS_X86_DISASSEMBLER_H
#define CS_X86_DISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c
index 4038e2a..a4863f3 100644
--- a/arch/X86/X86DisassemblerDecoder.c
+++ b/arch/X86/X86DisassemblerDecoder.c
@@ -1094,7 +1094,7 @@
hasModRMExtension = modRMRequired(insn->opcodeType,
instructionClass,
- insn->opcode);
+ insn->opcode) != 0;
if (hasModRMExtension) {
if (readModRM(insn))
diff --git a/arch/X86/X86DisassemblerDecoder.h b/arch/X86/X86DisassemblerDecoder.h
index 2fccdd1..777fb90 100644
--- a/arch/X86/X86DisassemblerDecoder.h
+++ b/arch/X86/X86DisassemblerDecoder.h
@@ -24,7 +24,9 @@
#else
#include <stdio.h>
#endif
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "X86DisassemblerDecoderCommon.h"
diff --git a/arch/X86/X86DisassemblerDecoderCommon.h b/arch/X86/X86DisassemblerDecoderCommon.h
index 8bd6a50..cc1549a 100644
--- a/arch/X86/X86DisassemblerDecoderCommon.h
+++ b/arch/X86/X86DisassemblerDecoderCommon.h
@@ -25,7 +25,9 @@
#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H
#define CS_X86_DISASSEMBLERDECODERCOMMON_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
#define CONTEXTS_SYM x86DisassemblerContexts
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index a5a248f..247ab3a 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -20,7 +20,7 @@
#if !defined(CAPSTONE_HAS_OSXKERNEL)
#include <ctype.h>
#endif
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
@@ -787,7 +787,7 @@
if (MI->flat_insn->detail->x86.op_count > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
else if (opsize > 0)
- MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = (uint8_t)opsize;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
@@ -904,7 +904,7 @@
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
if (opsize > 0)
- MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = (uint8_t)opsize;
else if (MI->flat_insn->detail->x86.op_count > 0) {
if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size =
diff --git a/arch/XCore/XCoreDisassembler.h b/arch/XCore/XCoreDisassembler.h
index f72907a..e50fc55 100644
--- a/arch/XCore/XCoreDisassembler.h
+++ b/arch/XCore/XCoreDisassembler.h
@@ -4,7 +4,9 @@
#ifndef CS_XCOREDISASSEMBLER_H
#define CS_XCOREDISASSEMBLER_H
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
+#endif
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
diff --git a/arch/XCore/XCoreGenAsmWriter.inc b/arch/XCore/XCoreGenAsmWriter.inc
index 85c2fee..95babb2 100644
--- a/arch/XCore/XCoreGenAsmWriter.inc
+++ b/arch/XCore/XCoreGenAsmWriter.inc
@@ -10,7 +10,7 @@
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#include <stdio.h> // debug
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
/// printInstruction - This method is automatically generated by tablegen
diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c
index c4c741f..c050c58 100644
--- a/arch/XCore/XCoreInstPrinter.c
+++ b/arch/XCore/XCoreInstPrinter.c
@@ -19,7 +19,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "../../myinttypes.h"
+#include <capstone/platform.h>
#include "XCoreInstPrinter.h"
#include "../../MCInst.h"
@@ -91,7 +91,7 @@
// base register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
@@ -109,7 +109,7 @@
if (id) {
// index register
if (MI->csh->detail) {
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
}
} else {
// a number means disp
@@ -160,7 +160,7 @@
if (reg != 0xffff && reg != -0xffff) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
if (reg) {
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID;
}
@@ -171,7 +171,7 @@
// the last op should be the memory base
MI->flat_insn->detail->xcore.op_count--;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
if (reg > 0)
@@ -181,7 +181,7 @@
}
} else {
if (reg) {
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
// done, create the next operand slot
MI->flat_insn->detail->xcore.op_count++;
}
@@ -199,9 +199,9 @@
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
else
- MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
+ MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;