Initial set of changes to support building with MSVC 2013. Right now there's a bunch fo assumptions in the .vcxproj file and some things are not as clean as they should be, but it does build a full build and works (at least the x86 side). The point of this initial checkpoint is to make sure that nothing breaks on the GCC side, that everyone is ok with the changes to the source (or if better fixes/typing can be done).
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index 510813f..e95e0ff 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -41,7 +41,7 @@
{
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
- *c = tolower((int) *c);
+ *c = (char)tolower((int) *c);
bool res = (strcmp(s1, lower) == 0);
cs_mem_free(lower);
@@ -60,7 +60,7 @@
}
*Valid = false;
- return -1;
+ return (uint32_t)-1;
}
bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value)
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index b1a67e3..64b9c9b 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -215,9 +215,14 @@
static uint64_t getFeatureBits(int feature)
{
// enable all features
- return -1;
+ return (uint64_t)-1;
}
+#ifdef _MSC_VER
+#pragma warning(disable:4242)
+#pragma warning(disable:4244)
+#pragma warning(disable:4706)
+#endif
#include "AArch64GenDisassemblerTables.inc"
#define GET_INSTRINFO_ENUM
@@ -308,10 +313,12 @@
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -320,10 +327,12 @@
DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -332,10 +341,12 @@
uint64_t Address,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -344,10 +355,12 @@
DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -356,10 +369,12 @@
DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -368,10 +383,12 @@
DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -381,10 +398,12 @@
DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -393,10 +412,12 @@
DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -415,10 +436,12 @@
DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -438,10 +461,12 @@
uint64_t Address,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 30)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
+ Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -450,10 +475,12 @@
unsigned RegID,
void *Decoder)
{
+ uint16_t Register;
+
if (RegNo > 31)
return MCDisassembler_Fail;
- uint16_t Register = getReg(Decoder, RegID, RegNo);
+ Register = getReg(Decoder, RegID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 21dc187..0f42023 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -61,7 +61,7 @@
static void printOffsetSImm9Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
- int32_t Imm = unpackSignedImm(9, MCOperand_getImm(MOImm));
+ int32_t Imm = (int32_t)unpackSignedImm(9, MCOperand_getImm(MOImm));
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -78,7 +78,7 @@
static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
SStream *O, unsigned MemSize, unsigned RmSize)
{
- unsigned ExtImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned ExtImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned OptionHi = ExtImm >> 1;
unsigned S = ExtImm & 1;
bool IsLSL = OptionHi == 1 && RmSize == 64;
@@ -143,7 +143,7 @@
SStream_concat(O, "#%u"PRIu64, Imm12);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm12;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Imm12;
MI->flat_insn.arm64.op_count++;
}
}
@@ -170,7 +170,7 @@
SStream_concat(O, "%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -179,7 +179,7 @@
SStream *O, unsigned RegWidth)
{
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum);
- unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - MCOperand_getImm(ImmROp);
+ unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - (unsigned int)MCOperand_getImm(ImmROp);
if (LSB > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", LSB);
@@ -195,7 +195,7 @@
static void printBFIWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
- unsigned Width = MCOperand_getImm(ImmSOp) + 1;
+ unsigned Width = (unsigned int)MCOperand_getImm(ImmSOp) + 1;
if (Width > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Width);
@@ -208,8 +208,8 @@
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum - 1);
- unsigned ImmR = MCOperand_getImm(ImmROp);
- unsigned ImmS = MCOperand_getImm(ImmSOp);
+ unsigned ImmR = (unsigned int)MCOperand_getImm(ImmROp);
+ unsigned ImmS = (unsigned int)MCOperand_getImm(ImmSOp);
//assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
@@ -232,7 +232,7 @@
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_CIMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = MCOperand_getImm(CRx);
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)MCOperand_getImm(CRx);
MI->flat_insn.arm64.op_count++;
}
}
@@ -247,7 +247,7 @@
SStream_concat(O, "#%u", 64 - MCOperand_getImm(ScaleOp));
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - MCOperand_getImm(ScaleOp);
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - (int32_t)MCOperand_getImm(ScaleOp);
MI->flat_insn.arm64.op_count++;
}
}
@@ -259,7 +259,7 @@
//assert(MOImm8.isImm()
// && "Immediate operand required for floating-point immediate inst");
- uint32_t Imm8 = MCOperand_getImm(MOImm8);
+ uint32_t Imm8 = (uint32_t)MCOperand_getImm(MOImm8);
uint32_t Fraction = Imm8 & 0xf;
uint32_t Exponent = (Imm8 >> 4) & 0x7;
uint32_t Negative = (Imm8 >> 7) & 0x1;
@@ -326,7 +326,7 @@
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = SImm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)SImm;
MI->flat_insn.arm64.op_count++;
}
@@ -341,14 +341,14 @@
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint64_t Val;
- A64Imms_isLogicalImmBits(RegWidth, MCOperand_getImm(MO), &Val);
+ A64Imms_isLogicalImmBits(RegWidth, (uint32_t)MCOperand_getImm(MO), &Val);
if (Val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, Val);
else
SStream_concat(O, "#%"PRIu64, Val);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Val;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Val;
MI->flat_insn.arm64.op_count++;
}
}
@@ -359,7 +359,7 @@
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MOImm)) {
- uint32_t Imm = MCOperand_getImm(MOImm) * MemSize;
+ uint32_t Imm = (uint32_t)MCOperand_getImm(MOImm) * MemSize;
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -395,7 +395,7 @@
default: break; // llvm_unreachable("Invalid shift specifier in logical instruction");
}
- unsigned int imm = MCOperand_getImm(MO);
+ unsigned int imm = (unsigned int)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", imm);
else
@@ -419,12 +419,12 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
if (MCOperand_getImm(ShiftMO) != 0) {
- unsigned int shift = MCOperand_getImm(ShiftMO) * 16;
+ unsigned int shift = (unsigned int)MCOperand_getImm(ShiftMO) * 16;
if (shift > HEX_THRESHOLD)
SStream_concat(O, ", lsl #0x%x", shift);
else
@@ -443,7 +443,7 @@
{
bool ValidName;
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- char *Name = NamedImmMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName);
+ char *Name = NamedImmMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName);
if (ValidName)
SStream_concat(O, Name);
@@ -455,7 +455,7 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -469,7 +469,7 @@
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- SysRegMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName, Name);
+ SysRegMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName, Name);
if (ValidName) {
SStream_concat(O, Name);
}
@@ -490,6 +490,7 @@
// easily. We will only accumulate more of these hacks.
unsigned Reg0 = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
+ MCOperand *MO;
if (isStackReg(Reg0) || isStackReg(Reg1)) {
A64SE_ShiftExtSpecifiers LSLEquiv;
@@ -500,7 +501,7 @@
LSLEquiv = A64SE_UXTW;
if (Ext == LSLEquiv) {
- unsigned int shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned int shift = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (shift > HEX_THRESHOLD)
SStream_concat(O, "lsl #0x%x", shift);
else
@@ -528,9 +529,9 @@
if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
- MCOperand *MO = MCInst_getOperand(MI, OpNum);
+ MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(MO) != 0) {
- unsigned int shift = MCOperand_getImm(MO);
+ unsigned int shift = (unsigned int)MCOperand_getImm(MO);
if (shift > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", shift);
else
@@ -546,7 +547,7 @@
SStream *O, int MemScale)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
- int32_t Imm = unpackSignedImm(7, MCOperand_getImm(MOImm));
+ int32_t Imm = (int32_t)unpackSignedImm(7, MCOperand_getImm(MOImm));
if (Imm * MemScale > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm * MemScale);
@@ -605,10 +606,10 @@
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)imm;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@@ -669,7 +670,7 @@
else
SStream_concat(O, " #%"PRIu64, Imm);
if (MI->csh->detail)
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = Imm;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = (unsigned int)Imm;
}
static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
@@ -690,7 +691,7 @@
//assert(MOUImm.isImm() &&
// "Immediate operand required for Neon vector immediate inst.");
- unsigned Imm = MCOperand_getImm(MOUImm);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@@ -710,7 +711,7 @@
//assert(MOUImm.isImm()
// && "Immediate operand required for Neon vector immediate inst.");
- unsigned Imm = MCOperand_getImm(MOUImm);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
@@ -732,7 +733,7 @@
//assert(MOUImm8.isImm() &&
// "Immediate operand required for Neon vector immediate bytemask inst.");
- uint32_t UImm8 = MCOperand_getImm(MOUImm8);
+ uint32_t UImm8 = (uint32_t)MCOperand_getImm(MOUImm8);
uint64_t Mask = 0;
// Replicates 0x00 or 0xff byte in a 64-bit vector
@@ -748,7 +749,7 @@
SStream_concat(O, "#%"PRIu64, Mask);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
- MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Mask;
+ MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Mask;
MI->flat_insn.arm64.op_count++;
}
}
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index ff608a5..3ecada2 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -2966,8 +2966,8 @@
// some alias instruction only need to be defined locally to satisfy
// some lookup functions
// just make sure these IDs never reuse any other IDs ARM_INS_*
-#define ARM64_INS_NEGS -1
-#define ARM64_INS_NGCS -2
+#define ARM64_INS_NEGS (unsigned short)-1
+#define ARM64_INS_NGCS (unsigned short)-2
// all alias instructions & their semantic infos
static insn_map alias_insns[] = {
@@ -3003,13 +3003,13 @@
handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV);
diff --git a/arch/AArch64/AArch64Module.c b/arch/AArch64/AArch64Module.c
index c3d18f6..83b4f4b 100644
--- a/arch/AArch64/AArch64Module.c
+++ b/arch/AArch64/AArch64Module.c
@@ -11,11 +11,13 @@
static cs_err init(cs_struct *ud)
{
+ MCRegisterInfo *mri;
+
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
- MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
+ mri = cs_mem_malloc(sizeof(*mri));
AArch64_init(mri);
ud->printer = AArch64_printInst;
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
index 0c14315..daf52e4 100644
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@@ -56,7 +56,7 @@
static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
{
switch (Op) {
- default: return -1; //llvm_unreachable("Unknown shift opc!");
+ default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!");
case ARM_AM_asr: return 2;
case ARM_AM_lsl: return 0;
case ARM_AM_lsr: return 1;
@@ -391,7 +391,7 @@
//assert (isT2SOImmTwoPartVal(Imm) &&
// "Immedate cannot be encoded as two part immediate!");
// Try a shifter operand as one part
- unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
+ unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
// If the rest is encodable as an immediate, then return it.
if (getT2SOImmVal(V) != -1) return V;
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index b487d0d..43bd467 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -93,7 +93,7 @@
//assert(NumTZ <= 3 && "Invalid IT mask!");
// push condition codes onto the stack the correct order for the pops
for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
- bool T = ((Mask >> Pos) & 1) == CondBit0;
+ bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
if (T)
ITStatus_push_back(it, CCBits);
else
@@ -364,7 +364,7 @@
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int mode)
{
- uint64_t Bits = -1; // everything by default
+ uint64_t Bits = (uint64_t)-1; // everything by default
// FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
Bits &= (~ARM_FeatureVFPOnlySP);
@@ -397,6 +397,11 @@
return Bits;
}
+#ifdef _MSC_VER
+#pragma warning(disable:4242)
+#pragma warning(disable:4244)
+#pragma warning(disable:4706)
+#endif
#include "ARMGenDisassemblerTables.inc"
static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
@@ -564,6 +569,9 @@
static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
{
DecodeStatus S = MCDisassembler_Success;
+ MCOperandInfo *OpInfo;
+ unsigned short NumOps;
+ unsigned int i;
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
@@ -608,9 +616,9 @@
if (ITStatus_instrInITBlock(&(ud->ITBlock)))
ITStatus_advanceITState(&(ud->ITBlock));
- MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
- unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
- unsigned i;
+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+
for (i = 0; i < NumOps; ++i) {
if (i == MCInst_getNumOperands(MI)) break;
if (MCOperandInfo_isPredicate(&OpInfo[i])) {
@@ -640,13 +648,17 @@
static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
{
unsigned CC;
+ unsigned short NumOps;
+ MCOperandInfo *OpInfo;
+ unsigned i;
+
CC = ITStatus_getITCC(&(ud->ITBlock));
if (ITStatus_instrInITBlock(&(ud->ITBlock)))
ITStatus_advanceITState(&(ud->ITBlock));
- MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
- unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
- unsigned i;
+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+
for (i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isPredicate(&OpInfo[i])) {
MCOperand_setImm(MCInst_getOperand(MI, i), CC);
@@ -1125,6 +1137,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
+ ARM_AM_ShiftOpc Shift;
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
@@ -1134,7 +1147,7 @@
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler_Fail;
- ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
+ Shift = ARM_AM_lsl;
switch (type) {
case 0:
Shift = ARM_AM_lsl;
@@ -1163,6 +1176,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
+ ARM_AM_ShiftOpc Shift;
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
@@ -1174,7 +1188,7 @@
if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
return MCDisassembler_Fail;
- ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
+ Shift = ARM_AM_lsl;
switch (type) {
case 0:
Shift = ARM_AM_lsl;
@@ -1297,6 +1311,7 @@
// create the final mask.
unsigned msb = fieldFromInstruction_4(Val, 5, 5);
unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
+ uint32_t lsb_mask;
DecodeStatus S = MCDisassembler_Success;
if (lsb > msb) {
@@ -1309,7 +1324,7 @@
uint32_t msb_mask = 0xFFFFFFFF;
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
- uint32_t lsb_mask = (1U << lsb) - 1;
+ lsb_mask = (1U << lsb) - 1;
MCInst_addOperand(Inst, MCOperand_CreateImm(~(msb_mask ^ lsb_mask)));
return S;
@@ -1464,6 +1479,8 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
+ ARM_AM_AddrOpc Op;
+ ARM_AM_ShiftOpc Opc;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
@@ -1514,7 +1531,7 @@
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler_Fail;
- ARM_AM_AddrOpc Op = ARM_AM_add;
+ Op = ARM_AM_add;
if (!fieldFromInstruction_4(Insn, 23, 1))
Op = ARM_AM_sub;
@@ -1531,7 +1548,7 @@
if (reg) {
if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler_Fail;
- ARM_AM_ShiftOpc Opc = ARM_AM_lsl;
+ Opc = ARM_AM_lsl;
switch( fieldFromInstruction_4(Insn, 5, 2)) {
case 0:
Opc = ARM_AM_lsl;
@@ -1570,6 +1587,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
+ ARM_AM_ShiftOpc ShOp;
unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
@@ -1577,7 +1595,7 @@
unsigned imm = fieldFromInstruction_4(Val, 7, 5);
unsigned U = fieldFromInstruction_4(Val, 12, 1);
- ARM_AM_ShiftOpc ShOp = ARM_AM_lsl;
+ ShOp = ARM_AM_lsl;
switch (type) {
case 0:
ShOp = ARM_AM_lsl;
@@ -2130,8 +2148,8 @@
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler_Fail;
- if (!add) imm *= -1;
- if (imm == 0 && !add) imm = INT32_MIN;
+ if (!add) imm *= (unsigned int)-1;
+ if (imm == 0 && !add) imm = (unsigned int)INT32_MIN;
MCInst_addOperand(Inst, MCOperand_CreateImm(imm));
//if (Rn == 15)
// tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
@@ -4891,6 +4909,8 @@
static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ DecodeStatus S;
+
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@@ -4899,7 +4919,7 @@
if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
- DecodeStatus S = MCDisassembler_Success;
+ S = MCDisassembler_Success;
if (Rt == Rn || Rn == Rt2)
S = MCDisassembler_SoftFail;
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index bef0e14..8093c07 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -301,7 +301,7 @@
MCOperand *MO2 = MCInst_getOperand(MI, 2);
MCOperand *MO3 = MCInst_getOperand(MI, 3);
- SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp(MCOperand_getImm(MO3))));
+ SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
printSBitModifierOperand(MI, 6, O);
printPredicateOperand(MI, 4, O);
@@ -339,7 +339,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, 1);
MCOperand *MO2 = MCInst_getOperand(MI, 2);
- SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp(MCOperand_getImm(MO2))));
+ SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
printSBitModifierOperand(MI, 5, O);
printPredicateOperand(MI, 3, O);
@@ -359,13 +359,13 @@
MI->flat_insn.arm.op_count++;
}
- if (ARM_AM_getSORegShOp(MCOperand_getImm(MO2)) == ARM_AM_rrx) {
+ if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
//printAnnotation(O, Annot);
return;
}
SStream_concat(O, ", %s", markup("<imm:"));
- unsigned tmp = translateShiftImm(getSORegOffset(MCOperand_getImm(MO2)));
+ unsigned tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -373,7 +373,7 @@
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type =
- (arm_shifter)ARM_AM_getSORegShOp(MCOperand_getImm(MO2));
+ (arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
}
return;
@@ -557,7 +557,7 @@
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, markup("<imm:"));
//O << "#" << formatImm(Op.getImm());
- int32_t imm = MCOperand_getImm(Op);
+ int32_t imm = (int32_t)MCOperand_getImm(Op);
// relative branch only has relative offset, so we have to update it
// to reflect absolute address.
@@ -566,9 +566,9 @@
if (ARM_rel_branch(MI->csh, MCInst_getOpcode(MI))) {
// only do this for relative branch
if (MI->csh->mode & CS_MODE_THUMB)
- imm += MI->address + 4;
+ imm += (int32_t)MI->address + 4;
else
- imm += MI->address + 8;
+ imm += (int32_t)MI->address + 8;
if (imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", imm);
@@ -641,7 +641,7 @@
}
// Print the shift opc.
- ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(MCOperand_getImm(MO3));
+ ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
if (ShOpc == ARM_AM_rrx)
@@ -664,13 +664,13 @@
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = MCOperand_getImm(MO2) >> 3;
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
MI->flat_insn.arm.op_count++;
}
// Print the shift opc.
- printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
- getSORegOffset(MCOperand_getImm(MO2)), UseMarkup);
+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
+ getSORegOffset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
//===--------------------------------------------------------------------===//
@@ -692,15 +692,15 @@
}
if (!MCOperand_getReg(MO2)) {
- unsigned tmp = getAM2Offset(MCOperand_getImm(MO3));
+ unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
if (tmp) { // Don't print +0.
SStream_concat(O, ", %s", markup("<imm:"));
if (tmp > HEX_THRESHOLD)
- SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
+ SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
else
- SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
+ SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
if (MI->csh->detail) {
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op(MCOperand_getImm(MO3));
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = tmp;
}
SStream_concat(O, markup(">"));
@@ -711,14 +711,14 @@
}
SStream_concat(O, ", ");
- SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))));
+ SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))));
printRegName(O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
}
- printRegImmShift(MI, O, getAM2ShiftOpc(MCOperand_getImm(MO3)),
- getAM2Offset(MCOperand_getImm(MO3)), UseMarkup);
+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
+ getAM2Offset((unsigned int)MCOperand_getImm(MO3)), UseMarkup);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@@ -779,14 +779,14 @@
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
if (!MCOperand_getReg(MO1)) {
- unsigned ImmOffs = getAM2Offset(MCOperand_getImm(MO2));
+ unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
- ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))), ImmOffs,
+ ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
else
SStream_concat(O, "%s#%s%u%s", markup("<imm:"),
- ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))), ImmOffs,
+ ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
@@ -796,7 +796,7 @@
return;
}
- SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))));
+ SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))));
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
@@ -804,8 +804,8 @@
MI->flat_insn.arm.op_count++;
}
- printRegImmShift(MI, O, getAM2ShiftOpc(MCOperand_getImm(MO2)),
- getAM2Offset(MCOperand_getImm(MO2)), UseMarkup);
+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
+ getAM2Offset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
//===--------------------------------------------------------------------===//
@@ -817,7 +817,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
- ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO3));
+ ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -838,7 +838,7 @@
return;
}
- unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO3));
+ unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@@ -854,7 +854,7 @@
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -ImmOffs;
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
MI->flat_insn.arm.op_count++;
}
@@ -866,7 +866,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
- ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO3));
+ ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -888,7 +888,7 @@
}
//If the op is sub we have to print the immediate even if it is 0
- unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO3));
+ unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) {
if (ImmOffs > HEX_THRESHOLD)
@@ -901,9 +901,9 @@
if (MI->csh->detail) {
if (op)
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = MCOperand_getImm(MO3);
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)MCOperand_getImm(MO3);
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = -MCOperand_getImm(MO3);
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)-MCOperand_getImm(MO3);
}
SStream_concat(O, "]%s", markup(">"));
@@ -920,7 +920,7 @@
}
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
- unsigned IdxMode = getAM3IdxMode(MCOperand_getImm(MO3));
+ unsigned IdxMode = getAM3IdxMode((unsigned int)MCOperand_getImm(MO3));
if (IdxMode == ARMII_IndexModePost) {
printAM3PostIndexOp(MI, Op, O);
@@ -934,7 +934,7 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
- ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO2));
+ ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO2));
if (MCOperand_getReg(MO1)) {
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
@@ -947,7 +947,7 @@
return;
}
- unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO2));
+ unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@@ -962,7 +962,7 @@
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
else
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -ImmOffs;
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
MI->flat_insn.arm.op_count++;
}
@@ -971,7 +971,7 @@
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- unsigned Imm = MCOperand_getImm(MO);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MO);
if ((Imm & 0xff) > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
(Imm & 0xff), markup(">"));
@@ -1002,7 +1002,7 @@
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- unsigned Imm = MCOperand_getImm(MO);
+ unsigned Imm = (unsigned int)MCOperand_getImm(MO);
if (((Imm & 0xff) << 2) > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
((Imm & 0xff) << 2), markup(">"));
@@ -1025,16 +1025,16 @@
SStream_concat(O, "%s[", markup("<mem:"));
printRegName(O, MCOperand_getReg(MO1));
- unsigned ImmOffs = ARM_AM_getAM5Offset(MCOperand_getImm(MO2));
- unsigned Op = ARM_AM_getAM5Op(MCOperand_getImm(MO2));
+ unsigned ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
+ unsigned Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
if (ImmOffs * 4 > HEX_THRESHOLD)
SStream_concat(O, ", %s#%s0x%x%s", markup("<imm:"),
- ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op(MCOperand_getImm(MO2))),
+ ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
ImmOffs * 4, markup(">"));
else
SStream_concat(O, ", %s#%s%u%s", markup("<imm:"),
- ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op(MCOperand_getImm(MO2))),
+ ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
ImmOffs * 4, markup(">"));
}
SStream_concat(O, "]%s", markup(">"));
@@ -1050,7 +1050,7 @@
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- unsigned tmp = MCOperand_getImm(MO2);
+ unsigned tmp = (unsigned int)MCOperand_getImm(MO2);
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
SStream_concat(O, ":0x%x", (tmp << 3));
@@ -1094,7 +1094,7 @@
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- uint32_t v = ~MCOperand_getImm(MO);
+ uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
int32_t lsb = CountTrailingZeros_32(v);
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
@@ -1121,7 +1121,7 @@
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// FIXME: HasV80Ops becomes a mode
// SStream_concat(O, ARM_MB_MemBOptToString(val,
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
@@ -1130,13 +1130,13 @@
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, "%s", ARM_ISB_InstSyncBOptToString(val));
}
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned ShiftOp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
bool isASR = (ShiftOp & (1 << 5)) != 0;
unsigned Amt = ShiftOp & 0x1f;
if (isASR) {
@@ -1163,7 +1163,7 @@
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm == 0)
return;
//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
@@ -1179,7 +1179,7 @@
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// A shift amount of 32 is encoded as 0.
if (Imm == 0)
Imm = 32;
@@ -1243,13 +1243,13 @@
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
- SStream_concat(O, "%s", ARM_PROC_IModToString(MCOperand_getImm(Op)));
+ SStream_concat(O, "%s", ARM_PROC_IModToString((unsigned int)MCOperand_getImm(Op)));
}
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
- unsigned IFlags = MCOperand_getImm(Op);
+ unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
int i;
for (i=2; i >= 0; --i)
if (IFlags & (1 << i))
@@ -1269,13 +1269,16 @@
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
- unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
- unsigned Mask = MCOperand_getImm(Op) & 0xf;
+#if 0 // TODO once below is fixed
+ unsigned SpecRegRBit = (unsigned int)MCOperand_getImm(Op) >> 4;
+ unsigned Mask = (unsigned int)MCOperand_getImm(Op) & 0xf;
+#endif
// FIXME: FeatureMClass becomes mode??
//if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
- if (true) {
- unsigned SYSm = MCOperand_getImm(Op);
+ //if (true)
+ {
+ unsigned SYSm = (unsigned int)MCOperand_getImm(Op);
unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits
// which are only for writes.
@@ -1321,7 +1324,7 @@
case 0x814: SStream_concat(O, "control"); return;
}
}
-
+#if 0 // TODO once above is fixed
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
@@ -1346,6 +1349,7 @@
if (Mask & 2) SStream_concat(O, "x");
if (Mask & 1) SStream_concat(O, "c");
}
+#endif
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
@@ -1387,7 +1391,7 @@
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
else
@@ -1408,7 +1412,7 @@
SStream_concat(O, "p%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_PIMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
}
@@ -1418,14 +1422,14 @@
SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_CIMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
}
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "{0x%x}", tmp);
else
@@ -1472,7 +1476,7 @@
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
//<< "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
- unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "%s#0x%x", markup("<imm:"), tmp);
else
@@ -1487,7 +1491,7 @@
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// << "#" << formatImm((Imm == 0 ? 32 : Imm))
unsigned tmp = Imm == 0 ? 32 : Imm;
if (tmp > HEX_THRESHOLD)
@@ -1507,8 +1511,8 @@
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
{
// (3 - the number of trailing zeros) is the number of then / else.
- unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
- unsigned Firstcond = MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
+ unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
//assert(NumTZ <= 3 && "Invalid IT mask!");
@@ -1567,7 +1571,7 @@
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- unsigned ImmOffs = MCOperand_getImm(MO2);
+ unsigned ImmOffs = (unsigned int)MCOperand_getImm(MO2);
if (ImmOffs) {
unsigned tmp = ImmOffs * Scale;
SStream_concat(O, ", %s", markup("<imm:"));
@@ -1623,8 +1627,8 @@
// Print the shift opc.
//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
- printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
- getSORegOffset(MCOperand_getImm(MO2)), UseMarkup);
+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
+ getSORegOffset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
@@ -1632,6 +1636,8 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
+ int32_t OffImm;
+ bool isSub;
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, OpNum, O);
@@ -1646,8 +1652,8 @@
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
- bool isSub = OffImm < 0;
+ OffImm = (int32_t)MCOperand_getImm(MO2);
+ isSub = OffImm < 0;
// Special value for #-0. All others are normal.
if (OffImm == INT32_MIN)
OffImm = 0;
@@ -1670,6 +1676,8 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
+ int32_t OffImm;
+ bool isSub;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -1678,8 +1686,8 @@
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
- bool isSub = OffImm < 0;
+ OffImm = (int32_t)MCOperand_getImm(MO2);
+ isSub = OffImm < 0;
// Don't print +0.
if (OffImm == INT32_MIN)
OffImm = 0;
@@ -1704,6 +1712,8 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
+ int32_t OffImm;
+ bool isSub;
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, OpNum, O);
@@ -1717,8 +1727,8 @@
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
- bool isSub = OffImm < 0;
+ OffImm = (int32_t)MCOperand_getImm(MO2);
+ isSub = OffImm < 0;
//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
@@ -1756,7 +1766,7 @@
SStream_concat(O, markup("<imm:"));
//<< "#" <<
// formatImm(MCOperand_getImm(MO2.getImm() * 4)
- unsigned tmp = MCOperand_getImm(MO2) * 4;
+ unsigned tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -1851,7 +1861,7 @@
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
- unsigned ShAmt = MCOperand_getImm(MO3);
+ unsigned ShAmt = (unsigned int)MCOperand_getImm(MO3);
if (ShAmt) {
//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
SStream_concat(O, ", lsl ");
@@ -1871,17 +1881,17 @@
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
- SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat(MCOperand_getImm(MO)), markup(">"));
+ SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat((unsigned int)MCOperand_getImm(MO)), markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_FP;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat(MCOperand_getImm(MO));
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
MI->flat_insn.arm.op_count++;
}
}
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned EncodedImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned EltBits;
uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
if (Val > HEX_THRESHOLD)
@@ -1890,14 +1900,14 @@
SStream_concat(O, "%s#%"PRIu64"%s", markup("<imm:"), Val, markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
- MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Val;
+ MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)Val;
MI->flat_insn.arm.op_count++;
}
}
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm + 1 > HEX_THRESHOLD)
SStream_concat(O, "%s#0x%x%s", markup("<imm:"), Imm + 1, markup(">"));
else
@@ -1911,7 +1921,7 @@
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm == 0)
return;
SStream_concat(O, ", ror %s#", markup("<imm:"));
@@ -1931,7 +1941,7 @@
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, markup("<imm:"));
- unsigned tmp = 16 - MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -1947,7 +1957,7 @@
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, markup("<imm:"));
- unsigned tmp = 32 - MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -1962,7 +1972,7 @@
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
{
- unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "[0x%x]",tmp);
else
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index 61d0420..bbb10fd 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -2313,13 +2313,13 @@
handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR);
diff --git a/arch/ARM/ARMModule.c b/arch/ARM/ARMModule.c
index 441c3fb..8e32b03 100644
--- a/arch/ARM/ARMModule.c
+++ b/arch/ARM/ARMModule.c
@@ -9,12 +9,14 @@
static cs_err init(cs_struct *ud)
{
+ MCRegisterInfo *mri;
+
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM |
CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
- MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
+ mri = cs_mem_malloc(sizeof(*mri));
ARM_init(mri);
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 806a8b7..8bd8062 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -152,7 +152,7 @@
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int mode)
{
- uint64_t Bits = -1; // include every features by default
+ uint64_t Bits = (uint64_t)-1; // include every features by default
// ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
// some features are mutually execlusive
@@ -180,6 +180,11 @@
return Bits;
}
+#ifdef _MSC_VER
+#pragma warning(disable:4242)
+#pragma warning(disable:4244)
+#pragma warning(disable:4706)
+#endif
#include "MipsGenDisassemblerTables.inc"
#define GET_REGINFO_ENUM
@@ -249,12 +254,13 @@
uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
{
uint32_t Insn;
+ DecodeStatus Result;
if (code_len < 4)
// not enough data
return MCDisassembler_Fail;
- DecodeStatus Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
+ Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
mode & CS_MODE_MICRO);
if (Result == MCDisassembler_Fail)
return MCDisassembler_Fail;
@@ -724,7 +730,7 @@
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
{
// First we need to grab the pos(lsb) from MCInst.
- int Pos = MCOperand_getImm(MCInst_getOperand(Inst, 2));
+ int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
int Size = (int) Insn - Pos + 1;
MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Size, 16)));
return MCDisassembler_Success;
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index ebbf139..dd13422 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -1457,7 +1457,7 @@
};
static insn_map alias_insns[] = {
- { -2, MIPS_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
+ { (unsigned short)-2, MIPS_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
{ Mips_SUBu, MIPS_INS_NEGU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
};
@@ -1473,13 +1473,13 @@
if (h->detail) {
memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(alias_insns[i].regs_use);
memcpy(insn->detail->regs_write, alias_insns[i].regs_mod, sizeof(alias_insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(alias_insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(alias_insns[i].regs_mod);
memcpy(insn->detail->groups, alias_insns[i].groups, sizeof(alias_insns[i].groups));
- insn->detail->groups_count = count_positive(alias_insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(alias_insns[i].groups);
if (alias_insns[i].branch || alias_insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
@@ -1498,13 +1498,13 @@
if (h->detail) {
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c
index bfe0cd3..dd4c1b4 100644
--- a/arch/Mips/MipsModule.c
+++ b/arch/Mips/MipsModule.c
@@ -11,12 +11,14 @@
static cs_err init(cs_struct *ud)
{
+ MCRegisterInfo *mri;
+
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
CS_MODE_MICRO | CS_MODE_N64 | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
- MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
+ mri = cs_mem_malloc(sizeof(*mri));
Mips_init(mri);
ud->printer = Mips_printInst;
diff --git a/arch/PowerPC/PPCDisassembler.c b/arch/PowerPC/PPCDisassembler.c
index cc666b0..bcb7304 100644
--- a/arch/PowerPC/PPCDisassembler.c
+++ b/arch/PowerPC/PPCDisassembler.c
@@ -104,7 +104,7 @@
static uint64_t getFeatureBits(int feature)
{
// enable all features
- return -1;
+ return (uint64_t)-1;
}
static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
@@ -264,6 +264,11 @@
return MCDisassembler_Success;
}
+#ifdef _MSC_VER
+#pragma warning(disable:4242)
+#pragma warning(disable:4244)
+#pragma warning(disable:4706)
+#endif
#include "PPCGenDisassemblerTables.inc"
static DecodeStatus getInstruction(MCInst *MI,
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index ea6bdc2..bc530f1 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -71,9 +71,9 @@
{
// Check for slwi/srwi mnemonics.
if (MCInst_getOpcode(MI) == PPC_RLWINM) {
- unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, 2));
- unsigned char MB = MCOperand_getImm(MCInst_getOperand(MI, 3));
- unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, 4));
+ unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
+ unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
+ unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
bool useSubstituteMnemonic = false;
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
@@ -110,8 +110,8 @@
}
if (MCInst_getOpcode(MI) == PPC_RLDICR) {
- unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, 2));
- unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, 3));
+ unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
+ unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
SStream_concat(O, "sldi\t");
@@ -146,7 +146,7 @@
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
SStream *O, const char *Modifier)
{
- unsigned Code = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
MI->flat_insn.ppc.bc = (ppc_bc)Code;
@@ -238,7 +238,7 @@
static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
- int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
Value = SignExtend32(Value, 5);
if (Value >= 0) {
@@ -262,7 +262,7 @@
static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
- unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 31 && "Invalid u5imm argument!");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
@@ -278,7 +278,7 @@
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
- unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
+ unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 63 && "Invalid u6imm argument!");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
@@ -370,8 +370,11 @@
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
- if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
- return printOperand(MI, OpNo, O);
+ if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
+ {
+ printOperand(MI, OpNo, O);
+ return;
+ }
// Branches can take an immediate operand. This is used by the branch
// selection pass to print .+8, an eight byte displacement from the PC.
@@ -381,8 +384,11 @@
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
- if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
- return printOperand(MI, OpNo, O);
+ if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
+ {
+ printOperand(MI, OpNo, O);
+ return;
+ }
int tmp = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (tmp >= 0) {
@@ -512,7 +518,7 @@
}
if (MCOperand_isImm(Op)) {
- int32_t imm = MCOperand_getImm(Op);
+ int32_t imm = (int32_t)MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index 378e1bc..a2f9558 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -914,8 +914,7 @@
{ PPC_gBCLRL, PPC_INS_BCLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
};
-static insn_map alias_insns[] = {
-};
+static insn_map alias_insns[] = {0, 0, {0}, {0}, {0}, 0, 0};
// given internal insn id, return public instruction info
void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
@@ -932,13 +931,13 @@
handle.detail = h->detail;
memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(alias_insns[i].regs_use);
memcpy(insn->detail->regs_write, alias_insns[i].regs_mod, sizeof(alias_insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(alias_insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(alias_insns[i].regs_mod);
memcpy(insn->detail->groups, alias_insns[i].groups, sizeof(alias_insns[i].groups));
- insn->detail->groups_count = count_positive(alias_insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(alias_insns[i].groups);
if (alias_insns[i].branch || alias_insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
@@ -961,13 +960,13 @@
handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
@@ -1431,8 +1430,7 @@
};
// special alias insn
-static name_map alias_insn_names[] = {
-};
+static name_map alias_insn_names[] = {0, 0};
const char *PPC_insn_name(csh handle, unsigned int id)
{
diff --git a/arch/PowerPC/PPCModule.c b/arch/PowerPC/PPCModule.c
index d2e3b82..2ed3497 100644
--- a/arch/PowerPC/PPCModule.c
+++ b/arch/PowerPC/PPCModule.c
@@ -11,12 +11,14 @@
static cs_err init(cs_struct *ud)
{
+ MCRegisterInfo *mri;
+
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
- MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
+ mri = cs_mem_malloc(sizeof(*mri));
PPC_init(mri);
ud->printer = PPC_printInst;
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index c88ff2f..fdfb981 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -221,7 +221,7 @@
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
switch (Imm) {
- default: printf("Invalid avxcc argument!\n"); break;
+ default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat(O, "eq"); break;
case 1: SStream_concat(O, "lt"); break;
case 2: SStream_concat(O, "le"); break;
@@ -391,9 +391,9 @@
if (MCOperand_getReg(IndexReg)) {
SStream_concat(O, ", ");
_printOperand(MI, Op+2, O);
- unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
+ uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
if (MI->csh->detail)
- MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = ScaleVal;
+ MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
if (ScaleVal != 1) {
SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">"));
}
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index c9d22ca..ec0c07c 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -146,13 +146,13 @@
case TYPE_XMM32:
case TYPE_XMM64:
case TYPE_XMM128:
- MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_XMM0 + (immediate >> 4)));
+ MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_XMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_XMM256:
- MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_YMM0 + (immediate >> 4)));
+ MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_YMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_XMM512:
- MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + (immediate >> 4)));
+ MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_REL8:
if(immediate & 0x80)
@@ -624,10 +624,10 @@
MODE_64BIT);
if (ret) {
- *size = insn.readerCursor - address;
+ *size = (uint16_t)(insn.readerCursor - address);
return false;
} else {
- *size = insn.length;
+ *size = (uint16_t)insn.length;
result = (!translateInstruction(instr, &insn)) ? true : false;
// save segment for printing hack
instr->x86_segment = x86_map_segment(insn.segmentOverride);
diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c
index e462960..448f412 100644
--- a/arch/X86/X86DisassemblerDecoder.c
+++ b/arch/X86/X86DisassemblerDecoder.c
@@ -43,7 +43,7 @@
#ifndef NDEBUG
#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
#else
-#define debug(s) do { } while (0)
+#define debug(s) ((void) 0)
#endif
/*
@@ -802,7 +802,7 @@
hasModRMExtension = modRMRequired(insn->opcodeType,
instructionClass,
- insn->opcode);
+ insn->opcode) == TRUE;
if (hasModRMExtension) {
if (readModRM(insn))
@@ -831,7 +831,7 @@
*/
static BOOL is16BitEquivalent(const char* orig, const char* equiv)
{
- off_t i;
+ size_t i;
for (i = 0;; i++) {
if (orig[i] == '\0' && equiv[i] == '\0')
@@ -1157,7 +1157,7 @@
return 0;
insn->consumedDisplacement = TRUE;
- insn->displacementOffset = insn->readerCursor - insn->startLocation;
+ insn->displacementOffset = (uint8_t)(insn->readerCursor - insn->startLocation);
switch (insn->eaDisplacement) {
case EA_DISP_NONE:
@@ -1381,13 +1381,13 @@
*valid = 0; \
return 0; \
case TYPE_Rv: \
- return base + index; \
+ return (uint8_t)(base + index); \
case TYPE_R8: \
if (insn->rexPrefix && \
- index >= 4 && index <= 7) { \
- return prefix##_SPL + (index - 4); \
+ index >= 4 && index <= 7) { \
+ return prefix##_SPL + (index - 4); \
} else { \
- return prefix##_AL + index; \
+ return prefix##_AL + index; \
} \
case TYPE_R16: \
return prefix##_AX + index; \
@@ -1472,7 +1472,7 @@
case ENCODING_REG:
insn->reg = (Reg)fixupRegValue(insn,
(OperandType)op->type,
- insn->reg - insn->regBase,
+ (uint8_t)(insn->reg - insn->regBase),
&valid);
if (!valid)
return -1;
@@ -1481,7 +1481,7 @@
if (insn->eaBase >= insn->eaRegBase) {
insn->eaBase = (EABase)fixupRMValue(insn,
(OperandType)op->type,
- insn->eaBase - insn->eaRegBase,
+ (uint8_t)(insn->eaBase - insn->eaRegBase),
&valid);
if (!valid)
return -1;
@@ -1608,7 +1608,7 @@
size = insn->immediateSize;
else
insn->immediateSize = size;
- insn->immediateOffset = insn->readerCursor - insn->startLocation;
+ insn->immediateOffset = (uint8_t)(insn->readerCursor - insn->startLocation);
switch (size) {
case 1:
@@ -1841,7 +1841,7 @@
insn->operands = &x86OperandSets[insn->spec->operands][0];
- insn->length = insn->readerCursor - insn->startLocation;
+ insn->length = (size_t)(insn->readerCursor - insn->startLocation);
dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
startLoc, insn->readerCursor, insn->length);
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index c9f2432..db4dc20 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -239,7 +239,7 @@
if (get_first_op(O->buffer, tmp)) {
int post;
char *acc_regs[] = { "al", "ax", "eax", "rax", NULL };
- int acc_regs_id[] = { X86_REG_AL, X86_REG_AX, X86_REG_EAX, X86_REG_RAX };
+ unsigned int acc_regs_id[] = { X86_REG_AL, X86_REG_AX, X86_REG_EAX, X86_REG_RAX };
if (tmp[0] != 0 && ((post = str_in_list(acc_regs, tmp)) != -1)) {
// first op is register, so set operand size following register size
MI->flat_insn.x86.op_size = 1 << post;
@@ -290,7 +290,7 @@
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
switch (Imm) {
- default: printf("Invalid avxcc argument!\n"); break;
+ default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat(O, "eq"); break;
case 1: SStream_concat(O, "lt"); break;
case 2: SStream_concat(O, "le"); break;
@@ -415,7 +415,7 @@
static void printMemReference(MCInst *MI, unsigned Op, SStream *O) // qqq
{
MCOperand *BaseReg = MCInst_getOperand(MI, Op);
- unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
+ uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
MCOperand *IndexReg = MCInst_getOperand(MI, Op+2);
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
@@ -424,7 +424,7 @@
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
- MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = ScaleVal;
+ MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
}
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 905bc1f..9f0f7a9 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -6614,13 +6614,13 @@
if (h->detail) {
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
- insn->detail->regs_read_count = count_positive(insns[i].regs_use);
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
@@ -6645,7 +6645,7 @@
if (insn->id == X86_INS_LOCK || insn->id == X86_INS_REP ||
insn->id == X86_INS_REPNE) {
// then save this as prev_prefix
- h->prev_prefix = insn->id;
+ h->prev_prefix = (uint8_t)insn->id;
return false;
}
@@ -6654,8 +6654,7 @@
return true;
}
- // neither prefix instruction nor having previous instruction as prefix,
- // so we cannot combine this with a prefix
+ // cannot combine this with a prefix
return false;
}