commit 553bb488d792a4f1ff0777fc2deac5090c791c5c
author Nguyen Anh Quynh <aquynh@gmail.com> Mon May 26 23:47:04 2014 +0800
committer Nguyen Anh Quynh <aquynh@gmail.com> Mon May 26 23:47:45 2014 +0800
tree 379f4b1b381d89f4f26fdd9e1da09e9f7442b7d5
parent 52a8d2afa21b5ef6f5b969a6adbb5036fb30250e

python: support XCore

arch/XCore/XCoreInstPrinter.c

diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c
index ce617b7..1f4f704 100644
--- a/arch/XCore/XCoreInstPrinter.c
+++ b/arch/XCore/XCoreInstPrinter.c
@@ -55,7 +55,7 @@
 			}
 			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
 			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
-			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.sign = 1;
+			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
 		} else {
 			// the last op should be the memory base
 			MI->flat_insn.xcore.op_count--;
@@ -64,9 +64,9 @@
 			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
 			MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
 			if (reg > 0)
-				MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.sign = 1;
+				MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
 			else
-				MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.sign = -1;
+				MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = -1;
 		}
 	} else {
 		// done, create the next operand slot