Merge branch 'cs_insn_const' of https://github.com/obs1dium/capstone into next
diff --git a/.gitignore b/.gitignore
index cc6a940..0e8174c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,6 +38,11 @@
bindings/ocaml/test_mips
bindings/ocaml/test_x86
bindings/ocaml/test_detail
+bindings/ocaml/test_ppc
+bindings/ocaml/test_sparc
+bindings/ocaml/test_systemz
+bindings/ocaml/test_xcore
+
# test binaries
tests/test
diff --git a/CMakeLists.txt b/CMakeLists.txt
index c55c2ec..59c9995 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -22,6 +22,7 @@
option(XCORE_SUPPORT "XCore support" ON)
option(X86_SUPPORT "x86 support" ON)
option(X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
+option(X86_ATT_DISABLE, "Disable x86 AT&T syntax" OFF)
if (BUILD_DIET)
add_definitions(-DCAPSTONE_DIET)
@@ -35,6 +36,10 @@
add_definitions(-DCAPSTONE_X86_REDUCE)
endif ()
+if (X86_ATT_DISABLE)
+ add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
+endif ()
+
## sources
set(SOURCES
cs.c
diff --git a/COMPILE.TXT b/COMPILE.TXT
index bc63ccc..f9dfaea 100644
--- a/COMPILE.TXT
+++ b/COMPILE.TXT
@@ -21,12 +21,13 @@
The other way of customize Capstone without having to edit config.mk is to
pass the desired options on the commandline to ./make.sh. Currently,
- Capstone supports 4 options, as followings.
+ Capstone supports 5 options, as followings.
- CAPSTONE_ARCHS: specify list of architectures to compiled in.
- CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
- CAPSTONE_DIET: use this to make the output binaries more compact.
- CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
+ - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
modes are disable.
diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT
index 83394e1..a19ba43 100644
--- a/COMPILE_CMAKE.TXT
+++ b/COMPILE_CMAKE.TXT
@@ -37,9 +37,10 @@
- USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
- BUILD_DIET: change this to ON to make the binaries more compact.
- X86_REDUCE: change this to ON to make X86 binary smaller.
+ - X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
- modes are disable. To use your own memory allocations, turn ON both DIET &
+ modes are disabled. To use your own memory allocations, turn ON both DIET &
X86_REDUCE, run "cmake" with: -DUSE_SYS_DYN_MEM=0 -DBUILD_DIET=1 -DX86_REDUCE=1
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
index a8767dd..c872394 100644
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@@ -44,6 +44,8 @@
- CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
- CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
- CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
+ - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
+ AT&T syntax on x86.
By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
modes are disable.
diff --git a/Makefile b/Makefile
index 18ea309..7033086 100644
--- a/Makefile
+++ b/Makefile
@@ -33,6 +33,10 @@
CFLAGS ?= -O3
endif
+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
+endif
+
CFLAGS += -fPIC -Wall -Iinclude
ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
@@ -201,8 +205,10 @@
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
# assembly syntax is irrelevant in Diet mode, when this info is suppressed
ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
endif
+endif
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
endif
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 0e0b98b..0ebc41d 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -16,7 +16,7 @@
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
// this code is only relevant when DIET mode is disable
-#if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET)
+#if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE)
#include <ctype.h>
#include <inttypes.h>
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index 8bceb12..5a21ae4 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -715,7 +715,7 @@
if (instr->flat_insn->detail) {
instr->flat_insn->detail->x86.op_count = 0;
memset(instr->flat_insn->detail->x86.prefix, 0, sizeof(instr->flat_insn->detail->x86.prefix));
- memset(instr->flat_insn->detail->x86.operands, 0, 4 * sizeof(instr->flat_insn->detail->x86.operands[0]));
+ memset(instr->flat_insn->detail->x86.operands, 0, ARR_SIZE(instr->flat_insn->detail->x86.operands));
}
if (handle->mode & CS_MODE_16)
diff --git a/arch/X86/X86Module.c b/arch/X86/X86Module.c
index 1df1498..ce1de15 100644
--- a/arch/X86/X86Module.c
+++ b/arch/X86/X86Module.c
@@ -44,10 +44,14 @@
break;
case CS_OPT_SYNTAX_ATT:
-#ifndef CAPSTONE_DIET
+#if !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE)
handle->printer = X86_ATT_printInst;
handle->syntax = CS_OPT_SYNTAX_ATT;
break;
+#elif !defined(CAPSTONE_DIET) && defined(CAPSTONE_X86_ATT_DISABLE)
+ // ATT syntax is unsupported
+ handle->errnum = CS_ERR_X86_ATT;
+ return CS_ERR_X86_ATT;
#else
// this is irrelevant in CAPSTONE_DIET mode
handle->errnum = CS_ERR_DIET;
diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java
index 1951205..e62020b 100644
--- a/bindings/java/capstone/Capstone.java
+++ b/bindings/java/capstone/Capstone.java
@@ -301,6 +301,9 @@
public static final int CS_ERR_MEMSETUP = 8;
public static final int CS_ERR_VERSION = 9; //Unsupported version (bindings)
public static final int CS_ERR_DIET = 10; //Information irrelevant in diet engine
+ public static final int CS_ERR_SKIPDATA = 11; //Access irrelevant data for "data" instruction in SKIPDATA mode
+ public static final int CS_ERR_X86_ATT = 12; //X86 AT&T syntax is unsupported (opt-out at compile time)
+ public static final int CS_ERR_X86_INTEL = 13; //X86 Intel syntax is unsupported (opt-out at compile time)
// Capstone option type
public static final int CS_OPT_SYNTAX = 1; // Intel X86 asm syntax (CS_ARCH_X86 arch)
diff --git a/bindings/ocaml/Makefile b/bindings/ocaml/Makefile
index 4e655c0..664c37f 100644
--- a/bindings/ocaml/Makefile
+++ b/bindings/ocaml/Makefile
@@ -4,7 +4,7 @@
LIB = capstone
FLAGS = '-Wall -Wextra -Wwrite-strings'
-all: arm.cmxa arm64.cmxa mips.cmxa ppc.cmxa x86.cmxa capstone.cmxa test.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_arm64.cmx test_mips.cmx test_ppc.cmx ocaml.o
+all: arm.cmxa arm64.cmxa mips.cmxa ppc.cmxa x86.cmxa sparc.cmxa systemz.cmxa xcore.cmxa capstone.cmxa test.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_arm64.cmx test_mips.cmx test_ppc.cmx test_sparc.cmx test_systemz.cmx test_xcore.cmx ocaml.o
ocamlopt -o test -ccopt $(FLAGS) ocaml.o capstone.cmx test.cmx -cclib -l$(LIB)
ocamlopt -o test_detail -ccopt $(FLAGS) capstone.cmx ocaml.o test_detail.cmx -cclib -l$(LIB)
ocamlopt -o test_x86 -ccopt $(FLAGS) capstone.cmx ocaml.o x86.cmx test_x86.cmx -cclib -l$(LIB)
@@ -12,6 +12,10 @@
ocamlopt -o test_arm64 -ccopt $(FLAGS) capstone.cmx ocaml.o arm64.cmx test_arm64.cmx -cclib -l$(LIB)
ocamlopt -o test_mips -ccopt $(FLAGS) capstone.cmx ocaml.o mips.cmx test_mips.cmx -cclib -l$(LIB)
ocamlopt -o test_ppc -ccopt $(FLAGS) capstone.cmx ocaml.o ppc.cmx test_ppc.cmx -cclib -l$(LIB)
+ ocamlopt -o test_sparc -ccopt $(FLAGS) capstone.cmx ocaml.o sparc.cmx test_sparc.cmx -cclib -l$(LIB)
+ ocamlopt -o test_systemz -ccopt $(FLAGS) capstone.cmx ocaml.o systemz.cmx test_systemz.cmx -cclib -l$(LIB)
+ ocamlopt -o test_xcore -ccopt $(FLAGS) capstone.cmx ocaml.o xcore.cmx test_xcore.cmx -cclib -l$(LIB)
+
test.cmx: test.ml
ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
@@ -34,6 +38,15 @@
test_ppc.cmx: test_ppc.ml
ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
+test_sparc.cmx: test_sparc.ml
+ ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
+
+test_systemz.cmx: test_systemz.ml
+ ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
+
+test_xcore.cmx: test_xcore.ml
+ ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB)
+
ocaml.o: ocaml.c
ocamlc -ccopt $(FLAGS) -c $<
@@ -109,6 +122,42 @@
ppc.cmxa: ppc.cmx
ocamlopt -ccopt $(FLAGS) -a -o $@ $<
+sparc.mli: sparc.ml
+ ocamlc -ccopt $(FLAGS) -i $< > $@
+
+sparc.cmi: sparc.mli
+ ocamlc -ccopt $(FLAGS) -c $<
+
+sparc.cmx: sparc.ml sparc.cmi
+ ocamlopt -ccopt $(FLAGS) -c $<
+
+sparc.cmxa: sparc.cmx
+ ocamlopt -ccopt $(FLAGS) -a -o $@ $<
+
+systemz.mli: systemz.ml
+ ocamlc -ccopt $(FLAGS) -i $< > $@
+
+systemz.cmi: systemz.mli
+ ocamlc -ccopt $(FLAGS) -c $<
+
+systemz.cmx: systemz.ml systemz.cmi
+ ocamlopt -ccopt $(FLAGS) -c $<
+
+systemz.cmxa: systemz.cmx
+ ocamlopt -ccopt $(FLAGS) -a -o $@ $<
+
+xcore.mli: xcore.ml
+ ocamlc -ccopt $(FLAGS) -i $< > $@
+
+xcore.cmi: xcore.mli
+ ocamlc -ccopt $(FLAGS) -c $<
+
+xcore.cmx: xcore.ml xcore.cmi
+ ocamlopt -ccopt $(FLAGS) -c $<
+
+xcore.cmxa: xcore.cmx
+ ocamlopt -ccopt $(FLAGS) -a -o $@ $<
+
clean:
- rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test test_detail test_x86 test_arm test_arm64 test_mips
+ rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test test_detail test_x86 test_arm test_arm64 test_mips test_ppc test_sparc test_systemz test_xcore
diff --git a/bindings/ocaml/capstone.ml b/bindings/ocaml/capstone.ml
index 69bf11e..04f449d 100644
--- a/bindings/ocaml/capstone.ml
+++ b/bindings/ocaml/capstone.ml
@@ -6,18 +6,25 @@
open Mips
open Ppc
open X86
+open Sparc
+open Systemz
+open Xcore
open Printf (* debug *)
type arch =
| CS_ARCH_ARM
| CS_ARCH_ARM64
| CS_ARCH_MIPS
- | CS_ARCH_PPC
| CS_ARCH_X86
+ | CS_ARCH_PPC
+ | CS_ARCH_SPARC
+ | CS_ARCH_SYSZ
+ | CS_ARCH_XCORE
+ | CS_ARCH_MAX
+ | CS_ARCH_ALL
type mode =
| CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *)
- | CS_MODE_SYNTAX_INTEL (* Intel X86 asm syntax (default for CS_ARCH_X86) *)
| CS_MODE_ARM (* ARM mode *)
| CS_MODE_16 (* 16-bit mode (for X86, Mips) *)
| CS_MODE_32 (* 32-bit mode (for X86, Mips) *)
@@ -25,15 +32,37 @@
| CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *)
| CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *)
| CS_MODE_N64 (* Nintendo-64 mode (MIPS architecture) *)
- | CS_MODE_SYNTAX_ATT (* X86 ATT asm syntax (for CS_ARCH_X86 only) *)
+ | CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *)
| CS_MODE_BIG_ENDIAN (* big-endian mode *)
+
+type opt_type =
+ | CS_OPT_SYNTAX (* Asssembly output syntax *)
+ | CS_OPT_DETAIL (* Break down instruction structure into details *)
+ | CS_OPT_MODE (* Change engine's mode at run-time *)
+ | CS_OPT_MEM (* User-defined dynamic memory related functions *)
+ | CS_OPT_SKIPDATA (* Skip data when disassembling. Then engine is in SKIPDATA mode. *)
+ | CS_OPT_SKIPDATA_SETUP (* Setup user-defined function for SKIPDATA option *)
+
+
+type opt_value =
+ | CS_OPT_OFF (* Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. *)
+ | CS_OPT_ON (* Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). *)
+ | CS_OPT_SYNTAX_DEFAULT (* Default asm syntax (CS_OPT_SYNTAX). *)
+ | CS_OPT_SYNTAX_INTEL (* X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). *)
+ | CS_OPT_SYNTAX_ATT (* X86 ATT asm syntax (CS_OPT_SYNTAX). *)
+ | CS_OPT_SYNTAX_NOREGNAME (* Prints register name with only number (CS_OPT_SYNTAX) *)
+
type cs_arch =
| CS_INFO_ARM of cs_arm
| CS_INFO_ARM64 of cs_arm64
| CS_INFO_MIPS of cs_mips
- | CS_INFO_PPC of cs_ppc
| CS_INFO_X86 of cs_x86
+ | CS_INFO_PPC of cs_ppc
+ | CS_INFO_SPARC of cs_sparc
+ | CS_INFO_SYSZ of cs_sysz
+ | CS_INFO_XCORE of cs_xcore
+
type cs_insn0 = {
id: int;
@@ -96,7 +125,7 @@
let csh = cs_open arch mode in
object
val handle = match csh with
- | None -> failwith "impossible to open an handle\n"
+ | None -> failwith "impossible to open an handle"
| Some v -> v
method get_csh = handle
diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c
index 6eb916f..72fa7a6 100644
--- a/bindings/ocaml/ocaml.c
+++ b/bindings/ocaml/ocaml.c
@@ -313,7 +313,8 @@
Store_field(tmp2, 0, tmp);
Store_field(array, i, tmp2);
}
- } else // empty array
+ } else
+ // empty array
array = Atom(0);
Store_field(op_info_val, 4, array);
@@ -419,6 +420,161 @@
Store_field(rec_insn, 12, arch_info);
break;
+ case CS_ARCH_SPARC:
+
+ arch_info = caml_alloc(1, 3);
+
+ op_info_val = caml_alloc(4, 0);
+
+ Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sparc.cc));
+ Store_field(op_info_val, 1, Val_int(insn[j-1].detail->sparc.hint));
+
+ lcount = insn[j-1].detail->sparc.op_count;
+
+ Store_field(op_info_val, 2, Val_int(lcount));
+
+ if (lcount > 0) {
+ array = caml_alloc(lcount, 0);
+ for (i = 0; i < lcount; i++) {
+ tmp2 = caml_alloc(1, 0);
+ switch(insn[j-1].detail->sparc.operands[i].type) {
+ case SPARC_OP_REG:
+ tmp = caml_alloc(1, 1);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].reg));
+ break;
+ case SPARC_OP_IMM:
+ tmp = caml_alloc(1, 2);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].imm));
+ break;
+ case SPARC_OP_MEM:
+ tmp = caml_alloc(1, 3);
+ tmp3 = caml_alloc(3, 0);
+ Store_field(tmp3, 0, Val_int(insn[j-1].detail->sparc.operands[i].mem.base));
+ Store_field(tmp3, 1, Val_int(insn[j-1].detail->sparc.operands[i].mem.index));
+ Store_field(tmp3, 2, Val_int(insn[j-1].detail->sparc.operands[i].mem.disp));
+ Store_field(tmp, 0, tmp3);
+ break;
+ default: break;
+ }
+ Store_field(tmp2, 0, tmp);
+ Store_field(array, i, tmp2);
+ }
+ } else // empty array
+ array = Atom(0);
+
+ Store_field(op_info_val, 3, array);
+
+ // finally, insert this into arch_info
+ Store_field(arch_info, 0, op_info_val);
+
+ Store_field(rec_insn, 12, arch_info);
+
+ break;
+
+ case CS_ARCH_SYSZ:
+
+ arch_info = caml_alloc(1, 3);
+
+ op_info_val = caml_alloc(3, 0);
+
+ Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sysz.cc));
+ lcount = insn[j-1].detail->sysz.op_count;
+
+ Store_field(op_info_val, 1, Val_int(lcount));
+
+ if (lcount > 0) {
+ array = caml_alloc(lcount, 0);
+ for (i = 0; i < lcount; i++) {
+ tmp2 = caml_alloc(1, 0);
+ switch(insn[j-1].detail->sysz.operands[i].type) {
+ case SYSZ_OP_REG:
+ tmp = caml_alloc(1, 1);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg));
+ break;
+ case SYSZ_OP_IMM:
+ tmp = caml_alloc(1, 2);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].imm));
+ break;
+ case SYSZ_OP_ACREG:
+ tmp = caml_alloc(1, 2);
+ Store_field(tmp, 0, Val_int(0)); /* XXX */
+ break;
+ case SYSZ_OP_MEM:
+ tmp = caml_alloc(1, 3);
+ tmp3 = caml_alloc(4, 0);
+ Store_field(tmp3, 0, Val_int(insn[j-1].detail->sysz.operands[i].mem.base));
+ Store_field(tmp3, 1, Val_int(insn[j-1].detail->sysz.operands[i].mem.index));
+ Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.length));
+ Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.disp));
+ Store_field(tmp, 0, tmp3);
+ break;
+ default: break;
+ }
+ Store_field(tmp2, 0, tmp);
+ Store_field(array, i, tmp2);
+ }
+ } else // empty array
+ array = Atom(0);
+
+ Store_field(op_info_val, 3, array);
+
+ // finally, insert this into arch_info
+ Store_field(arch_info, 0, op_info_val);
+
+ Store_field(rec_insn, 12, arch_info);
+
+ break;
+
+ case CS_ARCH_XCORE:
+
+ arch_info = caml_alloc(1, 3);
+
+ op_info_val = caml_alloc(2, 0);
+
+ lcount = insn[j-1].detail->xcore.op_count;
+
+ Store_field(op_info_val, 0, Val_int(lcount));
+
+ if (lcount > 0) {
+ array = caml_alloc(lcount, 0);
+ for (i = 0; i < lcount; i++) {
+ tmp2 = caml_alloc(1, 0);
+ switch(insn[j-1].detail->xcore.operands[i].type) {
+ case XCORE_OP_REG:
+ tmp = caml_alloc(1, 1);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].reg));
+ break;
+ case XCORE_OP_IMM:
+ tmp = caml_alloc(1, 2);
+ Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].imm));
+ break;
+ case XCORE_OP_MEM:
+ tmp = caml_alloc(1, 3);
+ tmp3 = caml_alloc(4, 0);
+ Store_field(tmp3, 0, Val_int(insn[j-1].detail->xcore.operands[i].mem.base));
+ Store_field(tmp3, 1, Val_int(insn[j-1].detail->xcore.operands[i].mem.index));
+ Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.disp));
+ Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.direct));
+ Store_field(tmp, 0, tmp3);
+ break;
+ default: break;
+ }
+ Store_field(tmp2, 0, tmp);
+ Store_field(array, i, tmp2);
+ }
+ } else
+ // empty array
+ array = Atom(0);
+
+ Store_field(op_info_val, 2, array);
+
+ // finally, insert this into arch_info
+ Store_field(arch_info, 0, op_info_val);
+
+ Store_field(rec_insn, 12, arch_info);
+
+ break;
+
default: break;
}
@@ -455,10 +611,25 @@
arch = CS_ARCH_MIPS;
break;
case 3:
- arch = CS_ARCH_PPC;
+ arch = CS_ARCH_X86;
break;
case 4:
- arch = CS_ARCH_X86;
+ arch = CS_ARCH_PPC;
+ break;
+ case 5:
+ arch = CS_ARCH_SPARC;
+ break;
+ case 6:
+ arch = CS_ARCH_SYSZ;
+ break;
+ case 7:
+ arch = CS_ARCH_XCORE;
+ break;
+ case 8:
+ arch = CS_ARCH_MAX;
+ break;
+ case 9:
+ arch = CS_ARCH_ALL;
break;
default:
caml_invalid_argument("Error message");
@@ -472,33 +643,30 @@
mode |= CS_MODE_LITTLE_ENDIAN;
break;
case 1:
- mode |= CS_OPT_SYNTAX_INTEL;
- break;
- case 2:
mode |= CS_MODE_ARM;
break;
- case 3:
+ case 2:
mode |= CS_MODE_16;
break;
- case 4:
+ case 3:
mode |= CS_MODE_32;
break;
- case 5:
+ case 4:
mode |= CS_MODE_64;
break;
- case 6:
+ case 5:
mode |= CS_MODE_THUMB;
break;
- case 7:
+ case 6:
mode |= CS_MODE_MICRO;
break;
- case 8:
+ case 7:
mode |= CS_MODE_N64;
break;
- case 9:
- mode |= CS_OPT_SYNTAX_ATT;
+ case 8:
+ mode |= CS_MODE_V9;
break;
- case 10:
+ case 9:
mode |= CS_MODE_BIG_ENDIAN;
break;
default:
@@ -507,12 +675,12 @@
}
_mode = Field(_mode, 1); /* point to the tail for next loop */
}
-
- //CS_ERR_OK = 0, // No error: everything was fine
- if (cs_open(arch, mode, &handle) != 0)
+ cs_err ret = cs_open(arch, mode, &handle);
+ if (ret != CS_ERR_OK) {
return Val_emptylist;
+ }
- if (cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON) != 0)
+ if (cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON) != CS_ERR_OK)
CAMLreturn(Val_int(0));
code = (uint8_t *)String_val(_code);
@@ -563,10 +731,25 @@
arch = CS_ARCH_MIPS;
break;
case 3:
- arch = CS_ARCH_PPC;
+ arch = CS_ARCH_X86;
break;
case 4:
- arch = CS_ARCH_X86;
+ arch = CS_ARCH_PPC;
+ break;
+ case 5:
+ arch = CS_ARCH_SPARC;
+ break;
+ case 6:
+ arch = CS_ARCH_SYSZ;
+ break;
+ case 7:
+ arch = CS_ARCH_XCORE;
+ break;
+ case 8:
+ arch = CS_ARCH_MAX;
+ break;
+ case 9:
+ arch = CS_ARCH_ALL;
break;
default:
caml_invalid_argument("Error message");
@@ -581,33 +764,30 @@
mode |= CS_MODE_LITTLE_ENDIAN;
break;
case 1:
- mode |= CS_OPT_SYNTAX_INTEL;
- break;
- case 2:
mode |= CS_MODE_ARM;
break;
- case 3:
+ case 2:
mode |= CS_MODE_16;
break;
- case 4:
+ case 3:
mode |= CS_MODE_32;
break;
- case 5:
+ case 4:
mode |= CS_MODE_64;
break;
- case 6:
+ case 5:
mode |= CS_MODE_THUMB;
break;
- case 7:
+ case 6:
mode |= CS_MODE_MICRO;
break;
- case 8:
+ case 7:
mode |= CS_MODE_N64;
break;
- case 9:
- mode |= CS_OPT_SYNTAX_ATT;
+ case 8:
+ mode |= CS_MODE_V9;
break;
- case 10:
+ case 9:
mode |= CS_MODE_BIG_ENDIAN;
break;
default:
diff --git a/bindings/ocaml/sparc.ml b/bindings/ocaml/sparc.ml
new file mode 100644
index 0000000..e32dac3
--- /dev/null
+++ b/bindings/ocaml/sparc.ml
@@ -0,0 +1,463 @@
+(* Capstone Disassembler Engine
+ * By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+type sparc_op_mem = {
+ base: int;
+ index: int;
+ displ: int;
+}
+
+type sparc_op =
+ | SPARC_OP_INVALID of int
+ | SPARC_OP_REG of int
+ | SPARC_OP_IMM of int
+ | SPARC_OP_MEM of sparc_op_mem
+
+type cs_sparc = {
+ cc: int;
+ hint: int;
+ op_count: int;
+ operands: sparc_op array;
+}
+
+(* Enums corresponding to Sparc condition codes, both icc's and fcc's. *)
+
+let _SPARC_CC_INVALID = 0;;
+
+(* Integer condition codes *)
+let _SPARC_CC_ICC_A = 8+256;;
+let _SPARC_CC_ICC_N = 0+256;;
+let _SPARC_CC_ICC_NE = 9+256;;
+let _SPARC_CC_ICC_E = 1+256;;
+let _SPARC_CC_ICC_G = 10+256;;
+let _SPARC_CC_ICC_LE = 2+256;;
+let _SPARC_CC_ICC_GE = 11+256;;
+let _SPARC_CC_ICC_L = 3+256;;
+let _SPARC_CC_ICC_GU = 12+256;;
+let _SPARC_CC_ICC_LEU = 4+256;;
+let _SPARC_CC_ICC_CC = 13+256;;
+let _SPARC_CC_ICC_CS = 5+256;;
+let _SPARC_CC_ICC_POS = 14+256;;
+let _SPARC_CC_ICC_NEG = 6+256;;
+let _SPARC_CC_ICC_VC = 15+256;;
+let _SPARC_CC_ICC_VS = 7+256;;
+
+(* Floating condition codes *)
+let _SPARC_CC_FCC_A = 8+16+256;;
+let _SPARC_CC_FCC_N = 0+16+256;;
+let _SPARC_CC_FCC_U = 7+16+256;;
+let _SPARC_CC_FCC_G = 6+16+256;;
+let _SPARC_CC_FCC_UG = 5+16+256;;
+let _SPARC_CC_FCC_L = 4+16+256;;
+let _SPARC_CC_FCC_UL = 3+16+256;;
+let _SPARC_CC_FCC_LG = 2+16+256;;
+let _SPARC_CC_FCC_NE = 1+16+256;;
+let _SPARC_CC_FCC_E = 9+16+256;;
+let _SPARC_CC_FCC_UE = 10+16+256;;
+let _SPARC_CC_FCC_GE = 11+16+256;;
+let _SPARC_CC_FCC_UGE = 12+16+256;;
+let _SPARC_CC_FCC_LE = 13+16+256;;
+let _SPARC_CC_FCC_ULE = 14+16+256;;
+let _SPARC_CC_FCC_O = 15+16+256;;
+
+(* Branch hint *)
+let _SPARC_HINT_INVALID = 0;;
+let _SPARC_HINT_A = 1 lsl 0;;
+let _SPARC_HINT_PT = 1 lsl 1;;
+let _SPARC_HINT_PN = 1 lsl 2;;
+
+(* Operand type for instruction's operands *)
+
+let _SPARC_OP_INVALID = 0;;
+let _SPARC_OP_REG = 1;;
+let _SPARC_OP_IMM = 2;;
+let _SPARC_OP_MEM = 3;;
+
+(* SPARC registers *)
+
+let _SPARC_REG_INVALID = 0;;
+let _SPARC_REG_F0 = 1;;
+let _SPARC_REG_F1 = 2;;
+let _SPARC_REG_F2 = 3;;
+let _SPARC_REG_F3 = 4;;
+let _SPARC_REG_F4 = 5;;
+let _SPARC_REG_F5 = 6;;
+let _SPARC_REG_F6 = 7;;
+let _SPARC_REG_F7 = 8;;
+let _SPARC_REG_F8 = 9;;
+let _SPARC_REG_F9 = 10;;
+let _SPARC_REG_F10 = 11;;
+let _SPARC_REG_F11 = 12;;
+let _SPARC_REG_F12 = 13;;
+let _SPARC_REG_F13 = 14;;
+let _SPARC_REG_F14 = 15;;
+let _SPARC_REG_F15 = 16;;
+let _SPARC_REG_F16 = 17;;
+let _SPARC_REG_F17 = 18;;
+let _SPARC_REG_F18 = 19;;
+let _SPARC_REG_F19 = 20;;
+let _SPARC_REG_F20 = 21;;
+let _SPARC_REG_F21 = 22;;
+let _SPARC_REG_F22 = 23;;
+let _SPARC_REG_F23 = 24;;
+let _SPARC_REG_F24 = 25;;
+let _SPARC_REG_F25 = 26;;
+let _SPARC_REG_F26 = 27;;
+let _SPARC_REG_F27 = 28;;
+let _SPARC_REG_F28 = 29;;
+let _SPARC_REG_F29 = 30;;
+let _SPARC_REG_F30 = 31;;
+let _SPARC_REG_F31 = 32;;
+let _SPARC_REG_F32 = 33;;
+let _SPARC_REG_F34 = 34;;
+let _SPARC_REG_F36 = 35;;
+let _SPARC_REG_F38 = 36;;
+let _SPARC_REG_F40 = 37;;
+let _SPARC_REG_F42 = 38;;
+let _SPARC_REG_F44 = 39;;
+let _SPARC_REG_F46 = 40;;
+let _SPARC_REG_F48 = 41;;
+let _SPARC_REG_F50 = 42;;
+let _SPARC_REG_F52 = 43;;
+let _SPARC_REG_F54 = 44;;
+let _SPARC_REG_F56 = 45;;
+let _SPARC_REG_F58 = 46;;
+let _SPARC_REG_F60 = 47;;
+let _SPARC_REG_F62 = 48;;
+let _SPARC_REG_FCC0 = 49;;
+let _SPARC_REG_FCC1 = 50;;
+let _SPARC_REG_FCC2 = 51;;
+let _SPARC_REG_FCC3 = 52;;
+let _SPARC_REG_FP = 53;;
+let _SPARC_REG_G0 = 54;;
+let _SPARC_REG_G1 = 55;;
+let _SPARC_REG_G2 = 56;;
+let _SPARC_REG_G3 = 57;;
+let _SPARC_REG_G4 = 58;;
+let _SPARC_REG_G5 = 59;;
+let _SPARC_REG_G6 = 60;;
+let _SPARC_REG_G7 = 61;;
+let _SPARC_REG_I0 = 62;;
+let _SPARC_REG_I1 = 63;;
+let _SPARC_REG_I2 = 64;;
+let _SPARC_REG_I3 = 65;;
+let _SPARC_REG_I4 = 66;;
+let _SPARC_REG_I5 = 67;;
+let _SPARC_REG_I7 = 68;;
+let _SPARC_REG_ICC = 69;;
+let _SPARC_REG_L0 = 70;;
+let _SPARC_REG_L1 = 71;;
+let _SPARC_REG_L2 = 72;;
+let _SPARC_REG_L3 = 73;;
+let _SPARC_REG_L4 = 74;;
+let _SPARC_REG_L5 = 75;;
+let _SPARC_REG_L6 = 76;;
+let _SPARC_REG_L7 = 77;;
+let _SPARC_REG_O0 = 78;;
+let _SPARC_REG_O1 = 79;;
+let _SPARC_REG_O2 = 80;;
+let _SPARC_REG_O3 = 81;;
+let _SPARC_REG_O4 = 82;;
+let _SPARC_REG_O5 = 83;;
+let _SPARC_REG_O7 = 84;;
+let _SPARC_REG_SP = 85;;
+let _SPARC_REG_Y = 86;;
+let _SPARC_REG_MAX = 87;;
+let _SPARC_REG_O6 = _SPARC_REG_SP;;
+let _SPARC_REG_I6 = _SPARC_REG_FP;;
+
+(* SPARC instruction *)
+
+let _SPARC_INS_INVALID = 0;;
+let _SPARC_INS_ADDCC = 1;;
+let _SPARC_INS_ADDX = 2;;
+let _SPARC_INS_ADDXCC = 3;;
+let _SPARC_INS_ADDXC = 4;;
+let _SPARC_INS_ADDXCCC = 5;;
+let _SPARC_INS_ADD = 6;;
+let _SPARC_INS_ALIGNADDR = 7;;
+let _SPARC_INS_ALIGNADDRL = 8;;
+let _SPARC_INS_ANDCC = 9;;
+let _SPARC_INS_ANDNCC = 10;;
+let _SPARC_INS_ANDN = 11;;
+let _SPARC_INS_AND = 12;;
+let _SPARC_INS_ARRAY16 = 13;;
+let _SPARC_INS_ARRAY32 = 14;;
+let _SPARC_INS_ARRAY8 = 15;;
+let _SPARC_INS_BA = 16;;
+let _SPARC_INS_B = 17;;
+let _SPARC_INS_JMP = 18;;
+let _SPARC_INS_BMASK = 19;;
+let _SPARC_INS_FB = 20;;
+let _SPARC_INS_BRGEZ = 21;;
+let _SPARC_INS_BRGZ = 22;;
+let _SPARC_INS_BRLEZ = 23;;
+let _SPARC_INS_BRLZ = 24;;
+let _SPARC_INS_BRNZ = 25;;
+let _SPARC_INS_BRZ = 26;;
+let _SPARC_INS_BSHUFFLE = 27;;
+let _SPARC_INS_CALL = 28;;
+let _SPARC_INS_CASX = 29;;
+let _SPARC_INS_CAS = 30;;
+let _SPARC_INS_CMASK16 = 31;;
+let _SPARC_INS_CMASK32 = 32;;
+let _SPARC_INS_CMASK8 = 33;;
+let _SPARC_INS_CMP = 34;;
+let _SPARC_INS_EDGE16 = 35;;
+let _SPARC_INS_EDGE16L = 36;;
+let _SPARC_INS_EDGE16LN = 37;;
+let _SPARC_INS_EDGE16N = 38;;
+let _SPARC_INS_EDGE32 = 39;;
+let _SPARC_INS_EDGE32L = 40;;
+let _SPARC_INS_EDGE32LN = 41;;
+let _SPARC_INS_EDGE32N = 42;;
+let _SPARC_INS_EDGE8 = 43;;
+let _SPARC_INS_EDGE8L = 44;;
+let _SPARC_INS_EDGE8LN = 45;;
+let _SPARC_INS_EDGE8N = 46;;
+let _SPARC_INS_FABSD = 47;;
+let _SPARC_INS_FABSQ = 48;;
+let _SPARC_INS_FABSS = 49;;
+let _SPARC_INS_FADDD = 50;;
+let _SPARC_INS_FADDQ = 51;;
+let _SPARC_INS_FADDS = 52;;
+let _SPARC_INS_FALIGNDATA = 53;;
+let _SPARC_INS_FAND = 54;;
+let _SPARC_INS_FANDNOT1 = 55;;
+let _SPARC_INS_FANDNOT1S = 56;;
+let _SPARC_INS_FANDNOT2 = 57;;
+let _SPARC_INS_FANDNOT2S = 58;;
+let _SPARC_INS_FANDS = 59;;
+let _SPARC_INS_FCHKSM16 = 60;;
+let _SPARC_INS_FCMPD = 61;;
+let _SPARC_INS_FCMPEQ16 = 62;;
+let _SPARC_INS_FCMPEQ32 = 63;;
+let _SPARC_INS_FCMPGT16 = 64;;
+let _SPARC_INS_FCMPGT32 = 65;;
+let _SPARC_INS_FCMPLE16 = 66;;
+let _SPARC_INS_FCMPLE32 = 67;;
+let _SPARC_INS_FCMPNE16 = 68;;
+let _SPARC_INS_FCMPNE32 = 69;;
+let _SPARC_INS_FCMPQ = 70;;
+let _SPARC_INS_FCMPS = 71;;
+let _SPARC_INS_FDIVD = 72;;
+let _SPARC_INS_FDIVQ = 73;;
+let _SPARC_INS_FDIVS = 74;;
+let _SPARC_INS_FDMULQ = 75;;
+let _SPARC_INS_FDTOI = 76;;
+let _SPARC_INS_FDTOQ = 77;;
+let _SPARC_INS_FDTOS = 78;;
+let _SPARC_INS_FDTOX = 79;;
+let _SPARC_INS_FEXPAND = 80;;
+let _SPARC_INS_FHADDD = 81;;
+let _SPARC_INS_FHADDS = 82;;
+let _SPARC_INS_FHSUBD = 83;;
+let _SPARC_INS_FHSUBS = 84;;
+let _SPARC_INS_FITOD = 85;;
+let _SPARC_INS_FITOQ = 86;;
+let _SPARC_INS_FITOS = 87;;
+let _SPARC_INS_FLCMPD = 88;;
+let _SPARC_INS_FLCMPS = 89;;
+let _SPARC_INS_FLUSHW = 90;;
+let _SPARC_INS_FMEAN16 = 91;;
+let _SPARC_INS_FMOVD = 92;;
+let _SPARC_INS_FMOVQ = 93;;
+let _SPARC_INS_FMOVRDGEZ = 94;;
+let _SPARC_INS_FMOVRQGEZ = 95;;
+let _SPARC_INS_FMOVRSGEZ = 96;;
+let _SPARC_INS_FMOVRDGZ = 97;;
+let _SPARC_INS_FMOVRQGZ = 98;;
+let _SPARC_INS_FMOVRSGZ = 99;;
+let _SPARC_INS_FMOVRDLEZ = 100;;
+let _SPARC_INS_FMOVRQLEZ = 101;;
+let _SPARC_INS_FMOVRSLEZ = 102;;
+let _SPARC_INS_FMOVRDLZ = 103;;
+let _SPARC_INS_FMOVRQLZ = 104;;
+let _SPARC_INS_FMOVRSLZ = 105;;
+let _SPARC_INS_FMOVRDNZ = 106;;
+let _SPARC_INS_FMOVRQNZ = 107;;
+let _SPARC_INS_FMOVRSNZ = 108;;
+let _SPARC_INS_FMOVRDZ = 109;;
+let _SPARC_INS_FMOVRQZ = 110;;
+let _SPARC_INS_FMOVRSZ = 111;;
+let _SPARC_INS_FMOVS = 112;;
+let _SPARC_INS_FMUL8SUX16 = 113;;
+let _SPARC_INS_FMUL8ULX16 = 114;;
+let _SPARC_INS_FMUL8X16 = 115;;
+let _SPARC_INS_FMUL8X16AL = 116;;
+let _SPARC_INS_FMUL8X16AU = 117;;
+let _SPARC_INS_FMULD = 118;;
+let _SPARC_INS_FMULD8SUX16 = 119;;
+let _SPARC_INS_FMULD8ULX16 = 120;;
+let _SPARC_INS_FMULQ = 121;;
+let _SPARC_INS_FMULS = 122;;
+let _SPARC_INS_FNADDD = 123;;
+let _SPARC_INS_FNADDS = 124;;
+let _SPARC_INS_FNAND = 125;;
+let _SPARC_INS_FNANDS = 126;;
+let _SPARC_INS_FNEGD = 127;;
+let _SPARC_INS_FNEGQ = 128;;
+let _SPARC_INS_FNEGS = 129;;
+let _SPARC_INS_FNHADDD = 130;;
+let _SPARC_INS_FNHADDS = 131;;
+let _SPARC_INS_FNOR = 132;;
+let _SPARC_INS_FNORS = 133;;
+let _SPARC_INS_FNOT1 = 134;;
+let _SPARC_INS_FNOT1S = 135;;
+let _SPARC_INS_FNOT2 = 136;;
+let _SPARC_INS_FNOT2S = 137;;
+let _SPARC_INS_FONE = 138;;
+let _SPARC_INS_FONES = 139;;
+let _SPARC_INS_FOR = 140;;
+let _SPARC_INS_FORNOT1 = 141;;
+let _SPARC_INS_FORNOT1S = 142;;
+let _SPARC_INS_FORNOT2 = 143;;
+let _SPARC_INS_FORNOT2S = 144;;
+let _SPARC_INS_FORS = 145;;
+let _SPARC_INS_FPACK16 = 146;;
+let _SPARC_INS_FPACK32 = 147;;
+let _SPARC_INS_FPACKFIX = 148;;
+let _SPARC_INS_FPADD16 = 149;;
+let _SPARC_INS_FPADD16S = 150;;
+let _SPARC_INS_FPADD32 = 151;;
+let _SPARC_INS_FPADD32S = 152;;
+let _SPARC_INS_FPADD64 = 153;;
+let _SPARC_INS_FPMERGE = 154;;
+let _SPARC_INS_FPSUB16 = 155;;
+let _SPARC_INS_FPSUB16S = 156;;
+let _SPARC_INS_FPSUB32 = 157;;
+let _SPARC_INS_FPSUB32S = 158;;
+let _SPARC_INS_FQTOD = 159;;
+let _SPARC_INS_FQTOI = 160;;
+let _SPARC_INS_FQTOS = 161;;
+let _SPARC_INS_FQTOX = 162;;
+let _SPARC_INS_FSLAS16 = 163;;
+let _SPARC_INS_FSLAS32 = 164;;
+let _SPARC_INS_FSLL16 = 165;;
+let _SPARC_INS_FSLL32 = 166;;
+let _SPARC_INS_FSMULD = 167;;
+let _SPARC_INS_FSQRTD = 168;;
+let _SPARC_INS_FSQRTQ = 169;;
+let _SPARC_INS_FSQRTS = 170;;
+let _SPARC_INS_FSRA16 = 171;;
+let _SPARC_INS_FSRA32 = 172;;
+let _SPARC_INS_FSRC1 = 173;;
+let _SPARC_INS_FSRC1S = 174;;
+let _SPARC_INS_FSRC2 = 175;;
+let _SPARC_INS_FSRC2S = 176;;
+let _SPARC_INS_FSRL16 = 177;;
+let _SPARC_INS_FSRL32 = 178;;
+let _SPARC_INS_FSTOD = 179;;
+let _SPARC_INS_FSTOI = 180;;
+let _SPARC_INS_FSTOQ = 181;;
+let _SPARC_INS_FSTOX = 182;;
+let _SPARC_INS_FSUBD = 183;;
+let _SPARC_INS_FSUBQ = 184;;
+let _SPARC_INS_FSUBS = 185;;
+let _SPARC_INS_FXNOR = 186;;
+let _SPARC_INS_FXNORS = 187;;
+let _SPARC_INS_FXOR = 188;;
+let _SPARC_INS_FXORS = 189;;
+let _SPARC_INS_FXTOD = 190;;
+let _SPARC_INS_FXTOQ = 191;;
+let _SPARC_INS_FXTOS = 192;;
+let _SPARC_INS_FZERO = 193;;
+let _SPARC_INS_FZEROS = 194;;
+let _SPARC_INS_JMPL = 195;;
+let _SPARC_INS_LDD = 196;;
+let _SPARC_INS_LD = 197;;
+let _SPARC_INS_LDQ = 198;;
+let _SPARC_INS_LDSB = 199;;
+let _SPARC_INS_LDSH = 200;;
+let _SPARC_INS_LDSW = 201;;
+let _SPARC_INS_LDUB = 202;;
+let _SPARC_INS_LDUH = 203;;
+let _SPARC_INS_LDX = 204;;
+let _SPARC_INS_LZCNT = 205;;
+let _SPARC_INS_MEMBAR = 206;;
+let _SPARC_INS_MOVDTOX = 207;;
+let _SPARC_INS_MOV = 208;;
+let _SPARC_INS_MOVRGEZ = 209;;
+let _SPARC_INS_MOVRGZ = 210;;
+let _SPARC_INS_MOVRLEZ = 211;;
+let _SPARC_INS_MOVRLZ = 212;;
+let _SPARC_INS_MOVRNZ = 213;;
+let _SPARC_INS_MOVRZ = 214;;
+let _SPARC_INS_MOVSTOSW = 215;;
+let _SPARC_INS_MOVSTOUW = 216;;
+let _SPARC_INS_MULX = 217;;
+let _SPARC_INS_NOP = 218;;
+let _SPARC_INS_ORCC = 219;;
+let _SPARC_INS_ORNCC = 220;;
+let _SPARC_INS_ORN = 221;;
+let _SPARC_INS_OR = 222;;
+let _SPARC_INS_PDIST = 223;;
+let _SPARC_INS_PDISTN = 224;;
+let _SPARC_INS_POPC = 225;;
+let _SPARC_INS_RD = 226;;
+let _SPARC_INS_RESTORE = 227;;
+let _SPARC_INS_RETT = 228;;
+let _SPARC_INS_SAVE = 229;;
+let _SPARC_INS_SDIVCC = 230;;
+let _SPARC_INS_SDIVX = 231;;
+let _SPARC_INS_SDIV = 232;;
+let _SPARC_INS_SETHI = 233;;
+let _SPARC_INS_SHUTDOWN = 234;;
+let _SPARC_INS_SIAM = 235;;
+let _SPARC_INS_SLLX = 236;;
+let _SPARC_INS_SLL = 237;;
+let _SPARC_INS_SMULCC = 238;;
+let _SPARC_INS_SMUL = 239;;
+let _SPARC_INS_SRAX = 240;;
+let _SPARC_INS_SRA = 241;;
+let _SPARC_INS_SRLX = 242;;
+let _SPARC_INS_SRL = 243;;
+let _SPARC_INS_STBAR = 244;;
+let _SPARC_INS_STB = 245;;
+let _SPARC_INS_STD = 246;;
+let _SPARC_INS_ST = 247;;
+let _SPARC_INS_STH = 248;;
+let _SPARC_INS_STQ = 249;;
+let _SPARC_INS_STX = 250;;
+let _SPARC_INS_SUBCC = 251;;
+let _SPARC_INS_SUBX = 252;;
+let _SPARC_INS_SUBXCC = 253;;
+let _SPARC_INS_SUB = 254;;
+let _SPARC_INS_SWAP = 255;;
+let _SPARC_INS_TA = 256;;
+let _SPARC_INS_TADDCCTV = 257;;
+let _SPARC_INS_TADDCC = 258;;
+let _SPARC_INS_T = 259;;
+let _SPARC_INS_TSUBCCTV = 260;;
+let _SPARC_INS_TSUBCC = 261;;
+let _SPARC_INS_UDIVCC = 262;;
+let _SPARC_INS_UDIVX = 263;;
+let _SPARC_INS_UDIV = 264;;
+let _SPARC_INS_UMULCC = 265;;
+let _SPARC_INS_UMULXHI = 266;;
+let _SPARC_INS_UMUL = 267;;
+let _SPARC_INS_UNIMP = 268;;
+let _SPARC_INS_FCMPED = 269;;
+let _SPARC_INS_FCMPEQ = 270;;
+let _SPARC_INS_FCMPES = 271;;
+let _SPARC_INS_WR = 272;;
+let _SPARC_INS_XMULX = 273;;
+let _SPARC_INS_XMULXHI = 274;;
+let _SPARC_INS_XNORCC = 275;;
+let _SPARC_INS_XNOR = 276;;
+let _SPARC_INS_XORCC = 277;;
+let _SPARC_INS_XOR = 278;;
+let _SPARC_INS_MAX = 279;;
+
+(* Group of SPARC instructions *)
+
+let _SPARC_GRP_INVALID = 0;;
+let _SPARC_GRP_HARDQUAD = 1;;
+let _SPARC_GRP_V9 = 2;;
+let _SPARC_GRP_VIS = 3;;
+let _SPARC_GRP_VIS2 = 4;;
+let _SPARC_GRP_VIS3 = 5;;
+let _SPARC_GRP_32BIT = 6;;
+let _SPARC_GRP_64BIT = 7;;
+let _SPARC_GRP_JUMP = 8;;
+let _SPARC_GRP_MAX = 9;;
diff --git a/bindings/ocaml/systemz.ml b/bindings/ocaml/systemz.ml
new file mode 100644
index 0000000..c96ac50
--- /dev/null
+++ b/bindings/ocaml/systemz.ml
@@ -0,0 +1,783 @@
+(* Capstone Disassembler Engine
+ * By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+type sysz_op_mem = {
+ base: int;
+ index: int;
+ length: int64;
+ displ: int64;
+}
+
+type sysz_op =
+ | SYSZ_OP_INVALID of int
+ | SYSZ_OP_REG of int
+ | SYSZ_OP_ACREG of int
+ | SYSZ_OP_IMM of int
+ | SYSZ_OP_MEM of sysz_op_mem
+
+type cs_sysz = {
+ cc: int;
+ op_count: int;
+ operands: sysz_op array;
+}
+
+
+
+(* Enums corresponding to SystemZ condition codes *)
+
+let _SYSZ_CC_INVALID = 0;;
+let _SYSZ_CC_O = 1;;
+let _SYSZ_CC_H = 2;;
+let _SYSZ_CC_NLE = 3;;
+let _SYSZ_CC_L = 4;;
+let _SYSZ_CC_NHE = 5;;
+let _SYSZ_CC_LH = 6;;
+let _SYSZ_CC_NE = 7;;
+let _SYSZ_CC_E = 8;;
+let _SYSZ_CC_NLH = 9;;
+let _SYSZ_CC_HE = 10;;
+let _SYSZ_CC_NL = 11;;
+let _SYSZ_CC_LE = 12;;
+let _SYSZ_CC_NH = 13;;
+let _SYSZ_CC_NO = 14;;
+
+(* Operand type for instruction's operands *)
+
+let _SYSZ_OP_INVALID = 0;;
+let _SYSZ_OP_REG = 1;;
+let _SYSZ_OP_ACREG = 2;;
+let _SYSZ_OP_IMM = 3;;
+let _SYSZ_OP_MEM = 4;;
+
+(* SystemZ registers *)
+
+let _SYSZ_REG_INVALID = 0;;
+let _SYSZ_REG_0 = 1;;
+let _SYSZ_REG_1 = 2;;
+let _SYSZ_REG_2 = 3;;
+let _SYSZ_REG_3 = 4;;
+let _SYSZ_REG_4 = 5;;
+let _SYSZ_REG_5 = 6;;
+let _SYSZ_REG_6 = 7;;
+let _SYSZ_REG_7 = 8;;
+let _SYSZ_REG_8 = 9;;
+let _SYSZ_REG_9 = 10;;
+let _SYSZ_REG_10 = 11;;
+let _SYSZ_REG_11 = 12;;
+let _SYSZ_REG_12 = 13;;
+let _SYSZ_REG_13 = 14;;
+let _SYSZ_REG_14 = 15;;
+let _SYSZ_REG_15 = 16;;
+let _SYSZ_REG_CC = 17;;
+let _SYSZ_REG_F0 = 18;;
+let _SYSZ_REG_F1 = 19;;
+let _SYSZ_REG_F2 = 20;;
+let _SYSZ_REG_F3 = 21;;
+let _SYSZ_REG_F4 = 22;;
+let _SYSZ_REG_F5 = 23;;
+let _SYSZ_REG_F6 = 24;;
+let _SYSZ_REG_F7 = 25;;
+let _SYSZ_REG_F8 = 26;;
+let _SYSZ_REG_F9 = 27;;
+let _SYSZ_REG_F10 = 28;;
+let _SYSZ_REG_F11 = 29;;
+let _SYSZ_REG_F12 = 30;;
+let _SYSZ_REG_F13 = 31;;
+let _SYSZ_REG_F14 = 32;;
+let _SYSZ_REG_F15 = 33;;
+let _SYSZ_REG_R0L = 34;;
+let _SYSZ_REG_MAX = 35;;
+
+(* SystemZ instruction *)
+
+let _SYSZ_INS_INVALID = 0;;
+let _SYSZ_INS_A = 1;;
+let _SYSZ_INS_ADB = 2;;
+let _SYSZ_INS_ADBR = 3;;
+let _SYSZ_INS_AEB = 4;;
+let _SYSZ_INS_AEBR = 5;;
+let _SYSZ_INS_AFI = 6;;
+let _SYSZ_INS_AG = 7;;
+let _SYSZ_INS_AGF = 8;;
+let _SYSZ_INS_AGFI = 9;;
+let _SYSZ_INS_AGFR = 10;;
+let _SYSZ_INS_AGHI = 11;;
+let _SYSZ_INS_AGHIK = 12;;
+let _SYSZ_INS_AGR = 13;;
+let _SYSZ_INS_AGRK = 14;;
+let _SYSZ_INS_AGSI = 15;;
+let _SYSZ_INS_AH = 16;;
+let _SYSZ_INS_AHI = 17;;
+let _SYSZ_INS_AHIK = 18;;
+let _SYSZ_INS_AHY = 19;;
+let _SYSZ_INS_AIH = 20;;
+let _SYSZ_INS_AL = 21;;
+let _SYSZ_INS_ALC = 22;;
+let _SYSZ_INS_ALCG = 23;;
+let _SYSZ_INS_ALCGR = 24;;
+let _SYSZ_INS_ALCR = 25;;
+let _SYSZ_INS_ALFI = 26;;
+let _SYSZ_INS_ALG = 27;;
+let _SYSZ_INS_ALGF = 28;;
+let _SYSZ_INS_ALGFI = 29;;
+let _SYSZ_INS_ALGFR = 30;;
+let _SYSZ_INS_ALGHSIK = 31;;
+let _SYSZ_INS_ALGR = 32;;
+let _SYSZ_INS_ALGRK = 33;;
+let _SYSZ_INS_ALHSIK = 34;;
+let _SYSZ_INS_ALR = 35;;
+let _SYSZ_INS_ALRK = 36;;
+let _SYSZ_INS_ALY = 37;;
+let _SYSZ_INS_AR = 38;;
+let _SYSZ_INS_ARK = 39;;
+let _SYSZ_INS_ASI = 40;;
+let _SYSZ_INS_AXBR = 41;;
+let _SYSZ_INS_AY = 42;;
+let _SYSZ_INS_BCR = 43;;
+let _SYSZ_INS_BRC = 44;;
+let _SYSZ_INS_BRCL = 45;;
+let _SYSZ_INS_CGIJ = 46;;
+let _SYSZ_INS_CGRJ = 47;;
+let _SYSZ_INS_CIJ = 48;;
+let _SYSZ_INS_CLGIJ = 49;;
+let _SYSZ_INS_CLGRJ = 50;;
+let _SYSZ_INS_CLIJ = 51;;
+let _SYSZ_INS_CLRJ = 52;;
+let _SYSZ_INS_CRJ = 53;;
+let _SYSZ_INS_BER = 54;;
+let _SYSZ_INS_JE = 55;;
+let _SYSZ_INS_JGE = 56;;
+let _SYSZ_INS_LOCE = 57;;
+let _SYSZ_INS_LOCGE = 58;;
+let _SYSZ_INS_LOCGRE = 59;;
+let _SYSZ_INS_LOCRE = 60;;
+let _SYSZ_INS_STOCE = 61;;
+let _SYSZ_INS_STOCGE = 62;;
+let _SYSZ_INS_BHR = 63;;
+let _SYSZ_INS_BHER = 64;;
+let _SYSZ_INS_JHE = 65;;
+let _SYSZ_INS_JGHE = 66;;
+let _SYSZ_INS_LOCHE = 67;;
+let _SYSZ_INS_LOCGHE = 68;;
+let _SYSZ_INS_LOCGRHE = 69;;
+let _SYSZ_INS_LOCRHE = 70;;
+let _SYSZ_INS_STOCHE = 71;;
+let _SYSZ_INS_STOCGHE = 72;;
+let _SYSZ_INS_JH = 73;;
+let _SYSZ_INS_JGH = 74;;
+let _SYSZ_INS_LOCH = 75;;
+let _SYSZ_INS_LOCGH = 76;;
+let _SYSZ_INS_LOCGRH = 77;;
+let _SYSZ_INS_LOCRH = 78;;
+let _SYSZ_INS_STOCH = 79;;
+let _SYSZ_INS_STOCGH = 80;;
+let _SYSZ_INS_CGIJNLH = 81;;
+let _SYSZ_INS_CGRJNLH = 82;;
+let _SYSZ_INS_CIJNLH = 83;;
+let _SYSZ_INS_CLGIJNLH = 84;;
+let _SYSZ_INS_CLGRJNLH = 85;;
+let _SYSZ_INS_CLIJNLH = 86;;
+let _SYSZ_INS_CLRJNLH = 87;;
+let _SYSZ_INS_CRJNLH = 88;;
+let _SYSZ_INS_CGIJE = 89;;
+let _SYSZ_INS_CGRJE = 90;;
+let _SYSZ_INS_CIJE = 91;;
+let _SYSZ_INS_CLGIJE = 92;;
+let _SYSZ_INS_CLGRJE = 93;;
+let _SYSZ_INS_CLIJE = 94;;
+let _SYSZ_INS_CLRJE = 95;;
+let _SYSZ_INS_CRJE = 96;;
+let _SYSZ_INS_CGIJNLE = 97;;
+let _SYSZ_INS_CGRJNLE = 98;;
+let _SYSZ_INS_CIJNLE = 99;;
+let _SYSZ_INS_CLGIJNLE = 100;;
+let _SYSZ_INS_CLGRJNLE = 101;;
+let _SYSZ_INS_CLIJNLE = 102;;
+let _SYSZ_INS_CLRJNLE = 103;;
+let _SYSZ_INS_CRJNLE = 104;;
+let _SYSZ_INS_CGIJH = 105;;
+let _SYSZ_INS_CGRJH = 106;;
+let _SYSZ_INS_CIJH = 107;;
+let _SYSZ_INS_CLGIJH = 108;;
+let _SYSZ_INS_CLGRJH = 109;;
+let _SYSZ_INS_CLIJH = 110;;
+let _SYSZ_INS_CLRJH = 111;;
+let _SYSZ_INS_CRJH = 112;;
+let _SYSZ_INS_CGIJNL = 113;;
+let _SYSZ_INS_CGRJNL = 114;;
+let _SYSZ_INS_CIJNL = 115;;
+let _SYSZ_INS_CLGIJNL = 116;;
+let _SYSZ_INS_CLGRJNL = 117;;
+let _SYSZ_INS_CLIJNL = 118;;
+let _SYSZ_INS_CLRJNL = 119;;
+let _SYSZ_INS_CRJNL = 120;;
+let _SYSZ_INS_CGIJHE = 121;;
+let _SYSZ_INS_CGRJHE = 122;;
+let _SYSZ_INS_CIJHE = 123;;
+let _SYSZ_INS_CLGIJHE = 124;;
+let _SYSZ_INS_CLGRJHE = 125;;
+let _SYSZ_INS_CLIJHE = 126;;
+let _SYSZ_INS_CLRJHE = 127;;
+let _SYSZ_INS_CRJHE = 128;;
+let _SYSZ_INS_CGIJNHE = 129;;
+let _SYSZ_INS_CGRJNHE = 130;;
+let _SYSZ_INS_CIJNHE = 131;;
+let _SYSZ_INS_CLGIJNHE = 132;;
+let _SYSZ_INS_CLGRJNHE = 133;;
+let _SYSZ_INS_CLIJNHE = 134;;
+let _SYSZ_INS_CLRJNHE = 135;;
+let _SYSZ_INS_CRJNHE = 136;;
+let _SYSZ_INS_CGIJL = 137;;
+let _SYSZ_INS_CGRJL = 138;;
+let _SYSZ_INS_CIJL = 139;;
+let _SYSZ_INS_CLGIJL = 140;;
+let _SYSZ_INS_CLGRJL = 141;;
+let _SYSZ_INS_CLIJL = 142;;
+let _SYSZ_INS_CLRJL = 143;;
+let _SYSZ_INS_CRJL = 144;;
+let _SYSZ_INS_CGIJNH = 145;;
+let _SYSZ_INS_CGRJNH = 146;;
+let _SYSZ_INS_CIJNH = 147;;
+let _SYSZ_INS_CLGIJNH = 148;;
+let _SYSZ_INS_CLGRJNH = 149;;
+let _SYSZ_INS_CLIJNH = 150;;
+let _SYSZ_INS_CLRJNH = 151;;
+let _SYSZ_INS_CRJNH = 152;;
+let _SYSZ_INS_CGIJLE = 153;;
+let _SYSZ_INS_CGRJLE = 154;;
+let _SYSZ_INS_CIJLE = 155;;
+let _SYSZ_INS_CLGIJLE = 156;;
+let _SYSZ_INS_CLGRJLE = 157;;
+let _SYSZ_INS_CLIJLE = 158;;
+let _SYSZ_INS_CLRJLE = 159;;
+let _SYSZ_INS_CRJLE = 160;;
+let _SYSZ_INS_CGIJNE = 161;;
+let _SYSZ_INS_CGRJNE = 162;;
+let _SYSZ_INS_CIJNE = 163;;
+let _SYSZ_INS_CLGIJNE = 164;;
+let _SYSZ_INS_CLGRJNE = 165;;
+let _SYSZ_INS_CLIJNE = 166;;
+let _SYSZ_INS_CLRJNE = 167;;
+let _SYSZ_INS_CRJNE = 168;;
+let _SYSZ_INS_CGIJLH = 169;;
+let _SYSZ_INS_CGRJLH = 170;;
+let _SYSZ_INS_CIJLH = 171;;
+let _SYSZ_INS_CLGIJLH = 172;;
+let _SYSZ_INS_CLGRJLH = 173;;
+let _SYSZ_INS_CLIJLH = 174;;
+let _SYSZ_INS_CLRJLH = 175;;
+let _SYSZ_INS_CRJLH = 176;;
+let _SYSZ_INS_BLR = 177;;
+let _SYSZ_INS_BLER = 178;;
+let _SYSZ_INS_JLE = 179;;
+let _SYSZ_INS_JGLE = 180;;
+let _SYSZ_INS_LOCLE = 181;;
+let _SYSZ_INS_LOCGLE = 182;;
+let _SYSZ_INS_LOCGRLE = 183;;
+let _SYSZ_INS_LOCRLE = 184;;
+let _SYSZ_INS_STOCLE = 185;;
+let _SYSZ_INS_STOCGLE = 186;;
+let _SYSZ_INS_BLHR = 187;;
+let _SYSZ_INS_JLH = 188;;
+let _SYSZ_INS_JGLH = 189;;
+let _SYSZ_INS_LOCLH = 190;;
+let _SYSZ_INS_LOCGLH = 191;;
+let _SYSZ_INS_LOCGRLH = 192;;
+let _SYSZ_INS_LOCRLH = 193;;
+let _SYSZ_INS_STOCLH = 194;;
+let _SYSZ_INS_STOCGLH = 195;;
+let _SYSZ_INS_JL = 196;;
+let _SYSZ_INS_JGL = 197;;
+let _SYSZ_INS_LOCL = 198;;
+let _SYSZ_INS_LOCGL = 199;;
+let _SYSZ_INS_LOCGRL = 200;;
+let _SYSZ_INS_LOCRL = 201;;
+let _SYSZ_INS_LOC = 202;;
+let _SYSZ_INS_LOCG = 203;;
+let _SYSZ_INS_LOCGR = 204;;
+let _SYSZ_INS_LOCR = 205;;
+let _SYSZ_INS_STOCL = 206;;
+let _SYSZ_INS_STOCGL = 207;;
+let _SYSZ_INS_BNER = 208;;
+let _SYSZ_INS_JNE = 209;;
+let _SYSZ_INS_JGNE = 210;;
+let _SYSZ_INS_LOCNE = 211;;
+let _SYSZ_INS_LOCGNE = 212;;
+let _SYSZ_INS_LOCGRNE = 213;;
+let _SYSZ_INS_LOCRNE = 214;;
+let _SYSZ_INS_STOCNE = 215;;
+let _SYSZ_INS_STOCGNE = 216;;
+let _SYSZ_INS_BNHR = 217;;
+let _SYSZ_INS_BNHER = 218;;
+let _SYSZ_INS_JNHE = 219;;
+let _SYSZ_INS_JGNHE = 220;;
+let _SYSZ_INS_LOCNHE = 221;;
+let _SYSZ_INS_LOCGNHE = 222;;
+let _SYSZ_INS_LOCGRNHE = 223;;
+let _SYSZ_INS_LOCRNHE = 224;;
+let _SYSZ_INS_STOCNHE = 225;;
+let _SYSZ_INS_STOCGNHE = 226;;
+let _SYSZ_INS_JNH = 227;;
+let _SYSZ_INS_JGNH = 228;;
+let _SYSZ_INS_LOCNH = 229;;
+let _SYSZ_INS_LOCGNH = 230;;
+let _SYSZ_INS_LOCGRNH = 231;;
+let _SYSZ_INS_LOCRNH = 232;;
+let _SYSZ_INS_STOCNH = 233;;
+let _SYSZ_INS_STOCGNH = 234;;
+let _SYSZ_INS_BNLR = 235;;
+let _SYSZ_INS_BNLER = 236;;
+let _SYSZ_INS_JNLE = 237;;
+let _SYSZ_INS_JGNLE = 238;;
+let _SYSZ_INS_LOCNLE = 239;;
+let _SYSZ_INS_LOCGNLE = 240;;
+let _SYSZ_INS_LOCGRNLE = 241;;
+let _SYSZ_INS_LOCRNLE = 242;;
+let _SYSZ_INS_STOCNLE = 243;;
+let _SYSZ_INS_STOCGNLE = 244;;
+let _SYSZ_INS_BNLHR = 245;;
+let _SYSZ_INS_JNLH = 246;;
+let _SYSZ_INS_JGNLH = 247;;
+let _SYSZ_INS_LOCNLH = 248;;
+let _SYSZ_INS_LOCGNLH = 249;;
+let _SYSZ_INS_LOCGRNLH = 250;;
+let _SYSZ_INS_LOCRNLH = 251;;
+let _SYSZ_INS_STOCNLH = 252;;
+let _SYSZ_INS_STOCGNLH = 253;;
+let _SYSZ_INS_JNL = 254;;
+let _SYSZ_INS_JGNL = 255;;
+let _SYSZ_INS_LOCNL = 256;;
+let _SYSZ_INS_LOCGNL = 257;;
+let _SYSZ_INS_LOCGRNL = 258;;
+let _SYSZ_INS_LOCRNL = 259;;
+let _SYSZ_INS_STOCNL = 260;;
+let _SYSZ_INS_STOCGNL = 261;;
+let _SYSZ_INS_BNOR = 262;;
+let _SYSZ_INS_JNO = 263;;
+let _SYSZ_INS_JGNO = 264;;
+let _SYSZ_INS_LOCNO = 265;;
+let _SYSZ_INS_LOCGNO = 266;;
+let _SYSZ_INS_LOCGRNO = 267;;
+let _SYSZ_INS_LOCRNO = 268;;
+let _SYSZ_INS_STOCNO = 269;;
+let _SYSZ_INS_STOCGNO = 270;;
+let _SYSZ_INS_BOR = 271;;
+let _SYSZ_INS_JO = 272;;
+let _SYSZ_INS_JGO = 273;;
+let _SYSZ_INS_LOCO = 274;;
+let _SYSZ_INS_LOCGO = 275;;
+let _SYSZ_INS_LOCGRO = 276;;
+let _SYSZ_INS_LOCRO = 277;;
+let _SYSZ_INS_STOCO = 278;;
+let _SYSZ_INS_STOCGO = 279;;
+let _SYSZ_INS_STOC = 280;;
+let _SYSZ_INS_STOCG = 281;;
+let _SYSZ_INS_BASR = 282;;
+let _SYSZ_INS_BR = 283;;
+let _SYSZ_INS_BRAS = 284;;
+let _SYSZ_INS_BRASL = 285;;
+let _SYSZ_INS_J = 286;;
+let _SYSZ_INS_JG = 287;;
+let _SYSZ_INS_BRCT = 288;;
+let _SYSZ_INS_BRCTG = 289;;
+let _SYSZ_INS_C = 290;;
+let _SYSZ_INS_CDB = 291;;
+let _SYSZ_INS_CDBR = 292;;
+let _SYSZ_INS_CDFBR = 293;;
+let _SYSZ_INS_CDGBR = 294;;
+let _SYSZ_INS_CDLFBR = 295;;
+let _SYSZ_INS_CDLGBR = 296;;
+let _SYSZ_INS_CEB = 297;;
+let _SYSZ_INS_CEBR = 298;;
+let _SYSZ_INS_CEFBR = 299;;
+let _SYSZ_INS_CEGBR = 300;;
+let _SYSZ_INS_CELFBR = 301;;
+let _SYSZ_INS_CELGBR = 302;;
+let _SYSZ_INS_CFDBR = 303;;
+let _SYSZ_INS_CFEBR = 304;;
+let _SYSZ_INS_CFI = 305;;
+let _SYSZ_INS_CFXBR = 306;;
+let _SYSZ_INS_CG = 307;;
+let _SYSZ_INS_CGDBR = 308;;
+let _SYSZ_INS_CGEBR = 309;;
+let _SYSZ_INS_CGF = 310;;
+let _SYSZ_INS_CGFI = 311;;
+let _SYSZ_INS_CGFR = 312;;
+let _SYSZ_INS_CGFRL = 313;;
+let _SYSZ_INS_CGH = 314;;
+let _SYSZ_INS_CGHI = 315;;
+let _SYSZ_INS_CGHRL = 316;;
+let _SYSZ_INS_CGHSI = 317;;
+let _SYSZ_INS_CGR = 318;;
+let _SYSZ_INS_CGRL = 319;;
+let _SYSZ_INS_CGXBR = 320;;
+let _SYSZ_INS_CH = 321;;
+let _SYSZ_INS_CHF = 322;;
+let _SYSZ_INS_CHHSI = 323;;
+let _SYSZ_INS_CHI = 324;;
+let _SYSZ_INS_CHRL = 325;;
+let _SYSZ_INS_CHSI = 326;;
+let _SYSZ_INS_CHY = 327;;
+let _SYSZ_INS_CIH = 328;;
+let _SYSZ_INS_CL = 329;;
+let _SYSZ_INS_CLC = 330;;
+let _SYSZ_INS_CLFDBR = 331;;
+let _SYSZ_INS_CLFEBR = 332;;
+let _SYSZ_INS_CLFHSI = 333;;
+let _SYSZ_INS_CLFI = 334;;
+let _SYSZ_INS_CLFXBR = 335;;
+let _SYSZ_INS_CLG = 336;;
+let _SYSZ_INS_CLGDBR = 337;;
+let _SYSZ_INS_CLGEBR = 338;;
+let _SYSZ_INS_CLGF = 339;;
+let _SYSZ_INS_CLGFI = 340;;
+let _SYSZ_INS_CLGFR = 341;;
+let _SYSZ_INS_CLGFRL = 342;;
+let _SYSZ_INS_CLGHRL = 343;;
+let _SYSZ_INS_CLGHSI = 344;;
+let _SYSZ_INS_CLGR = 345;;
+let _SYSZ_INS_CLGRL = 346;;
+let _SYSZ_INS_CLGXBR = 347;;
+let _SYSZ_INS_CLHF = 348;;
+let _SYSZ_INS_CLHHSI = 349;;
+let _SYSZ_INS_CLHRL = 350;;
+let _SYSZ_INS_CLI = 351;;
+let _SYSZ_INS_CLIH = 352;;
+let _SYSZ_INS_CLIY = 353;;
+let _SYSZ_INS_CLR = 354;;
+let _SYSZ_INS_CLRL = 355;;
+let _SYSZ_INS_CLST = 356;;
+let _SYSZ_INS_CLY = 357;;
+let _SYSZ_INS_CPSDR = 358;;
+let _SYSZ_INS_CR = 359;;
+let _SYSZ_INS_CRL = 360;;
+let _SYSZ_INS_CS = 361;;
+let _SYSZ_INS_CSG = 362;;
+let _SYSZ_INS_CSY = 363;;
+let _SYSZ_INS_CXBR = 364;;
+let _SYSZ_INS_CXFBR = 365;;
+let _SYSZ_INS_CXGBR = 366;;
+let _SYSZ_INS_CXLFBR = 367;;
+let _SYSZ_INS_CXLGBR = 368;;
+let _SYSZ_INS_CY = 369;;
+let _SYSZ_INS_DDB = 370;;
+let _SYSZ_INS_DDBR = 371;;
+let _SYSZ_INS_DEB = 372;;
+let _SYSZ_INS_DEBR = 373;;
+let _SYSZ_INS_DL = 374;;
+let _SYSZ_INS_DLG = 375;;
+let _SYSZ_INS_DLGR = 376;;
+let _SYSZ_INS_DLR = 377;;
+let _SYSZ_INS_DSG = 378;;
+let _SYSZ_INS_DSGF = 379;;
+let _SYSZ_INS_DSGFR = 380;;
+let _SYSZ_INS_DSGR = 381;;
+let _SYSZ_INS_DXBR = 382;;
+let _SYSZ_INS_EAR = 383;;
+let _SYSZ_INS_FIDBR = 384;;
+let _SYSZ_INS_FIDBRA = 385;;
+let _SYSZ_INS_FIEBR = 386;;
+let _SYSZ_INS_FIEBRA = 387;;
+let _SYSZ_INS_FIXBR = 388;;
+let _SYSZ_INS_FIXBRA = 389;;
+let _SYSZ_INS_FLOGR = 390;;
+let _SYSZ_INS_IC = 391;;
+let _SYSZ_INS_ICY = 392;;
+let _SYSZ_INS_IIHF = 393;;
+let _SYSZ_INS_IIHH = 394;;
+let _SYSZ_INS_IIHL = 395;;
+let _SYSZ_INS_IILF = 396;;
+let _SYSZ_INS_IILH = 397;;
+let _SYSZ_INS_IILL = 398;;
+let _SYSZ_INS_IPM = 399;;
+let _SYSZ_INS_L = 400;;
+let _SYSZ_INS_LA = 401;;
+let _SYSZ_INS_LAA = 402;;
+let _SYSZ_INS_LAAG = 403;;
+let _SYSZ_INS_LAAL = 404;;
+let _SYSZ_INS_LAALG = 405;;
+let _SYSZ_INS_LAN = 406;;
+let _SYSZ_INS_LANG = 407;;
+let _SYSZ_INS_LAO = 408;;
+let _SYSZ_INS_LAOG = 409;;
+let _SYSZ_INS_LARL = 410;;
+let _SYSZ_INS_LAX = 411;;
+let _SYSZ_INS_LAXG = 412;;
+let _SYSZ_INS_LAY = 413;;
+let _SYSZ_INS_LB = 414;;
+let _SYSZ_INS_LBH = 415;;
+let _SYSZ_INS_LBR = 416;;
+let _SYSZ_INS_LCDBR = 417;;
+let _SYSZ_INS_LCEBR = 418;;
+let _SYSZ_INS_LCGFR = 419;;
+let _SYSZ_INS_LCGR = 420;;
+let _SYSZ_INS_LCR = 421;;
+let _SYSZ_INS_LCXBR = 422;;
+let _SYSZ_INS_LD = 423;;
+let _SYSZ_INS_LDEB = 424;;
+let _SYSZ_INS_LDEBR = 425;;
+let _SYSZ_INS_LDGR = 426;;
+let _SYSZ_INS_LDR = 427;;
+let _SYSZ_INS_LDXBR = 428;;
+let _SYSZ_INS_LDY = 429;;
+let _SYSZ_INS_LE = 430;;
+let _SYSZ_INS_LEDBR = 431;;
+let _SYSZ_INS_LER = 432;;
+let _SYSZ_INS_LEXBR = 433;;
+let _SYSZ_INS_LEY = 434;;
+let _SYSZ_INS_LFH = 435;;
+let _SYSZ_INS_LG = 436;;
+let _SYSZ_INS_LGB = 437;;
+let _SYSZ_INS_LGBR = 438;;
+let _SYSZ_INS_LGDR = 439;;
+let _SYSZ_INS_LGF = 440;;
+let _SYSZ_INS_LGFI = 441;;
+let _SYSZ_INS_LGFR = 442;;
+let _SYSZ_INS_LGFRL = 443;;
+let _SYSZ_INS_LGH = 444;;
+let _SYSZ_INS_LGHI = 445;;
+let _SYSZ_INS_LGHR = 446;;
+let _SYSZ_INS_LGHRL = 447;;
+let _SYSZ_INS_LGR = 448;;
+let _SYSZ_INS_LGRL = 449;;
+let _SYSZ_INS_LH = 450;;
+let _SYSZ_INS_LHH = 451;;
+let _SYSZ_INS_LHI = 452;;
+let _SYSZ_INS_LHR = 453;;
+let _SYSZ_INS_LHRL = 454;;
+let _SYSZ_INS_LHY = 455;;
+let _SYSZ_INS_LLC = 456;;
+let _SYSZ_INS_LLCH = 457;;
+let _SYSZ_INS_LLCR = 458;;
+let _SYSZ_INS_LLGC = 459;;
+let _SYSZ_INS_LLGCR = 460;;
+let _SYSZ_INS_LLGF = 461;;
+let _SYSZ_INS_LLGFR = 462;;
+let _SYSZ_INS_LLGFRL = 463;;
+let _SYSZ_INS_LLGH = 464;;
+let _SYSZ_INS_LLGHR = 465;;
+let _SYSZ_INS_LLGHRL = 466;;
+let _SYSZ_INS_LLH = 467;;
+let _SYSZ_INS_LLHH = 468;;
+let _SYSZ_INS_LLHR = 469;;
+let _SYSZ_INS_LLHRL = 470;;
+let _SYSZ_INS_LLIHF = 471;;
+let _SYSZ_INS_LLIHH = 472;;
+let _SYSZ_INS_LLIHL = 473;;
+let _SYSZ_INS_LLILF = 474;;
+let _SYSZ_INS_LLILH = 475;;
+let _SYSZ_INS_LLILL = 476;;
+let _SYSZ_INS_LMG = 477;;
+let _SYSZ_INS_LNDBR = 478;;
+let _SYSZ_INS_LNEBR = 479;;
+let _SYSZ_INS_LNGFR = 480;;
+let _SYSZ_INS_LNGR = 481;;
+let _SYSZ_INS_LNR = 482;;
+let _SYSZ_INS_LNXBR = 483;;
+let _SYSZ_INS_LPDBR = 484;;
+let _SYSZ_INS_LPEBR = 485;;
+let _SYSZ_INS_LPGFR = 486;;
+let _SYSZ_INS_LPGR = 487;;
+let _SYSZ_INS_LPR = 488;;
+let _SYSZ_INS_LPXBR = 489;;
+let _SYSZ_INS_LR = 490;;
+let _SYSZ_INS_LRL = 491;;
+let _SYSZ_INS_LRV = 492;;
+let _SYSZ_INS_LRVG = 493;;
+let _SYSZ_INS_LRVGR = 494;;
+let _SYSZ_INS_LRVR = 495;;
+let _SYSZ_INS_LT = 496;;
+let _SYSZ_INS_LTDBR = 497;;
+let _SYSZ_INS_LTEBR = 498;;
+let _SYSZ_INS_LTG = 499;;
+let _SYSZ_INS_LTGF = 500;;
+let _SYSZ_INS_LTGFR = 501;;
+let _SYSZ_INS_LTGR = 502;;
+let _SYSZ_INS_LTR = 503;;
+let _SYSZ_INS_LTXBR = 504;;
+let _SYSZ_INS_LXDB = 505;;
+let _SYSZ_INS_LXDBR = 506;;
+let _SYSZ_INS_LXEB = 507;;
+let _SYSZ_INS_LXEBR = 508;;
+let _SYSZ_INS_LXR = 509;;
+let _SYSZ_INS_LY = 510;;
+let _SYSZ_INS_LZDR = 511;;
+let _SYSZ_INS_LZER = 512;;
+let _SYSZ_INS_LZXR = 513;;
+let _SYSZ_INS_MADB = 514;;
+let _SYSZ_INS_MADBR = 515;;
+let _SYSZ_INS_MAEB = 516;;
+let _SYSZ_INS_MAEBR = 517;;
+let _SYSZ_INS_MDB = 518;;
+let _SYSZ_INS_MDBR = 519;;
+let _SYSZ_INS_MDEB = 520;;
+let _SYSZ_INS_MDEBR = 521;;
+let _SYSZ_INS_MEEB = 522;;
+let _SYSZ_INS_MEEBR = 523;;
+let _SYSZ_INS_MGHI = 524;;
+let _SYSZ_INS_MH = 525;;
+let _SYSZ_INS_MHI = 526;;
+let _SYSZ_INS_MHY = 527;;
+let _SYSZ_INS_MLG = 528;;
+let _SYSZ_INS_MLGR = 529;;
+let _SYSZ_INS_MS = 530;;
+let _SYSZ_INS_MSDB = 531;;
+let _SYSZ_INS_MSDBR = 532;;
+let _SYSZ_INS_MSEB = 533;;
+let _SYSZ_INS_MSEBR = 534;;
+let _SYSZ_INS_MSFI = 535;;
+let _SYSZ_INS_MSG = 536;;
+let _SYSZ_INS_MSGF = 537;;
+let _SYSZ_INS_MSGFI = 538;;
+let _SYSZ_INS_MSGFR = 539;;
+let _SYSZ_INS_MSGR = 540;;
+let _SYSZ_INS_MSR = 541;;
+let _SYSZ_INS_MSY = 542;;
+let _SYSZ_INS_MVC = 543;;
+let _SYSZ_INS_MVGHI = 544;;
+let _SYSZ_INS_MVHHI = 545;;
+let _SYSZ_INS_MVHI = 546;;
+let _SYSZ_INS_MVI = 547;;
+let _SYSZ_INS_MVIY = 548;;
+let _SYSZ_INS_MVST = 549;;
+let _SYSZ_INS_MXBR = 550;;
+let _SYSZ_INS_MXDB = 551;;
+let _SYSZ_INS_MXDBR = 552;;
+let _SYSZ_INS_N = 553;;
+let _SYSZ_INS_NC = 554;;
+let _SYSZ_INS_NG = 555;;
+let _SYSZ_INS_NGR = 556;;
+let _SYSZ_INS_NGRK = 557;;
+let _SYSZ_INS_NI = 558;;
+let _SYSZ_INS_NIHF = 559;;
+let _SYSZ_INS_NIHH = 560;;
+let _SYSZ_INS_NIHL = 561;;
+let _SYSZ_INS_NILF = 562;;
+let _SYSZ_INS_NILH = 563;;
+let _SYSZ_INS_NILL = 564;;
+let _SYSZ_INS_NIY = 565;;
+let _SYSZ_INS_NR = 566;;
+let _SYSZ_INS_NRK = 567;;
+let _SYSZ_INS_NY = 568;;
+let _SYSZ_INS_O = 569;;
+let _SYSZ_INS_OC = 570;;
+let _SYSZ_INS_OG = 571;;
+let _SYSZ_INS_OGR = 572;;
+let _SYSZ_INS_OGRK = 573;;
+let _SYSZ_INS_OI = 574;;
+let _SYSZ_INS_OIHF = 575;;
+let _SYSZ_INS_OIHH = 576;;
+let _SYSZ_INS_OIHL = 577;;
+let _SYSZ_INS_OILF = 578;;
+let _SYSZ_INS_OILH = 579;;
+let _SYSZ_INS_OILL = 580;;
+let _SYSZ_INS_OIY = 581;;
+let _SYSZ_INS_OR = 582;;
+let _SYSZ_INS_ORK = 583;;
+let _SYSZ_INS_OY = 584;;
+let _SYSZ_INS_PFD = 585;;
+let _SYSZ_INS_PFDRL = 586;;
+let _SYSZ_INS_RISBG = 587;;
+let _SYSZ_INS_RISBHG = 588;;
+let _SYSZ_INS_RISBLG = 589;;
+let _SYSZ_INS_RLL = 590;;
+let _SYSZ_INS_RLLG = 591;;
+let _SYSZ_INS_RNSBG = 592;;
+let _SYSZ_INS_ROSBG = 593;;
+let _SYSZ_INS_RXSBG = 594;;
+let _SYSZ_INS_S = 595;;
+let _SYSZ_INS_SDB = 596;;
+let _SYSZ_INS_SDBR = 597;;
+let _SYSZ_INS_SEB = 598;;
+let _SYSZ_INS_SEBR = 599;;
+let _SYSZ_INS_SG = 600;;
+let _SYSZ_INS_SGF = 601;;
+let _SYSZ_INS_SGFR = 602;;
+let _SYSZ_INS_SGR = 603;;
+let _SYSZ_INS_SGRK = 604;;
+let _SYSZ_INS_SH = 605;;
+let _SYSZ_INS_SHY = 606;;
+let _SYSZ_INS_SL = 607;;
+let _SYSZ_INS_SLB = 608;;
+let _SYSZ_INS_SLBG = 609;;
+let _SYSZ_INS_SLBR = 610;;
+let _SYSZ_INS_SLFI = 611;;
+let _SYSZ_INS_SLG = 612;;
+let _SYSZ_INS_SLBGR = 613;;
+let _SYSZ_INS_SLGF = 614;;
+let _SYSZ_INS_SLGFI = 615;;
+let _SYSZ_INS_SLGFR = 616;;
+let _SYSZ_INS_SLGR = 617;;
+let _SYSZ_INS_SLGRK = 618;;
+let _SYSZ_INS_SLL = 619;;
+let _SYSZ_INS_SLLG = 620;;
+let _SYSZ_INS_SLLK = 621;;
+let _SYSZ_INS_SLR = 622;;
+let _SYSZ_INS_SLRK = 623;;
+let _SYSZ_INS_SLY = 624;;
+let _SYSZ_INS_SQDB = 625;;
+let _SYSZ_INS_SQDBR = 626;;
+let _SYSZ_INS_SQEB = 627;;
+let _SYSZ_INS_SQEBR = 628;;
+let _SYSZ_INS_SQXBR = 629;;
+let _SYSZ_INS_SR = 630;;
+let _SYSZ_INS_SRA = 631;;
+let _SYSZ_INS_SRAG = 632;;
+let _SYSZ_INS_SRAK = 633;;
+let _SYSZ_INS_SRK = 634;;
+let _SYSZ_INS_SRL = 635;;
+let _SYSZ_INS_SRLG = 636;;
+let _SYSZ_INS_SRLK = 637;;
+let _SYSZ_INS_SRST = 638;;
+let _SYSZ_INS_ST = 639;;
+let _SYSZ_INS_STC = 640;;
+let _SYSZ_INS_STCH = 641;;
+let _SYSZ_INS_STCY = 642;;
+let _SYSZ_INS_STD = 643;;
+let _SYSZ_INS_STDY = 644;;
+let _SYSZ_INS_STE = 645;;
+let _SYSZ_INS_STEY = 646;;
+let _SYSZ_INS_STFH = 647;;
+let _SYSZ_INS_STG = 648;;
+let _SYSZ_INS_STGRL = 649;;
+let _SYSZ_INS_STH = 650;;
+let _SYSZ_INS_STHH = 651;;
+let _SYSZ_INS_STHRL = 652;;
+let _SYSZ_INS_STHY = 653;;
+let _SYSZ_INS_STMG = 654;;
+let _SYSZ_INS_STRL = 655;;
+let _SYSZ_INS_STRV = 656;;
+let _SYSZ_INS_STRVG = 657;;
+let _SYSZ_INS_STY = 658;;
+let _SYSZ_INS_SXBR = 659;;
+let _SYSZ_INS_SY = 660;;
+let _SYSZ_INS_TM = 661;;
+let _SYSZ_INS_TMHH = 662;;
+let _SYSZ_INS_TMHL = 663;;
+let _SYSZ_INS_TMLH = 664;;
+let _SYSZ_INS_TMLL = 665;;
+let _SYSZ_INS_TMY = 666;;
+let _SYSZ_INS_X = 667;;
+let _SYSZ_INS_XC = 668;;
+let _SYSZ_INS_XG = 669;;
+let _SYSZ_INS_XGR = 670;;
+let _SYSZ_INS_XGRK = 671;;
+let _SYSZ_INS_XI = 672;;
+let _SYSZ_INS_XIHF = 673;;
+let _SYSZ_INS_XILF = 674;;
+let _SYSZ_INS_XIY = 675;;
+let _SYSZ_INS_XR = 676;;
+let _SYSZ_INS_XRK = 677;;
+let _SYSZ_INS_XY = 678;;
+let _SYSZ_INS_MAX = 679;;
+
+(* Group of SystemZ instructions *)
+
+let _SYSZ_GRP_INVALID = 0;;
+let _SYSZ_GRP_FEATUREDISTINCTOPS = 1;;
+let _SYSZ_GRP_FEATUREFPEXTENSION = 2;;
+let _SYSZ_GRP_FEATUREHIGHWORD = 3;;
+let _SYSZ_GRP_FEATUREINTERLOCKEDACCESS1 = 4;;
+let _SYSZ_GRP_FEATURELOADSTOREONCOND = 5;;
+let _SYSZ_GRP_JUMP = 6;;
+let _SYSZ_GRP_MAX = 7;;
diff --git a/bindings/ocaml/test.ml b/bindings/ocaml/test.ml
index 16975c7..e1948b5 100644
--- a/bindings/ocaml/test.ml
+++ b/bindings/ocaml/test.ml
@@ -15,19 +15,30 @@
let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";;
let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";;
let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";;
+let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";;
+let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";;
+let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";;
+let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";;
+let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";;
let all_tests = [
- (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_32; CS_MODE_SYNTAX_ATT], _X86_CODE32, "X86 32bit (ATT syntax)");
- (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)");
- (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM");
- (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON");
- (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB");
- (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2");
- (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64");
- (CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)");
- (CS_ARCH_MIPS, [CS_MODE_64;CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)");
+ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0);
+ (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0);
+ (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0);
+ (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0);
+ (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0);
+ (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0);
+ (CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0);
+ (CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0);
+ (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0);
+ (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64, print register with number only", 0);
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0);
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0);
+ (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0);
+ (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0);
];;
@@ -35,7 +46,7 @@
printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;;
let print_arch x =
- let (arch, mode, code, comment) = x in
+ let (arch, mode, code, comment, syntax) = x in
let insns = cs_disasm_quick arch mode code 0x1000L 0L in
printf "*************\n";
printf "Platform: %s\n" comment;
@@ -49,7 +60,7 @@
printf "0x%x\t%s\t%s\n" insn#address insn#mnemonic insn#op_str;;
let print_arch_cls x =
- let (arch, mode, code, comment) = x in (
+ let (arch, mode, code, comment, syntax) = x in (
let d = new cs arch mode in
let insns = d#disasm code 0x1000L 0L in
printf "*************\n";
diff --git a/bindings/ocaml/test_arm.ml b/bindings/ocaml/test_arm.ml
index 22254a5..7867022 100644
--- a/bindings/ocaml/test_arm.ml
+++ b/bindings/ocaml/test_arm.ml
@@ -60,6 +60,9 @@
| CS_INFO_X86 _ -> ();
| CS_INFO_MIPS _ -> ();
| CS_INFO_PPC _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
| CS_INFO_ARM arm ->
if arm.cc != _ARM_CC_AL && arm.cc != _ARM_CC_INVALID then
printf "\tCode condition: %u\n" arm.cc;
diff --git a/bindings/ocaml/test_arm64.ml b/bindings/ocaml/test_arm64.ml
index d699aaf..4836f05 100644
--- a/bindings/ocaml/test_arm64.ml
+++ b/bindings/ocaml/test_arm64.ml
@@ -52,6 +52,9 @@
| CS_INFO_MIPS _ -> ();
| CS_INFO_PPC _ -> ();
| CS_INFO_X86 _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
| CS_INFO_ARM64 arm64 ->
if arm64.cc != _ARM64_CC_AL && arm64.cc != _ARM64_CC_INVALID then
printf "\tCode condition: %u\n" arm64.cc;
diff --git a/bindings/ocaml/test_detail.ml b/bindings/ocaml/test_detail.ml
index 313dfa3..67d8d93 100644
--- a/bindings/ocaml/test_detail.ml
+++ b/bindings/ocaml/test_detail.ml
@@ -16,21 +16,28 @@
let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";;
let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";;
let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";;
+let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";;
+let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";;
+let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";;
+let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";;
let all_tests = [
- (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_32; CS_MODE_SYNTAX_ATT], _X86_CODE32, "X86 32bit (ATT syntax)");
- (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)");
- (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM");
- (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON");
- (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB");
- (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2");
- (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64");
- (CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)");
- (CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)");
- (CS_ARCH_PPC, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64");
-
+ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0);
+ (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0);
+ (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0);
+ (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0);
+ (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0);
+ (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0);
+ (CS_ARCH_MIPS, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0);
+ (CS_ARCH_MIPS, [CS_MODE_64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0);
+ (CS_ARCH_PPC, [CS_MODE_32; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0);
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0);
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0);
+ (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0);
+ (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0);
];;
@@ -65,7 +72,7 @@
let print_arch x =
- let (arch, mode, code, comment) = x in
+ let (arch, mode, code, comment, syntax) = x in
let insns = cs_disasm_quick arch mode code 0x1000L 0L in
printf "*************\n";
printf "Platform: %s\n" comment;
@@ -104,7 +111,7 @@
let print_arch_cls x =
- let (arch, mode, code, comment) = x in
+ let (arch, mode, code, comment, syntax) = x in
let d = new cs arch mode in
let insns = d#disasm code 0x1000L 0L in
printf "*************\n";
diff --git a/bindings/ocaml/test_mips.ml b/bindings/ocaml/test_mips.ml
index b0f5a82..94e4cab 100644
--- a/bindings/ocaml/test_mips.ml
+++ b/bindings/ocaml/test_mips.ml
@@ -44,6 +44,9 @@
| CS_INFO_ARM64 _ -> ();
| CS_INFO_PPC _ -> ();
| CS_INFO_X86 _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
| CS_INFO_MIPS mips ->
(* print all operands info (type & value) *)
diff --git a/bindings/ocaml/test_ppc.ml b/bindings/ocaml/test_ppc.ml
index 62c1ca3..7c0dbee 100644
--- a/bindings/ocaml/test_ppc.ml
+++ b/bindings/ocaml/test_ppc.ml
@@ -32,7 +32,6 @@
printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.displ;
);
);
-
();;
@@ -42,6 +41,9 @@
| CS_INFO_ARM64 _ -> ();
| CS_INFO_MIPS _ -> ();
| CS_INFO_X86 _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
| CS_INFO_PPC ppc ->
(* print all operands info (type & value) *)
@@ -54,7 +56,7 @@
let print_insn mode insn =
printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;
- let csh = cs_open CS_ARCH_MIPS mode in
+ let csh = cs_open CS_ARCH_PPC mode in
match csh with
| None -> ()
| Some v -> print_detail v insn.arch
diff --git a/bindings/ocaml/test_sparc.ml b/bindings/ocaml/test_sparc.ml
new file mode 100644
index 0000000..49ac30d
--- /dev/null
+++ b/bindings/ocaml/test_sparc.ml
@@ -0,0 +1,99 @@
+(* Capstone Disassembler Engine
+* By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+open Printf
+open Capstone
+open Sparc
+
+
+let print_string_hex comment str =
+ printf "%s" comment;
+ for i = 0 to (Array.length str - 1) do
+ printf "0x%02x " str.(i)
+ done;
+ printf "\n"
+
+
+let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";;
+let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";;
+
+
+let all_tests = [
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc");
+ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9");
+];;
+
+let print_op csh i op =
+ ( match op with
+ | SPARC_OP_INVALID _ -> (); (* this would never happens *)
+ | SPARC_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name csh reg);
+ | SPARC_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm;
+ | SPARC_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i;
+ if mem.base != 0 then
+ printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name csh mem.base);
+ if mem.index != 0 then
+ printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index;
+ if mem.displ != 0 then
+ printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.displ;
+ );
+ );
+
+ ();;
+
+
+let print_detail csh arch =
+ match arch with
+ | CS_INFO_ARM _ -> ();
+ | CS_INFO_ARM64 _ -> ();
+ | CS_INFO_MIPS _ -> ();
+ | CS_INFO_X86 _ -> ();
+ | CS_INFO_PPC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
+ | CS_INFO_SPARC sparc ->
+
+ (* print all operands info (type & value) *)
+ if (Array.length sparc.operands) > 0 then (
+ printf "\top_count: %d\n" (Array.length sparc.operands);
+ Array.iteri (print_op csh) sparc.operands;
+ );
+ printf "\n";;
+
+
+let print_insn mode insn =
+ printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;
+ let csh = cs_open CS_ARCH_SPARC mode in
+ match csh with
+ | None -> ()
+ | Some v -> print_detail v insn.arch
+
+
+let print_arch x =
+ let (arch, mode, code, comment) = x in
+ let insns = cs_disasm_quick arch mode code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn mode) insns;;
+
+
+
+List.iter print_arch all_tests;;
+
+
+
+(* all below code use OO class of Capstone *)
+let print_insn_cls csh insn =
+ printf "0x%x\t%s\t%s\n" insn#address insn#mnemonic insn#op_str;
+ print_detail csh insn#arch;;
+
+
+let print_arch_cls x =
+ let (arch, mode, code, comment) = x in (
+ let d = new cs arch mode in
+ let insns = d#disasm code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn_cls d#get_csh) insns;
+ );;
+
+List.iter print_arch_cls all_tests;;
diff --git a/bindings/ocaml/test_systemz.ml b/bindings/ocaml/test_systemz.ml
new file mode 100644
index 0000000..4734782
--- /dev/null
+++ b/bindings/ocaml/test_systemz.ml
@@ -0,0 +1,101 @@
+(* Capstone Disassembler Engine
+* By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+open Printf
+open Capstone
+open Systemz
+
+
+let print_string_hex comment str =
+ printf "%s" comment;
+ for i = 0 to (Array.length str - 1) do
+ printf "0x%02x " str.(i)
+ done;
+ printf "\n"
+
+
+let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";;
+
+
+
+let all_tests = [
+ (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ");
+];;
+
+let print_op csh i op =
+ ( match op with
+ | SYSZ_OP_INVALID _ -> (); (* this would never happens *)
+ | SYSZ_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name csh reg);
+ | SYSZ_OP_ACREG reg -> (); (* XXX *)
+ | SYSZ_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm;
+ | SYSZ_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i;
+ if mem.base != 0 then
+ printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name csh mem.base);
+ if mem.index != 0 then
+ printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index;
+ if mem.length != 0L then
+ printf "\t\t\toperands[%u].mem.length: 0x%Lx\n" i mem.length;
+ if mem.displ != 0L then
+ printf "\t\t\toperands[%u].mem.disp: 0x%Lx\n" i mem.displ;
+ );
+ );
+
+ ();;
+
+
+let print_detail csh arch =
+ match arch with
+ | CS_INFO_ARM _ -> ();
+ | CS_INFO_ARM64 _ -> ();
+ | CS_INFO_MIPS _ -> ();
+ | CS_INFO_X86 _ -> ();
+ | CS_INFO_PPC _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_XCORE _ -> ();
+ | CS_INFO_SYSZ sysz ->
+
+ (* print all operands info (type & value) *)
+ if (Array.length sysz.operands) > 0 then (
+ printf "\top_count: %d\n" (Array.length sysz.operands);
+ Array.iteri (print_op csh) sysz.operands;
+ );
+ printf "\n";;
+
+
+let print_insn mode insn =
+ printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;
+ let csh = cs_open CS_ARCH_SYSZ mode in
+ match csh with
+ | None -> ()
+ | Some v -> print_detail v insn.arch
+
+
+let print_arch x =
+ let (arch, mode, code, comment) = x in
+ let insns = cs_disasm_quick arch mode code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn mode) insns;;
+
+
+
+List.iter print_arch all_tests;;
+
+
+
+(* all below code use OO class of Capstone *)
+let print_insn_cls csh insn =
+ printf "0x%x\t%s\t%s\n" insn#address insn#mnemonic insn#op_str;
+ print_detail csh insn#arch;;
+
+
+let print_arch_cls x =
+ let (arch, mode, code, comment) = x in (
+ let d = new cs arch mode in
+ let insns = d#disasm code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn_cls d#get_csh) insns;
+ );;
+
+List.iter print_arch_cls all_tests;;
diff --git a/bindings/ocaml/test_x86.ml b/bindings/ocaml/test_x86.ml
index 3536ab3..469c7ce 100644
--- a/bindings/ocaml/test_x86.ml
+++ b/bindings/ocaml/test_x86.ml
@@ -20,10 +20,10 @@
let all_tests = [
- (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_32; CS_MODE_SYNTAX_ATT], _X86_CODE32, "X86 32bit (ATT syntax)");
- (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)");
- (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)");
+ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0);
+ (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0);
];;
let print_op csh i op =
@@ -52,6 +52,9 @@
| CS_INFO_ARM _ -> ();
| CS_INFO_MIPS _ -> ();
| CS_INFO_PPC _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE _ -> ();
| CS_INFO_X86 x86 ->
print_string_hex "\tPrefix: " x86.prefix;
@@ -105,7 +108,7 @@
let print_arch x =
- let (arch, mode, code, comment) = x in
+ let (arch, mode, code, comment, syntax) = x in
let insns = cs_disasm_quick arch mode code 0x1000L 0L in
printf "*************\n";
printf "Platform: %s\n" comment;
@@ -124,7 +127,7 @@
let print_arch_cls x =
- let (arch, mode, code, comment) = x in (
+ let (arch, mode, code, comment, syntax) = x in (
let d = new cs arch mode in
let insns = d#disasm code 0x1000L 0L in
printf "*************\n";
diff --git a/bindings/ocaml/test_xcore.ml b/bindings/ocaml/test_xcore.ml
new file mode 100644
index 0000000..c27eea0
--- /dev/null
+++ b/bindings/ocaml/test_xcore.ml
@@ -0,0 +1,98 @@
+(* Capstone Disassembler Engine
+* By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+open Printf
+open Capstone
+open Xcore
+
+
+let print_string_hex comment str =
+ printf "%s" comment;
+ for i = 0 to (Array.length str - 1) do
+ printf "0x%02x " str.(i)
+ done;
+ printf "\n"
+
+
+let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";;
+
+let all_tests = [
+ (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore");
+];;
+
+let print_op csh i op =
+ ( match op with
+ | XCORE_OP_INVALID _ -> (); (* this would never happens *)
+ | XCORE_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name csh reg);
+ | XCORE_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm;
+ | XCORE_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i;
+ if mem.base != 0 then
+ printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name csh mem.base);
+ if mem.index != 0 then
+ printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index;
+ if mem.displ != 0 then
+ printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.displ;
+ if mem.direct != 0 then
+ printf "\t\t\toperands[%u].mem.direct: 0x%x\n" i mem.direct;
+ );
+ );
+
+ ();;
+
+
+let print_detail csh arch =
+ match arch with
+ | CS_INFO_ARM _ -> ();
+ | CS_INFO_ARM64 _ -> ();
+ | CS_INFO_MIPS _ -> ();
+ | CS_INFO_X86 _ -> ();
+ | CS_INFO_PPC _ -> ();
+ | CS_INFO_SPARC _ -> ();
+ | CS_INFO_SYSZ _ -> ();
+ | CS_INFO_XCORE xcore ->
+
+ (* print all operands info (type & value) *)
+ if (Array.length xcore.operands) > 0 then (
+ printf "\top_count: %d\n" (Array.length xcore.operands);
+ Array.iteri (print_op csh) xcore.operands;
+ );
+ printf "\n";;
+
+
+let print_insn mode insn =
+ printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;
+ let csh = cs_open CS_ARCH_XCORE mode in
+ match csh with
+ | None -> ()
+ | Some v -> print_detail v insn.arch
+
+
+let print_arch x =
+ let (arch, mode, code, comment) = x in
+ let insns = cs_disasm_quick arch mode code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn mode) insns;;
+
+
+
+List.iter print_arch all_tests;;
+
+
+
+(* all below code use OO class of Capstone *)
+let print_insn_cls csh insn =
+ printf "0x%x\t%s\t%s\n" insn#address insn#mnemonic insn#op_str;
+ print_detail csh insn#arch;;
+
+
+let print_arch_cls x =
+ let (arch, mode, code, comment) = x in (
+ let d = new cs arch mode in
+ let insns = d#disasm code 0x1000L 0L in
+ printf "*************\n";
+ printf "Platform: %s\n" comment;
+ List.iter (print_insn_cls d#get_csh) insns;
+ );;
+
+List.iter print_arch_cls all_tests;;
diff --git a/bindings/ocaml/xcore.ml b/bindings/ocaml/xcore.ml
new file mode 100644
index 0000000..9b39cdc
--- /dev/null
+++ b/bindings/ocaml/xcore.ml
@@ -0,0 +1,190 @@
+(* Capstone Disassembler Engine
+ * By Guillaume Jeanne <guillaume.jeanne@ensimag.fr>, 2014> *)
+
+type xcore_op_mem = {
+ base: int;
+ index: int;
+ displ: int;
+ direct: int;
+}
+
+type xcore_op =
+ | XCORE_OP_INVALID of int
+ | XCORE_OP_REG of int
+ | XCORE_OP_IMM of int
+ | XCORE_OP_MEM of xcore_op_mem
+
+type cs_xcore = {
+ op_count: int;
+ operands: xcore_op array;
+}
+
+(* Operand type for instruction's operands *)
+
+let _XCORE_OP_INVALID = 0;;
+let _XCORE_OP_REG = 1;;
+let _XCORE_OP_IMM = 2;;
+let _XCORE_OP_MEM = 3;;
+
+(* XCore registers *)
+
+let _XCORE_REG_INVALID = 0;;
+let _XCORE_REG_CP = 1;;
+let _XCORE_REG_DP = 2;;
+let _XCORE_REG_LR = 3;;
+let _XCORE_REG_SP = 4;;
+let _XCORE_REG_R0 = 5;;
+let _XCORE_REG_R1 = 6;;
+let _XCORE_REG_R2 = 7;;
+let _XCORE_REG_R3 = 8;;
+let _XCORE_REG_R4 = 9;;
+let _XCORE_REG_R5 = 10;;
+let _XCORE_REG_R6 = 11;;
+let _XCORE_REG_R7 = 12;;
+let _XCORE_REG_R8 = 13;;
+let _XCORE_REG_R9 = 14;;
+let _XCORE_REG_R10 = 15;;
+let _XCORE_REG_R11 = 16;;
+
+(* pseudo registers *)
+let _XCORE_REG_PC = 17;;
+let _XCORE_REG_SCP = 18;;
+let _XCORE_REG_SSR = 19;;
+let _XCORE_REG_ET = 20;;
+let _XCORE_REG_ED = 21;;
+let _XCORE_REG_SED = 22;;
+let _XCORE_REG_KEP = 23;;
+let _XCORE_REG_KSP = 24;;
+let _XCORE_REG_ID = 25;;
+let _XCORE_REG_MAX = 26;;
+
+(* XCore instruction *)
+
+let _XCORE_INS_INVALID = 0;;
+let _XCORE_INS_ADD = 1;;
+let _XCORE_INS_ANDNOT = 2;;
+let _XCORE_INS_AND = 3;;
+let _XCORE_INS_ASHR = 4;;
+let _XCORE_INS_BAU = 5;;
+let _XCORE_INS_BITREV = 6;;
+let _XCORE_INS_BLA = 7;;
+let _XCORE_INS_BLAT = 8;;
+let _XCORE_INS_BL = 9;;
+let _XCORE_INS_BF = 10;;
+let _XCORE_INS_BT = 11;;
+let _XCORE_INS_BU = 12;;
+let _XCORE_INS_BRU = 13;;
+let _XCORE_INS_BYTEREV = 14;;
+let _XCORE_INS_CHKCT = 15;;
+let _XCORE_INS_CLRE = 16;;
+let _XCORE_INS_CLRPT = 17;;
+let _XCORE_INS_CLRSR = 18;;
+let _XCORE_INS_CLZ = 19;;
+let _XCORE_INS_CRC8 = 20;;
+let _XCORE_INS_CRC32 = 21;;
+let _XCORE_INS_DCALL = 22;;
+let _XCORE_INS_DENTSP = 23;;
+let _XCORE_INS_DGETREG = 24;;
+let _XCORE_INS_DIVS = 25;;
+let _XCORE_INS_DIVU = 26;;
+let _XCORE_INS_DRESTSP = 27;;
+let _XCORE_INS_DRET = 28;;
+let _XCORE_INS_ECALLF = 29;;
+let _XCORE_INS_ECALLT = 30;;
+let _XCORE_INS_EDU = 31;;
+let _XCORE_INS_EEF = 32;;
+let _XCORE_INS_EET = 33;;
+let _XCORE_INS_EEU = 34;;
+let _XCORE_INS_ENDIN = 35;;
+let _XCORE_INS_ENTSP = 36;;
+let _XCORE_INS_EQ = 37;;
+let _XCORE_INS_EXTDP = 38;;
+let _XCORE_INS_EXTSP = 39;;
+let _XCORE_INS_FREER = 40;;
+let _XCORE_INS_FREET = 41;;
+let _XCORE_INS_GETD = 42;;
+let _XCORE_INS_GET = 43;;
+let _XCORE_INS_GETN = 44;;
+let _XCORE_INS_GETR = 45;;
+let _XCORE_INS_GETSR = 46;;
+let _XCORE_INS_GETST = 47;;
+let _XCORE_INS_GETTS = 48;;
+let _XCORE_INS_INCT = 49;;
+let _XCORE_INS_INIT = 50;;
+let _XCORE_INS_INPW = 51;;
+let _XCORE_INS_INSHR = 52;;
+let _XCORE_INS_INT = 53;;
+let _XCORE_INS_IN = 54;;
+let _XCORE_INS_KCALL = 55;;
+let _XCORE_INS_KENTSP = 56;;
+let _XCORE_INS_KRESTSP = 57;;
+let _XCORE_INS_KRET = 58;;
+let _XCORE_INS_LADD = 59;;
+let _XCORE_INS_LD16S = 60;;
+let _XCORE_INS_LD8U = 61;;
+let _XCORE_INS_LDA16 = 62;;
+let _XCORE_INS_LDAP = 63;;
+let _XCORE_INS_LDAW = 64;;
+let _XCORE_INS_LDC = 65;;
+let _XCORE_INS_LDW = 66;;
+let _XCORE_INS_LDIVU = 67;;
+let _XCORE_INS_LMUL = 68;;
+let _XCORE_INS_LSS = 69;;
+let _XCORE_INS_LSUB = 70;;
+let _XCORE_INS_LSU = 71;;
+let _XCORE_INS_MACCS = 72;;
+let _XCORE_INS_MACCU = 73;;
+let _XCORE_INS_MJOIN = 74;;
+let _XCORE_INS_MKMSK = 75;;
+let _XCORE_INS_MSYNC = 76;;
+let _XCORE_INS_MUL = 77;;
+let _XCORE_INS_NEG = 78;;
+let _XCORE_INS_NOT = 79;;
+let _XCORE_INS_OR = 80;;
+let _XCORE_INS_OUTCT = 81;;
+let _XCORE_INS_OUTPW = 82;;
+let _XCORE_INS_OUTSHR = 83;;
+let _XCORE_INS_OUTT = 84;;
+let _XCORE_INS_OUT = 85;;
+let _XCORE_INS_PEEK = 86;;
+let _XCORE_INS_REMS = 87;;
+let _XCORE_INS_REMU = 88;;
+let _XCORE_INS_RETSP = 89;;
+let _XCORE_INS_SETCLK = 90;;
+let _XCORE_INS_SET = 91;;
+let _XCORE_INS_SETC = 92;;
+let _XCORE_INS_SETD = 93;;
+let _XCORE_INS_SETEV = 94;;
+let _XCORE_INS_SETN = 95;;
+let _XCORE_INS_SETPSC = 96;;
+let _XCORE_INS_SETPT = 97;;
+let _XCORE_INS_SETRDY = 98;;
+let _XCORE_INS_SETSR = 99;;
+let _XCORE_INS_SETTW = 100;;
+let _XCORE_INS_SETV = 101;;
+let _XCORE_INS_SEXT = 102;;
+let _XCORE_INS_SHL = 103;;
+let _XCORE_INS_SHR = 104;;
+let _XCORE_INS_SSYNC = 105;;
+let _XCORE_INS_ST16 = 106;;
+let _XCORE_INS_ST8 = 107;;
+let _XCORE_INS_STW = 108;;
+let _XCORE_INS_SUB = 109;;
+let _XCORE_INS_SYNCR = 110;;
+let _XCORE_INS_TESTCT = 111;;
+let _XCORE_INS_TESTLCL = 112;;
+let _XCORE_INS_TESTWCT = 113;;
+let _XCORE_INS_TSETMR = 114;;
+let _XCORE_INS_START = 115;;
+let _XCORE_INS_WAITEF = 116;;
+let _XCORE_INS_WAITET = 117;;
+let _XCORE_INS_WAITEU = 118;;
+let _XCORE_INS_XOR = 119;;
+let _XCORE_INS_ZEXT = 120;;
+let _XCORE_INS_MAX = 121;;
+
+(* Group of XCore instructions *)
+
+let _XCORE_GRP_INVALID = 0;;
+let _XCORE_GRP_JUMP = 1;;
+let _XCORE_GRP_MAX = 2;;
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 7988cf7..169f9ca 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -63,6 +63,8 @@
'CS_ERR_MEMSETUP',
'CS_ERR_DIET',
'CS_ERR_SKIPDATA',
+ 'CS_ERR_X86_ATT',
+ 'CS_ERR_X86_INTEL',
'CS_SUPPORT_DIET',
'CS_SUPPORT_X86_REDUCE',
@@ -132,6 +134,8 @@
CS_ERR_VERSION = 9 # Unsupported version (bindings)
CS_ERR_DIET = 10 # Information irrelevant in diet engine
CS_ERR_SKIPDATA = 11 # Access irrelevant data for "data" instruction in SKIPDATA mode
+CS_ERR_X86_ATT = 12 # X86 AT&T syntax is unsupported (opt-out at compile time)
+CS_ERR_X86_INTEL = 13 # X86 Intel syntax is unsupported (opt-out at compile time)
# query id for cs_support()
CS_SUPPORT_DIET = CS_ARCH_ALL + 1
diff --git a/config.mk b/config.mk
index 8b66b5a..2504f7f 100644
--- a/config.mk
+++ b/config.mk
@@ -55,6 +55,11 @@
CAPSTONE_X86_REDUCE ?= no
+################################################################################
+# Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to
+# disable AT&T syntax on x86 to reduce library size.
+
+CAPSTONE_X86_ATT_DISABLE ?= no
################################################################################
# Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building
diff --git a/include/capstone.h b/include/capstone.h
index 134d824..8abb882 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -243,6 +243,8 @@
CS_ERR_VERSION, // Unsupported version (bindings)
CS_ERR_DIET, // Access irrelevant data in "diet" engine
CS_ERR_SKIPDATA, // Access irrelevant data for "data" instruction in SKIPDATA mode
+ CS_ERR_X86_ATT, // X86 AT&T syntax is unsupported (opt-out at compile time)
+ CS_ERR_X86_INTEL, // X86 Intel syntax is unsupported (opt-out at compile time)
} cs_err;
/*
diff --git a/msvc/capstone_dll/capstone_dll.vcxproj b/msvc/capstone_dll/capstone_dll.vcxproj
index 8b5f9bc..d5ddcfc 100644
--- a/msvc/capstone_dll/capstone_dll.vcxproj
+++ b/msvc/capstone_dll/capstone_dll.vcxproj
@@ -84,7 +84,7 @@
</PrecompiledHeader>
<WarningLevel>Level3</WarningLevel>
<Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -100,7 +100,7 @@
</PrecompiledHeader>
<WarningLevel>Level3</WarningLevel>
<Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -118,7 +118,7 @@
<Optimization>MaxSpeed</Optimization>
<FunctionLevelLinking>true</FunctionLevelLinking>
<IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -138,7 +138,7 @@
<Optimization>MaxSpeed</Optimization>
<FunctionLevelLinking>true</FunctionLevelLinking>
<IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_WINDOWS;_USRDLL;CAPSTONE_SHARED;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
diff --git a/msvc/capstone_static/capstone_static.vcxproj b/msvc/capstone_static/capstone_static.vcxproj
index b280902..6d8215f 100644
--- a/msvc/capstone_static/capstone_static.vcxproj
+++ b/msvc/capstone_static/capstone_static.vcxproj
@@ -125,7 +125,7 @@
</PrecompiledHeader>
<WarningLevel>Level3</WarningLevel>
<Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -140,7 +140,7 @@
</PrecompiledHeader>
<WarningLevel>Level3</WarningLevel>
<Optimization>Disabled</Optimization>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -157,7 +157,7 @@
<Optimization>MaxSpeed</Optimization>
<FunctionLevelLinking>true</FunctionLevelLinking>
<IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>
@@ -176,7 +176,7 @@
<Optimization>MaxSpeed</Optimization>
<FunctionLevelLinking>true</FunctionLevelLinking>
<IntrinsicFunctions>true</IntrinsicFunctions>
- <PreprocessorDefinitions>CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <PreprocessorDefinitions>CAPSTONE_X86_ATT_DISABLE_NO;CAPSTONE_DIET_NO;CAPSTONE_X86_REDUCE_NO;CAPSTONE_HAS_ARM;CAPSTONE_HAS_ARM64;CAPSTONE_HAS_MIPS;CAPSTONE_HAS_POWERPC;CAPSTONE_HAS_SPARC;CAPSTONE_HAS_SYSZ;CAPSTONE_HAS_X86;CAPSTONE_HAS_XCORE;CAPSTONE_USE_SYS_DYN_MEM;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<SDLCheck>true</SDLCheck>
<AdditionalIncludeDirectories>..\..\include;..\headers;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
</ClCompile>