Merge branch 'next' into xcore
diff --git a/.gitignore b/.gitignore
index 4801c25..1e4e2bc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,6 +38,7 @@
tests/test_skipdata
tests/test_sparc
tests/test_systemz
+tests/test_xcore
tests/*.static
# vim tmp file
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
index 4878c50..71d7f86 100644
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@@ -12,10 +12,10 @@
(0) Tailor Capstone to your need.
- Out of 7 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
- SystemZ & X86), if you just need several selected archs, choose the ones you
- want to compile in by opening Visual Studio solution "msvc\capstone.sln", then
- directly editing the projects "capstone_static" & "capstone_dll" for static
+ Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
+ SystemZ, X86 & XCore), if you just need several selected archs, choose the ones
+ you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
+ then directly editing the projects "capstone_static" & "capstone_dll" for static
and dynamic libraries, respectively. This must be done before going to the
next steps.
@@ -30,8 +30,9 @@
- CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
- CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
- CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
+ - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
- By default, all 7 architectures are compiled in.
+ By default, all 8 architectures are compiled in.
Besides, Capstone also allows some more customization via following macros.
diff --git a/HACK.TXT b/HACK.TXT
index 8516cb3..18dba98 100644
--- a/HACK.TXT
+++ b/HACK.TXT
@@ -9,7 +9,8 @@
│ ├── PowerPC <- PowerPC engine
│ ├── Sparc <- Sparc engine
│ ├── SystemZ <- SystemZ engine
-│ └── X86 <- X86 engine
+│ ├── X86 <- X86 engine
+│ └── XCore <- XCore engine
├── bindings <- all bindings are under this dir
│ ├── java <- Java bindings + test code
│ ├── ocaml <- Ocaml bindings + test code
diff --git a/MCInst.h b/MCInst.h
index ff34b19..b24d238 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -129,6 +129,7 @@
cs_ppc ppc; // PowerPC architecture
cs_sparc sparc; // Sparc architecture
cs_sysz sysz; // SystemZ architecture
+ cs_xcore xcore; // XCore architecture
};
} cs_insn_flat;
diff --git a/Makefile b/Makefile
index bda36b3..628f37b 100644
--- a/Makefile
+++ b/Makefile
@@ -204,9 +204,26 @@
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
endif
+
+DEP_XCORE =
+DEP_XCORE += arch/XCore/XCoreGenAsmWriter.inc
+DEP_XCORE += arch/XCore/XCoreGenInstrInfo.inc
+DEP_XCORE += arch/XCore/XCoreGenDisassemblerTables.inc
+DEP_XCORE += arch/XCore/XCoreGenRegisterInfo.inc
+
+LIBOBJ_XCORE =
+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
+ CFLAGS += -DCAPSTONE_HAS_XCORE
+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreDisassembler.o
+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreInstPrinter.o
+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreMapping.o
+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreModule.o
+endif
+
+
LIBOBJ =
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
-LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86)
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE)
LIBOBJ += $(OBJDIR)/MCInst.o
@@ -296,6 +313,7 @@
$(LIBOBJ_SPARC): $(DEP_SPARC)
$(LIBOBJ_SYSZ): $(DEP_SYSZ)
$(LIBOBJ_X86): $(DEP_X86)
+$(LIBOBJ_XCORE): $(DEP_XCORE)
ifeq ($(CAPSTONE_STATIC),yes)
$(ARCHIVE): $(LIBOBJ)
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index 8fcec80..411f775 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/arm64.h"
#include "../../utils.h"
#include "AArch64Mapping.h"
diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h
index 45fdb70..950cdf3 100644
--- a/arch/AArch64/AArch64Mapping.h
+++ b/arch/AArch64/AArch64Mapping.h
@@ -5,7 +5,6 @@
#define CS_ARM64_MAP_H
#include "../../include/capstone.h"
-#include "../../include/arm64.h"
// return name of regiser in friendly string
const char *AArch64_reg_name(csh handle, unsigned int reg);
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index d56bd8a..436de51 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/arm.h"
#include "../../cs_priv.h"
#include "ARMMapping.h"
diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h
index f3b99e2..6445b19 100644
--- a/arch/ARM/ARMMapping.h
+++ b/arch/ARM/ARMMapping.h
@@ -5,7 +5,6 @@
#define CS_ARM_MAP_H
#include "../../include/capstone.h"
-#include "../../include/arm.h"
#include "../../utils.h"
// return name of regiser in friendly string
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index 74b39ef..347ed9b 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/mips.h"
#include "../../utils.h"
#include "MipsMapping.h"
diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h
index 28fa0d9..b5221da 100644
--- a/arch/Mips/MipsMapping.h
+++ b/arch/Mips/MipsMapping.h
@@ -5,7 +5,6 @@
#define CS_MIPS_MAP_H
#include "../../include/capstone.h"
-#include "../../include/mips.h"
// return name of regiser in friendly string
const char *Mips_reg_name(csh handle, unsigned int reg);
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index 043ca3f..7611bf1 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/ppc.h"
#include "../../utils.h"
#include "PPCMapping.h"
diff --git a/arch/PowerPC/PPCMapping.h b/arch/PowerPC/PPCMapping.h
index 01ab8ec..ad1cc8a 100644
--- a/arch/PowerPC/PPCMapping.h
+++ b/arch/PowerPC/PPCMapping.h
@@ -5,7 +5,6 @@
#define CS_PPC_MAP_H
#include "../../include/capstone.h"
-#include "../../include/ppc.h"
// return name of regiser in friendly string
const char *PPC_reg_name(csh handle, unsigned int reg);
diff --git a/arch/Sparc/SparcMapping.c b/arch/Sparc/SparcMapping.c
index 9011131..fdd9384 100644
--- a/arch/Sparc/SparcMapping.c
+++ b/arch/Sparc/SparcMapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/sparc.h"
#include "../../utils.h"
#include "SparcMapping.h"
diff --git a/arch/Sparc/SparcMapping.h b/arch/Sparc/SparcMapping.h
index 3de9335..9db678a 100644
--- a/arch/Sparc/SparcMapping.h
+++ b/arch/Sparc/SparcMapping.h
@@ -5,7 +5,6 @@
#define CS_SPARC_MAP_H
#include "../../include/capstone.h"
-#include "../../include/sparc.h"
// return name of regiser in friendly string
const char *Sparc_reg_name(csh handle, unsigned int reg);
diff --git a/arch/SystemZ/SystemZGenDisassemblerTables.inc b/arch/SystemZ/SystemZGenDisassemblerTables.inc
index b1368d0..761187c 100644
--- a/arch/SystemZ/SystemZGenDisassemblerTables.inc
+++ b/arch/SystemZ/SystemZGenDisassemblerTables.inc
@@ -1,6 +1,6 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
-|* * Sparc Disassembler *|
+|* * SystemZ Disassembler *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c
index 3f78866..c8e44a6 100644
--- a/arch/SystemZ/SystemZMapping.c
+++ b/arch/SystemZ/SystemZMapping.c
@@ -6,7 +6,6 @@
#include <stdio.h> // debug
#include <string.h>
-#include "../../include/systemz.h"
#include "../../utils.h"
#include "SystemZMapping.h"
diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h
index 9a20ab6..21f8d43 100644
--- a/arch/SystemZ/SystemZMapping.h
+++ b/arch/SystemZ/SystemZMapping.h
@@ -5,7 +5,6 @@
#define CS_SYSZ_MAP_H
#include "../../include/capstone.h"
-#include "../../include/systemz.h"
// return name of regiser in friendly string
const char *SystemZ_reg_name(csh handle, unsigned int reg);
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 9fa98ef..6e6d7ad 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -9,7 +9,6 @@
#include "X86DisassemblerDecoder.h"
#include "../../utils.h"
-#include "../../include/x86.h"
uint64_t arch_masks[9] = {
diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h
index c958a2c..2869554 100644
--- a/arch/X86/X86Mapping.h
+++ b/arch/X86/X86Mapping.h
@@ -5,7 +5,6 @@
#define CS_X86_MAP_H
#include "../../include/capstone.h"
-#include "../../include/x86.h"
#include "../../cs_priv.h"
// map sib_base to x86_reg
diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c
new file mode 100644
index 0000000..79f6d0d
--- /dev/null
+++ b/arch/XCore/XCoreDisassembler.c
@@ -0,0 +1,786 @@
+//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include <stdio.h> // DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+static uint64_t getFeatureBits(int mode)
+{
+ // support everything
+ return (uint64_t)-1;
+}
+
+static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
+{
+ if (code_len < 2)
+ // insufficient data
+ return false;
+
+ // Encoded as a little-endian 16-bit word in the stream.
+ *insn = (code[0] << 0) | (code[1] << 8);
+ return true;
+}
+
+static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
+{
+ if (code_len < 4)
+ // insufficient data
+ return false;
+
+ // Encoded as a little-endian 32-bit word in the stream.
+ *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
+ return true;
+}
+
+static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+ MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+ return rc->RegsBegin[RegNo];
+}
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
+ uint64_t Address, void *Decoder);
+
+#include "XCoreGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "XCoreGenRegisterInfo.inc"
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 11)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+ uint64_t Address, void *Decoder)
+{
+ unsigned Reg;
+ if (RegNo > 15)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo);
+ MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder)
+{
+ static unsigned Values[] = {
+ 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
+ };
+
+ if (Val > 11)
+ return MCDisassembler_Fail;
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Values[Val]));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
+ uint64_t Address, void *Decoder)
+{
+ MCInst_addOperand(Inst, MCOperand_CreateImm(-(int64_t)Val));
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2)
+{
+ unsigned Op1High, Op2High;
+ unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
+
+ if (Combined < 27)
+ return MCDisassembler_Fail;
+
+ if (fieldFromInstruction_4(Insn, 5, 1)) {
+ if (Combined == 31)
+ return MCDisassembler_Fail;
+ Combined += 5;
+ }
+
+ Combined -= 27;
+ Op1High = Combined % 3;
+ Op2High = Combined / 3;
+ *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2);
+ *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode3OpInstruction(unsigned Insn,
+ unsigned *Op1, unsigned *Op2, unsigned *Op3)
+{
+ unsigned Op1High, Op2High, Op3High;
+ unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
+ if (Combined >= 27)
+ return MCDisassembler_Fail;
+
+ Op1High = Combined % 3;
+ Op2High = (Combined / 3) % 3;
+ Op3High = Combined / 9;
+ *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2);
+ *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2);
+ *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2);
+
+ return MCDisassembler_Success;
+}
+
+#define GET_INSTRINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ // Try and decode as a 3R instruction.
+ unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
+ switch (Opcode) {
+ case 0x0:
+ MCInst_setOpcode(Inst, XCore_STW_2rus);
+ return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x1:
+ MCInst_setOpcode(Inst, XCore_LDW_2rus);
+ return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x2:
+ MCInst_setOpcode(Inst, XCore_ADD_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x3:
+ MCInst_setOpcode(Inst, XCore_SUB_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x4:
+ MCInst_setOpcode(Inst, XCore_SHL_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x5:
+ MCInst_setOpcode(Inst, XCore_SHR_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x6:
+ MCInst_setOpcode(Inst, XCore_EQ_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x7:
+ MCInst_setOpcode(Inst, XCore_AND_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x8:
+ MCInst_setOpcode(Inst, XCore_OR_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x9:
+ MCInst_setOpcode(Inst, XCore_LDW_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x10:
+ MCInst_setOpcode(Inst, XCore_LD16S_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x11:
+ MCInst_setOpcode(Inst, XCore_LD8U_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x12:
+ MCInst_setOpcode(Inst, XCore_ADD_2rus);
+ return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x13:
+ MCInst_setOpcode(Inst, XCore_SUB_2rus);
+ return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x14:
+ MCInst_setOpcode(Inst, XCore_SHL_2rus);
+ return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+ case 0x15:
+ MCInst_setOpcode(Inst, XCore_SHR_2rus);
+ return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+ case 0x16:
+ MCInst_setOpcode(Inst, XCore_EQ_2rus);
+ return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x17:
+ MCInst_setOpcode(Inst, XCore_TSETR_3r);
+ return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
+ case 0x18:
+ MCInst_setOpcode(Inst, XCore_LSS_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x19:
+ MCInst_setOpcode(Inst, XCore_LSU_3r);
+ return Decode3RInstruction(Inst, Insn, Address, Decoder);
+ }
+
+ return MCDisassembler_Fail;
+}
+
+static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Op1));
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Op2));
+
+ return S;
+}
+
+static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeBitpOperand(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeBitpOperand(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ // Try and decode as a L3R / L2RUS instruction.
+ unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
+ fieldFromInstruction_4(Insn, 27, 5) << 4;
+ switch (Opcode) {
+ case 0x0c:
+ MCInst_setOpcode(Inst, XCore_STW_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x1c:
+ MCInst_setOpcode(Inst, XCore_XOR_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x2c:
+ MCInst_setOpcode(Inst, XCore_ASHR_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x3c:
+ MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x4c:
+ MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x5c:
+ MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x6c:
+ MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x7c:
+ MCInst_setOpcode(Inst, XCore_MUL_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x8c:
+ MCInst_setOpcode(Inst, XCore_DIVS_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x9c:
+ MCInst_setOpcode(Inst, XCore_DIVU_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x10c:
+ MCInst_setOpcode(Inst, XCore_ST16_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x11c:
+ MCInst_setOpcode(Inst, XCore_ST8_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x12c:
+ MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
+ return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+ case 0x12d:
+ MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
+ return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+ case 0x12e:
+ MCInst_setOpcode(Inst, XCore_INPW_l2rus);
+ return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+ case 0x13c:
+ MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
+ return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x14c:
+ MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
+ return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
+ case 0x15c:
+ MCInst_setOpcode(Inst, XCore_CRC_l3r);
+ return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
+ case 0x18c:
+ MCInst_setOpcode(Inst, XCore_REMS_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ case 0x19c:
+ MCInst_setOpcode(Inst, XCore_REMU_l3r);
+ return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+ }
+
+ return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
+ if (S != MCDisassembler_Success)
+ return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+
+ return S;
+}
+
+static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Op1));
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Op3));
+ }
+
+ return S;
+}
+
+static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeBitpOperand(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ MCInst_addOperand(Inst, MCOperand_CreateImm(Op3));
+ }
+
+ return S;
+}
+
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeBitpOperand(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3, Op4, Op5, Op6;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S != MCDisassembler_Success)
+ return S;
+
+ S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
+ if (S != MCDisassembler_Success)
+ return S;
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
+ return S;
+}
+
+static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Opcode;
+
+ // Try and decode as a L6R instruction.
+ MCInst_clear(Inst);
+ Opcode = fieldFromInstruction_4(Insn, 27, 5);
+ switch (Opcode) {
+ default:
+ break;
+ case 0x00:
+ MCInst_setOpcode(Inst, XCore_LMUL_l6r);
+ return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
+ }
+
+ return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3, Op4, Op5;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S != MCDisassembler_Success)
+ return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
+
+ S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
+ if (S != MCDisassembler_Success)
+ return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
+
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
+ return S;
+}
+
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ }
+
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+ return S;
+}
+
+static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+ void *Decoder)
+{
+ unsigned Op1, Op2, Op3;
+ unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ }
+
+ if (S == MCDisassembler_Success) {
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ }
+
+ return S;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
+ uint16_t *size, uint64_t address, void *info)
+{
+ uint16_t insn16;
+ uint32_t insn32;
+ DecodeStatus Result;
+
+ if (!readInstruction16(code, code_len, &insn16)) {
+ return MCDisassembler_Fail;
+ }
+
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
+ if (Result != MCDisassembler_Fail) {
+ *size = 2;
+ return Result;
+ }
+
+ if (!readInstruction32(code, code_len, &insn32)) {
+ return MCDisassembler_Fail;
+ }
+
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
+ if (Result != MCDisassembler_Fail) {
+ *size = 4;
+ return Result;
+ }
+
+ return MCDisassembler_Fail;
+}
+
+void XCore_init(MCRegisterInfo *MRI)
+{
+ /*
+ InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
+ XCoreMCRegisterClasses, 2,
+ XCoreRegUnitRoots,
+ 16,
+ XCoreRegDiffLists,
+ XCoreRegStrings,
+ XCoreSubRegIdxLists,
+ 1,
+ XCoreSubRegIdxRanges,
+ XCoreRegEncodingTable);
+ */
+
+
+ MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
+ 0, 0,
+ XCoreMCRegisterClasses, 2,
+ 0, 0,
+ XCoreRegDiffLists,
+ 0,
+ XCoreSubRegIdxLists, 1,
+ 0);
+}
+
+#endif
diff --git a/arch/XCore/XCoreDisassembler.h b/arch/XCore/XCoreDisassembler.h
new file mode 100644
index 0000000..07cb9ff
--- /dev/null
+++ b/arch/XCore/XCoreDisassembler.h
@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_XCOREDISASSEMBLER_H
+#define CS_XCOREDISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "../../include/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void XCore_init(MCRegisterInfo *MRI);
+
+bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+ MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
diff --git a/arch/XCore/XCoreGenAsmWriter.inc b/arch/XCore/XCoreGenAsmWriter.inc
new file mode 100644
index 0000000..28b94a8
--- /dev/null
+++ b/arch/XCore/XCoreGenAsmWriter.inc
@@ -0,0 +1,769 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include <stdio.h> // debug
+#include <inttypes.h>
+
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+ static const uint32_t OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 665U, // DBG_VALUE
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 658U, // BUNDLE
+ 687U, // LIFETIME_START
+ 645U, // LIFETIME_END
+ 0U, // STACKMAP
+ 0U, // PATCHPOINT
+ 2250U, // ADD_2rus
+ 2250U, // ADD_3r
+ 10363U, // ADJCALLSTACKDOWN
+ 10383U, // ADJCALLSTACKUP
+ 2361840U, // ANDNOT_2r
+ 2255U, // AND_3r
+ 2404U, // ASHR_l2rus
+ 2404U, // ASHR_l3r
+ 10769U, // BAU_1r
+ 2099777U, // BITREV_l2r
+ 19161U, // BLACP_lu10
+ 19161U, // BLACP_u10
+ 10672U, // BLAT_lu6
+ 10672U, // BLAT_u6
+ 10425U, // BLA_1r
+ 10510U, // BLRB_lu10
+ 10510U, // BLRB_u10
+ 10510U, // BLRF_lu10
+ 10510U, // BLRF_u10
+ 2099418U, // BRBF_lru6
+ 2099418U, // BRBF_ru6
+ 2099638U, // BRBT_lru6
+ 2099638U, // BRBT_ru6
+ 10774U, // BRBU_lu6
+ 10774U, // BRBU_u6
+ 2099418U, // BRFF_lru6
+ 2099418U, // BRFF_ru6
+ 2099638U, // BRFT_lru6
+ 2099638U, // BRFT_ru6
+ 10774U, // BRFU_lu6
+ 10774U, // BRFU_u6
+ 10791U, // BRU_1r
+ 553511U, // BR_JT
+ 815655U, // BR_JT32
+ 2099768U, // BYTEREV_l2r
+ 2132815U, // CHKCT_2r
+ 2132815U, // CHKCT_rus
+ 1163U, // CLRE_0R
+ 19301U, // CLRPT_1R
+ 10614U, // CLRSR_branch_lu6
+ 10614U, // CLRSR_branch_u6
+ 10614U, // CLRSR_lu6
+ 10614U, // CLRSR_u6
+ 2099807U, // CLZ_l2r
+ 5247047U, // CRC8_l4r
+ 17041459U, // CRC_l3r
+ 1168U, // DCALL_0R
+ 1200U, // DENTSP_0R
+ 10488U, // DGETREG_1r
+ 2474U, // DIVS_l3r
+ 2610U, // DIVU_l3r
+ 1207U, // DRESTSP_0R
+ 1242U, // DRET_0R
+ 10475U, // ECALLF_1r
+ 10723U, // ECALLT_1r
+ 19342U, // EDU_1r
+ 6334686U, // EEF_2r
+ 6334929U, // EET_2r
+ 19351U, // EEU_1r
+ 2099310U, // EH_RETURN
+ 6334765U, // ENDIN_2r
+ 10569U, // ENTSP_lu6
+ 10569U, // ENTSP_u6
+ 2400U, // EQ_2rus
+ 2400U, // EQ_3r
+ 10554U, // EXTDP_lu6
+ 10554U, // EXTDP_u6
+ 10585U, // EXTSP_lu6
+ 10585U, // EXTSP_u6
+ 10401U, // FRAME_TO_ARGS_OFFSET
+ 19256U, // FREER_1r
+ 1236U, // FREET_0R
+ 6334676U, // GETD_l2r
+ 1139U, // GETED_0R
+ 1224U, // GETET_0R
+ 1151U, // GETID_0R
+ 1174U, // GETKEP_0R
+ 1187U, // GETKSP_0R
+ 6334772U, // GETN_l2r
+ 51670U, // GETPS_l2r
+ 2099588U, // GETR_rus
+ 10252U, // GETSR_lu6
+ 10252U, // GETSR_u6
+ 6334968U, // GETST_2r
+ 6334883U, // GETTS_2r
+ 6334906U, // INCT_2r
+ 62438U, // INITCP_2r
+ 70630U, // INITDP_2r
+ 78822U, // INITLR_l2r
+ 87014U, // INITPC_2r
+ 95206U, // INITSP_2r
+ 8432212U, // INPW_l2rus
+ 6596970U, // INSHR_2r
+ 6334955U, // INT_2r
+ 6334768U, // IN_2r
+ 675U, // Int_MemBarrier
+ 10528U, // KCALL_1r
+ 10528U, // KCALL_lu6
+ 10528U, // KCALL_u6
+ 10568U, // KENTSP_lu6
+ 10568U, // KENTSP_u6
+ 10576U, // KRESTSP_lu6
+ 10576U, // KRESTSP_u6
+ 1247U, // KRET_0R
+ 45093065U, // LADD_l5r
+ 12585354U, // LD16S_3r
+ 12585483U, // LD8U_3r
+ 14682170U, // LDA16B_l3r
+ 12585018U, // LDA16F_l3r
+ 10241U, // LDAPB_lu10
+ 10241U, // LDAPB_u10
+ 10241U, // LDAPF_lu10
+ 10241U, // LDAPF_lu10_ba
+ 10241U, // LDAPF_u10
+ 14682697U, // LDAWB_l2rus
+ 14682697U, // LDAWB_l3r
+ 19134U, // LDAWCP_lu6
+ 19134U, // LDAWCP_u6
+ 100937U, // LDAWDP_lru6
+ 100937U, // LDAWDP_ru6
+ 2099282U, // LDAWFI
+ 12585545U, // LDAWF_l2rus
+ 12585545U, // LDAWF_l3r
+ 109129U, // LDAWSP_lru6
+ 109129U, // LDAWSP_ru6
+ 2099396U, // LDC_lru6
+ 2099396U, // LDC_ru6
+ 1105U, // LDET_0R
+ 184551985U, // LDIVU_l5r
+ 1075U, // LDSED_0R
+ 1015U, // LDSPC_0R
+ 1045U, // LDSSR_0R
+ 117327U, // LDWCP_lru6
+ 19148U, // LDWCP_lu10
+ 117327U, // LDWCP_ru6
+ 19148U, // LDWCP_u10
+ 100943U, // LDWDP_lru6
+ 100943U, // LDWDP_ru6
+ 2099292U, // LDWFI
+ 109135U, // LDWSP_lru6
+ 109135U, // LDWSP_ru6
+ 12585551U, // LDW_2rus
+ 12585551U, // LDW_3r
+ 268437799U, // LMUL_l6r
+ 2462U, // LSS_3r
+ 45093054U, // LSUB_l5r
+ 2604U, // LSU_3r
+ 452987281U, // MACCS_l4r
+ 452987418U, // MACCU_l4r
+ 19224U, // MJOIN_1r
+ 2099463U, // MKMSK_2r
+ 2099463U, // MKMSK_rus
+ 19169U, // MSYNC_1r
+ 2344U, // MUL_l3r
+ 2099443U, // NEG
+ 2099699U, // NOT
+ 2418U, // OR_3r
+ 2132826U, // OUTCT_2r
+ 2132826U, // OUTCT_rus
+ 78681013U, // OUTPW_l2rus
+ 2136899U, // OUTSHR_2r
+ 2132859U, // OUTT_2r
+ 2132869U, // OUT_2r
+ 6334721U, // PEEK_2r
+ 2456U, // REMS_l3r
+ 2593U, // REMU_l3r
+ 10561U, // RETSP_lu6
+ 10561U, // RETSP_u6
+ 612U, // SELECT_CC
+ 2132748U, // SETCLK_l2r
+ 10264U, // SETCP_1r
+ 2132728U, // SETC_l2r
+ 2132728U, // SETC_lru6
+ 2132728U, // SETC_ru6
+ 10273U, // SETDP_1r
+ 2132738U, // SETD_2r
+ 125856U, // SETEV_1r
+ 632U, // SETKEP_0R
+ 2132771U, // SETN_l2r
+ 2132716U, // SETPSC_2r
+ 2132951U, // SETPS_l2r
+ 2132848U, // SETPT_2r
+ 2132939U, // SETRDY_l2r
+ 10282U, // SETSP_1r
+ 10621U, // SETSR_branch_lu6
+ 10621U, // SETSR_branch_u6
+ 10621U, // SETSR_lu6
+ 10621U, // SETSR_u6
+ 2132928U, // SETTW_l2r
+ 125867U, // SETV_1r
+ 2361855U, // SEXT_2r
+ 2361855U, // SEXT_rus
+ 2331U, // SHL_2rus
+ 2331U, // SHL_3r
+ 2405U, // SHR_2rus
+ 2405U, // SHR_3r
+ 1133U, // SSYNC_0r
+ 12585025U, // ST16_l3r
+ 12585037U, // ST8_l3r
+ 1119U, // STET_0R
+ 1090U, // STSED_0R
+ 1030U, // STSPC_0R
+ 1060U, // STSSR_0R
+ 100954U, // STWDP_lru6
+ 100954U, // STWDP_ru6
+ 2099301U, // STWFI
+ 109146U, // STWSP_lru6
+ 109146U, // STWSP_ru6
+ 12585562U, // STW_2rus
+ 12585562U, // STW_l3r
+ 2239U, // SUB_2rus
+ 2239U, // SUB_3r
+ 19245U, // SYNCR_1r
+ 6334912U, // TESTCT_2r
+ 6334738U, // TESTLCL_l2r
+ 6334920U, // TESTWCT_2r
+ 2100415U, // TSETMR_2r
+ 138207U, // TSETR_3r
+ 19438U, // TSTART_1R
+ 10467U, // WAITEF_1R
+ 10715U, // WAITET_1R
+ 1252U, // WAITEU_0R
+ 2417U, // XOR_l3r
+ 2361861U, // ZEXT_2r
+ 2361861U, // ZEXT_rus
+ 0U
+ };
+
+#ifndef CAPSTONE_DIET
+ static char AsmStrs[] = {
+ /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0,
+ /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0,
+ /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0,
+ /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0,
+ /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0,
+ /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0,
+ /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0,
+ /* 64 */ 's', 't', '1', '6', 32, 0,
+ /* 70 */ 'c', 'r', 'c', '8', 32, 0,
+ /* 76 */ 's', 't', '8', 32, 0,
+ /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0,
+ /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0,
+ /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0,
+ /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0,
+ /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
+ /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
+ /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0,
+ /* 184 */ 'b', 'l', 'a', 32, 0,
+ /* 189 */ 'l', 's', 'u', 'b', 32, 0,
+ /* 195 */ 'l', 'd', 'c', 32, 0,
+ /* 200 */ 'l', 'a', 'd', 'd', 32, 0,
+ /* 206 */ 'a', 'n', 'd', 32, 0,
+ /* 211 */ 'g', 'e', 't', 'd', 32, 0,
+ /* 217 */ 'b', 'f', 32, 0,
+ /* 221 */ 'e', 'e', 'f', 32, 0,
+ /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0,
+ /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0,
+ /* 242 */ 'n', 'e', 'g', 32, 0,
+ /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0,
+ /* 256 */ 'p', 'e', 'e', 'k', 32, 0,
+ /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0,
+ /* 269 */ 'b', 'l', 32, 0,
+ /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0,
+ /* 282 */ 's', 'h', 'l', 32, 0,
+ /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0,
+ /* 294 */ 'l', 'm', 'u', 'l', 32, 0,
+ /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0,
+ /* 307 */ 'g', 'e', 't', 'n', 32, 0,
+ /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0,
+ /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0,
+ /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0,
+ /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0,
+ /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0,
+ /* 351 */ 'e', 'q', 32, 0,
+ /* 355 */ 'a', 's', 'h', 'r', 32, 0,
+ /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0,
+ /* 368 */ 'x', 'o', 'r', 32, 0,
+ /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0,
+ /* 380 */ 's', 'e', 't', 's', 'r', 32, 0,
+ /* 387 */ 'g', 'e', 't', 'r', 32, 0,
+ /* 393 */ 'l', 'd', '1', '6', 's', 32, 0,
+ /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0,
+ /* 407 */ 'r', 'e', 'm', 's', 32, 0,
+ /* 413 */ 'l', 's', 's', 32, 0,
+ /* 418 */ 'g', 'e', 't', 't', 's', 32, 0,
+ /* 425 */ 'd', 'i', 'v', 's', 32, 0,
+ /* 431 */ 'b', 'l', 'a', 't', 32, 0,
+ /* 437 */ 'b', 't', 32, 0,
+ /* 441 */ 'i', 'n', 'c', 't', 32, 0,
+ /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0,
+ /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0,
+ /* 464 */ 'e', 'e', 't', 32, 0,
+ /* 469 */ 'g', 'e', 't', 32, 0,
+ /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0,
+ /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0,
+ /* 490 */ 'i', 'n', 't', 32, 0,
+ /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0,
+ /* 503 */ 'g', 'e', 't', 's', 't', 32, 0,
+ /* 510 */ 's', 'e', 'x', 't', 32, 0,
+ /* 516 */ 'z', 'e', 'x', 't', 32, 0,
+ /* 522 */ 'l', 'd', '8', 'u', 32, 0,
+ /* 528 */ 'b', 'a', 'u', 32, 0,
+ /* 533 */ 'b', 'u', 32, 0,
+ /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0,
+ /* 544 */ 'r', 'e', 'm', 'u', 32, 0,
+ /* 550 */ 'b', 'r', 'u', 32, 0,
+ /* 555 */ 'l', 's', 'u', 32, 0,
+ /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0,
+ /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0,
+ /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0,
+ /* 584 */ 'l', 'd', 'a', 'w', 32, 0,
+ /* 590 */ 'l', 'd', 'w', 32, 0,
+ /* 595 */ 'i', 'n', 'p', 'w', 32, 0,
+ /* 601 */ 's', 't', 'w', 32, 0,
+ /* 606 */ 'c', 'l', 'z', 32, 0,
+ /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
+ /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0,
+ /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
+ /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
+ /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
+ /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0,
+ /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0,
+ /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0,
+ /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0,
+ /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0,
+ /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0,
+ /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0,
+ /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0,
+ /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0,
+ /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0,
+ /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0,
+ /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0,
+ /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0,
+ /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0,
+ /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0,
+ /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0,
+ /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0,
+ /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0,
+ /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0,
+ /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0,
+ /* 990 */ 's', 'e', 't', 32, 't', '[', 0,
+ /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0,
+ /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0,
+ /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
+ /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
+ /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
+ /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
+ /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
+ /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
+ /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
+ /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
+ /* 1132 */ 's', 's', 'y', 'n', 'c', 0,
+ /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0,
+ /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0,
+ /* 1162 */ 'c', 'l', 'r', 'e', 0,
+ /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0,
+ /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0,
+ /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0,
+ /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0,
+ /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0,
+ /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0,
+ /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0,
+ /* 1235 */ 'f', 'r', 'e', 'e', 't', 0,
+ /* 1241 */ 'd', 'r', 'e', 't', 0,
+ /* 1246 */ 'k', 'r', 'e', 't', 0,
+ /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0,
+ };
+#endif
+
+ // Emit the opcode for the instruction.
+ uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
+ // assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+ SStream_concat(O, "%s", AsmStrs+(Bits & 2047)-1);
+#endif
+
+
+ if (strchr(AsmStrs+(Bits & 2047)-1, '[')) {
+ set_mem_access(MI, true, 0);
+ }
+
+ // Fragment 0 encoded into 2 bits for 4 unique commands.
+ //printf(">>%s\n", AsmStrs+(Bits & 2047)-1);
+ //printf("Frag-0: %u\n", (Bits >> 11) & 3);
+ switch ((Bits >> 11) & 3) {
+ default: // unreachable.
+ case 0:
+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE...
+ return;
+ break;
+ case 1:
+ // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,...
+ printOperand(MI, 0, O);
+ break;
+ case 2:
+ // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,...
+ printOperand(MI, 1, O);
+ break;
+ case 3:
+ // OUTSHR_2r, TSETR_3r
+ printOperand(MI, 2, O);
+ break;
+ }
+
+
+ // Fragment 1 encoded into 5 bits for 17 unique commands.
+ //printf("Frag-1: %u\n", (Bits >> 13) & 31);
+ switch ((Bits >> 13) & 31) {
+ default: // unreachable.
+ case 0:
+ // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,...
+ SStream_concat(O, "%s", ", ");
+ break;
+ case 1:
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B...
+ return;
+ break;
+ case 2:
+ // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,...
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 3:
+ // BR_JT, BR_JT32
+ SStream_concat(O, "%s", "\n");
+ break;
+ case 4:
+ // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT...
+ SStream_concat(O, "%s", "], ");
+ set_mem_access(MI, false, 0);
+ break;
+ case 5:
+ // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
+ SStream_concat(O, "%s", ", res[");
+ set_mem_access(MI, true, 0);
+ break;
+ case 6:
+ // GETPS_l2r
+ SStream_concat(O, "%s", ", ps[");
+ set_mem_access(MI, true, 0);
+ printOperand(MI, 1, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 7:
+ // INITCP_2r
+ SStream_concat(O, "%s", "]:cp, ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 8:
+ // INITDP_2r
+ SStream_concat(O, "%s", "]:dp, ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 9:
+ // INITLR_l2r
+ SStream_concat(O, "%s", "]:lr, ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 10:
+ // INITPC_2r
+ SStream_concat(O, "%s", "]:pc, ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 11:
+ // INITSP_2r
+ SStream_concat(O, "%s", "]:sp, ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 12:
+ // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6
+ SStream_concat(O, "%s", ", dp[");
+ set_mem_access(MI, true, XCORE_REG_DP);
+ printOperand(MI, 1, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 13:
+ // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6
+ SStream_concat(O, "%s", ", sp[");
+ set_mem_access(MI, true, XCORE_REG_SP);
+ printOperand(MI, 1, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 14:
+ // LDWCP_lru6, LDWCP_ru6
+ SStream_concat(O, "%s", ", cp[");
+ set_mem_access(MI, true, XCORE_REG_CP);
+ printOperand(MI, 1, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 15:
+ // SETEV_1r, SETV_1r
+ SStream_concat(O, "%s", "], r11");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 16:
+ // TSETR_3r
+ SStream_concat(O, "%s", "]:r");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 0, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 3 bits for 5 unique commands.
+ //printf("Frag-2: %u\n", (Bits >> 18) & 7);
+ switch ((Bits >> 18) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,...
+ printOperand(MI, 1, O);
+ break;
+ case 1:
+ // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus
+ printOperand(MI, 2, O);
+ break;
+ case 2:
+ // BR_JT
+ printInlineJT(MI, 0, O);
+ return;
+ break;
+ case 3:
+ // BR_JT32
+ printInlineJT32(MI, 0, O);
+ return;
+ break;
+ case 4:
+ // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus
+ printOperand(MI, 0, O);
+ SStream_concat(O, "%s", ", ");
+ break;
+ }
+
+
+ // Fragment 3 encoded into 3 bits for 8 unique commands.
+ //printf("Frag-3: %u\n", (Bits >> 21) & 7);
+ switch ((Bits >> 21) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV...
+ SStream_concat(O, "%s", ", ");
+ break;
+ case 1:
+ // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_...
+ return;
+ break;
+ case 2:
+ // CRC8_l4r
+ printOperand(MI, 3, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 4, O);
+ return;
+ break;
+ case 3:
+ // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 4:
+ // INPW_l2rus
+ SStream_concat(O, "%s", "], ");
+ set_mem_access(MI, false, 0);
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 5:
+ // LADD_l5r, LSUB_l5r, OUTPW_l2rus
+ printOperand(MI, 2, O);
+ break;
+ case 6:
+ // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3...
+ SStream_concat(O, "%s", "[");
+ set_mem_access(MI, true, 0xffff);
+ printOperand(MI, 2, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ case 7:
+ // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r
+ SStream_concat(O, "%s", "[-");
+ set_mem_access(MI, true, -0xffff);
+ printOperand(MI, 2, O);
+ SStream_concat(O, "%s", "]");
+ set_mem_access(MI, false, 0);
+ return;
+ break;
+ }
+
+
+ // Fragment 4 encoded into 3 bits for 5 unique commands.
+ //printf("Frag-4: %u\n", (Bits >> 24) & 7);
+ switch ((Bits >> 24) & 7) {
+ default: // unreachable.
+ case 0:
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
+ printOperand(MI, 2, O);
+ break;
+ case 1:
+ // CRC_l3r
+ printOperand(MI, 3, O);
+ return;
+ break;
+ case 2:
+ // LADD_l5r, LSUB_l5r
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 3, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 4, O);
+ return;
+ break;
+ case 3:
+ // LDIVU_l5r, MACCS_l4r, MACCU_l4r
+ printOperand(MI, 4, O);
+ SStream_concat(O, "%s", ", ");
+ break;
+ case 4:
+ // OUTPW_l2rus
+ return;
+ break;
+ }
+
+
+ // Fragment 5 encoded into 2 bits for 4 unique commands.
+ //printf("Frag-5: %u\n", (Bits >> 27) & 3);
+ switch ((Bits >> 27) & 3) {
+ default: // unreachable.
+ case 0:
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
+ return;
+ break;
+ case 1:
+ // LDIVU_l5r
+ printOperand(MI, 2, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 3, O);
+ return;
+ break;
+ case 2:
+ // LMUL_l6r
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 3, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 4, O);
+ SStream_concat(O, "%s", ", ");
+ printOperand(MI, 5, O);
+ return;
+ break;
+ case 3:
+ // MACCS_l4r, MACCU_l4r
+ printOperand(MI, 5, O);
+ return;
+ break;
+ }
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo)
+{
+ // assert(RegNo && RegNo < 17 && "Invalid register number!");
+
+#ifndef CAPSTONE_DIET
+ static const char AsmStrs[] = {
+ /* 0 */ 'r', '1', '0', 0,
+ /* 4 */ 'r', '0', 0,
+ /* 7 */ 'r', '1', '1', 0,
+ /* 11 */ 'r', '1', 0,
+ /* 14 */ 'r', '2', 0,
+ /* 17 */ 'r', '3', 0,
+ /* 20 */ 'r', '4', 0,
+ /* 23 */ 'r', '5', 0,
+ /* 26 */ 'r', '6', 0,
+ /* 29 */ 'r', '7', 0,
+ /* 32 */ 'r', '8', 0,
+ /* 35 */ 'r', '9', 0,
+ /* 38 */ 'c', 'p', 0,
+ /* 41 */ 'd', 'p', 0,
+ /* 44 */ 's', 'p', 0,
+ /* 47 */ 'l', 'r', 0,
+ };
+
+ static const uint32_t RegAsmOffset[] = {
+ 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35,
+ 0, 7,
+ };
+
+ //int i;
+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
+ //printf("*************************\n");
+ return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
+}
diff --git a/arch/XCore/XCoreGenDisassemblerTables.inc b/arch/XCore/XCoreGenDisassemblerTables.inc
new file mode 100644
index 0000000..aca4113
--- /dev/null
+++ b/arch/XCore/XCoreGenDisassemblerTables.inc
@@ -0,0 +1,853 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * XCore Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
+{ \
+ InsnType fieldMask; \
+ if (numBits == sizeof(InsnType)*8) \
+ fieldMask = (InsnType)(-1LL); \
+ else \
+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+ return (insn & fieldMask) >> startBit; \
+}
+
+static uint8_t DecoderTable16[] = {
+/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115
+/* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 10 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19
+/* 15 */ MCD_OPC_Decode, 240, 1, 0, // Opcode: WAITEU_0R
+/* 19 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27
+/* 24 */ MCD_OPC_Decode, 56, 0, // Opcode: CLRE_0R
+/* 27 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36
+/* 32 */ MCD_OPC_Decode, 215, 1, 0, // Opcode: SSYNC_0r
+/* 36 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44
+/* 41 */ MCD_OPC_Decode, 90, 0, // Opcode: FREET_0R
+/* 44 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52
+/* 49 */ MCD_OPC_Decode, 65, 0, // Opcode: DCALL_0R
+/* 52 */ MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60
+/* 57 */ MCD_OPC_Decode, 122, 0, // Opcode: KRET_0R
+/* 60 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68
+/* 65 */ MCD_OPC_Decode, 71, 0, // Opcode: DRET_0R
+/* 68 */ MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77
+/* 73 */ MCD_OPC_Decode, 196, 1, 0, // Opcode: SETKEP_0R
+/* 77 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 80 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87
+/* 84 */ MCD_OPC_Decode, 74, 1, // Opcode: EDU_1r
+/* 87 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94
+/* 91 */ MCD_OPC_Decode, 77, 1, // Opcode: EEU_1r
+/* 94 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 97 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104
+/* 101 */ MCD_OPC_Decode, 108, 2, // Opcode: INITPC_2r
+/* 104 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111
+/* 108 */ MCD_OPC_Decode, 102, 2, // Opcode: GETST_2r
+/* 111 */ MCD_OPC_Decode, 227, 1, 3, // Opcode: STW_2rus
+/* 115 */ MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233
+/* 119 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 122 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131
+/* 127 */ MCD_OPC_Decode, 149, 1, 0, // Opcode: LDSPC_0R
+/* 131 */ MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140
+/* 136 */ MCD_OPC_Decode, 220, 1, 0, // Opcode: STSPC_0R
+/* 140 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149
+/* 145 */ MCD_OPC_Decode, 150, 1, 0, // Opcode: LDSSR_0R
+/* 149 */ MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158
+/* 154 */ MCD_OPC_Decode, 221, 1, 0, // Opcode: STSSR_0R
+/* 158 */ MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167
+/* 163 */ MCD_OPC_Decode, 219, 1, 0, // Opcode: STSED_0R
+/* 167 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176
+/* 172 */ MCD_OPC_Decode, 218, 1, 0, // Opcode: STET_0R
+/* 176 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184
+/* 181 */ MCD_OPC_Decode, 92, 0, // Opcode: GETED_0R
+/* 184 */ MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192
+/* 189 */ MCD_OPC_Decode, 93, 0, // Opcode: GETET_0R
+/* 192 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 195 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203
+/* 199 */ MCD_OPC_Decode, 239, 1, 1, // Opcode: WAITET_1R
+/* 203 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211
+/* 207 */ MCD_OPC_Decode, 238, 1, 1, // Opcode: WAITEF_1R
+/* 211 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 214 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221
+/* 218 */ MCD_OPC_Decode, 106, 2, // Opcode: INITDP_2r
+/* 221 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229
+/* 225 */ MCD_OPC_Decode, 180, 1, 4, // Opcode: OUTT_2r
+/* 229 */ MCD_OPC_Decode, 160, 1, 3, // Opcode: LDW_2rus
+/* 233 */ MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337
+/* 237 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 240 */ MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248
+/* 245 */ MCD_OPC_Decode, 66, 0, // Opcode: DENTSP_0R
+/* 248 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256
+/* 253 */ MCD_OPC_Decode, 70, 0, // Opcode: DRESTSP_0R
+/* 256 */ MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264
+/* 261 */ MCD_OPC_Decode, 94, 0, // Opcode: GETID_0R
+/* 264 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272
+/* 269 */ MCD_OPC_Decode, 95, 0, // Opcode: GETKEP_0R
+/* 272 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280
+/* 277 */ MCD_OPC_Decode, 96, 0, // Opcode: GETKSP_0R
+/* 280 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289
+/* 285 */ MCD_OPC_Decode, 148, 1, 0, // Opcode: LDSED_0R
+/* 289 */ MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298
+/* 294 */ MCD_OPC_Decode, 146, 1, 0, // Opcode: LDET_0R
+/* 298 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 301 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308
+/* 305 */ MCD_OPC_Decode, 89, 1, // Opcode: FREER_1r
+/* 308 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316
+/* 312 */ MCD_OPC_Decode, 168, 1, 1, // Opcode: MJOIN_1r
+/* 316 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 319 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326
+/* 323 */ MCD_OPC_Decode, 109, 2, // Opcode: INITSP_2r
+/* 326 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334
+/* 330 */ MCD_OPC_Decode, 194, 1, 4, // Opcode: SETD_2r
+/* 334 */ MCD_OPC_Decode, 20, 5, // Opcode: ADD_3r
+/* 337 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382
+/* 341 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 344 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352
+/* 348 */ MCD_OPC_Decode, 237, 1, 1, // Opcode: TSTART_1R
+/* 352 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360
+/* 356 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: MSYNC_1r
+/* 360 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 363 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370
+/* 367 */ MCD_OPC_Decode, 105, 2, // Opcode: INITCP_2r
+/* 370 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378
+/* 374 */ MCD_OPC_Decode, 235, 1, 6, // Opcode: TSETMR_2r
+/* 378 */ MCD_OPC_Decode, 230, 1, 5, // Opcode: SUB_3r
+/* 382 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416
+/* 386 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 389 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396
+/* 393 */ MCD_OPC_Decode, 33, 1, // Opcode: BLA_1r
+/* 396 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403
+/* 400 */ MCD_OPC_Decode, 27, 1, // Opcode: BAU_1r
+/* 403 */ MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412
+/* 409 */ MCD_OPC_Decode, 76, 2, // Opcode: EET_2r
+/* 412 */ MCD_OPC_Decode, 212, 1, 5, // Opcode: SHL_3r
+/* 416 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459
+/* 420 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 423 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430
+/* 427 */ MCD_OPC_Decode, 50, 1, // Opcode: BRU_1r
+/* 430 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438
+/* 434 */ MCD_OPC_Decode, 202, 1, 1, // Opcode: SETSP_1r
+/* 438 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 441 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448
+/* 445 */ MCD_OPC_Decode, 23, 7, // Opcode: ANDNOT_2r
+/* 448 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455
+/* 452 */ MCD_OPC_Decode, 75, 2, // Opcode: EEF_2r
+/* 455 */ MCD_OPC_Decode, 214, 1, 5, // Opcode: SHR_3r
+/* 459 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504
+/* 463 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 466 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474
+/* 470 */ MCD_OPC_Decode, 193, 1, 1, // Opcode: SETDP_1r
+/* 474 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482
+/* 478 */ MCD_OPC_Decode, 189, 1, 1, // Opcode: SETCP_1r
+/* 482 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 485 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493
+/* 489 */ MCD_OPC_Decode, 209, 1, 7, // Opcode: SEXT_2r
+/* 493 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501
+/* 497 */ MCD_OPC_Decode, 210, 1, 8, // Opcode: SEXT_rus
+/* 501 */ MCD_OPC_Decode, 83, 5, // Opcode: EQ_3r
+/* 504 */ MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547
+/* 508 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 511 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518
+/* 515 */ MCD_OPC_Decode, 67, 1, // Opcode: DGETREG_1r
+/* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526
+/* 522 */ MCD_OPC_Decode, 195, 1, 1, // Opcode: SETEV_1r
+/* 526 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 529 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536
+/* 533 */ MCD_OPC_Decode, 103, 2, // Opcode: GETTS_2r
+/* 536 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544
+/* 540 */ MCD_OPC_Decode, 200, 1, 4, // Opcode: SETPT_2r
+/* 544 */ MCD_OPC_Decode, 24, 5, // Opcode: AND_3r
+/* 547 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592
+/* 551 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 554 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561
+/* 558 */ MCD_OPC_Decode, 115, 1, // Opcode: KCALL_1r
+/* 561 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569
+/* 565 */ MCD_OPC_Decode, 208, 1, 1, // Opcode: SETV_1r
+/* 569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 572 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580
+/* 576 */ MCD_OPC_Decode, 242, 1, 7, // Opcode: ZEXT_2r
+/* 580 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588
+/* 584 */ MCD_OPC_Decode, 243, 1, 8, // Opcode: ZEXT_rus
+/* 588 */ MCD_OPC_Decode, 175, 1, 5, // Opcode: OR_3r
+/* 592 */ MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636
+/* 596 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 599 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606
+/* 603 */ MCD_OPC_Decode, 72, 1, // Opcode: ECALLF_1r
+/* 606 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613
+/* 610 */ MCD_OPC_Decode, 73, 1, // Opcode: ECALLT_1r
+/* 613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 616 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624
+/* 620 */ MCD_OPC_Decode, 176, 1, 2, // Opcode: OUTCT_2r
+/* 624 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632
+/* 628 */ MCD_OPC_Decode, 177, 1, 9, // Opcode: OUTCT_rus
+/* 632 */ MCD_OPC_Decode, 161, 1, 5, // Opcode: LDW_3r
+/* 636 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659
+/* 640 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 643 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651
+/* 647 */ MCD_OPC_Decode, 223, 1, 10, // Opcode: STWDP_ru6
+/* 651 */ MCD_OPC_FilterValue, 1, 53, 2, // Skip to: 1220
+/* 655 */ MCD_OPC_Decode, 226, 1, 10, // Opcode: STWSP_ru6
+/* 659 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682
+/* 663 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 666 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674
+/* 670 */ MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWDP_ru6
+/* 674 */ MCD_OPC_FilterValue, 1, 30, 2, // Skip to: 1220
+/* 678 */ MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWSP_ru6
+/* 682 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705
+/* 686 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 689 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697
+/* 693 */ MCD_OPC_Decode, 138, 1, 10, // Opcode: LDAWDP_ru6
+/* 697 */ MCD_OPC_FilterValue, 1, 7, 2, // Skip to: 1220
+/* 701 */ MCD_OPC_Decode, 143, 1, 10, // Opcode: LDAWSP_ru6
+/* 705 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728
+/* 709 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 712 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720
+/* 716 */ MCD_OPC_Decode, 145, 1, 10, // Opcode: LDC_ru6
+/* 720 */ MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 1220
+/* 724 */ MCD_OPC_Decode, 153, 1, 10, // Opcode: LDWCP_ru6
+/* 728 */ MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812
+/* 732 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 735 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773
+/* 739 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 742 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749
+/* 746 */ MCD_OPC_Decode, 49, 11, // Opcode: BRFU_u6
+/* 749 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756
+/* 753 */ MCD_OPC_Decode, 32, 11, // Opcode: BLAT_u6
+/* 756 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763
+/* 760 */ MCD_OPC_Decode, 85, 11, // Opcode: EXTDP_u6
+/* 763 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770
+/* 767 */ MCD_OPC_Decode, 117, 11, // Opcode: KCALL_u6
+/* 770 */ MCD_OPC_Decode, 47, 12, // Opcode: BRFT_ru6
+/* 773 */ MCD_OPC_FilterValue, 1, 187, 1, // Skip to: 1220
+/* 777 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 780 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787
+/* 784 */ MCD_OPC_Decode, 43, 13, // Opcode: BRBU_u6
+/* 787 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794
+/* 791 */ MCD_OPC_Decode, 81, 11, // Opcode: ENTSP_u6
+/* 794 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801
+/* 798 */ MCD_OPC_Decode, 87, 11, // Opcode: EXTSP_u6
+/* 801 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809
+/* 805 */ MCD_OPC_Decode, 186, 1, 11, // Opcode: RETSP_u6
+/* 809 */ MCD_OPC_Decode, 41, 14, // Opcode: BRBT_ru6
+/* 812 */ MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883
+/* 816 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 819 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858
+/* 823 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 826 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833
+/* 830 */ MCD_OPC_Decode, 61, 11, // Opcode: CLRSR_u6
+/* 833 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841
+/* 837 */ MCD_OPC_Decode, 206, 1, 11, // Opcode: SETSR_u6
+/* 841 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848
+/* 845 */ MCD_OPC_Decode, 119, 11, // Opcode: KENTSP_u6
+/* 848 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855
+/* 852 */ MCD_OPC_Decode, 121, 11, // Opcode: KRESTSP_u6
+/* 855 */ MCD_OPC_Decode, 45, 12, // Opcode: BRFF_ru6
+/* 858 */ MCD_OPC_FilterValue, 1, 102, 1, // Skip to: 1220
+/* 862 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 865 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872
+/* 869 */ MCD_OPC_Decode, 101, 11, // Opcode: GETSR_u6
+/* 872 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880
+/* 876 */ MCD_OPC_Decode, 136, 1, 11, // Opcode: LDAWCP_u6
+/* 880 */ MCD_OPC_Decode, 39, 14, // Opcode: BRBF_ru6
+/* 883 */ MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925
+/* 887 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 890 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897
+/* 894 */ MCD_OPC_Decode, 57, 1, // Opcode: CLRPT_1R
+/* 897 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905
+/* 901 */ MCD_OPC_Decode, 231, 1, 1, // Opcode: SYNCR_1r
+/* 905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 908 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915
+/* 912 */ MCD_OPC_Decode, 99, 9, // Opcode: GETR_rus
+/* 915 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922
+/* 919 */ MCD_OPC_Decode, 104, 2, // Opcode: INCT_2r
+/* 922 */ MCD_OPC_Decode, 124, 5, // Opcode: LD16S_3r
+/* 925 */ MCD_OPC_FilterValue, 17, 21, 0, // Skip to: 950
+/* 929 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 932 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940
+/* 936 */ MCD_OPC_Decode, 174, 1, 2, // Opcode: NOT
+/* 940 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947
+/* 944 */ MCD_OPC_Decode, 112, 2, // Opcode: INT_2r
+/* 947 */ MCD_OPC_Decode, 125, 5, // Opcode: LD8U_3r
+/* 950 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 975
+/* 954 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 957 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 965
+/* 961 */ MCD_OPC_Decode, 173, 1, 2, // Opcode: NEG
+/* 965 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 972
+/* 969 */ MCD_OPC_Decode, 79, 2, // Opcode: ENDIN_2r
+/* 972 */ MCD_OPC_Decode, 19, 3, // Opcode: ADD_2rus
+/* 975 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 983
+/* 979 */ MCD_OPC_Decode, 229, 1, 3, // Opcode: SUB_2rus
+/* 983 */ MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1010
+/* 987 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 990 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 998
+/* 994 */ MCD_OPC_Decode, 169, 1, 2, // Opcode: MKMSK_2r
+/* 998 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1006
+/* 1002 */ MCD_OPC_Decode, 170, 1, 15, // Opcode: MKMSK_rus
+/* 1006 */ MCD_OPC_Decode, 211, 1, 16, // Opcode: SHL_2rus
+/* 1010 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1037
+/* 1014 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 1017 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1025
+/* 1021 */ MCD_OPC_Decode, 181, 1, 4, // Opcode: OUT_2r
+/* 1025 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1033
+/* 1029 */ MCD_OPC_Decode, 179, 1, 7, // Opcode: OUTSHR_2r
+/* 1033 */ MCD_OPC_Decode, 213, 1, 16, // Opcode: SHR_2rus
+/* 1037 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1061
+/* 1041 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 1044 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1051
+/* 1048 */ MCD_OPC_Decode, 113, 2, // Opcode: IN_2r
+/* 1051 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1058
+/* 1055 */ MCD_OPC_Decode, 111, 7, // Opcode: INSHR_2r
+/* 1058 */ MCD_OPC_Decode, 82, 3, // Opcode: EQ_2rus
+/* 1061 */ MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1088
+/* 1065 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 1068 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1076
+/* 1072 */ MCD_OPC_Decode, 182, 1, 2, // Opcode: PEEK_2r
+/* 1076 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1084
+/* 1080 */ MCD_OPC_Decode, 232, 1, 2, // Opcode: TESTCT_2r
+/* 1084 */ MCD_OPC_Decode, 236, 1, 17, // Opcode: TSETR_3r
+/* 1088 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1115
+/* 1092 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 1095 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1103
+/* 1099 */ MCD_OPC_Decode, 198, 1, 4, // Opcode: SETPSC_2r
+/* 1103 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1111
+/* 1107 */ MCD_OPC_Decode, 234, 1, 2, // Opcode: TESTWCT_2r
+/* 1111 */ MCD_OPC_Decode, 163, 1, 5, // Opcode: LSS_3r
+/* 1115 */ MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1140
+/* 1119 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 1122 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1129
+/* 1126 */ MCD_OPC_Decode, 54, 2, // Opcode: CHKCT_2r
+/* 1129 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1136
+/* 1133 */ MCD_OPC_Decode, 55, 15, // Opcode: CHKCT_rus
+/* 1136 */ MCD_OPC_Decode, 165, 1, 5, // Opcode: LSU_3r
+/* 1140 */ MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1161
+/* 1144 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 1147 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1154
+/* 1151 */ MCD_OPC_Decode, 37, 18, // Opcode: BLRF_u10
+/* 1154 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1220
+/* 1158 */ MCD_OPC_Decode, 35, 19, // Opcode: BLRB_u10
+/* 1161 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1184
+/* 1165 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 1168 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1176
+/* 1172 */ MCD_OPC_Decode, 132, 1, 18, // Opcode: LDAPF_u10
+/* 1176 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1220
+/* 1180 */ MCD_OPC_Decode, 129, 1, 19, // Opcode: LDAPB_u10
+/* 1184 */ MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1206
+/* 1188 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ...
+/* 1191 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1198
+/* 1195 */ MCD_OPC_Decode, 30, 18, // Opcode: BLACP_u10
+/* 1198 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1220
+/* 1202 */ MCD_OPC_Decode, 154, 1, 18, // Opcode: LDWCP_u10
+/* 1206 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1220
+/* 1210 */ MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1220
+/* 1216 */ MCD_OPC_Decode, 192, 1, 12, // Opcode: SETC_ru6
+/* 1220 */ MCD_OPC_Fail,
+ 0
+};
+
+static uint8_t DecoderTable32[] = {
+/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96
+/* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 10 */ MCD_OPC_FilterValue, 31, 214, 3, // Skip to: 996
+/* 14 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 17 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31
+/* 21 */ MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45
+/* 28 */ MCD_OPC_Decode, 28, 20, // Opcode: BITREV_l2r
+/* 31 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45
+/* 35 */ MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45
+/* 42 */ MCD_OPC_Decode, 53, 20, // Opcode: BYTEREV_l2r
+/* 45 */ MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56
+/* 52 */ MCD_OPC_Decode, 228, 1, 21, // Opcode: STW_l3r
+/* 56 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ...
+/* 59 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66
+/* 63 */ MCD_OPC_Decode, 63, 22, // Opcode: CRC8_l4r
+/* 66 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74
+/* 70 */ MCD_OPC_Decode, 167, 1, 23, // Opcode: MACCU_l4r
+/* 74 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 77 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85
+/* 81 */ MCD_OPC_Decode, 147, 1, 24, // Opcode: LDIVU_l5r
+/* 85 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92
+/* 89 */ MCD_OPC_Decode, 123, 24, // Opcode: LADD_l5r
+/* 92 */ MCD_OPC_Decode, 162, 1, 25, // Opcode: LMUL_l6r
+/* 96 */ MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186
+/* 100 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 103 */ MCD_OPC_FilterValue, 31, 121, 3, // Skip to: 996
+/* 107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 110 */ MCD_OPC_FilterValue, 0, 114, 3, // Skip to: 996
+/* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 117 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136
+/* 121 */ MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156
+/* 127 */ MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156
+/* 133 */ MCD_OPC_Decode, 62, 20, // Opcode: CLZ_l2r
+/* 136 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156
+/* 140 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156
+/* 146 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156
+/* 152 */ MCD_OPC_Decode, 188, 1, 26, // Opcode: SETCLK_l2r
+/* 156 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172
+/* 162 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172
+/* 168 */ MCD_OPC_Decode, 241, 1, 21, // Opcode: XOR_l3r
+/* 172 */ MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182
+/* 178 */ MCD_OPC_Decode, 166, 1, 23, // Opcode: MACCS_l4r
+/* 182 */ MCD_OPC_Decode, 164, 1, 24, // Opcode: LSUB_l5r
+/* 186 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219
+/* 190 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 193 */ MCD_OPC_FilterValue, 159, 251, 3, 29, 3, // Skip to: 996
+/* 199 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 202 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209
+/* 206 */ MCD_OPC_Decode, 107, 20, // Opcode: INITLR_l2r
+/* 209 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216
+/* 213 */ MCD_OPC_Decode, 98, 20, // Opcode: GETPS_l2r
+/* 216 */ MCD_OPC_Decode, 26, 21, // Opcode: ASHR_l3r
+/* 219 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254
+/* 223 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 226 */ MCD_OPC_FilterValue, 159, 251, 3, 252, 2, // Skip to: 996
+/* 232 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 235 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243
+/* 239 */ MCD_OPC_Decode, 199, 1, 26, // Opcode: SETPS_l2r
+/* 243 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250
+/* 247 */ MCD_OPC_Decode, 91, 20, // Opcode: GETD_l2r
+/* 250 */ MCD_OPC_Decode, 141, 1, 21, // Opcode: LDAWF_l3r
+/* 254 */ MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290
+/* 258 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 261 */ MCD_OPC_FilterValue, 159, 251, 3, 217, 2, // Skip to: 996
+/* 267 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 270 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278
+/* 274 */ MCD_OPC_Decode, 233, 1, 20, // Opcode: TESTLCL_l2r
+/* 278 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286
+/* 282 */ MCD_OPC_Decode, 207, 1, 26, // Opcode: SETTW_l2r
+/* 286 */ MCD_OPC_Decode, 134, 1, 21, // Opcode: LDAWB_l3r
+/* 290 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 325
+/* 294 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 297 */ MCD_OPC_FilterValue, 159, 251, 3, 181, 2, // Skip to: 996
+/* 303 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 306 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314
+/* 310 */ MCD_OPC_Decode, 201, 1, 26, // Opcode: SETRDY_l2r
+/* 314 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322
+/* 318 */ MCD_OPC_Decode, 190, 1, 20, // Opcode: SETC_l2r
+/* 322 */ MCD_OPC_Decode, 127, 21, // Opcode: LDA16F_l3r
+/* 325 */ MCD_OPC_FilterValue, 6, 30, 0, // Skip to: 359
+/* 329 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 332 */ MCD_OPC_FilterValue, 159, 251, 3, 146, 2, // Skip to: 996
+/* 338 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
+/* 341 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 349
+/* 345 */ MCD_OPC_Decode, 197, 1, 26, // Opcode: SETN_l2r
+/* 349 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 356
+/* 353 */ MCD_OPC_Decode, 97, 20, // Opcode: GETN_l2r
+/* 356 */ MCD_OPC_Decode, 126, 21, // Opcode: LDA16B_l3r
+/* 359 */ MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 375
+/* 363 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 996
+/* 371 */ MCD_OPC_Decode, 172, 1, 21, // Opcode: MUL_l3r
+/* 375 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 390
+/* 379 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 996
+/* 387 */ MCD_OPC_Decode, 68, 21, // Opcode: DIVS_l3r
+/* 390 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 405
+/* 394 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 996
+/* 402 */ MCD_OPC_Decode, 69, 21, // Opcode: DIVU_l3r
+/* 405 */ MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 440
+/* 409 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 412 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 426
+/* 416 */ MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 996
+/* 422 */ MCD_OPC_Decode, 222, 1, 27, // Opcode: STWDP_lru6
+/* 426 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 996
+/* 430 */ MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 996
+/* 436 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: STWSP_lru6
+/* 440 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 475
+/* 444 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 447 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 461
+/* 451 */ MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 996
+/* 457 */ MCD_OPC_Decode, 155, 1, 27, // Opcode: LDWDP_lru6
+/* 461 */ MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 996
+/* 465 */ MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 996
+/* 471 */ MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWSP_lru6
+/* 475 */ MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 510
+/* 479 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 482 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 496
+/* 486 */ MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 996
+/* 492 */ MCD_OPC_Decode, 137, 1, 27, // Opcode: LDAWDP_lru6
+/* 496 */ MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 996
+/* 500 */ MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 996
+/* 506 */ MCD_OPC_Decode, 142, 1, 27, // Opcode: LDAWSP_lru6
+/* 510 */ MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 545
+/* 514 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 517 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 531
+/* 521 */ MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 996
+/* 527 */ MCD_OPC_Decode, 144, 1, 27, // Opcode: LDC_lru6
+/* 531 */ MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 996
+/* 535 */ MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 996
+/* 541 */ MCD_OPC_Decode, 151, 1, 27, // Opcode: LDWCP_lru6
+/* 545 */ MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 643
+/* 549 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 552 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 597
+/* 556 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 559 */ MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 996
+/* 563 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 566 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 573
+/* 570 */ MCD_OPC_Decode, 48, 28, // Opcode: BRFU_lu6
+/* 573 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 580
+/* 577 */ MCD_OPC_Decode, 31, 28, // Opcode: BLAT_lu6
+/* 580 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 587
+/* 584 */ MCD_OPC_Decode, 84, 28, // Opcode: EXTDP_lu6
+/* 587 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 594
+/* 591 */ MCD_OPC_Decode, 116, 28, // Opcode: KCALL_lu6
+/* 594 */ MCD_OPC_Decode, 46, 29, // Opcode: BRFT_lru6
+/* 597 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 996
+/* 601 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 604 */ MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 996
+/* 608 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 611 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 618
+/* 615 */ MCD_OPC_Decode, 42, 30, // Opcode: BRBU_lu6
+/* 618 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 625
+/* 622 */ MCD_OPC_Decode, 80, 28, // Opcode: ENTSP_lu6
+/* 625 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 632
+/* 629 */ MCD_OPC_Decode, 86, 28, // Opcode: EXTSP_lu6
+/* 632 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 640
+/* 636 */ MCD_OPC_Decode, 185, 1, 28, // Opcode: RETSP_lu6
+/* 640 */ MCD_OPC_Decode, 40, 31, // Opcode: BRBT_lru6
+/* 643 */ MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 728
+/* 647 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 650 */ MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 696
+/* 654 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 657 */ MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 996
+/* 661 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 664 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 671
+/* 668 */ MCD_OPC_Decode, 60, 28, // Opcode: CLRSR_lu6
+/* 671 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 679
+/* 675 */ MCD_OPC_Decode, 205, 1, 28, // Opcode: SETSR_lu6
+/* 679 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 686
+/* 683 */ MCD_OPC_Decode, 118, 28, // Opcode: KENTSP_lu6
+/* 686 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 693
+/* 690 */ MCD_OPC_Decode, 120, 28, // Opcode: KRESTSP_lu6
+/* 693 */ MCD_OPC_Decode, 44, 29, // Opcode: BRFF_lru6
+/* 696 */ MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 996
+/* 700 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 703 */ MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 996
+/* 707 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 710 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 717
+/* 714 */ MCD_OPC_Decode, 100, 28, // Opcode: GETSR_lu6
+/* 717 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 725
+/* 721 */ MCD_OPC_Decode, 135, 1, 28, // Opcode: LDAWCP_lu6
+/* 725 */ MCD_OPC_Decode, 38, 31, // Opcode: BRBF_lru6
+/* 728 */ MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 744
+/* 732 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 996
+/* 740 */ MCD_OPC_Decode, 216, 1, 21, // Opcode: ST16_l3r
+/* 744 */ MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 760
+/* 748 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 996
+/* 756 */ MCD_OPC_Decode, 217, 1, 21, // Opcode: ST8_l3r
+/* 760 */ MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 795
+/* 764 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ...
+/* 767 */ MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 776
+/* 773 */ MCD_OPC_Decode, 25, 32, // Opcode: ASHR_l2rus
+/* 776 */ MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 786
+/* 782 */ MCD_OPC_Decode, 178, 1, 32, // Opcode: OUTPW_l2rus
+/* 786 */ MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 996
+/* 792 */ MCD_OPC_Decode, 110, 32, // Opcode: INPW_l2rus
+/* 795 */ MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 811
+/* 799 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 996
+/* 807 */ MCD_OPC_Decode, 140, 1, 33, // Opcode: LDAWF_l2rus
+/* 811 */ MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 827
+/* 815 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 996
+/* 823 */ MCD_OPC_Decode, 133, 1, 33, // Opcode: LDAWB_l2rus
+/* 827 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 842
+/* 831 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 996
+/* 839 */ MCD_OPC_Decode, 64, 34, // Opcode: CRC_l3r
+/* 842 */ MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 858
+/* 846 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 996
+/* 854 */ MCD_OPC_Decode, 183, 1, 21, // Opcode: REMS_l3r
+/* 858 */ MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 874
+/* 862 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 996
+/* 870 */ MCD_OPC_Decode, 184, 1, 21, // Opcode: REMU_l3r
+/* 874 */ MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 907
+/* 878 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 881 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 894
+/* 885 */ MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 996
+/* 891 */ MCD_OPC_Decode, 36, 35, // Opcode: BLRF_lu10
+/* 894 */ MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 996
+/* 898 */ MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 996
+/* 904 */ MCD_OPC_Decode, 34, 36, // Opcode: BLRB_lu10
+/* 907 */ MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 942
+/* 911 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 914 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 928
+/* 918 */ MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 996
+/* 924 */ MCD_OPC_Decode, 130, 1, 35, // Opcode: LDAPF_lu10
+/* 928 */ MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 996
+/* 932 */ MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 996
+/* 938 */ MCD_OPC_Decode, 128, 1, 36, // Opcode: LDAPB_lu10
+/* 942 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 976
+/* 946 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ...
+/* 949 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 962
+/* 953 */ MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 996
+/* 959 */ MCD_OPC_Decode, 29, 35, // Opcode: BLACP_lu10
+/* 962 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 996
+/* 966 */ MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 996
+/* 972 */ MCD_OPC_Decode, 152, 1, 35, // Opcode: LDWCP_lu10
+/* 976 */ MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 996
+/* 980 */ MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 996
+/* 986 */ MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 996
+/* 992 */ MCD_OPC_Decode, 191, 1, 29, // Opcode: SETC_lru6
+/* 996 */ MCD_OPC_Fail,
+ 0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
+{
+ return true; //llvm_unreachable("Invalid index!");
+}
+
+#define DecodeToMCInst(fname,fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+ uint64_t Address, void *Decoder) \
+{ \
+ InsnType tmp; \
+ switch (Idx) { \
+ default: \
+ case 0: \
+ return S; \
+ case 1: \
+ tmp = fieldname(insn, 0, 4); \
+ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 2: \
+ if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 3: \
+ if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 4: \
+ if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 5: \
+ if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 6: \
+ if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 7: \
+ if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 8: \
+ if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 9: \
+ if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 10: \
+ tmp = fieldname(insn, 6, 4); \
+ if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 6); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 11: \
+ tmp = fieldname(insn, 0, 6); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 12: \
+ tmp = fieldname(insn, 6, 4); \
+ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 6); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 13: \
+ tmp = fieldname(insn, 0, 6); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 14: \
+ tmp = fieldname(insn, 6, 4); \
+ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 6); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 15: \
+ if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 16: \
+ if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 17: \
+ if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 18: \
+ tmp = fieldname(insn, 0, 10); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 19: \
+ tmp = fieldname(insn, 0, 10); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 20: \
+ if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 21: \
+ if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 22: \
+ if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 23: \
+ if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 24: \
+ if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 25: \
+ if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 26: \
+ if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 27: \
+ tmp = fieldname(insn, 22, 4); \
+ if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 6); \
+ tmp |= (fieldname(insn, 16, 6) << 0); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 28: \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 6); \
+ tmp |= (fieldname(insn, 16, 6) << 0); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 29: \
+ tmp = fieldname(insn, 22, 4); \
+ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 6); \
+ tmp |= (fieldname(insn, 16, 6) << 0); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 30: \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 6); \
+ tmp |= (fieldname(insn, 16, 6) << 0); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 31: \
+ tmp = fieldname(insn, 22, 4); \
+ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 6); \
+ tmp |= (fieldname(insn, 16, 6) << 0); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 32: \
+ if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 33: \
+ if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 34: \
+ if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 35: \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 10); \
+ tmp |= (fieldname(insn, 16, 10) << 0); \
+ MCInst_addOperand(MI, MCOperand_CreateImm(tmp)); \
+ return S; \
+ case 36: \
+ tmp = 0; \
+ tmp |= (fieldname(insn, 0, 10) << 10); \
+ tmp |= (fieldname(insn, 16, 10) << 0); \
+ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ } \
+}
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+{ \
+ uint64_t Bits = getFeatureBits(feature); \
+ uint8_t *Ptr = DecodeTable; \
+ uint32_t CurFieldValue = 0, ExpectedValue; \
+ DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
+ for (;;) { \
+ switch (*Ptr) { \
+ default: \
+ return MCDisassembler_Fail; \
+ case MCD_OPC_ExtractField: { \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ ++Ptr; \
+ CurFieldValue = fieldname(insn, Start, Len); \
+ break; \
+ } \
+ case MCD_OPC_FilterValue: { \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ if (Val != CurFieldValue) \
+ Ptr += NumToSkip; \
+ break; \
+ } \
+ case MCD_OPC_CheckField: { \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ if (ExpectedValue != FieldValue) \
+ Ptr += NumToSkip; \
+ break; \
+ } \
+ case MCD_OPC_CheckPredicate: { \
+ PIdx = decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ Pred = checkDecoderPredicate(PIdx, Bits); \
+ if (!Pred) \
+ Ptr += NumToSkip; \
+ (void)Pred; \
+ break; \
+ } \
+ case MCD_OPC_Decode: { \
+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
+ Ptr += Len; \
+ MCInst_setOpcode(MI, Opc); \
+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
+ } \
+ case MCD_OPC_SoftFail: { \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ Ptr += Len; \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ if (Fail) \
+ S = MCDisassembler_SoftFail; \
+ break; \
+ } \
+ case MCD_OPC_Fail: { \
+ return MCDisassembler_Fail; \
+ } \
+ } \
+ } \
+}
+
+
+FieldFromInstruction(fieldFromInstruction_2, uint16_t)
+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
+FieldFromInstruction(fieldFromInstruction_4, uint32_t)
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
diff --git a/arch/XCore/XCoreGenInstrInfo.inc b/arch/XCore/XCoreGenInstrInfo.inc
new file mode 100644
index 0000000..39159c1
--- /dev/null
+++ b/arch/XCore/XCoreGenInstrInfo.inc
@@ -0,0 +1,264 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Instruction Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+ XCore_PHI = 0,
+ XCore_INLINEASM = 1,
+ XCore_CFI_INSTRUCTION = 2,
+ XCore_EH_LABEL = 3,
+ XCore_GC_LABEL = 4,
+ XCore_KILL = 5,
+ XCore_EXTRACT_SUBREG = 6,
+ XCore_INSERT_SUBREG = 7,
+ XCore_IMPLICIT_DEF = 8,
+ XCore_SUBREG_TO_REG = 9,
+ XCore_COPY_TO_REGCLASS = 10,
+ XCore_DBG_VALUE = 11,
+ XCore_REG_SEQUENCE = 12,
+ XCore_COPY = 13,
+ XCore_BUNDLE = 14,
+ XCore_LIFETIME_START = 15,
+ XCore_LIFETIME_END = 16,
+ XCore_STACKMAP = 17,
+ XCore_PATCHPOINT = 18,
+ XCore_ADD_2rus = 19,
+ XCore_ADD_3r = 20,
+ XCore_ADJCALLSTACKDOWN = 21,
+ XCore_ADJCALLSTACKUP = 22,
+ XCore_ANDNOT_2r = 23,
+ XCore_AND_3r = 24,
+ XCore_ASHR_l2rus = 25,
+ XCore_ASHR_l3r = 26,
+ XCore_BAU_1r = 27,
+ XCore_BITREV_l2r = 28,
+ XCore_BLACP_lu10 = 29,
+ XCore_BLACP_u10 = 30,
+ XCore_BLAT_lu6 = 31,
+ XCore_BLAT_u6 = 32,
+ XCore_BLA_1r = 33,
+ XCore_BLRB_lu10 = 34,
+ XCore_BLRB_u10 = 35,
+ XCore_BLRF_lu10 = 36,
+ XCore_BLRF_u10 = 37,
+ XCore_BRBF_lru6 = 38,
+ XCore_BRBF_ru6 = 39,
+ XCore_BRBT_lru6 = 40,
+ XCore_BRBT_ru6 = 41,
+ XCore_BRBU_lu6 = 42,
+ XCore_BRBU_u6 = 43,
+ XCore_BRFF_lru6 = 44,
+ XCore_BRFF_ru6 = 45,
+ XCore_BRFT_lru6 = 46,
+ XCore_BRFT_ru6 = 47,
+ XCore_BRFU_lu6 = 48,
+ XCore_BRFU_u6 = 49,
+ XCore_BRU_1r = 50,
+ XCore_BR_JT = 51,
+ XCore_BR_JT32 = 52,
+ XCore_BYTEREV_l2r = 53,
+ XCore_CHKCT_2r = 54,
+ XCore_CHKCT_rus = 55,
+ XCore_CLRE_0R = 56,
+ XCore_CLRPT_1R = 57,
+ XCore_CLRSR_branch_lu6 = 58,
+ XCore_CLRSR_branch_u6 = 59,
+ XCore_CLRSR_lu6 = 60,
+ XCore_CLRSR_u6 = 61,
+ XCore_CLZ_l2r = 62,
+ XCore_CRC8_l4r = 63,
+ XCore_CRC_l3r = 64,
+ XCore_DCALL_0R = 65,
+ XCore_DENTSP_0R = 66,
+ XCore_DGETREG_1r = 67,
+ XCore_DIVS_l3r = 68,
+ XCore_DIVU_l3r = 69,
+ XCore_DRESTSP_0R = 70,
+ XCore_DRET_0R = 71,
+ XCore_ECALLF_1r = 72,
+ XCore_ECALLT_1r = 73,
+ XCore_EDU_1r = 74,
+ XCore_EEF_2r = 75,
+ XCore_EET_2r = 76,
+ XCore_EEU_1r = 77,
+ XCore_EH_RETURN = 78,
+ XCore_ENDIN_2r = 79,
+ XCore_ENTSP_lu6 = 80,
+ XCore_ENTSP_u6 = 81,
+ XCore_EQ_2rus = 82,
+ XCore_EQ_3r = 83,
+ XCore_EXTDP_lu6 = 84,
+ XCore_EXTDP_u6 = 85,
+ XCore_EXTSP_lu6 = 86,
+ XCore_EXTSP_u6 = 87,
+ XCore_FRAME_TO_ARGS_OFFSET = 88,
+ XCore_FREER_1r = 89,
+ XCore_FREET_0R = 90,
+ XCore_GETD_l2r = 91,
+ XCore_GETED_0R = 92,
+ XCore_GETET_0R = 93,
+ XCore_GETID_0R = 94,
+ XCore_GETKEP_0R = 95,
+ XCore_GETKSP_0R = 96,
+ XCore_GETN_l2r = 97,
+ XCore_GETPS_l2r = 98,
+ XCore_GETR_rus = 99,
+ XCore_GETSR_lu6 = 100,
+ XCore_GETSR_u6 = 101,
+ XCore_GETST_2r = 102,
+ XCore_GETTS_2r = 103,
+ XCore_INCT_2r = 104,
+ XCore_INITCP_2r = 105,
+ XCore_INITDP_2r = 106,
+ XCore_INITLR_l2r = 107,
+ XCore_INITPC_2r = 108,
+ XCore_INITSP_2r = 109,
+ XCore_INPW_l2rus = 110,
+ XCore_INSHR_2r = 111,
+ XCore_INT_2r = 112,
+ XCore_IN_2r = 113,
+ XCore_Int_MemBarrier = 114,
+ XCore_KCALL_1r = 115,
+ XCore_KCALL_lu6 = 116,
+ XCore_KCALL_u6 = 117,
+ XCore_KENTSP_lu6 = 118,
+ XCore_KENTSP_u6 = 119,
+ XCore_KRESTSP_lu6 = 120,
+ XCore_KRESTSP_u6 = 121,
+ XCore_KRET_0R = 122,
+ XCore_LADD_l5r = 123,
+ XCore_LD16S_3r = 124,
+ XCore_LD8U_3r = 125,
+ XCore_LDA16B_l3r = 126,
+ XCore_LDA16F_l3r = 127,
+ XCore_LDAPB_lu10 = 128,
+ XCore_LDAPB_u10 = 129,
+ XCore_LDAPF_lu10 = 130,
+ XCore_LDAPF_lu10_ba = 131,
+ XCore_LDAPF_u10 = 132,
+ XCore_LDAWB_l2rus = 133,
+ XCore_LDAWB_l3r = 134,
+ XCore_LDAWCP_lu6 = 135,
+ XCore_LDAWCP_u6 = 136,
+ XCore_LDAWDP_lru6 = 137,
+ XCore_LDAWDP_ru6 = 138,
+ XCore_LDAWFI = 139,
+ XCore_LDAWF_l2rus = 140,
+ XCore_LDAWF_l3r = 141,
+ XCore_LDAWSP_lru6 = 142,
+ XCore_LDAWSP_ru6 = 143,
+ XCore_LDC_lru6 = 144,
+ XCore_LDC_ru6 = 145,
+ XCore_LDET_0R = 146,
+ XCore_LDIVU_l5r = 147,
+ XCore_LDSED_0R = 148,
+ XCore_LDSPC_0R = 149,
+ XCore_LDSSR_0R = 150,
+ XCore_LDWCP_lru6 = 151,
+ XCore_LDWCP_lu10 = 152,
+ XCore_LDWCP_ru6 = 153,
+ XCore_LDWCP_u10 = 154,
+ XCore_LDWDP_lru6 = 155,
+ XCore_LDWDP_ru6 = 156,
+ XCore_LDWFI = 157,
+ XCore_LDWSP_lru6 = 158,
+ XCore_LDWSP_ru6 = 159,
+ XCore_LDW_2rus = 160,
+ XCore_LDW_3r = 161,
+ XCore_LMUL_l6r = 162,
+ XCore_LSS_3r = 163,
+ XCore_LSUB_l5r = 164,
+ XCore_LSU_3r = 165,
+ XCore_MACCS_l4r = 166,
+ XCore_MACCU_l4r = 167,
+ XCore_MJOIN_1r = 168,
+ XCore_MKMSK_2r = 169,
+ XCore_MKMSK_rus = 170,
+ XCore_MSYNC_1r = 171,
+ XCore_MUL_l3r = 172,
+ XCore_NEG = 173,
+ XCore_NOT = 174,
+ XCore_OR_3r = 175,
+ XCore_OUTCT_2r = 176,
+ XCore_OUTCT_rus = 177,
+ XCore_OUTPW_l2rus = 178,
+ XCore_OUTSHR_2r = 179,
+ XCore_OUTT_2r = 180,
+ XCore_OUT_2r = 181,
+ XCore_PEEK_2r = 182,
+ XCore_REMS_l3r = 183,
+ XCore_REMU_l3r = 184,
+ XCore_RETSP_lu6 = 185,
+ XCore_RETSP_u6 = 186,
+ XCore_SELECT_CC = 187,
+ XCore_SETCLK_l2r = 188,
+ XCore_SETCP_1r = 189,
+ XCore_SETC_l2r = 190,
+ XCore_SETC_lru6 = 191,
+ XCore_SETC_ru6 = 192,
+ XCore_SETDP_1r = 193,
+ XCore_SETD_2r = 194,
+ XCore_SETEV_1r = 195,
+ XCore_SETKEP_0R = 196,
+ XCore_SETN_l2r = 197,
+ XCore_SETPSC_2r = 198,
+ XCore_SETPS_l2r = 199,
+ XCore_SETPT_2r = 200,
+ XCore_SETRDY_l2r = 201,
+ XCore_SETSP_1r = 202,
+ XCore_SETSR_branch_lu6 = 203,
+ XCore_SETSR_branch_u6 = 204,
+ XCore_SETSR_lu6 = 205,
+ XCore_SETSR_u6 = 206,
+ XCore_SETTW_l2r = 207,
+ XCore_SETV_1r = 208,
+ XCore_SEXT_2r = 209,
+ XCore_SEXT_rus = 210,
+ XCore_SHL_2rus = 211,
+ XCore_SHL_3r = 212,
+ XCore_SHR_2rus = 213,
+ XCore_SHR_3r = 214,
+ XCore_SSYNC_0r = 215,
+ XCore_ST16_l3r = 216,
+ XCore_ST8_l3r = 217,
+ XCore_STET_0R = 218,
+ XCore_STSED_0R = 219,
+ XCore_STSPC_0R = 220,
+ XCore_STSSR_0R = 221,
+ XCore_STWDP_lru6 = 222,
+ XCore_STWDP_ru6 = 223,
+ XCore_STWFI = 224,
+ XCore_STWSP_lru6 = 225,
+ XCore_STWSP_ru6 = 226,
+ XCore_STW_2rus = 227,
+ XCore_STW_l3r = 228,
+ XCore_SUB_2rus = 229,
+ XCore_SUB_3r = 230,
+ XCore_SYNCR_1r = 231,
+ XCore_TESTCT_2r = 232,
+ XCore_TESTLCL_l2r = 233,
+ XCore_TESTWCT_2r = 234,
+ XCore_TSETMR_2r = 235,
+ XCore_TSETR_3r = 236,
+ XCore_TSTART_1R = 237,
+ XCore_WAITEF_1R = 238,
+ XCore_WAITET_1R = 239,
+ XCore_WAITEU_0R = 240,
+ XCore_XOR_l3r = 241,
+ XCore_ZEXT_2r = 242,
+ XCore_ZEXT_rus = 243,
+ XCore_INSTRUCTION_LIST_END = 244
+};
+
+#endif // GET_INSTRINFO_ENUM
diff --git a/arch/XCore/XCoreGenRegisterInfo.inc b/arch/XCore/XCoreGenRegisterInfo.inc
new file mode 100644
index 0000000..cd38d5f
--- /dev/null
+++ b/arch/XCore/XCoreGenRegisterInfo.inc
@@ -0,0 +1,110 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+ XCore_NoRegister,
+ XCore_CP = 1,
+ XCore_DP = 2,
+ XCore_LR = 3,
+ XCore_SP = 4,
+ XCore_R0 = 5,
+ XCore_R1 = 6,
+ XCore_R2 = 7,
+ XCore_R3 = 8,
+ XCore_R4 = 9,
+ XCore_R5 = 10,
+ XCore_R6 = 11,
+ XCore_R7 = 12,
+ XCore_R8 = 13,
+ XCore_R9 = 14,
+ XCore_R10 = 15,
+ XCore_R11 = 16,
+ XCore_NUM_TARGET_REGS // 17
+};
+
+// Register classes
+enum {
+ XCore_RRegsRegClassID = 0,
+ XCore_GRRegsRegClassID = 1
+};
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static MCPhysReg XCoreRegDiffLists[] = {
+ /* 0 */ 65535, 0,
+};
+
+static uint16_t XCoreSubRegIdxLists[] = {
+ /* 0 */ 0,
+};
+
+static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
+ { 3, 0, 0, 0, 0 },
+ { 38, 1, 1, 0, 1 },
+ { 41, 1, 1, 0, 1 },
+ { 47, 1, 1, 0, 1 },
+ { 44, 1, 1, 0, 1 },
+ { 4, 1, 1, 0, 1 },
+ { 11, 1, 1, 0, 1 },
+ { 14, 1, 1, 0, 1 },
+ { 17, 1, 1, 0, 1 },
+ { 20, 1, 1, 0, 1 },
+ { 23, 1, 1, 0, 1 },
+ { 26, 1, 1, 0, 1 },
+ { 29, 1, 1, 0, 1 },
+ { 32, 1, 1, 0, 1 },
+ { 35, 1, 1, 0, 1 },
+ { 0, 1, 1, 0, 1 },
+ { 7, 1, 1, 0, 1 },
+};
+
+ // RRegs Register Class...
+ static MCPhysReg RRegs[] = {
+ XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR,
+ };
+
+ // RRegs Bit set.
+ static uint8_t RRegsBits[] = {
+ 0xfe, 0xff, 0x01,
+ };
+
+ // GRRegs Register Class...
+ static MCPhysReg GRRegs[] = {
+ XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11,
+ };
+
+ // GRRegs Bit set.
+ static uint8_t GRRegsBits[] = {
+ 0xe0, 0xff, 0x01,
+ };
+
+static MCRegisterClass XCoreMCRegisterClasses[] = {
+ { "RRegs", RRegs, RRegsBits, 16, sizeof(RRegsBits), XCore_RRegsRegClassID, 4, 4, 1, 0 },
+ { "GRRegs", GRRegs, GRRegsBits, 12, sizeof(GRRegsBits), XCore_GRRegsRegClassID, 4, 4, 1, 1 },
+};
+
+#endif // GET_REGINFO_MC_DESC
diff --git a/arch/XCore/XCoreInstPrinter.c b/arch/XCore/XCoreInstPrinter.c
new file mode 100644
index 0000000..1f4f704
--- /dev/null
+++ b/arch/XCore/XCoreInstPrinter.c
@@ -0,0 +1,145 @@
+//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an XCore MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "XCoreInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "XCoreMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+ /*
+ if (((cs_struct *)ud)->detail != CS_OPT_ON)
+ return;
+ */
+}
+
+static void set_mem_access(MCInst *MI, bool status, int reg)
+{
+ if (MI->csh->detail != CS_OPT_ON)
+ return;
+
+ MI->csh->doing_mem = status;
+ if (status) {
+ if (reg != 0xffff && reg != -0xffff) {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_MEM;
+ if (reg) {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = reg;
+ } else {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = XCORE_REG_INVALID;
+ }
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
+ } else {
+ // the last op should be the memory base
+ MI->flat_insn.xcore.op_count--;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_MEM;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = XCORE_REG_INVALID;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = 0;
+ if (reg > 0)
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = 1;
+ else
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.direct = -1;
+ }
+ } else {
+ // done, create the next operand slot
+ MI->flat_insn.xcore.op_count++;
+ }
+}
+
+static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
+{
+ if (MCOperand_isReg(MO)) {
+ unsigned reg;
+
+ reg = MCOperand_getReg(MO);
+ SStream_concat(O, "%s", getRegisterName(reg));
+
+ if (MI->csh->detail) {
+ if (MI->csh->doing_mem) {
+ if (MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base == ARM_REG_INVALID)
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.base = reg;
+ else
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.index = reg;
+ } else {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_REG;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].reg = reg;
+ MI->flat_insn.xcore.op_count++;
+ }
+ }
+ } else if (MCOperand_isImm(MO)) {
+ int32_t Imm = (int32_t)MCOperand_getImm(MO);
+
+ if (Imm >= 0) {
+ if (Imm > HEX_THRESHOLD)
+ SStream_concat(O, "0x%x", Imm);
+ else
+ SStream_concat(O, "%u", Imm);
+ } else {
+ if (Imm < -HEX_THRESHOLD)
+ SStream_concat(O, "-0x%x", -Imm);
+ else
+ SStream_concat(O, "-%u", -Imm);
+ }
+
+ if (MI->csh->detail) {
+ if (MI->csh->doing_mem) {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].mem.disp = Imm;
+ } else {
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].type = XCORE_OP_IMM;
+ MI->flat_insn.xcore.operands[MI->flat_insn.xcore.op_count].imm = Imm;
+ MI->flat_insn.xcore.op_count++;
+ }
+ }
+ }
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+ _printOperand(MI, MCInst_getOperand(MI, OpNum), O);
+}
+
+static void printInlineJT(MCInst *MI, int OpNum, SStream *O)
+{
+}
+
+static void printInlineJT32(MCInst *MI, int OpNum, SStream *O)
+{
+}
+
+#define PRINT_ALIAS_INSTR
+#include "XCoreGenAsmWriter.inc"
+
+void XCore_printInst(MCInst *MI, SStream *O, void *Info)
+{
+ printInstruction(MI, O, Info);
+}
+
+#endif
diff --git a/arch/XCore/XCoreInstPrinter.h b/arch/XCore/XCoreInstPrinter.h
new file mode 100644
index 0000000..c78d3f0
--- /dev/null
+++ b/arch/XCore/XCoreInstPrinter.h
@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_XCOREINSTPRINTER_H
+#define CS_XCOREINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void XCore_printInst(MCInst *MI, SStream *O, void *Info);
+
+void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif
diff --git a/arch/XCore/XCoreMapping.c b/arch/XCore/XCoreMapping.c
new file mode 100644
index 0000000..ade5b9e
--- /dev/null
+++ b/arch/XCore/XCoreMapping.c
@@ -0,0 +1,1541 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "XCoreMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+
+#ifndef CAPSTONE_DIET
+static name_map reg_name_maps[] = {
+ { XCORE_REG_INVALID, NULL },
+
+ { XCORE_REG_CP, "cp" },
+ { XCORE_REG_DP, "dp" },
+ { XCORE_REG_LR, "lr" },
+ { XCORE_REG_SP, "sp" },
+ { XCORE_REG_R0, "r0" },
+ { XCORE_REG_R1, "r1" },
+ { XCORE_REG_R2, "r2" },
+ { XCORE_REG_R3, "r3" },
+ { XCORE_REG_R4, "r4" },
+ { XCORE_REG_R5, "r5" },
+ { XCORE_REG_R6, "r6" },
+ { XCORE_REG_R7, "r7" },
+ { XCORE_REG_R8, "r8" },
+ { XCORE_REG_R9, "r9" },
+ { XCORE_REG_R10, "r10" },
+ { XCORE_REG_R11, "r11" },
+};
+#endif
+
+const char *XCore_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+ if (reg >= XCORE_REG_MAX)
+ return NULL;
+
+ return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
+}
+
+static insn_map insns[] = {
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+
+ {
+ XCore_ADD_2rus, XCORE_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ADD_3r, XCORE_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ANDNOT_2r, XCORE_INS_ANDNOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_AND_3r, XCORE_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ASHR_l2rus, XCORE_INS_ASHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ASHR_l3r, XCORE_INS_ASHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BAU_1r, XCORE_INS_BAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_BITREV_l2r, XCORE_INS_BITREV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLACP_lu10, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLACP_u10, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLAT_lu6, XCORE_INS_BLAT,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLAT_u6, XCORE_INS_BLAT,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLA_1r, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLRB_lu10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLRB_u10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLRF_lu10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BLRF_u10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_BRBF_lru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRBF_ru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRBT_lru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRBT_ru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRBU_lu6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRBU_u6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFF_lru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFF_ru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFT_lru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFT_ru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFU_lu6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRFU_u6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ XCore_BRU_1r, XCORE_INS_BRU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_BYTEREV_l2r, XCORE_INS_BYTEREV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CHKCT_2r, XCORE_INS_CHKCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CHKCT_rus, XCORE_INS_CHKCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CLRE_0R, XCORE_INS_CLRE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CLRPT_1R, XCORE_INS_CLRPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CLRSR_branch_lu6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_CLRSR_branch_u6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_CLRSR_lu6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CLRSR_u6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CLZ_l2r, XCORE_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CRC8_l4r, XCORE_INS_CRC8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_CRC_l3r, XCORE_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DCALL_0R, XCORE_INS_DCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DENTSP_0R, XCORE_INS_DENTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DGETREG_1r, XCORE_INS_DGETREG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DIVS_l3r, XCORE_INS_DIVS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DIVU_l3r, XCORE_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DRESTSP_0R, XCORE_INS_DRESTSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_DRET_0R, XCORE_INS_DRET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ECALLF_1r, XCORE_INS_ECALLF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ECALLT_1r, XCORE_INS_ECALLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EDU_1r, XCORE_INS_EDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EEF_2r, XCORE_INS_EEF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EET_2r, XCORE_INS_EET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EEU_1r, XCORE_INS_EEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ENDIN_2r, XCORE_INS_ENDIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ENTSP_lu6, XCORE_INS_ENTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ENTSP_u6, XCORE_INS_ENTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EQ_2rus, XCORE_INS_EQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EQ_3r, XCORE_INS_EQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EXTDP_lu6, XCORE_INS_EXTDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EXTDP_u6, XCORE_INS_EXTDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EXTSP_lu6, XCORE_INS_EXTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_EXTSP_u6, XCORE_INS_EXTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_FREER_1r, XCORE_INS_FREER,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_FREET_0R, XCORE_INS_FREET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETD_l2r, XCORE_INS_GETD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETED_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETET_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETID_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETKEP_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETKSP_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETN_l2r, XCORE_INS_GETN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETPS_l2r, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETR_rus, XCORE_INS_GETR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETSR_lu6, XCORE_INS_GETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETSR_u6, XCORE_INS_GETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETST_2r, XCORE_INS_GETST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_GETTS_2r, XCORE_INS_GETTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INCT_2r, XCORE_INS_INCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INITCP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INITDP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INITLR_l2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INITPC_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INITSP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INPW_l2rus, XCORE_INS_INPW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INSHR_2r, XCORE_INS_INSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_INT_2r, XCORE_INS_INT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_IN_2r, XCORE_INS_IN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KCALL_1r, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KCALL_lu6, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KCALL_u6, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KENTSP_lu6, XCORE_INS_KENTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KENTSP_u6, XCORE_INS_KENTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KRESTSP_lu6, XCORE_INS_KRESTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KRESTSP_u6, XCORE_INS_KRESTSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_KRET_0R, XCORE_INS_KRET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LADD_l5r, XCORE_INS_LADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LD16S_3r, XCORE_INS_LD16S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LD8U_3r, XCORE_INS_LD8U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDA16B_l3r, XCORE_INS_LDA16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDA16F_l3r, XCORE_INS_LDA16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAPB_lu10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAPB_u10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAPF_lu10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAPF_lu10_ba, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAPF_u10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWB_l2rus, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWB_l3r, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWCP_lu6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWCP_u6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWDP_lru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWDP_ru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWF_l2rus, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWF_l3r, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWSP_lru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDAWSP_ru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDC_lru6, XCORE_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDC_ru6, XCORE_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDET_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDIVU_l5r, XCORE_INS_LDIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDSED_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDSPC_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDSSR_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWCP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWCP_lu10, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWCP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWCP_u10, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWDP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWDP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWSP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDWSP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDW_2rus, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LDW_3r, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LMUL_l6r, XCORE_INS_LMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LSS_3r, XCORE_INS_LSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LSUB_l5r, XCORE_INS_LSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_LSU_3r, XCORE_INS_LSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MACCS_l4r, XCORE_INS_MACCS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MACCU_l4r, XCORE_INS_MACCU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MJOIN_1r, XCORE_INS_MJOIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MKMSK_2r, XCORE_INS_MKMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MKMSK_rus, XCORE_INS_MKMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MSYNC_1r, XCORE_INS_MSYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_MUL_l3r, XCORE_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_NEG, XCORE_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_NOT, XCORE_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OR_3r, XCORE_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUTCT_2r, XCORE_INS_OUTCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUTCT_rus, XCORE_INS_OUTCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUTPW_l2rus, XCORE_INS_OUTPW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUTSHR_2r, XCORE_INS_OUTSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUTT_2r, XCORE_INS_OUTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_OUT_2r, XCORE_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_PEEK_2r, XCORE_INS_PEEK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_REMS_l3r, XCORE_INS_REMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_REMU_l3r, XCORE_INS_REMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_RETSP_lu6, XCORE_INS_RETSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_RETSP_u6, XCORE_INS_RETSP,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETCLK_l2r, XCORE_INS_SETCLK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETCP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETC_l2r, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETC_lru6, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETC_ru6, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETDP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETD_2r, XCORE_INS_SETD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETEV_1r, XCORE_INS_SETEV,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETKEP_0R, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETN_l2r, XCORE_INS_SETN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETPSC_2r, XCORE_INS_SETPSC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETPS_l2r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETPT_2r, XCORE_INS_SETPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETRDY_l2r, XCORE_INS_SETRDY,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETSP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETSR_branch_lu6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_SETSR_branch_u6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_SETSR_lu6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETSR_u6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETTW_l2r, XCORE_INS_SETTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SETV_1r, XCORE_INS_SETV,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SEXT_2r, XCORE_INS_SEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SEXT_rus, XCORE_INS_SEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SHL_2rus, XCORE_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SHL_3r, XCORE_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SHR_2rus, XCORE_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SHR_3r, XCORE_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SSYNC_0r, XCORE_INS_SSYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ST16_l3r, XCORE_INS_ST16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ST8_l3r, XCORE_INS_ST8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STET_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STSED_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STSPC_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STSSR_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STWDP_lru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STWDP_ru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STWSP_lru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STWSP_ru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STW_2rus, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_STW_l3r, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SUB_2rus, XCORE_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SUB_3r, XCORE_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_SYNCR_1r, XCORE_INS_SYNCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TESTCT_2r, XCORE_INS_TESTCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TESTLCL_l2r, XCORE_INS_TESTLCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TESTWCT_2r, XCORE_INS_TESTWCT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TSETMR_2r, XCORE_INS_TSETMR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TSETR_3r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_TSTART_1R, XCORE_INS_START,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_WAITEF_1R, XCORE_INS_WAITEF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_WAITET_1R, XCORE_INS_WAITET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_WAITEU_0R, XCORE_INS_WAITEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ XCore_XOR_l3r, XCORE_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ZEXT_2r, XCORE_INS_ZEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ XCore_ZEXT_rus, XCORE_INS_ZEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+};
+
+// given internal insn id, return public instruction info
+void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+ unsigned short i;
+
+ i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+ if (i != 0) {
+ insn->id = insns[i].mapid;
+
+ if (h->detail) {
+#ifndef CAPSTONE_DIET
+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
+
+ if (insns[i].branch || insns[i].indirect_branch) {
+ // this insn also belongs to JUMP group. add JUMP group
+ insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP;
+ insn->detail->groups_count++;
+ }
+#endif
+ }
+ }
+}
+
+#ifndef CAPSTONE_DIET
+static name_map insn_name_maps[] = {
+ { XCORE_INS_INVALID, NULL },
+
+ { XCORE_INS_ADD, "add" },
+ { XCORE_INS_ANDNOT, "andnot" },
+ { XCORE_INS_AND, "and" },
+ { XCORE_INS_ASHR, "ashr" },
+ { XCORE_INS_BAU, "bau" },
+ { XCORE_INS_BITREV, "bitrev" },
+ { XCORE_INS_BLA, "bla" },
+ { XCORE_INS_BLAT, "blat" },
+ { XCORE_INS_BL, "bl" },
+ { XCORE_INS_BF, "bf" },
+ { XCORE_INS_BT, "bt" },
+ { XCORE_INS_BU, "bu" },
+ { XCORE_INS_BRU, "bru" },
+ { XCORE_INS_BYTEREV, "byterev" },
+ { XCORE_INS_CHKCT, "chkct" },
+ { XCORE_INS_CLRE, "clre" },
+ { XCORE_INS_CLRPT, "clrpt" },
+ { XCORE_INS_CLRSR, "clrsr" },
+ { XCORE_INS_CLZ, "clz" },
+ { XCORE_INS_CRC8, "crc8" },
+ { XCORE_INS_CRC32, "crc32" },
+ { XCORE_INS_DCALL, "dcall" },
+ { XCORE_INS_DENTSP, "dentsp" },
+ { XCORE_INS_DGETREG, "dgetreg" },
+ { XCORE_INS_DIVS, "divs" },
+ { XCORE_INS_DIVU, "divu" },
+ { XCORE_INS_DRESTSP, "drestsp" },
+ { XCORE_INS_DRET, "dret" },
+ { XCORE_INS_ECALLF, "ecallf" },
+ { XCORE_INS_ECALLT, "ecallt" },
+ { XCORE_INS_EDU, "edu" },
+ { XCORE_INS_EEF, "eef" },
+ { XCORE_INS_EET, "eet" },
+ { XCORE_INS_EEU, "eeu" },
+ { XCORE_INS_ENDIN, "endin" },
+ { XCORE_INS_ENTSP, "entsp" },
+ { XCORE_INS_EQ, "eq" },
+ { XCORE_INS_EXTDP, "extdp" },
+ { XCORE_INS_EXTSP, "extsp" },
+ { XCORE_INS_FREER, "freer" },
+ { XCORE_INS_FREET, "freet" },
+ { XCORE_INS_GETD, "getd" },
+ { XCORE_INS_GET, "get" },
+ { XCORE_INS_GETN, "getn" },
+ { XCORE_INS_GETR, "getr" },
+ { XCORE_INS_GETSR, "getsr" },
+ { XCORE_INS_GETST, "getst" },
+ { XCORE_INS_GETTS, "getts" },
+ { XCORE_INS_INCT, "inct" },
+ { XCORE_INS_INIT, "init" },
+ { XCORE_INS_INPW, "inpw" },
+ { XCORE_INS_INSHR, "inshr" },
+ { XCORE_INS_INT, "int" },
+ { XCORE_INS_IN, "in" },
+ { XCORE_INS_KCALL, "kcall" },
+ { XCORE_INS_KENTSP, "kentsp" },
+ { XCORE_INS_KRESTSP, "krestsp" },
+ { XCORE_INS_KRET, "kret" },
+ { XCORE_INS_LADD, "ladd" },
+ { XCORE_INS_LD16S, "ld16s" },
+ { XCORE_INS_LD8U, "ld8u" },
+ { XCORE_INS_LDA16, "lda16" },
+ { XCORE_INS_LDAP, "ldap" },
+ { XCORE_INS_LDAW, "ldaw" },
+ { XCORE_INS_LDC, "ldc" },
+ { XCORE_INS_LDW, "ldw" },
+ { XCORE_INS_LDIVU, "ldivu" },
+ { XCORE_INS_LMUL, "lmul" },
+ { XCORE_INS_LSS, "lss" },
+ { XCORE_INS_LSUB, "lsub" },
+ { XCORE_INS_LSU, "lsu" },
+ { XCORE_INS_MACCS, "maccs" },
+ { XCORE_INS_MACCU, "maccu" },
+ { XCORE_INS_MJOIN, "mjoin" },
+ { XCORE_INS_MKMSK, "mkmsk" },
+ { XCORE_INS_MSYNC, "msync" },
+ { XCORE_INS_MUL, "mul" },
+ { XCORE_INS_NEG, "neg" },
+ { XCORE_INS_NOT, "not" },
+ { XCORE_INS_OR, "or" },
+ { XCORE_INS_OUTCT, "outct" },
+ { XCORE_INS_OUTPW, "outpw" },
+ { XCORE_INS_OUTSHR, "outshr" },
+ { XCORE_INS_OUTT, "outt" },
+ { XCORE_INS_OUT, "out" },
+ { XCORE_INS_PEEK, "peek" },
+ { XCORE_INS_REMS, "rems" },
+ { XCORE_INS_REMU, "remu" },
+ { XCORE_INS_RETSP, "retsp" },
+ { XCORE_INS_SETCLK, "setclk" },
+ { XCORE_INS_SET, "set" },
+ { XCORE_INS_SETC, "setc" },
+ { XCORE_INS_SETD, "setd" },
+ { XCORE_INS_SETEV, "setev" },
+ { XCORE_INS_SETN, "setn" },
+ { XCORE_INS_SETPSC, "setpsc" },
+ { XCORE_INS_SETPT, "setpt" },
+ { XCORE_INS_SETRDY, "setrdy" },
+ { XCORE_INS_SETSR, "setsr" },
+ { XCORE_INS_SETTW, "settw" },
+ { XCORE_INS_SETV, "setv" },
+ { XCORE_INS_SEXT, "sext" },
+ { XCORE_INS_SHL, "shl" },
+ { XCORE_INS_SHR, "shr" },
+ { XCORE_INS_SSYNC, "ssync" },
+ { XCORE_INS_ST16, "st16" },
+ { XCORE_INS_ST8, "st8" },
+ { XCORE_INS_STW, "stw" },
+ { XCORE_INS_SUB, "sub" },
+ { XCORE_INS_SYNCR, "syncr" },
+ { XCORE_INS_TESTCT, "testct" },
+ { XCORE_INS_TESTLCL, "testlcl" },
+ { XCORE_INS_TESTWCT, "testwct" },
+ { XCORE_INS_TSETMR, "tsetmr" },
+ { XCORE_INS_START, "start" },
+ { XCORE_INS_WAITEF, "waitef" },
+ { XCORE_INS_WAITET, "waitet" },
+ { XCORE_INS_WAITEU, "waiteu" },
+ { XCORE_INS_XOR, "xor" },
+ { XCORE_INS_ZEXT, "zext" },
+};
+
+// special alias insn
+static name_map alias_insn_names[] = {
+ { 0, NULL }
+};
+#endif
+
+const char *XCore_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+ unsigned int i;
+
+ if (id >= XCORE_INS_MAX)
+ return NULL;
+
+ // handle special alias first
+ for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+ if (alias_insn_names[i].id == id)
+ return alias_insn_names[i].name;
+ }
+
+ return insn_name_maps[id].name;
+#else
+ return NULL;
+#endif
+}
+
+// map internal raw register to 'public' register
+xcore_reg XCore_map_register(unsigned int r)
+{
+ static unsigned int map[] = { 0,
+ };
+
+ if (r < ARR_SIZE(map))
+ return map[r];
+
+ // cannot find this register
+ return 0;
+}
+
+#endif
diff --git a/arch/XCore/XCoreMapping.h b/arch/XCore/XCoreMapping.h
new file mode 100644
index 0000000..a21840f
--- /dev/null
+++ b/arch/XCore/XCoreMapping.h
@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_XCORE_MAP_H
+#define CS_XCORE_MAP_H
+
+#include "../../include/capstone.h"
+
+// return name of regiser in friendly string
+const char *XCore_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *XCore_insn_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+xcore_reg XCore_map_register(unsigned int r);
+
+#endif
+
diff --git a/arch/XCore/XCoreModule.c b/arch/XCore/XCoreModule.c
new file mode 100644
index 0000000..9ab4e26
--- /dev/null
+++ b/arch/XCore/XCoreModule.c
@@ -0,0 +1,51 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "XCoreDisassembler.h"
+#include "XCoreInstPrinter.h"
+#include "XCoreMapping.h"
+
+static cs_err init(cs_struct *ud)
+{
+ MCRegisterInfo *mri;
+
+ mri = cs_mem_malloc(sizeof(*mri));
+
+ XCore_init(mri);
+ ud->printer = XCore_printInst;
+ ud->printer_info = mri;
+ ud->getinsn_info = mri;
+ ud->disasm = XCore_getInstruction;
+ ud->post_printer = XCore_post_printer;
+
+ ud->reg_name = XCore_reg_name;
+ ud->insn_id = XCore_get_insn_id;
+ ud->insn_name = XCore_insn_name;
+
+ return CS_ERR_OK;
+}
+
+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+ return CS_ERR_OK;
+}
+
+static void destroy(cs_struct *handle)
+{
+}
+
+void XCore_enable(void)
+{
+ arch_init[CS_ARCH_XCORE] = init;
+ arch_option[CS_ARCH_XCORE] = option;
+ arch_destroy[CS_ARCH_XCORE] = destroy;
+
+ // support this arch
+ all_arch |= (1 << CS_ARCH_XCORE);
+}
+
+#endif
diff --git a/bindings/Makefile b/bindings/Makefile
index 89f8218..a597c8d 100644
--- a/bindings/Makefile
+++ b/bindings/Makefile
@@ -10,6 +10,7 @@
TEST_SPARC = $(TMPDIR)/test_sparc
TEST_SYSZ = $(TMPDIR)/test_systemz
TEST_X86 = $(TMPDIR)/test_x86
+TEST_XCORE = $(TMPDIR)/test_xcore
.PHONY: all expected python java ocaml
@@ -33,6 +34,7 @@
../tests/test_sparc > $(TEST_SPARC)_e
../tests/test_systemz > $(TEST_SYSZ)_e
../tests/test_x86 > $(TEST_X86)_e
+ ../tests/test_xcore > $(TEST_XCORE)_e
python: FORCE
cd python && $(MAKE)
@@ -44,6 +46,7 @@
python python/test_sparc.py > $(TEST_SPARC)_o
python python/test_systemz.py > $(TEST_SYSZ)_o
python python/test_x86.py > $(TEST_X86)_o
+ python python/test_xcore.py > $(TEST_XCORE)_o
$(MAKE) test_diff
java: FORCE
@@ -56,6 +59,7 @@
cd java && ./run.sh sparc > $(TEST_SPARC)_o
cd java && ./run.sh systemz > $(TEST_SYSZ)_o
cd java && ./run.sh x86 > $(TEST_X86)_o
+ cd java && ./run.sh xcore > $(TEST_XCORE)_o
$(MAKE) test_diff
ocaml: FORCE
@@ -69,6 +73,7 @@
$(DIFF) $(TEST_SPARC)_e $(TEST_SPARC)_o
$(DIFF) $(TEST_SYSZ)_e $(TEST_SYSZ)_o
$(DIFF) $(TEST_X86)_e $(TEST_X86)_o
+ $(DIFF) $(TEST_XCORE)_e $(TEST_XCORE)_o
clean:
rm -rf $(TMPDIR)
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index bfd0538..db6c9f8 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -5,7 +5,7 @@
INCL_DIR = '../include/'
-include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h' ]
+include = [ 'arm.h', 'arm64.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h' ]
template = {
'java': {
@@ -21,6 +21,7 @@
'ppc.h': 'Ppc',
'sparc.h': 'Sparc',
'systemz.h': 'Sysz',
+ 'xcore.h': 'Xcore',
'comment_open': '\t//',
'comment_close': '',
},
@@ -37,6 +38,7 @@
'ppc.h': 'ppc',
'sparc.h': 'sparc',
'systemz.h': 'sysz',
+ 'xcore.h': 'xcore',
'comment_open': '#',
'comment_close': '',
}
diff --git a/bindings/python/Makefile b/bindings/python/Makefile
index 39f6641..aebcef6 100644
--- a/bindings/python/Makefile
+++ b/bindings/python/Makefile
@@ -39,6 +39,8 @@
cp capstone/sysz_const.py $(OBJDIR)/pyx/sysz_const.pyx
cp capstone/x86.py $(OBJDIR)/pyx/x86.pyx
cp capstone/x86_const.py $(OBJDIR)/pyx/x86_const.pyx
+ cp capstone/xcore.py $(OBJDIR)/pyx/xcore.pyx
+ cp capstone/xcore_const.py $(OBJDIR)/pyx/xcore_const.pyx
cd $(OBJDIR) && python setup_cython.py build -b ./tmp install
clean:
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 91fae6f..41c7dc6 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -3,7 +3,7 @@
_python2 = sys.version_info.major < 3
if _python2:
range = xrange
-from capstone import arm, arm64, mips, ppc, sparc, systemz, x86
+from capstone import arm, arm64, mips, ppc, sparc, systemz, x86, xcore
__all__ = [
'Cs',
@@ -26,6 +26,7 @@
'CS_ARCH_PPC',
'CS_ARCH_SPARC',
'CS_ARCH_SYSZ',
+ 'CS_ARCH_XCORE',
'CS_ARCH_ALL',
'CS_MODE_LITTLE_ENDIAN',
@@ -84,7 +85,8 @@
CS_ARCH_PPC = 4
CS_ARCH_SPARC = 5
CS_ARCH_SYSZ = 6
-CS_ARCH_MAX = 7
+CS_ARCH_XCORE = 7
+CS_ARCH_MAX = 8
CS_ARCH_ALL = 0xFFFF
# disasm mode
@@ -194,6 +196,7 @@
('ppc', ppc.CsPpc),
('sparc', sparc.CsSparc),
('sysz', systemz.CsSysz),
+ ('xcore', xcore.CsXcore),
)
class _cs_detail(ctypes.Structure):
@@ -473,6 +476,8 @@
(self.cc, self.hint, self.operands) = sparc.get_arch_info(detail.arch.sparc)
elif arch == CS_ARCH_SYSZ:
(self.cc, self.operands) = systemz.get_arch_info(detail.arch.sysz)
+ elif arch == CS_ARCH_XCORE:
+ (self.operands) = xcore.get_arch_info(detail.arch.xcore)
def __getattr__(self, name):
@@ -790,7 +795,7 @@
archs = { "arm": CS_ARCH_ARM, "arm64": CS_ARCH_ARM64, \
"mips": CS_ARCH_MIPS, "ppc": CS_ARCH_PPC, "sparc": CS_ARCH_SPARC, \
- "sysz": CS_ARCH_SYSZ }
+ "sysz": CS_ARCH_SYSZ, 'xcore': CS_ARCH_XCORE }
all_archs = ""
keys = archs.keys()
diff --git a/bindings/python/capstone/capstone.py b/bindings/python/capstone/capstone.py
deleted file mode 100644
index 973e0e1..0000000
--- a/bindings/python/capstone/capstone.py
+++ /dev/null
@@ -1,793 +0,0 @@
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-import arm, arm64, mips, ppc, sparc, systemz, x86
-
-__all__ = [
- 'Cs',
- 'CsInsn',
-
- 'cs_disasm_quick',
- 'cs_version',
- 'cs_support',
- 'version_bind',
- 'debug',
-
- 'CS_API_MAJOR',
- 'CS_API_MINOR',
-
- 'CS_ARCH_ARM',
- 'CS_ARCH_ARM64',
- 'CS_ARCH_MIPS',
- 'CS_ARCH_X86',
- 'CS_ARCH_PPC',
- 'CS_ARCH_SPARC',
- 'CS_ARCH_SYSZ',
- 'CS_ARCH_ALL',
-
- 'CS_MODE_LITTLE_ENDIAN',
- 'CS_MODE_BIG_ENDIAN',
- 'CS_MODE_16',
- 'CS_MODE_32',
- 'CS_MODE_64',
- 'CS_MODE_ARM',
- 'CS_MODE_THUMB',
- 'CS_MODE_MICRO',
- 'CS_MODE_N64',
-
- 'CS_OPT_SYNTAX',
- 'CS_OPT_SYNTAX_DEFAULT',
- 'CS_OPT_SYNTAX_INTEL',
- 'CS_OPT_SYNTAX_ATT',
- 'CS_OPT_SYNTAX_NOREGNAME',
-
- 'CS_OPT_DETAIL',
- 'CS_OPT_MODE',
- 'CS_OPT_ON',
- 'CS_OPT_OFF',
-
- 'CS_ERR_OK',
- 'CS_ERR_MEM',
- 'CS_ERR_ARCH',
- 'CS_ERR_HANDLE',
- 'CS_ERR_CSH',
- 'CS_ERR_MODE',
- 'CS_ERR_OPTION',
- 'CS_ERR_DETAIL',
- 'CS_ERR_VERSION',
- 'CS_ERR_MEMSETUP',
- 'CS_ERR_DIET',
- 'CS_ERR_SKIPDATA',
-
- 'CS_SUPPORT_DIET',
- 'CS_SUPPORT_X86_REDUCE',
-
- 'CS_SKIPDATA_CALLBACK'
-]
-
-# Capstone C interface
-
-# API version
-CS_API_MAJOR = 2
-CS_API_MINOR = 2
-
-# architectures
-CS_ARCH_ARM = 0
-CS_ARCH_ARM64 = 1
-CS_ARCH_MIPS = 2
-CS_ARCH_X86 = 3
-CS_ARCH_PPC = 4
-CS_ARCH_SPARC = 5
-CS_ARCH_SYSZ = 6
-CS_ARCH_MAX = 7
-CS_ARCH_ALL = 0xFFFF
-
-# disasm mode
-CS_MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
-CS_MODE_ARM = 0 # ARM mode
-CS_MODE_16 = (1 << 1) # 16-bit mode (for X86, Mips)
-CS_MODE_32 = (1 << 2) # 32-bit mode (for X86, Mips)
-CS_MODE_64 = (1 << 3) # 64-bit mode (for X86, Mips)
-CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
-CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
-CS_MODE_N64 = (1 << 5) # Nintendo-64 mode (MIPS architecture)
-CS_MODE_V9 = (1 << 4) # Nintendo-64 mode (MIPS architecture)
-CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
-
-# Capstone option type
-CS_OPT_SYNTAX = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)
-CS_OPT_DETAIL = 2 # Break down instruction structure into details
-CS_OPT_MODE = 3 # Change engine's mode at run-time
-CS_OPT_MEM = 4 # Change engine's mode at run-time
-CS_OPT_SKIPDATA = 5 # Skip data when disassembling
-CS_OPT_SKIPDATA_SETUP = 6 # Setup user-defined function for SKIPDATA option
-
-# Capstone option value
-CS_OPT_OFF = 0 # Turn OFF an option - default option of CS_OPT_DETAIL
-CS_OPT_ON = 3 # Turn ON an option (CS_OPT_DETAIL)
-
-# Capstone syntax value
-CS_OPT_SYNTAX_DEFAULT = 0 # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
-CS_OPT_SYNTAX_INTEL = 1 # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_SYNTAX_ATT = 2 # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_SYNTAX_NOREGNAME = 3 # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC)
-
-# Capstone error type
-CS_ERR_OK = 0 # No error: everything was fine
-CS_ERR_MEM = 1 # Out-Of-Memory error: cs_open(), cs_disasm_ex()
-CS_ERR_ARCH = 2 # Unsupported architecture: cs_open()
-CS_ERR_HANDLE = 3 # Invalid handle: cs_op_count(), cs_op_index()
-CS_ERR_CSH = 4 # Invalid csh argument: cs_close(), cs_errno(), cs_option()
-CS_ERR_MODE = 5 # Invalid/unsupported mode: cs_open()
-CS_ERR_OPTION = 6 # Invalid/unsupported option: cs_option()
-CS_ERR_DETAIL = 7 # Invalid/unsupported option: cs_option()
-CS_ERR_MEMSETUP = 8
-CS_ERR_VERSION = 9 # Unsupported version (bindings)
-CS_ERR_DIET = 10 # Information irrelevant in diet engine
-CS_ERR_SKIPDATA = 11 # Access irrelevant data for "data" instruction in SKIPDATA mode
-
-# query id for cs_support()
-CS_SUPPORT_DIET = CS_ARCH_ALL+1
-CS_SUPPORT_X86_REDUCE = CS_ARCH_ALL+2
-
-import ctypes, ctypes.util, sys
-from os.path import split, join, dirname
-import distutils.sysconfig
-
-
-import inspect
-if not hasattr(sys.modules[__name__], '__file__'):
- __file__ = inspect.getfile(inspect.currentframe())
-
-_lib_path = split(__file__)[0]
-_all_libs = ['libcapstone.dll', 'libcapstone.so', 'libcapstone.dylib']
-_found = False
-
-for _lib in _all_libs:
- try:
- _lib_file = join(_lib_path, _lib)
- # print "Trying to load:", _lib_file
- _cs = ctypes.cdll.LoadLibrary(_lib_file)
- _found = True
- break
- except OSError:
- pass
-if _found == False:
- # try loading from default paths
- for _lib in _all_libs:
- try:
- _cs = ctypes.cdll.LoadLibrary(_lib)
- _found = True
- break
- except OSError:
- pass
-
-if _found == False:
- # last try: loading from python lib directory
- _lib_path = distutils.sysconfig.get_python_lib()
- for _lib in _all_libs:
- try:
- _lib_file = join(_lib_path, 'capstone', _lib)
- # print "Trying to load:", _lib_file
- _cs = ctypes.cdll.LoadLibrary(_lib_file)
- _found = True
- break
- except OSError:
- pass
- if _found == False:
- raise ImportError("ERROR: fail to load the dynamic library.")
-
-
-# low-level structure for C code
-class _cs_arch(ctypes.Union):
- _fields_ = (
- ('arm64', arm64.CsArm64),
- ('arm', arm.CsArm),
- ('mips', mips.CsMips),
- ('x86', x86.CsX86),
- ('ppc', ppc.CsPpc),
- ('sparc', sparc.CsSparc),
- ('sysz', systemz.CsSysz),
- )
-
-class _cs_detail(ctypes.Structure):
- _fields_ = (
- ('regs_read', ctypes.c_ubyte * 12),
- ('regs_read_count', ctypes.c_ubyte),
- ('regs_write', ctypes.c_ubyte * 20),
- ('regs_write_count', ctypes.c_ubyte),
- ('groups', ctypes.c_ubyte * 8),
- ('groups_count', ctypes.c_ubyte),
- ('arch', _cs_arch),
- )
-
-class _cs_insn(ctypes.Structure):
- _fields_ = (
- ('id', ctypes.c_uint),
- ('address', ctypes.c_uint64),
- ('size', ctypes.c_uint16),
- ('bytes', ctypes.c_ubyte * 16),
- ('mnemonic', ctypes.c_char * 32),
- ('op_str', ctypes.c_char * 160),
- ('detail', ctypes.POINTER(_cs_detail)),
- )
-
-# callback for SKIPDATA option
-CS_SKIPDATA_CALLBACK = ctypes.CFUNCTYPE(ctypes.c_size_t, ctypes.c_size_t, ctypes.c_void_p)
-
-class _cs_opt_skipdata(ctypes.Structure):
- _fields_ = (
- ('mnemonic', ctypes.c_char_p),
- ('callback', CS_SKIPDATA_CALLBACK),
- ('user_data', ctypes.c_void_p),
- )
-
-# setup all the function prototype
-def _setup_prototype(lib, fname, restype, *argtypes):
- getattr(lib, fname).restype = restype
- getattr(lib, fname).argtypes = argtypes
-
-_setup_prototype(_cs, "cs_open", ctypes.c_int, ctypes.c_uint, ctypes.c_uint, ctypes.POINTER(ctypes.c_size_t))
-_setup_prototype(_cs, "cs_disasm_ex", ctypes.c_size_t, ctypes.c_size_t, ctypes.POINTER(ctypes.c_char), ctypes.c_size_t, \
- ctypes.c_uint64, ctypes.c_size_t, ctypes.POINTER(ctypes.POINTER(_cs_insn)))
-_setup_prototype(_cs, "cs_free", None, ctypes.c_void_p, ctypes.c_size_t)
-_setup_prototype(_cs, "cs_close", ctypes.c_int, ctypes.POINTER(ctypes.c_size_t))
-_setup_prototype(_cs, "cs_reg_name", ctypes.c_char_p, ctypes.c_size_t, ctypes.c_uint)
-_setup_prototype(_cs, "cs_insn_name", ctypes.c_char_p, ctypes.c_size_t, ctypes.c_uint)
-_setup_prototype(_cs, "cs_op_count", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint)
-_setup_prototype(_cs, "cs_op_index", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint, ctypes.c_uint)
-_setup_prototype(_cs, "cs_errno", ctypes.c_int, ctypes.c_size_t)
-_setup_prototype(_cs, "cs_option", ctypes.c_int, ctypes.c_size_t, ctypes.c_int, ctypes.c_void_p)
-_setup_prototype(_cs, "cs_version", ctypes.c_int, ctypes.POINTER(ctypes.c_int), ctypes.POINTER(ctypes.c_int))
-_setup_prototype(_cs, "cs_support", ctypes.c_bool, ctypes.c_int)
-_setup_prototype(_cs, "cs_strerror", ctypes.c_char_p, ctypes.c_int)
-
-
-# access to error code via @errno of CsError
-class CsError(Exception):
- def __init__(self, errno):
- self.errno = errno
-
- def __str__(self):
- return _cs.cs_strerror(self.errno)
-
-
-# return the core's version
-def cs_version():
- major = ctypes.c_int()
- minor = ctypes.c_int()
- combined = _cs.cs_version(ctypes.byref(major), ctypes.byref(minor))
- return (major.value, minor.value, combined)
-
-
-# return the binding's version
-def version_bind():
- return (CS_API_MAJOR, CS_API_MINOR, (CS_API_MAJOR << 8) + CS_API_MINOR)
-
-
-def cs_support(query):
- return _cs.cs_support(query)
-
-
-# dummy class resembling Cs class, just for cs_disasm_quick()
-# this class only need to be referenced to via 2 fields: @csh & @arch
-class _dummy_cs(object):
- def __init__(self, csh, arch):
- self.csh = csh
- self.arch = arch
-
-
-# Quick & dirty Python function to disasm raw binary code
-# This function return CsInsn objects
-# NOTE: you might want to use more efficient Cs class & its methods.
-def cs_disasm_quick(arch, mode, code, offset, count = 0):
- # verify version compatibility with the core before doing anything
- (major, minor, _combined) = cs_version()
- if major != CS_API_MAJOR or minor != CS_API_MINOR:
- # our binding version is different from the core's API version
- raise CsError(CS_ERR_VERSION)
-
- csh = ctypes.c_size_t()
- status = _cs.cs_open(arch, mode, ctypes.byref(csh))
- if status != CS_ERR_OK:
- raise CsError(status)
-
- all_insn = ctypes.POINTER(_cs_insn)()
- res = _cs.cs_disasm_ex(csh, code, len(code), offset, count, ctypes.byref(all_insn))
- if res > 0:
- for i in xrange(res):
- yield CsInsn(_dummy_cs(csh, arch), all_insn[i])
-
- _cs.cs_free(all_insn, res)
- else:
- status = _cs.cs_errno(csh)
- if status != CS_ERR_OK:
- raise CsError(status)
- return
- yield
-
- status = _cs.cs_close(ctypes.byref(csh))
- if status != CS_ERR_OK:
- raise CsError(status)
-
-
-# Another quick, but lighter function to disasm raw binary code.
-# This function is faster than cs_disasm_quick() around 20% because
-# cs_disasm_lite() only return tuples of (address, size, mnemonic, op_str),
-# rather than CsInsn objects.
-# NOTE: you might want to use more efficient Cs class & its methods.
-def cs_disasm_lite(arch, mode, code, offset, count = 0):
- # verify version compatibility with the core before doing anything
- (major, minor, _combined) = cs_version()
- if major != CS_API_MAJOR or minor != CS_API_MINOR:
- # our binding version is different from the core's API version
- raise CsError(CS_ERR_VERSION)
-
- if cs_support(CS_SUPPORT_DIET):
- # Diet engine cannot provide @mnemonic & @op_str
- raise CsError(CS_ERR_DIET)
-
- csh = ctypes.c_size_t()
- status = _cs.cs_open(arch, mode, ctypes.byref(csh))
- if status != CS_ERR_OK:
- raise CsError(status)
-
- all_insn = ctypes.POINTER(_cs_insn)()
- res = _cs.cs_disasm_ex(csh, code, len(code), offset, count, ctypes.byref(all_insn))
- if res > 0:
- for i in xrange(res):
- insn = all_insn[i]
- yield (insn.address, insn.size, insn.mnemonic, insn.op_str)
-
- _cs.cs_free(all_insn, res)
- else:
- status = _cs.cs_errno(csh)
- if status != CS_ERR_OK:
- raise CsError(status)
- return
- yield
-
- status = _cs.cs_close(ctypes.byref(csh))
- if status != CS_ERR_OK:
- raise CsError(status)
-
-
-# Python-style class to disasm code
-class CsInsn(object):
- def __init__(self, cs, all_info):
- self._raw = all_info
- self._cs = cs
-
- # return instruction's ID.
- @property
- def id(self):
- return self._raw.id
-
- # return instruction's address.
- @property
- def address(self):
- return self._raw.address
-
- # return instruction's size.
- @property
- def size(self):
- return self._raw.size
-
- # return instruction's machine bytes (which should have @size bytes).
- @property
- def bytes(self):
- return bytearray(self._raw.bytes)[:self._raw.size]
-
- # return instruction's mnemonic.
- @property
- def mnemonic(self):
- if self._cs._diet:
- # Diet engine cannot provide @mnemonic.
- raise CsError(CS_ERR_DIET)
-
- return self._raw.mnemonic
-
- # return instruction's operands (in string).
- @property
- def op_str(self):
- if self._cs._diet:
- # Diet engine cannot provide @op_str.
- raise CsError(CS_ERR_DIET)
-
- return self._raw.op_str
-
- # return list of all implicit registers being read.
- @property
- def regs_read(self):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide @regs_read.
- raise CsError(CS_ERR_DIET)
-
- if self._cs._detail:
- detail = self._raw.detail.contents
- return detail.regs_read[:detail.regs_read_count]
-
- raise CsError(CS_ERR_DETAIL)
-
- # return list of all implicit registers being modified
- @property
- def regs_write(self):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide @regs_write
- raise CsError(CS_ERR_DIET)
-
- if self._cs._detail:
- detail = self._raw.detail.contents
- return detail.regs_write[:detail.regs_write_count]
-
- raise CsError(CS_ERR_DETAIL)
-
- # return list of semantic groups this instruction belongs to.
- @property
- def groups(self):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide @groups
- raise CsError(CS_ERR_DIET)
-
- if self._cs._detail:
- detail = self._raw.detail.contents
- return detail.groups[:detail.groups_count]
-
- raise CsError(CS_ERR_DETAIL)
-
- def __gen_detail(self):
- arch = self._cs.arch
- detail = self._raw.detail.contents
- if arch == CS_ARCH_ARM:
- (self.cc, self.update_flags, self.writeback, self.operands) = \
- arm.get_arch_info(detail.arch.arm)
- elif arch == CS_ARCH_ARM64:
- (self.cc, self.update_flags, self.writeback, self.operands) = \
- arm64.get_arch_info(detail.arch.arm64)
- elif arch == CS_ARCH_X86:
- (self.prefix, self.segment, self.opcode, self.op_size, self.addr_size, \
- self.disp_size, self.imm_size, self.modrm, self.sib, self.disp, \
- self.sib_index, self.sib_scale, self.sib_base, self.operands) = x86.get_arch_info(detail.arch.x86)
- elif arch == CS_ARCH_MIPS:
- self.operands = mips.get_arch_info(detail.arch.mips)
- elif arch == CS_ARCH_PPC:
- (self.bc, self.bh, self.update_cr0, self.operands) = \
- ppc.get_arch_info(detail.arch.ppc)
- elif arch == CS_ARCH_SPARC:
- (self.cc, self.hint, self.operands) = sparc.get_arch_info(detail.arch.sparc)
- elif arch == CS_ARCH_SYSZ:
- (self.cc, self.operands) = systemz.get_arch_info(detail.arch.sysz)
-
- def __getattr__(self, name):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if not self._cs._detail:
- raise CsError(CS_ERR_DETAIL)
-
- attr = object.__getattribute__
- if not attr(self, '_cs')._detail:
- return None
- _dict = attr(self, '__dict__')
- if 'operands' not in _dict:
- self.__gen_detail()
- if name not in _dict:
- return None
- return _dict[name]
-
- # get the last error code
- def errno(self):
- return _cs.cs_errno(self._cs.csh)
-
- # get the register name, given the register ID
- def reg_name(self, reg_id):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide register name
- raise CsError(CS_ERR_DIET)
-
- return _cs.cs_reg_name(self._cs.csh, reg_id)
-
- # get the instruction string
- def insn_name(self):
- if self._cs._diet:
- # Diet engine cannot provide instruction name
- raise CsError(CS_ERR_DIET)
-
- return _cs.cs_insn_name(self._cs.csh, self.id)
-
- # verify if this insn belong to group with id as @group_id
- def group(self, group_id):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide group information
- raise CsError(CS_ERR_DIET)
-
- return group_id in self.groups
-
- # verify if this instruction implicitly read register @reg_id
- def reg_read(self, reg_id):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide regs_read information
- raise CsError(CS_ERR_DIET)
-
- return reg_id in self.regs_read
-
- # verify if this instruction implicitly modified register @reg_id
- def reg_write(self, reg_id):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- if self._cs._diet:
- # Diet engine cannot provide regs_write information
- raise CsError(CS_ERR_DIET)
-
- return reg_id in self.regs_write
-
- # return number of operands having same operand type @op_type
- def op_count(self, op_type):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- c = 0
- for op in self.operands:
- if op.type == op_type:
- c += 1
- return c
-
- # get the operand at position @position of all operands having the same type @op_type
- def op_find(self, op_type, position):
- if self._raw.id == 0:
- raise CsError(CS_ERR_SKIPDATA)
-
- c = 0
- for op in self.operands:
- if op.type == op_type:
- c += 1
- if c == position:
- return op
-
-
-class Cs(object):
- def __init__(self, arch, mode):
- # verify version compatibility with the core before doing anything
- (major, minor, _combined) = cs_version()
- if major != CS_API_MAJOR or minor != CS_API_MINOR:
- self.csh = None
- # our binding version is different from the core's API version
- raise CsError(CS_ERR_VERSION)
-
- self.arch, self._mode = arch, mode
- self.csh = ctypes.c_size_t()
- status = _cs.cs_open(arch, mode, ctypes.byref(self.csh))
- if status != CS_ERR_OK:
- self.csh = None
- raise CsError(status)
-
- try:
- import ccapstone
- # rewire disasm to use the faster version
- self.disasm = ccapstone.Cs(self).disasm
- except:
- pass
-
- if arch == CS_ARCH_X86:
- # Intel syntax is default for X86
- self._syntax = CS_OPT_SYNTAX_INTEL
- else:
- self._syntax = None
-
- self._detail = False # by default, do not produce instruction details
- self._diet = cs_support(CS_SUPPORT_DIET)
- self._x86_compact = cs_support(CS_SUPPORT_X86_REDUCE)
-
- # default mnemonic for SKIPDATA
- self._skipdata_mnem = ".byte"
- self._skipdata = False
-
-
- # destructor to be called automatically when object is destroyed.
- def __del__(self):
- if self.csh:
- status = _cs.cs_close(ctypes.byref(self.csh))
- if status != CS_ERR_OK:
- raise CsError(status)
-
-
- #def option(self, opt_type, opt_value):
- # return _cs.cs_option(self.csh, opt_type, opt_value)
-
-
- # is this a diet engine?
- @property
- def diet(self):
- return self._diet
-
-
- # is this engine compiled with X86 compact option?
- @property
- def x86_compact(self):
- return self._x86_compact
-
-
- # return assembly syntax.
- @property
- def syntax(self):
- return self._syntax
-
-
- # setter: modify assembly syntax.
- @syntax.setter
- def syntax(self, style):
- status = _cs.cs_option(self.csh, CS_OPT_SYNTAX, style)
- if status != CS_ERR_OK:
- raise CsError(status)
- # save syntax
- self._syntax = style
-
-
- # return current skipdata status
- @property
- def skipdata(self):
- return self._skipdata
-
-
- # setter: modify skipdata status
- @syntax.setter
- def skipdata(self, opt):
- if opt == False:
- status = _cs.cs_option(self.csh, CS_OPT_SKIPDATA, CS_OPT_OFF)
- else:
- status = _cs.cs_option(self.csh, CS_OPT_SKIPDATA, CS_OPT_ON)
- if status != CS_ERR_OK:
- raise CsError(status)
-
- # save this option
- self._skipdata = opt
-
-
- # setter: modify "data" instruction's mnemonic for SKIPDATA
- @syntax.setter
- def skipdata_setup(self, opt):
- _skipdata_opt = _cs_opt_skipdata()
- _mnem, _cb, _ud = opt
- _skipdata_opt.mnemonic = _mnem
- _skipdata_opt.callback = ctypes.cast(_cb, CS_SKIPDATA_CALLBACK)
- _skipdata_opt.user_data = ctypes.cast(_ud, ctypes.c_void_p)
- status = _cs.cs_option(self.csh, CS_OPT_SKIPDATA_SETUP, ctypes.cast(ctypes.byref(_skipdata_opt), ctypes.c_void_p))
- if status != CS_ERR_OK:
- raise CsError(status)
-
- self._skipdata_opt = _skipdata_opt
-
-
- # is detail mode enable?
- @property
- def detail(self):
- return self._detail
-
-
- # check to see if this engine supports a particular arch,
- # or diet mode (depending on @query).
- def support(self, query):
- return cs_support(query)
-
-
- # modify detail mode.
- @detail.setter
- def detail(self, opt): # opt is boolean type, so must be either 'True' or 'False'
- if opt == False:
- status = _cs.cs_option(self.csh, CS_OPT_DETAIL, CS_OPT_OFF)
- else:
- status = _cs.cs_option(self.csh, CS_OPT_DETAIL, CS_OPT_ON)
- if status != CS_ERR_OK:
- raise CsError(status)
- # save detail
- self._detail = opt
-
-
- # return disassembly mode of this engine.
- @property
- def mode(self):
- return self._mode
-
-
- # modify engine's mode at run-time.
- @mode.setter
- def mode(self, opt): # opt is new disasm mode, of int type
- status = _cs.cs_option(self.csh, CS_OPT_MODE, opt)
- if status != CS_ERR_OK:
- raise CsError(status)
- # save mode
- self._mode = opt
-
-
- # Disassemble binary & return disassembled instructions in CsInsn objects
- def disasm(self, code, offset, count = 0):
- all_insn = ctypes.POINTER(_cs_insn)()
- res = _cs.cs_disasm_ex(self.csh, code, len(code), offset, count, ctypes.byref(all_insn))
- if res > 0:
- for i in xrange(res):
- yield CsInsn(self, all_insn[i])
- _cs.cs_free(all_insn, res)
- else:
- status = _cs.cs_errno(self.csh)
- if status != CS_ERR_OK:
- raise CsError(status)
- return
- yield
-
-
- # Light function to disassemble binary. This is about 20% faster than disasm() because
- # unlike disasm(), disasm_lite() only return tuples of (address, size, mnemonic, op_str),
- # rather than CsInsn objects.
- def disasm_lite(self, code, offset, count = 0):
- if self._diet:
- # Diet engine cannot provide @mnemonic & @op_str
- raise CsError(CS_ERR_DIET)
-
- all_insn = ctypes.POINTER(_cs_insn)()
- res = _cs.cs_disasm_ex(self.csh, code, len(code), offset, count, ctypes.byref(all_insn))
- if res > 0:
- for i in xrange(res):
- insn = all_insn[i]
- yield (insn.address, insn.size, insn.mnemonic, insn.op_str)
- _cs.cs_free(all_insn, res)
- else:
- status = _cs.cs_errno(self.csh)
- if status != CS_ERR_OK:
- raise CsError(status)
- return
- yield
-
-
-# print out debugging info
-def debug():
- # is Cython there?
- try:
- import ccapstone
- return ccapstone.debug()
- except:
- # no Cython, fallback to Python code below
- pass
-
- if cs_support(CS_SUPPORT_DIET):
- diet = "diet"
- else:
- diet = "standard"
-
- archs = { "arm": CS_ARCH_ARM, "arm64": CS_ARCH_ARM64, \
- "mips": CS_ARCH_MIPS, "ppc": CS_ARCH_PPC, "sparc": CS_ARCH_SPARC, \
- "sysz": CS_ARCH_SYSZ }
-
- all_archs = ""
- keys = archs.keys()
- keys.sort()
- for k in keys:
- if cs_support(archs[k]):
- all_archs += "-%s" %k
-
- if cs_support(CS_ARCH_X86):
- all_archs += "-x86"
- if cs_support(CS_SUPPORT_X86_REDUCE):
- all_archs += "_compact"
-
- (major, minor, _combined) = cs_version()
-
- return "python-%s%s-c%u.%u-b%u.%u" %(diet, all_archs, major, minor, CS_API_MAJOR, CS_API_MINOR)
-
diff --git a/bindings/python/capstone/xcore.py b/bindings/python/capstone/xcore.py
new file mode 100644
index 0000000..aac7f6c
--- /dev/null
+++ b/bindings/python/capstone/xcore.py
@@ -0,0 +1,49 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes, copy
+from .xcore_const import *
+
+# define the API
+class XcoreOpMem(ctypes.Structure):
+ _fields_ = (
+ ('base', ctypes.c_uint8),
+ ('index', ctypes.c_uint8),
+ ('disp', ctypes.c_int32),
+ ('direct', ctypes.c_int),
+ )
+
+class XcoreOpValue(ctypes.Union):
+ _fields_ = (
+ ('reg', ctypes.c_uint),
+ ('imm', ctypes.c_int32),
+ ('mem', XcoreOpMem),
+ )
+
+class XcoreOp(ctypes.Structure):
+ _fields_ = (
+ ('type', ctypes.c_uint),
+ ('value', XcoreOpValue),
+ )
+
+ @property
+ def imm(self):
+ return self.value.imm
+
+ @property
+ def reg(self):
+ return self.value.reg
+
+ @property
+ def mem(self):
+ return self.value.mem
+
+
+class CsXcore(ctypes.Structure):
+ _fields_ = (
+ ('op_count', ctypes.c_uint8),
+ ('operands', XcoreOp * 8),
+ )
+
+def get_arch_info(a):
+ return (copy.deepcopy(a.operands[:a.op_count]))
+
diff --git a/bindings/python/capstone/xcore_const.py b/bindings/python/capstone/xcore_const.py
new file mode 100644
index 0000000..c705d03
--- /dev/null
+++ b/bindings/python/capstone/xcore_const.py
@@ -0,0 +1,160 @@
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
+
+# Operand type for instruction's operands
+
+XCORE_OP_INVALID = 0
+XCORE_OP_REG = 1
+XCORE_OP_IMM = 2
+XCORE_OP_MEM = 3
+
+# XCore registers
+
+XCORE_REG_INVALID = 0
+XCORE_REG_CP = 1
+XCORE_REG_DP = 2
+XCORE_REG_LR = 3
+XCORE_REG_SP = 4
+XCORE_REG_R0 = 5
+XCORE_REG_R1 = 6
+XCORE_REG_R2 = 7
+XCORE_REG_R3 = 8
+XCORE_REG_R4 = 9
+XCORE_REG_R5 = 10
+XCORE_REG_R6 = 11
+XCORE_REG_R7 = 12
+XCORE_REG_R8 = 13
+XCORE_REG_R9 = 14
+XCORE_REG_R10 = 15
+XCORE_REG_R11 = 16
+XCORE_REG_MAX = 17
+
+# XCore instruction
+
+XCORE_INS_INVALID = 0
+XCORE_INS_ADD = 1
+XCORE_INS_ANDNOT = 2
+XCORE_INS_AND = 3
+XCORE_INS_ASHR = 4
+XCORE_INS_BAU = 5
+XCORE_INS_BITREV = 6
+XCORE_INS_BLA = 7
+XCORE_INS_BLAT = 8
+XCORE_INS_BL = 9
+XCORE_INS_BF = 10
+XCORE_INS_BT = 11
+XCORE_INS_BU = 12
+XCORE_INS_BRU = 13
+XCORE_INS_BYTEREV = 14
+XCORE_INS_CHKCT = 15
+XCORE_INS_CLRE = 16
+XCORE_INS_CLRPT = 17
+XCORE_INS_CLRSR = 18
+XCORE_INS_CLZ = 19
+XCORE_INS_CRC8 = 20
+XCORE_INS_CRC32 = 21
+XCORE_INS_DCALL = 22
+XCORE_INS_DENTSP = 23
+XCORE_INS_DGETREG = 24
+XCORE_INS_DIVS = 25
+XCORE_INS_DIVU = 26
+XCORE_INS_DRESTSP = 27
+XCORE_INS_DRET = 28
+XCORE_INS_ECALLF = 29
+XCORE_INS_ECALLT = 30
+XCORE_INS_EDU = 31
+XCORE_INS_EEF = 32
+XCORE_INS_EET = 33
+XCORE_INS_EEU = 34
+XCORE_INS_ENDIN = 35
+XCORE_INS_ENTSP = 36
+XCORE_INS_EQ = 37
+XCORE_INS_EXTDP = 38
+XCORE_INS_EXTSP = 39
+XCORE_INS_FREER = 40
+XCORE_INS_FREET = 41
+XCORE_INS_GETD = 42
+XCORE_INS_GET = 43
+XCORE_INS_GETN = 44
+XCORE_INS_GETR = 45
+XCORE_INS_GETSR = 46
+XCORE_INS_GETST = 47
+XCORE_INS_GETTS = 48
+XCORE_INS_INCT = 49
+XCORE_INS_INIT = 50
+XCORE_INS_INPW = 51
+XCORE_INS_INSHR = 52
+XCORE_INS_INT = 53
+XCORE_INS_IN = 54
+XCORE_INS_KCALL = 55
+XCORE_INS_KENTSP = 56
+XCORE_INS_KRESTSP = 57
+XCORE_INS_KRET = 58
+XCORE_INS_LADD = 59
+XCORE_INS_LD16S = 60
+XCORE_INS_LD8U = 61
+XCORE_INS_LDA16 = 62
+XCORE_INS_LDAP = 63
+XCORE_INS_LDAW = 64
+XCORE_INS_LDC = 65
+XCORE_INS_LDW = 66
+XCORE_INS_LDIVU = 67
+XCORE_INS_LMUL = 68
+XCORE_INS_LSS = 69
+XCORE_INS_LSUB = 70
+XCORE_INS_LSU = 71
+XCORE_INS_MACCS = 72
+XCORE_INS_MACCU = 73
+XCORE_INS_MJOIN = 74
+XCORE_INS_MKMSK = 75
+XCORE_INS_MSYNC = 76
+XCORE_INS_MUL = 77
+XCORE_INS_NEG = 78
+XCORE_INS_NOT = 79
+XCORE_INS_OR = 80
+XCORE_INS_OUTCT = 81
+XCORE_INS_OUTPW = 82
+XCORE_INS_OUTSHR = 83
+XCORE_INS_OUTT = 84
+XCORE_INS_OUT = 85
+XCORE_INS_PEEK = 86
+XCORE_INS_REMS = 87
+XCORE_INS_REMU = 88
+XCORE_INS_RETSP = 89
+XCORE_INS_SETCLK = 90
+XCORE_INS_SET = 91
+XCORE_INS_SETC = 92
+XCORE_INS_SETD = 93
+XCORE_INS_SETEV = 94
+XCORE_INS_SETN = 95
+XCORE_INS_SETPSC = 96
+XCORE_INS_SETPT = 97
+XCORE_INS_SETRDY = 98
+XCORE_INS_SETSR = 99
+XCORE_INS_SETTW = 100
+XCORE_INS_SETV = 101
+XCORE_INS_SEXT = 102
+XCORE_INS_SHL = 103
+XCORE_INS_SHR = 104
+XCORE_INS_SSYNC = 105
+XCORE_INS_ST16 = 106
+XCORE_INS_ST8 = 107
+XCORE_INS_STW = 108
+XCORE_INS_SUB = 109
+XCORE_INS_SYNCR = 110
+XCORE_INS_TESTCT = 111
+XCORE_INS_TESTLCL = 112
+XCORE_INS_TESTWCT = 113
+XCORE_INS_TSETMR = 114
+XCORE_INS_START = 115
+XCORE_INS_WAITEF = 116
+XCORE_INS_WAITET = 117
+XCORE_INS_WAITEU = 118
+XCORE_INS_XOR = 119
+XCORE_INS_ZEXT = 120
+XCORE_INS_MAX = 121
+
+# Group of XCore instructions
+
+XCORE_GRP_INVALID = 0
+XCORE_GRP_JUMP = 1
+XCORE_GRP_MAX = 2
diff --git a/bindings/python/setup_cython.py b/bindings/python/setup_cython.py
index 5d8b056..1dea2f5 100644
--- a/bindings/python/setup_cython.py
+++ b/bindings/python/setup_cython.py
@@ -19,6 +19,8 @@
Extension("capstone.ppc_const", ["pyx/ppc_const.pyx"], extra_compile_args=compile_args),
Extension("capstone.x86", ["pyx/x86.pyx"], extra_compile_args=compile_args),
Extension("capstone.x86_const", ["pyx/x86_const.pyx"], extra_compile_args=compile_args)
+ Extension("capstone.xcore", ["pyx/xcore.pyx"], extra_compile_args=compile_args),
+ Extension("capstone.xcore_const", ["pyx/xcore_const.pyx"], extra_compile_args=compile_args)
]
# clean package directory first
diff --git a/bindings/python/test.py b/bindings/python/test.py
index b032cb5..ed62d13 100755
--- a/bindings/python/test.py
+++ b/bindings/python/test.py
@@ -25,6 +25,7 @@
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
+XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
@@ -43,6 +44,7 @@
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", 0),
+ (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", 0),
)
diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py
index 2844399..03a4dd3 100755
--- a/bindings/python/test_detail.py
+++ b/bindings/python/test_detail.py
@@ -19,6 +19,7 @@
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
+XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
@@ -36,6 +37,7 @@
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", 0),
+ (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", 0),
)
diff --git a/config.mk b/config.mk
index 99d1a1e..8b66b5a 100644
--- a/config.mk
+++ b/config.mk
@@ -4,7 +4,7 @@
################################################################################
# Specify which archs you want to compile in. By default, we build all archs.
-CAPSTONE_ARCHS ?= arm aarch64 mips powerpc sparc systemz x86
+CAPSTONE_ARCHS ?= arm aarch64 mips powerpc sparc systemz x86 xcore
################################################################################
diff --git a/cs.c b/cs.c
index 05a5f1d..3317db3 100644
--- a/cs.c
+++ b/cs.c
@@ -33,6 +33,7 @@
extern void PPC_enable(void);
extern void Sparc_enable(void);
extern void SystemZ_enable(void);
+extern void XCore_enable(void);
static void archs_enable(void)
{
@@ -62,6 +63,10 @@
#ifdef CAPSTONE_HAS_X86
X86_enable();
#endif
+#ifdef CAPSTONE_HAS_XCORE
+ XCore_enable();
+#endif
+
initialized = true;
}
@@ -102,7 +107,7 @@
return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) |
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
- (1 << CS_ARCH_SYSZ));
+ (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE));
if ((unsigned int)query < CS_ARCH_MAX)
return all_arch & (1 << query);
@@ -333,6 +338,10 @@
case CS_ARCH_X86:
// X86 has no restriction on instruction alignment
return 1;
+ case CS_ARCH_XCORE:
+ // XCore instruction's length can be 2 or 4 bytes,
+ // so we just skip 2 bytes
+ return 2;
}
}
@@ -750,6 +759,11 @@
if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type)
count++;
break;
+ case CS_ARCH_XCORE:
+ for (i = 0; i < insn->detail->xcore.op_count; i++)
+ if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type)
+ count++;
+ break;
}
return count;
@@ -842,6 +856,14 @@
return i;
}
break;
+ case CS_ARCH_XCORE:
+ for (i = 0; i < insn->detail->xcore.op_count; i++) {
+ if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type)
+ count++;
+ if (count == post)
+ return i;
+ }
+ break;
}
return -1;
diff --git a/include/capstone.h b/include/capstone.h
index d3da50f..9ec8bce 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -40,6 +40,7 @@
CS_ARCH_PPC, // PowerPC architecture
CS_ARCH_SPARC, // Sparc architecture
CS_ARCH_SYSZ, // SystemZ architecture
+ CS_ARCH_XCORE, // XCore architecture
CS_ARCH_MAX,
CS_ARCH_ALL = 0xFFFF,
} cs_arch;
@@ -136,6 +137,7 @@
// Sparc: 4 bytes.
// SystemZ: 2 bytes.
// X86: 1 bytes.
+ // XCore: 2 bytes.
cs_skipdata_cb_t callback; // default value is NULL
// User-defined data to be passed to @callback function pointer.
@@ -150,6 +152,7 @@
#include "sparc.h"
#include "systemz.h"
#include "x86.h"
+#include "xcore.h"
// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
typedef struct cs_detail {
@@ -171,6 +174,7 @@
cs_ppc ppc; // PowerPC architecture
cs_sparc sparc; // Sparc architecture
cs_sysz sysz; // SystemZ architecture
+ cs_xcore xcore; // XCore architecture
};
} cs_detail;
diff --git a/include/xcore.h b/include/xcore.h
new file mode 100644
index 0000000..5bc6770
--- /dev/null
+++ b/include/xcore.h
@@ -0,0 +1,218 @@
+#ifndef CAPSTONE_XCORE_H
+#define CAPSTONE_XCORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Operand type for instruction's operands
+typedef enum xcore_op_type {
+ XCORE_OP_INVALID = 0, // Uninitialized.
+ XCORE_OP_REG, // Register operand.
+ XCORE_OP_IMM, // Immediate operand.
+ XCORE_OP_MEM, // Memory operand
+} xcore_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with XCORE_OP_MEM operand type above
+typedef struct xcore_op_mem {
+ uint8_t base; // base register
+ uint8_t index; // index register
+ int32_t disp; // displacement/offset value
+ int direct; // +1: forward, -1: backward
+} xcore_op_mem;
+
+// Instruction operand
+typedef struct cs_xcore_op {
+ xcore_op_type type; // operand type
+ union {
+ unsigned int reg; // register value for REG operand
+ int32_t imm; // immediate value for IMM operand
+ xcore_op_mem mem; // base/disp value for MEM operand
+ };
+} cs_xcore_op;
+
+// Instruction structure
+typedef struct cs_xcore {
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_xcore_op operands[8]; // operands for this instruction.
+} cs_xcore;
+
+//> XCore registers
+typedef enum xcore_reg {
+ XCORE_REG_INVALID = 0,
+
+ XCORE_REG_CP,
+ XCORE_REG_DP,
+ XCORE_REG_LR,
+ XCORE_REG_SP,
+ XCORE_REG_R0,
+ XCORE_REG_R1,
+ XCORE_REG_R2,
+ XCORE_REG_R3,
+ XCORE_REG_R4,
+ XCORE_REG_R5,
+ XCORE_REG_R6,
+ XCORE_REG_R7,
+ XCORE_REG_R8,
+ XCORE_REG_R9,
+ XCORE_REG_R10,
+ XCORE_REG_R11,
+
+ XCORE_REG_MAX,
+} xcore_reg;
+
+//> XCore instruction
+typedef enum xcore_insn {
+ XCORE_INS_INVALID = 0,
+
+ XCORE_INS_ADD,
+ XCORE_INS_ANDNOT,
+ XCORE_INS_AND,
+ XCORE_INS_ASHR,
+ XCORE_INS_BAU,
+ XCORE_INS_BITREV,
+ XCORE_INS_BLA,
+ XCORE_INS_BLAT,
+ XCORE_INS_BL,
+ XCORE_INS_BF,
+ XCORE_INS_BT,
+ XCORE_INS_BU,
+ XCORE_INS_BRU,
+ XCORE_INS_BYTEREV,
+ XCORE_INS_CHKCT,
+ XCORE_INS_CLRE,
+ XCORE_INS_CLRPT,
+ XCORE_INS_CLRSR,
+ XCORE_INS_CLZ,
+ XCORE_INS_CRC8,
+ XCORE_INS_CRC32,
+ XCORE_INS_DCALL,
+ XCORE_INS_DENTSP,
+ XCORE_INS_DGETREG,
+ XCORE_INS_DIVS,
+ XCORE_INS_DIVU,
+ XCORE_INS_DRESTSP,
+ XCORE_INS_DRET,
+ XCORE_INS_ECALLF,
+ XCORE_INS_ECALLT,
+ XCORE_INS_EDU,
+ XCORE_INS_EEF,
+ XCORE_INS_EET,
+ XCORE_INS_EEU,
+ XCORE_INS_ENDIN,
+ XCORE_INS_ENTSP,
+ XCORE_INS_EQ,
+ XCORE_INS_EXTDP,
+ XCORE_INS_EXTSP,
+ XCORE_INS_FREER,
+ XCORE_INS_FREET,
+ XCORE_INS_GETD,
+ XCORE_INS_GET,
+ XCORE_INS_GETN,
+ XCORE_INS_GETR,
+ XCORE_INS_GETSR,
+ XCORE_INS_GETST,
+ XCORE_INS_GETTS,
+ XCORE_INS_INCT,
+ XCORE_INS_INIT,
+ XCORE_INS_INPW,
+ XCORE_INS_INSHR,
+ XCORE_INS_INT,
+ XCORE_INS_IN,
+ XCORE_INS_KCALL,
+ XCORE_INS_KENTSP,
+ XCORE_INS_KRESTSP,
+ XCORE_INS_KRET,
+ XCORE_INS_LADD,
+ XCORE_INS_LD16S,
+ XCORE_INS_LD8U,
+ XCORE_INS_LDA16,
+ XCORE_INS_LDAP,
+ XCORE_INS_LDAW,
+ XCORE_INS_LDC,
+ XCORE_INS_LDW,
+ XCORE_INS_LDIVU,
+ XCORE_INS_LMUL,
+ XCORE_INS_LSS,
+ XCORE_INS_LSUB,
+ XCORE_INS_LSU,
+ XCORE_INS_MACCS,
+ XCORE_INS_MACCU,
+ XCORE_INS_MJOIN,
+ XCORE_INS_MKMSK,
+ XCORE_INS_MSYNC,
+ XCORE_INS_MUL,
+ XCORE_INS_NEG,
+ XCORE_INS_NOT,
+ XCORE_INS_OR,
+ XCORE_INS_OUTCT,
+ XCORE_INS_OUTPW,
+ XCORE_INS_OUTSHR,
+ XCORE_INS_OUTT,
+ XCORE_INS_OUT,
+ XCORE_INS_PEEK,
+ XCORE_INS_REMS,
+ XCORE_INS_REMU,
+ XCORE_INS_RETSP,
+ XCORE_INS_SETCLK,
+ XCORE_INS_SET,
+ XCORE_INS_SETC,
+ XCORE_INS_SETD,
+ XCORE_INS_SETEV,
+ XCORE_INS_SETN,
+ XCORE_INS_SETPSC,
+ XCORE_INS_SETPT,
+ XCORE_INS_SETRDY,
+ XCORE_INS_SETSR,
+ XCORE_INS_SETTW,
+ XCORE_INS_SETV,
+ XCORE_INS_SEXT,
+ XCORE_INS_SHL,
+ XCORE_INS_SHR,
+ XCORE_INS_SSYNC,
+ XCORE_INS_ST16,
+ XCORE_INS_ST8,
+ XCORE_INS_STW,
+ XCORE_INS_SUB,
+ XCORE_INS_SYNCR,
+ XCORE_INS_TESTCT,
+ XCORE_INS_TESTLCL,
+ XCORE_INS_TESTWCT,
+ XCORE_INS_TSETMR,
+ XCORE_INS_START,
+ XCORE_INS_WAITEF,
+ XCORE_INS_WAITET,
+ XCORE_INS_WAITEU,
+ XCORE_INS_XOR,
+ XCORE_INS_ZEXT,
+
+ XCORE_INS_MAX, // <-- mark the end of the list of instructions
+} xcore_insn;
+
+//> Group of XCore instructions
+typedef enum xcore_insn_group {
+ XCORE_GRP_INVALID = 0,
+
+ XCORE_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
+
+ XCORE_GRP_MAX, // <-- mark the end of the list of groups
+} xcore_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tests/Makefile b/tests/Makefile
index 1c5bec5..53c4cca 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -73,6 +73,9 @@
ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
SOURCES += test_x86.c
endif
+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
+SOURCES += test_xcore.c
+endif
OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o))
BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT)))
diff --git a/tests/test.c b/tests/test.c
index 09a4246..1c34603 100644
--- a/tests/test.c
+++ b/tests/test.c
@@ -50,6 +50,7 @@
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
+#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
struct platform {
cs_arch arch;
cs_mode mode;
@@ -176,6 +177,13 @@
sizeof(SYSZ_CODE) - 1,
"SystemZ"
},
+ {
+ CS_ARCH_XCORE,
+ (cs_mode)0,
+ (unsigned char*)XCORE_CODE,
+ sizeof(XCORE_CODE) - 1,
+ "XCore"
+ },
};
csh handle;
diff --git a/tests/test_detail.c b/tests/test_detail.c
index d8b9c5b..03e6eac 100644
--- a/tests/test_detail.c
+++ b/tests/test_detail.c
@@ -56,6 +56,7 @@
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
+#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
struct platform platforms[] = {
{
@@ -165,6 +166,13 @@
sizeof(SYSZ_CODE) - 1,
"SystemZ"
},
+ {
+ CS_ARCH_XCORE,
+ (cs_mode)0,
+ (unsigned char*)XCORE_CODE,
+ sizeof(XCORE_CODE) - 1,
+ "XCore"
+ },
};
csh handle;
diff --git a/tests/test_xcore.c b/tests/test_xcore.c
new file mode 100644
index 0000000..8e77270
--- /dev/null
+++ b/tests/test_xcore.c
@@ -0,0 +1,139 @@
+/* Capstone Disassembler Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#include <stdio.h>
+#include <inttypes.h>
+
+#include <capstone.h>
+
+struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ unsigned char *code;
+ size_t size;
+ char *comment;
+};
+
+static csh handle;
+
+static void print_string_hex(char *comment, unsigned char *str, int len)
+{
+ unsigned char *c;
+
+ printf("%s", comment);
+ for (c = str; c < str + len; c++) {
+ printf("0x%02x ", *c & 0xff);
+ }
+
+ printf("\n");
+}
+
+static void print_insn_detail(cs_insn *ins)
+{
+ cs_xcore *xcore;
+ int i;
+
+ // detail can be NULL on "data" instruction if SKIPDATA option is turned ON
+ if (ins->detail == NULL)
+ return;
+
+ xcore = &(ins->detail->xcore);
+ if (xcore->op_count)
+ printf("\top_count: %u\n", xcore->op_count);
+
+ for (i = 0; i < xcore->op_count; i++) {
+ cs_xcore_op *op = &(xcore->operands[i]);
+ switch((int)op->type) {
+ default:
+ break;
+ case XCORE_OP_REG:
+ printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
+ break;
+ case XCORE_OP_IMM:
+ printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
+ break;
+ case XCORE_OP_MEM:
+ printf("\t\toperands[%u].type: MEM\n", i);
+ if (op->mem.base != XCORE_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.base: REG = %s\n",
+ i, cs_reg_name(handle, op->mem.base));
+ if (op->mem.index != XCORE_REG_INVALID)
+ printf("\t\t\toperands[%u].mem.index: REG = %s\n",
+ i, cs_reg_name(handle, op->mem.index));
+ if (op->mem.disp != 0)
+ printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
+ if (op->mem.direct != 1)
+ printf("\t\t\toperands[%u].mem.direct: -1\n", i);
+
+
+ break;
+ }
+ }
+
+ printf("\n");
+}
+
+static void test()
+{
+#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
+
+ struct platform platforms[] = {
+ {
+ CS_ARCH_XCORE,
+ CS_MODE_BIG_ENDIAN,
+ (unsigned char*)XCORE_CODE,
+ sizeof(XCORE_CODE) - 1,
+ "XCore",
+ },
+ };
+
+ uint64_t address = 0x1000;
+ cs_insn *insn;
+ int i;
+ size_t count;
+
+ for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
+ cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
+ if (err) {
+ printf("Failed on cs_open() with error returned: %u\n", err);
+ continue;
+ }
+
+ cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
+
+ count = cs_disasm_ex(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
+ if (count) {
+ size_t j;
+
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("Disasm:\n");
+
+ for (j = 0; j < count; j++) {
+ printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
+ print_insn_detail(&insn[j]);
+ }
+ printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
+
+ // free memory allocated by cs_disasm_ex()
+ cs_free(insn, count);
+ } else {
+ printf("****************\n");
+ printf("Platform: %s\n", platforms[i].comment);
+ print_string_hex("Code:", platforms[i].code, platforms[i].size);
+ printf("ERROR: Failed to disasm given code!\n");
+ }
+
+ printf("\n");
+
+ cs_close(&handle);
+ }
+}
+
+int main()
+{
+ test();
+
+ return 0;
+}