x86: do not sign-extend immediate. this fixes the issues reported by LongLD
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index f604dc8..e78ef74 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -276,10 +276,7 @@
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
- if (imm < 0)
- SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">"));
- else
- SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">"));
+ SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">"));
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm;
MI->pub_insn.x86.op_count++;
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index 2c39007..7a4c8c1 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -84,68 +84,8 @@
static void translateImmediate(MCInst *mcInst, uint64_t immediate,
const OperandSpecifier *operand, InternalInstruction *insn)
{
- // Sign-extend the immediate if necessary.
OperandType type = (OperandType)operand->type;
- //bool isBranch = false;
- //uint64_t pcrel = 0;
- if (type == TYPE_RELv) {
- //isBranch = true;
- //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize;
- switch (insn->displacementSize) {
- case 1:
- if (immediate & 0x80)
- immediate |= ~(0xffull);
- break;
- case 2:
- if (immediate & 0x8000)
- immediate |= ~(0xffffull);
- break;
- case 4:
- if (immediate & 0x80000000)
- immediate |= ~(0xffffffffull);
- break;
- case 8:
- break;
- default:
- break;
- }
- }
- // By default sign-extend all X86 immediates based on their encoding.
- else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
- type == TYPE_IMM64) {
- uint32_t Opcode = MCInst_getOpcode(mcInst);
- switch (operand->encoding) {
- case ENCODING_IB:
- // Special case those X86 instructions that use the imm8 as a set of
- // bits, bit count, etc. and are not sign-extend.
- if (Opcode != X86_BLENDPSrri && Opcode != X86_BLENDPDrri &&
- Opcode != X86_PBLENDWrri && Opcode != X86_MPSADBWrri &&
- Opcode != X86_DPPSrri && Opcode != X86_DPPDrri &&
- Opcode != X86_INSERTPSrr && Opcode != X86_VBLENDPSYrri &&
- Opcode != X86_VBLENDPSYrmi && Opcode != X86_VBLENDPDYrri &&
- Opcode != X86_VBLENDPDYrmi && Opcode != X86_VPBLENDWrri &&
- Opcode != X86_VMPSADBWrri && Opcode != X86_VDPPSYrri &&
- Opcode != X86_VDPPSYrmi && Opcode != X86_VDPPDrri &&
- Opcode != X86_VINSERTPSrr)
- if (immediate & 0x80)
- immediate |= ~(0xffull);
- break;
- case ENCODING_IW:
- if (immediate & 0x8000)
- immediate |= ~(0xffffull);
- break;
- case ENCODING_ID:
- if (immediate & 0x80000000)
- immediate |= ~(0xffffffffull);
- break;
- case ENCODING_IO:
- break;
- default:
- break;
- }
- }
-
switch (type) {
case TYPE_XMM32:
case TYPE_XMM64:
@@ -158,19 +98,6 @@
case TYPE_XMM512:
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + (immediate >> 4)));
return;
- case TYPE_REL8:
- //isBranch = true;
- //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize;
- if (immediate & 0x80)
- immediate |= ~(0xffull);
- break;
- case TYPE_REL32:
- case TYPE_REL64:
- //isBranch = true;
- //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize;
- if (immediate & 0x80000000)
- immediate |= ~(0xffffffffull);
- break;
default:
// operand is 64 bits wide. Do nothing.
break;
@@ -242,7 +169,6 @@
MCOperand *indexReg;
MCOperand *displacement;
MCOperand *segmentReg;
- //uint64_t pcrel = 0;
if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) {
if (insn->sibBase != SIB_BASE_NONE) {
@@ -318,8 +244,6 @@
return true;
}
if (insn->mode == MODE_64BIT) {
- //pcrel = insn->startLocation +
- // insn->displacementOffset + insn->displacementSize;
baseReg = MCOperand_CreateReg(X86_RIP); // Section 2.2.1.6
} else
baseReg = MCOperand_CreateReg(0);
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index f9ff156..fc45198 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -376,10 +376,7 @@
MI->pub_insn.x86.op_count++;
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
- if (imm < 0)
- SStream_concat(O, "-0x%"PRIx64, -imm);
- else
- SStream_concat(O, "0x%"PRIx64, imm);
+ SStream_concat(O, "0x%"PRIx64, imm);
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm;
MI->pub_insn.x86.op_count++;
diff --git a/tests/test_x86.c b/tests/test_x86.c
index 4d9eb18..6bc4fb1 100644
--- a/tests/test_x86.c
+++ b/tests/test_x86.c
@@ -115,6 +115,7 @@
#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
//#define X86_CODE32 "\x64\xa1\x18\x00\x00\x00" // mov eax, dword ptr fs:[18]
//#define X86_CODE32 "\x64\xa3\x00\x00\x00\x00" // mov [fs:0x0], eax
+//#define X86_CODE32 "\xcd\x80"
struct platform platforms[] = {
{