support comments in autogen files, so constant files are more friendly
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index b9e98a2..c7db633 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -18,6 +18,8 @@
'arm64.h': 'Arm64',
'mips.h': 'Mips',
'x86.h': 'X86',
+ 'comment_open': '\t//',
+ 'comment_close': '',
},
'python': {
'header': "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n",
@@ -29,9 +31,14 @@
'arm64.h': 'arm64',
'mips.h': 'mips',
'x86.h': 'x86',
+ 'comment_open': '#',
+ 'comment_close': '',
}
}
+# markup for comments to be added to autogen files
+MARKUP = '//>'
+
def gen(templ):
global include, INCL_DIR
for target in include:
@@ -44,8 +51,15 @@
count = 0
for line in lines:
line = line.strip()
+
+ if line.startswith(MARKUP): # markup for comments
+ outfile.write("%s%s%s" %(templ['comment_open'], \
+ line.replace(MARKUP, ''), templ['comment_close']))
+ continue
+
if line == '' or line.startswith('//'):
continue
+
if not line.startswith(prefix.upper()):
continue
diff --git a/bindings/java/capstone/Arm64_const.java b/bindings/java/capstone/Arm64_const.java
index 5ee0270..5eae147 100644
--- a/bindings/java/capstone/Arm64_const.java
+++ b/bindings/java/capstone/Arm64_const.java
@@ -2,14 +2,14 @@
package capstone;
public class Arm64_const {
-
+ // ARM64 shift type
public static final int ARM64_SFT_INVALID = 0;
public static final int ARM64_SFT_LSL = 1;
public static final int ARM64_SFT_MSL = 2;
public static final int ARM64_SFT_LSR = 3;
public static final int ARM64_SFT_ASR = 4;
public static final int ARM64_SFT_ROR = 5;
-
+ // ARM64 extender type
public static final int ARM64_EXT_INVALID = 0;
public static final int ARM64_EXT_UXTB = 1;
public static final int ARM64_EXT_UXTH = 2;
@@ -19,7 +19,7 @@
public static final int ARM64_EXT_SXTH = 6;
public static final int ARM64_EXT_SXTW = 7;
public static final int ARM64_EXT_SXTX = 8;
-
+ // ARM64 condition code
public static final int ARM64_CC_INVALID = 0;
public static final int ARM64_CC_EQ = 1;
public static final int ARM64_CC_NE = 2;
@@ -37,14 +37,14 @@
public static final int ARM64_CC_LE = 14;
public static final int ARM64_CC_AL = 15;
public static final int ARM64_CC_NV = 16;
-
+ // Operand type for instruction's operands
public static final int ARM64_OP_INVALID = 0;
public static final int ARM64_OP_REG = 1;
public static final int ARM64_OP_CIMM = 2;
public static final int ARM64_OP_IMM = 3;
public static final int ARM64_OP_FP = 4;
public static final int ARM64_OP_MEM = 5;
-
+ // ARM64 registers
public static final int ARM64_REG_INVALID = 0;
public static final int ARM64_REG_NZCV = 1;
public static final int ARM64_REG_WSP = 2;
@@ -274,7 +274,7 @@
public static final int ARM64_REG_X29 = 226;
public static final int ARM64_REG_X30 = 227;
public static final int ARM64_REG_MAX = 228;
-
+ // ARM64 instruction
public static final int ARM64_INS_INVALID = 0;
public static final int ARM64_INS_ADC = 1;
public static final int ARM64_INS_ADDHN2 = 2;
@@ -642,7 +642,7 @@
public static final int ARM64_INS_NGC = 364;
public static final int ARM64_INS_NEG = 365;
public static final int ARM64_INS_MAX = 366;
-
+ // Group of ARM64 instructions
public static final int ARM64_GRP_INVALID = 0;
public static final int ARM64_GRP_NEON = 1;
public static final int ARM64_GRP_JUMP = 2;
diff --git a/bindings/java/capstone/Arm_const.java b/bindings/java/capstone/Arm_const.java
index 3dacba3..f7ac60d 100644
--- a/bindings/java/capstone/Arm_const.java
+++ b/bindings/java/capstone/Arm_const.java
@@ -2,7 +2,7 @@
package capstone;
public class Arm_const {
-
+ // ARM shift type
public static final int ARM_SFT_INVALID = 0;
public static final int ARM_SFT_ASR = 1;
public static final int ARM_SFT_LSL = 2;
@@ -14,7 +14,7 @@
public static final int ARM_SFT_LSR_REG = 8;
public static final int ARM_SFT_ROR_REG = 9;
public static final int ARM_SFT_RRX_REG = 10;
-
+ // ARM condition code
public static final int ARM_CC_INVALID = 0;
public static final int ARM_CC_EQ = 1;
public static final int ARM_CC_NE = 2;
@@ -31,7 +31,7 @@
public static final int ARM_CC_GT = 13;
public static final int ARM_CC_LE = 14;
public static final int ARM_CC_AL = 15;
-
+ // Operand type for instruction's operands
public static final int ARM_OP_INVALID = 0;
public static final int ARM_OP_REG = 1;
public static final int ARM_OP_CIMM = 2;
@@ -39,7 +39,7 @@
public static final int ARM_OP_IMM = 4;
public static final int ARM_OP_FP = 5;
public static final int ARM_OP_MEM = 6;
-
+ // ARM registers
public static final int ARM_REG_INVALID = 0;
public static final int ARM_REG_APSR = 1;
public static final int ARM_REG_APSR_NZCV = 2;
@@ -155,7 +155,7 @@
public static final int ARM_REG_R13 = ARM_REG_SP;
public static final int ARM_REG_R14 = ARM_REG_LR;
public static final int ARM_REG_R15 = ARM_REG_PC;
-
+ // ARM instruction
public static final int ARM_INS_INVALID = 0;
public static final int ARM_INS_ADC = 1;
public static final int ARM_INS_ADD = 2;
@@ -579,7 +579,7 @@
public static final int ARM_INS_POP = 420;
public static final int ARM_INS_PUSH = 421;
public static final int ARM_INS_MAX = 422;
-
+ // Group of ARM instructions
public static final int ARM_GRP_INVALID = 0;
public static final int ARM_GRP_CRYPTO = 1;
public static final int ARM_GRP_DATABARRIER = 2;
diff --git a/bindings/java/capstone/Mips_const.java b/bindings/java/capstone/Mips_const.java
index ec4dbbe..1571d12 100644
--- a/bindings/java/capstone/Mips_const.java
+++ b/bindings/java/capstone/Mips_const.java
@@ -2,12 +2,12 @@
package capstone;
public class Mips_const {
-
+ // Operand type for instruction's operands
public static final int MIPS_OP_INVALID = 0;
public static final int MIPS_OP_REG = 1;
public static final int MIPS_OP_IMM = 2;
public static final int MIPS_OP_MEM = 3;
-
+ // MIPS registers
public static final int MIPS_REG_INVALID = 0;
public static final int MIPS_REG_0 = 1;
public static final int MIPS_REG_1 = 2;
@@ -170,7 +170,7 @@
public static final int MIPS_REG_LO1 = MIPS_REG_HI1;
public static final int MIPS_REG_LO2 = MIPS_REG_HI2;
public static final int MIPS_REG_LO3 = MIPS_REG_HI3;
-
+ // MIPS instruction
public static final int MIPS_INS_INVALID = 0;
public static final int MIPS_INS_ABSQ_S = 1;
public static final int MIPS_INS_ADD = 2;
@@ -628,7 +628,7 @@
public static final int MIPS_INS_XORI = 454;
public static final int MIPS_INS_NOP = 455;
public static final int MIPS_INS_MAX = 456;
-
+ // Group of MIPS instructions
public static final int MIPS_GRP_INVALID = 0;
public static final int MIPS_GRP_BITCOUNT = 1;
public static final int MIPS_GRP_DSP = 2;
diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
index 3277c23..a20518b 100644
--- a/bindings/java/capstone/X86_const.java
+++ b/bindings/java/capstone/X86_const.java
@@ -2,7 +2,7 @@
package capstone;
public class X86_const {
-
+ // X86 registers
public static final int X86_REG_INVALID = 0;
public static final int X86_REG_AH = 1;
public static final int X86_REG_AL = 2;
@@ -237,13 +237,13 @@
public static final int X86_REG_R14W = 231;
public static final int X86_REG_R15W = 232;
public static final int X86_REG_MAX = 233;
-
+ // Operand type for instruction's operands
public static final int X86_OP_INVALID = 0;
public static final int X86_OP_REG = 1;
public static final int X86_OP_IMM = 2;
public static final int X86_OP_FP = 3;
public static final int X86_OP_MEM = 4;
-
+ // X86 instructions
public static final int X86_INS_INVALID = 0;
public static final int X86_INS_AAA = 1;
public static final int X86_INS_AAD = 2;
@@ -1491,7 +1491,7 @@
public static final int X86_INS_XSTORE = 1244;
public static final int X86_INS_XTEST = 1245;
public static final int X86_INS_MAX = 1246;
-
+ // Group of X86 instructions
public static final int X86_GRP_INVALID = 0;
public static final int X86_GRP_3DNOW = 1;
public static final int X86_GRP_AES = 2;
diff --git a/bindings/python/capstone/arm64_const.py b/bindings/python/capstone/arm64_const.py
index 3680126..4133724 100644
--- a/bindings/python/capstone/arm64_const.py
+++ b/bindings/python/capstone/arm64_const.py
@@ -1,12 +1,12 @@
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
-
+# ARM64 shift type
ARM64_SFT_INVALID = 0
ARM64_SFT_LSL = 1
ARM64_SFT_MSL = 2
ARM64_SFT_LSR = 3
ARM64_SFT_ASR = 4
ARM64_SFT_ROR = 5
-
+# ARM64 extender type
ARM64_EXT_INVALID = 0
ARM64_EXT_UXTB = 1
ARM64_EXT_UXTH = 2
@@ -16,7 +16,7 @@
ARM64_EXT_SXTH = 6
ARM64_EXT_SXTW = 7
ARM64_EXT_SXTX = 8
-
+# ARM64 condition code
ARM64_CC_INVALID = 0
ARM64_CC_EQ = 1
ARM64_CC_NE = 2
@@ -34,14 +34,14 @@
ARM64_CC_LE = 14
ARM64_CC_AL = 15
ARM64_CC_NV = 16
-
+# Operand type for instruction's operands
ARM64_OP_INVALID = 0
ARM64_OP_REG = 1
ARM64_OP_CIMM = 2
ARM64_OP_IMM = 3
ARM64_OP_FP = 4
ARM64_OP_MEM = 5
-
+# ARM64 registers
ARM64_REG_INVALID = 0
ARM64_REG_NZCV = 1
ARM64_REG_WSP = 2
@@ -271,7 +271,7 @@
ARM64_REG_X29 = 226
ARM64_REG_X30 = 227
ARM64_REG_MAX = 228
-
+# ARM64 instruction
ARM64_INS_INVALID = 0
ARM64_INS_ADC = 1
ARM64_INS_ADDHN2 = 2
@@ -639,7 +639,7 @@
ARM64_INS_NGC = 364
ARM64_INS_NEG = 365
ARM64_INS_MAX = 366
-
+# Group of ARM64 instructions
ARM64_GRP_INVALID = 0
ARM64_GRP_NEON = 1
ARM64_GRP_JUMP = 2
diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py
index dbd6252..7c3c139 100644
--- a/bindings/python/capstone/arm_const.py
+++ b/bindings/python/capstone/arm_const.py
@@ -1,5 +1,5 @@
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
-
+# ARM shift type
ARM_SFT_INVALID = 0
ARM_SFT_ASR = 1
ARM_SFT_LSL = 2
@@ -11,7 +11,7 @@
ARM_SFT_LSR_REG = 8
ARM_SFT_ROR_REG = 9
ARM_SFT_RRX_REG = 10
-
+# ARM condition code
ARM_CC_INVALID = 0
ARM_CC_EQ = 1
ARM_CC_NE = 2
@@ -28,7 +28,7 @@
ARM_CC_GT = 13
ARM_CC_LE = 14
ARM_CC_AL = 15
-
+# Operand type for instruction's operands
ARM_OP_INVALID = 0
ARM_OP_REG = 1
ARM_OP_CIMM = 2
@@ -36,7 +36,7 @@
ARM_OP_IMM = 4
ARM_OP_FP = 5
ARM_OP_MEM = 6
-
+# ARM registers
ARM_REG_INVALID = 0
ARM_REG_APSR = 1
ARM_REG_APSR_NZCV = 2
@@ -152,7 +152,7 @@
ARM_REG_R13 = ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC
-
+# ARM instruction
ARM_INS_INVALID = 0
ARM_INS_ADC = 1
ARM_INS_ADD = 2
@@ -576,7 +576,7 @@
ARM_INS_POP = 420
ARM_INS_PUSH = 421
ARM_INS_MAX = 422
-
+# Group of ARM instructions
ARM_GRP_INVALID = 0
ARM_GRP_CRYPTO = 1
ARM_GRP_DATABARRIER = 2
diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py
index 408ba7c..553d018 100644
--- a/bindings/python/capstone/mips_const.py
+++ b/bindings/python/capstone/mips_const.py
@@ -1,10 +1,10 @@
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
-
+# Operand type for instruction's operands
MIPS_OP_INVALID = 0
MIPS_OP_REG = 1
MIPS_OP_IMM = 2
MIPS_OP_MEM = 3
-
+# MIPS registers
MIPS_REG_INVALID = 0
MIPS_REG_0 = 1
MIPS_REG_1 = 2
@@ -167,7 +167,7 @@
MIPS_REG_LO1 = MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3
-
+# MIPS instruction
MIPS_INS_INVALID = 0
MIPS_INS_ABSQ_S = 1
MIPS_INS_ADD = 2
@@ -625,7 +625,7 @@
MIPS_INS_XORI = 454
MIPS_INS_NOP = 455
MIPS_INS_MAX = 456
-
+# Group of MIPS instructions
MIPS_GRP_INVALID = 0
MIPS_GRP_BITCOUNT = 1
MIPS_GRP_DSP = 2
diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
index bfaea07..340b01d 100644
--- a/bindings/python/capstone/x86_const.py
+++ b/bindings/python/capstone/x86_const.py
@@ -1,5 +1,5 @@
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
-
+# X86 registers
X86_REG_INVALID = 0
X86_REG_AH = 1
X86_REG_AL = 2
@@ -234,13 +234,13 @@
X86_REG_R14W = 231
X86_REG_R15W = 232
X86_REG_MAX = 233
-
+# Operand type for instruction's operands
X86_OP_INVALID = 0
X86_OP_REG = 1
X86_OP_IMM = 2
X86_OP_FP = 3
X86_OP_MEM = 4
-
+# X86 instructions
X86_INS_INVALID = 0
X86_INS_AAA = 1
X86_INS_AAD = 2
@@ -1488,7 +1488,7 @@
X86_INS_XSTORE = 1244
X86_INS_XTEST = 1245
X86_INS_MAX = 1246
-
+# Group of X86 instructions
X86_GRP_INVALID = 0
X86_GRP_3DNOW = 1
X86_GRP_AES = 2
diff --git a/include/arm.h b/include/arm.h
index d9d7487..7a81f90 100644
--- a/include/arm.h
+++ b/include/arm.h
@@ -11,6 +11,7 @@
#include <stdint.h>
#include <stdbool.h>
+//> ARM shift type
typedef enum arm_shifter {
ARM_SFT_INVALID = 0,
ARM_SFT_ASR, // shift with immediate const
@@ -25,7 +26,7 @@
ARM_SFT_RRX_REG, // shift with register
} arm_shifter;
-// ARM condition code
+//> ARM condition code
typedef enum arm_cc {
ARM_CC_INVALID = 0,
ARM_CC_EQ, // Equal Equal
@@ -45,7 +46,7 @@
ARM_CC_AL // Always (unconditional) Always (unconditional)
} arm_cc;
-// Operand type for instruction's operands
+//> Operand type for instruction's operands
typedef enum arm_op_type {
ARM_OP_INVALID = 0, // Uninitialized.
ARM_OP_REG, // Register operand.
@@ -93,7 +94,7 @@
cs_arm_op operands[20]; // operands for this instruction.
} cs_arm;
-// ARM registers
+//> ARM registers
typedef enum arm_reg {
ARM_REG_INVALID = 0,
ARM_REG_APSR,
@@ -215,7 +216,7 @@
ARM_REG_R15 = ARM_REG_PC,
} arm_reg;
-// ARM instruction
+//> ARM instruction
typedef enum arm_insn {
ARM_INS_INVALID = 0,
ARM_INS_ADC,
@@ -642,7 +643,7 @@
ARM_INS_MAX,
} arm_insn;
-// group of ARM instructions
+//> Group of ARM instructions
typedef enum arm_insn_group {
ARM_GRP_INVALID = 0,
ARM_GRP_CRYPTO,
diff --git a/include/arm64.h b/include/arm64.h
index 2872c43..ca1d203 100644
--- a/include/arm64.h
+++ b/include/arm64.h
@@ -11,6 +11,7 @@
#include <stdint.h>
#include <stdbool.h>
+//> ARM64 shift type
typedef enum arm64_shifter {
ARM64_SFT_INVALID = 0,
ARM64_SFT_LSL = 1,
@@ -20,6 +21,7 @@
ARM64_SFT_ROR = 5,
} arm64_shifter;
+//> ARM64 extender type
typedef enum arm64_extender {
ARM64_EXT_INVALID = 0,
ARM64_EXT_UXTB = 1,
@@ -32,7 +34,7 @@
ARM64_EXT_SXTX = 8,
} arm64_extender;
-// ARM64 condition code
+//> ARM64 condition code
typedef enum arm64_cc {
ARM64_CC_INVALID = 0,
ARM64_CC_EQ = 1, // Equal
@@ -55,7 +57,7 @@
// is "always".
} arm64_cc;
-// Operand type for instruction's operands
+//> Operand type for instruction's operands
typedef enum arm64_op_type {
ARM64_OP_INVALID = 0, // Uninitialized.
ARM64_OP_REG, // Register operand.
@@ -102,7 +104,7 @@
cs_arm64_op operands[8]; // operands for this instruction.
} cs_arm64;
-// ARM64 registers
+//> ARM64 registers
typedef enum arm64_reg {
ARM64_REG_INVALID = 0,
ARM64_REG_NZCV = 1,
@@ -336,7 +338,7 @@
ARM64_REG_MAX = 228, // <-- mark the end of the list of registers
} arm64_reg;
-// ARM64 instruction
+//> ARM64 instruction
typedef enum arm64_insn {
ARM64_INS_INVALID = 0,
ARM64_INS_ADC,
@@ -710,7 +712,7 @@
ARM64_INS_MAX,
} arm64_insn;
-// group of ARM64 instructions
+//> Group of ARM64 instructions
typedef enum arm64_insn_group {
ARM64_GRP_INVALID = 0,
ARM64_GRP_NEON,
diff --git a/include/mips.h b/include/mips.h
index 972bd13..073224d 100644
--- a/include/mips.h
+++ b/include/mips.h
@@ -11,7 +11,7 @@
#include <stdint.h>
#include <stdbool.h>
-// Operand type for instruction's operands
+//> Operand type for instruction's operands
typedef enum mips_op_type {
MIPS_OP_INVALID = 0, // Uninitialized.
MIPS_OP_REG, // Register operand.
@@ -44,7 +44,7 @@
cs_mips_op operands[8]; // operands for this instruction.
} cs_mips;
-// MIPS registers
+//> MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
// General purpose registers
@@ -224,7 +224,7 @@
MIPS_REG_LO3 = MIPS_REG_HI3,
} mips_reg;
-// MIPS instruction
+//> MIPS instruction
typedef enum mips_insn {
MIPS_INS_INVALID = 0,
MIPS_INS_ABSQ_S = 1,
@@ -688,7 +688,7 @@
MIPS_INS_MAX,
} mips_insn;
-// group of MIPS instructions
+//> Group of MIPS instructions
typedef enum mips_insn_group {
MIPS_GRP_INVALID = 0,
MIPS_GRP_BITCOUNT,
diff --git a/include/x86.h b/include/x86.h
index 0fa2a1f..392f09c 100644
--- a/include/x86.h
+++ b/include/x86.h
@@ -13,6 +13,7 @@
// Calculate relative address for X86-64, given cs_insn structure
#define X86_REL_ADDR(insn) (insn.addr + insn.size + insn.x86.disp)
+//> X86 registers
typedef enum x86_reg {
X86_REG_INVALID = 0,
X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL,
@@ -66,7 +67,7 @@
X86_REG_MAX // <-- mark the end of the list of registers
} x86_reg;
-// Operand type for instruction's operands
+//> Operand type for instruction's operands
typedef enum x86_op_type {
X86_OP_INVALID = 0, // Uninitialized.
X86_OP_REG, // Register operand.
@@ -147,6 +148,7 @@
cs_x86_op operands[8]; // operands for this instruction.
} cs_x86;
+//> X86 instructions
typedef enum x86_insn {
X86_INS_INVALID = 0,
X86_INS_AAA = 1,
@@ -1397,7 +1399,7 @@
X86_INS_MAX,
} x86_insn;
-// group of X86 instructions
+//> Group of X86 instructions
typedef enum x86_insn_group {
X86_GRP_INVALID = 0,
X86_GRP_3DNOW,