ocaml/python/java: fix some broken arm64 constants generated by const_generator.py
diff --git a/bindings/java/capstone/Arm64_const.java b/bindings/java/capstone/Arm64_const.java
index 347dc0d..d4fb509 100644
--- a/bindings/java/capstone/Arm64_const.java
+++ b/bindings/java/capstone/Arm64_const.java
@@ -140,7 +140,7 @@
public static final int ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b;
public static final int ARM64_SYSREG_ICH_VTR_EL2 = 0xe659;
public static final int ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b;
- public static final int ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d//1110011001011101;
+ public static final int ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d;
// System registers for MSR
public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;
@@ -153,7 +153,7 @@
public static final int ARM64_SYSREG_ICC_DIR_EL1 = 0xc659;
public static final int ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d;
public static final int ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e;
- public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f//1100011001011111;
+ public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f;
// System PState Field (MSR instruction)
diff --git a/bindings/ocaml/arm64_const.ml b/bindings/ocaml/arm64_const.ml
index 63e2c6c..847c476 100644
--- a/bindings/ocaml/arm64_const.ml
+++ b/bindings/ocaml/arm64_const.ml
@@ -137,7 +137,7 @@
let _ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b;;
let _ARM64_SYSREG_ICH_VTR_EL2 = 0xe659;;
let _ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b;;
-let _ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d//1110011001011101;;
+let _ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d;;
(* System registers for MSR *)
let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;;
@@ -150,7 +150,7 @@
let _ARM64_SYSREG_ICC_DIR_EL1 = 0xc659;;
let _ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d;;
let _ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e;;
-let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f//1100011001011111;;
+let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f;;
(* System PState Field (MSR instruction) *)
diff --git a/bindings/python/capstone/arm64_const.py b/bindings/python/capstone/arm64_const.py
index c2f47e3..9cbb413 100644
--- a/bindings/python/capstone/arm64_const.py
+++ b/bindings/python/capstone/arm64_const.py
@@ -137,7 +137,7 @@
ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b
ARM64_SYSREG_ICH_VTR_EL2 = 0xe659
ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b
-ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d//1110011001011101
+ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d
# System registers for MSR
ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828
@@ -150,7 +150,7 @@
ARM64_SYSREG_ICC_DIR_EL1 = 0xc659
ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d
ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e
-ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f//1100011001011111
+ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f
# System PState Field (MSR instruction)
diff --git a/include/arm64.h b/include/arm64.h
index 9dcdc39..39b3d6d 100644
--- a/include/arm64.h
+++ b/include/arm64.h
@@ -160,7 +160,7 @@
ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
- ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
+ ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
} arm64_sysreg;
typedef enum arm64_msr_reg {
@@ -179,7 +179,7 @@
ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
- ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111
} arm64_msr_reg;
//> System PState Field (MSR instruction)