Merge branch 'next' into msvc2
diff --git a/MathExtras.h b/MathExtras.h
index 605ce8e..e4d4bdf 100644
--- a/MathExtras.h
+++ b/MathExtras.h
@@ -23,6 +23,12 @@
# include <intrin.h>
#endif
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
// NOTE: The following support functions use the _32/_64 extensions instead of
// type overloading so that signed and unsigned integers can be used without
// ambiguity.
diff --git a/SStream.c b/SStream.c
index eebe52b..ec5a363 100644
--- a/SStream.c
+++ b/SStream.c
@@ -18,9 +18,9 @@
{
#ifndef CAPSTONE_DIET
va_list ap;
-
+ int ret = 0;
va_start(ap, fmt);
- int ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+ ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
va_end(ap);
ss->index += ret;
#endif
diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c
index e95e0ff..5f7dc2a 100644
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@@ -14,6 +14,7 @@
/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+#define _CRT_SECURE_NO_WARNINGS
#include "../../utils.h"
#include <stdio.h>
@@ -39,11 +40,12 @@
// return true if s1 == lower(f2), and false otherwise
static bool compare_lower_str(char *s1, char *s2)
{
+ bool res;
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
*c = (char)tolower((int) *c);
- bool res = (strcmp(s1, lower) == 0);
+ res = (strcmp(s1, lower) == 0);
cs_mem_free(lower);
return res;
@@ -74,6 +76,7 @@
{
char Buffer[22];
char *BufPtr = Buffer+21;
+ char *result = NULL;
Buffer[21] = '\0';
if (X == 0) *--BufPtr = '0'; // Handle special case...
@@ -85,7 +88,7 @@
if (isNeg) *--BufPtr = '-'; // Add negative sign...
- char *result = cs_strdup(BufPtr);
+ result = cs_strdup(BufPtr);
return result;
}
@@ -571,7 +574,11 @@
// result must be a big enough buffer: 128 bytes is more than enough
void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
{
+ int dummy = 0;
+ uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
+ char *Op1S = NULL, *CRnS = NULL, *CRmS = NULL, *Op2S = NULL;
unsigned i;
+
for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
if (SysRegPairs[i].Value == Bits) {
*Valid = true;
@@ -588,11 +595,11 @@
}
}
- uint32_t Op0 = (Bits >> 14) & 0x3;
- uint32_t Op1 = (Bits >> 11) & 0x7;
- uint32_t CRn = (Bits >> 7) & 0xf;
- uint32_t CRm = (Bits >> 3) & 0xf;
- uint32_t Op2 = Bits & 0x7;
+ Op0 = (Bits >> 14) & 0x3;
+ Op1 = (Bits >> 11) & 0x7;
+ CRn = (Bits >> 7) & 0xf;
+ CRm = (Bits >> 3) & 0xf;
+ Op2 = Bits & 0x7;
// Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
// name.
@@ -605,14 +612,13 @@
*Valid = true;
- char *Op1S, *CRnS, *CRmS, *Op2S;
Op1S = utostr(Op1, false);
CRnS = utostr(CRn, false);
CRmS = utostr(CRm, false);
Op2S = utostr(Op2, false);
//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
- int dummy = sprintf(result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+ dummy = sprintf(result, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
(void)dummy;
cs_mem_free(Op1S);
@@ -657,9 +663,9 @@
};
NamedImmMapper A64TLBI_TLBIMapper = {
- .Pairs = TLBIPairs,
- .NumPairs = ARR_SIZE(TLBIPairs),
- .TooBigImm = 0,
+ TLBIPairs,
+ ARR_SIZE(TLBIPairs),
+ 0,
};
static NamedImmMapper_Mapping ATPairs[] = {
@@ -678,9 +684,9 @@
};
NamedImmMapper A64AT_ATMapper = {
- .Pairs = ATPairs,
- .NumPairs = ARR_SIZE(ATPairs),
- .TooBigImm = 0,
+ ATPairs,
+ ARR_SIZE(ATPairs),
+ 0,
};
static NamedImmMapper_Mapping DBarrierPairs[] = {
@@ -699,9 +705,9 @@
};
NamedImmMapper A64DB_DBarrierMapper = {
- .Pairs = DBarrierPairs,
- .NumPairs = ARR_SIZE(DBarrierPairs),
- .TooBigImm = 16,
+ DBarrierPairs,
+ ARR_SIZE(DBarrierPairs),
+ 16,
};
static NamedImmMapper_Mapping DCPairs[] = {
@@ -716,9 +722,9 @@
};
NamedImmMapper A64DC_DCMapper = {
- .Pairs = DCPairs,
- .NumPairs = ARR_SIZE(DCPairs),
- .TooBigImm = 0,
+ DCPairs,
+ ARR_SIZE(DCPairs),
+ 0,
};
static NamedImmMapper_Mapping ICPairs[] = {
@@ -728,9 +734,9 @@
};
NamedImmMapper A64IC_ICMapper = {
- .Pairs = ICPairs,
- .NumPairs = ARR_SIZE(ICPairs),
- .TooBigImm = 0,
+ ICPairs,
+ ARR_SIZE(ICPairs),
+ 0,
};
static NamedImmMapper_Mapping ISBPairs[] = {
@@ -738,9 +744,9 @@
};
NamedImmMapper A64ISB_ISBMapper = {
- .Pairs = ISBPairs,
- .NumPairs = ARR_SIZE(ISBPairs),
- .TooBigImm = 16,
+ ISBPairs,
+ ARR_SIZE(ISBPairs),
+ 16,
};
static NamedImmMapper_Mapping PRFMPairs[] = {
@@ -765,9 +771,9 @@
};
NamedImmMapper A64PRFM_PRFMMapper = {
- .Pairs = PRFMPairs,
- .NumPairs = ARR_SIZE(PRFMPairs),
- .TooBigImm = 32,
+ PRFMPairs,
+ ARR_SIZE(PRFMPairs),
+ 32,
};
static NamedImmMapper_Mapping PStatePairs[] = {
@@ -777,9 +783,9 @@
};
NamedImmMapper A64PState_PStateMapper = {
- .Pairs = PStatePairs,
- .NumPairs = ARR_SIZE(PStatePairs),
- .TooBigImm = 0,
+ PStatePairs,
+ ARR_SIZE(PStatePairs),
+ 0,
};
static NamedImmMapper_Mapping MRSPairs[] = {
@@ -882,8 +888,9 @@
};
SysRegMapper AArch64_MRSMapper = {
- .InstPairs = MRSPairs,
- .NumInstPairs = ARR_SIZE(MRSPairs),
+ NULL,
+ MRSPairs,
+ ARR_SIZE(MRSPairs),
};
static NamedImmMapper_Mapping MSRPairs[] = {
@@ -905,8 +912,9 @@
};
SysRegMapper AArch64_MSRMapper = {
- .InstPairs = MSRPairs,
- .NumInstPairs = ARR_SIZE(MSRPairs),
+ NULL,
+ MSRPairs,
+ ARR_SIZE(MSRPairs),
};
// Encoding of the immediate for logical (immediate) instructions:
@@ -935,12 +943,14 @@
uint32_t N = Bits >> 12;
uint32_t ImmR = (Bits >> 6) & 0x3f;
uint32_t ImmS = Bits & 0x3f;
+ uint64_t Mask = 0, WidthMask = 0;
+ unsigned i = 0;
+ int Width = 0, Num1s = 0, Rotation = 0;
// N=1 encodes a 64-bit replication and is invalid for the 32-bit
// instructions.
if (RegWidth == 32 && N != 0) return false;
- int Width = 0;
if (N == 1)
Width = 64;
else if ((ImmS & 0x20) == 0)
@@ -958,20 +968,19 @@
return false;
}
- int Num1s = (ImmS & (Width - 1)) + 1;
+ Num1s = (ImmS & (Width - 1)) + 1;
// All encodings which would map to -1 (signed) are RESERVED.
if (Num1s == Width) return false;
- int Rotation = (ImmR & (Width - 1));
- uint64_t Mask = (1ULL << Num1s) - 1;
- uint64_t WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1;
+ Rotation = (ImmR & (Width - 1));
+ Mask = (1ULL << Num1s) - 1;
+ WidthMask = Width == 64 ? -1 : (1ULL << Width) - 1;
if (Rotation != 0 && Rotation != 64)
Mask = (Mask >> Rotation)
| ((Mask << (Width - Rotation)) & WidthMask);
*Imm = Mask;
- unsigned i;
for (i = 1; i < RegWidth / Width; ++i) {
Mask <<= Width;
*Imm |= Mask;
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 672232f..3fdd6f8 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -90,6 +90,11 @@
A64CC_Invalid
} A64CC_CondCodes;
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
inline static const char *A64CondCodeToString(A64CC_CondCodes CC)
{
switch (CC) {
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index de25cf3..ddac728 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -32,14 +32,12 @@
// Forward-declarations used in the auto-generated files.
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
-static DecodeStatus
-DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
+static DecodeStatus DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
-static DecodeStatus
-DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
+static DecodeStatus DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
@@ -262,13 +260,15 @@
uint16_t *Size,
uint64_t Address, MCRegisterInfo *MRI)
{
+ uint32_t insn = 0;
+ DecodeStatus result;
+
if (code_len < 4) {
// not enough data
*Size = 0;
return MCDisassembler_Fail;
}
- uint32_t insn;
if (ud->big_endian)
insn = (code[3] << 0) | (code[2] << 8) |
(code[1] << 16) | (code[0] << 24);
@@ -277,7 +277,7 @@
(code[1] << 8) | (code[0] << 0);
// Calling the auto-generated decoder function.
- DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, MRI, 0);
+ result = decodeInstruction(DecoderTableA6432, MI, insn, Address, MRI, 0);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
@@ -700,6 +700,7 @@
uint64_t Address,
void *Decoder)
{
+ unsigned ExtractOp = 0, InsertOp = 0;
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
@@ -759,7 +760,6 @@
// Otherwise it's definitely either an extract or an insert depending on which
// of ImmR or ImmS is larger.
- unsigned ExtractOp = 0, InsertOp = 0;
switch (Opc) {
default: break; // never reach
case SBFM:
@@ -1166,6 +1166,7 @@
// TransferBytes = NumVecs * OneLaneBytes
unsigned TransferBytes = 0;
unsigned NumVecs = 0;
+ unsigned Rt = 0, Rn = 0, Rm = 0, Q = 0, S = 0, lane = 0, NumLanes = 0;
unsigned Opc = MCInst_getOpcode(Inst);
switch (Opc) {
case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
@@ -1492,9 +1493,9 @@
return MCDisassembler_Fail;
} // End of switch (Opc)
- unsigned Rt = fieldFromInstruction(Insn, 0, 5);
- unsigned Rn = fieldFromInstruction(Insn, 5, 5);
- unsigned Rm = fieldFromInstruction(Insn, 16, 5);
+ Rt = fieldFromInstruction(Insn, 0, 5);
+ Rn = fieldFromInstruction(Insn, 5, 5);
+ Rm = fieldFromInstruction(Insn, 16, 5);
// Decode post-index of load duplicate lane
if (IsLoadDup) {
@@ -1571,12 +1572,12 @@
}
// Decode lane
- unsigned Q = fieldFromInstruction(Insn, 30, 1);
- unsigned S = fieldFromInstruction(Insn, 10, 3);
- unsigned lane = 0;
+ Q = fieldFromInstruction(Insn, 30, 1);
+ S = fieldFromInstruction(Insn, 10, 3);
+ lane = 0;
// Calculate the number of lanes by number of vectors and transfered bytes.
// NumLanes = 16 bytes / bytes of each lane
- unsigned NumLanes = 16 / (TransferBytes / NumVecs);
+ NumLanes = 16 / (TransferBytes / NumVecs);
switch (NumLanes) {
case 16: // A vector has 16 lanes, each lane is 1 bytes.
lane = (Q << 3) | S;
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index 0de6bf8..415bb6f 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -8871,6 +8871,7 @@
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
const char *AsmString;
+ char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return NULL;
@@ -11316,7 +11317,7 @@
return NULL;
}
- char *tmp = cs_strdup(AsmString), *AsmMnem, *AsmOps;
+ tmp = cs_strdup(AsmString);
AsmMnem = tmp;
AsmOps = strchr(tmp, ' ');
if (AsmOps) {
@@ -11326,7 +11327,6 @@
SStream_concat(OS, "%s", AsmMnem);
if (AsmOps) {
SStream_concat(OS, "\t");
- char *c;
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc
index 0149755..9487a80 100644
--- a/arch/AArch64/AArch64GenDisassemblerTables.inc
+++ b/arch/AArch64/AArch64GenDisassemblerTables.inc
@@ -14036,48 +14036,48 @@
{ \
uint64_t Bits = getFeatureBits(feature); \
uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
+ uint32_t CurFieldValue = 0, ExpectedValue = 0; \
DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
for (;;) { \
switch (*Ptr) { \
default: \
return MCDisassembler_Fail; \
case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
++Ptr; \
CurFieldValue = fieldname(insn, Start, Len); \
break; \
} \
case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (Val != CurFieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
@@ -14085,21 +14085,19 @@
break; \
} \
case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
+ DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \
S = MCDisassembler_SoftFail; \
break; \
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index d5926d2..97a391a 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -315,7 +315,8 @@
SStream *O, unsigned field_width, unsigned scale)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
+ uint64_t UImm = 0, Sign = 0, SImm = 0;
+ int64_t tmp = 0;
if (!MCOperand_isImm(MO)) {
printOperand(MI, OpNum, O);
return;
@@ -323,9 +324,9 @@
// The immediate of LDR (lit) instructions is a signed 19-bit immediate, which
// is multiplied by 4 (because all A64 instructions are 32-bits wide).
- uint64_t UImm = MCOperand_getImm(MO);
- uint64_t Sign = UImm & (1LL << (field_width - 1));
- int64_t SImm = scale * ((UImm & ~Sign) - Sign);
+ UImm = MCOperand_getImm(MO);
+ Sign = UImm & (1LL << (field_width - 1));
+ SImm = scale * ((UImm & ~Sign) - Sign);
// this is a relative address, so add with the address
// of current instruction
@@ -343,10 +344,11 @@
else
SStream_concat(O, "#%"PRIu64, SImm);
} else {
+ tmp = -(int64_t)SImm;
if (SImm < -HEX_THRESHOLD)
- SStream_concat(O, "#-0x%"PRIx64, -SImm);
+ SStream_concat(O, "#-0x%"PRIx64, tmp);
else
- SStream_concat(O, "#-%"PRIu64, -SImm);
+ SStream_concat(O, "#-%"PRIu64, tmp);
}
}
@@ -396,7 +398,7 @@
SStream *O, A64SE_ShiftExtSpecifiers Shift)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
+ unsigned int imm = 0;
// LSL #0 is not printed
if (Shift == A64SE_LSL && MCOperand_isImm(MO) && MCOperand_getImm(MO) == 0)
return;
@@ -409,7 +411,7 @@
default: break; // llvm_unreachable("Invalid shift specifier in logical instruction");
}
- unsigned int imm = (unsigned int)MCOperand_getImm(MO);
+ imm = (unsigned int)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", imm);
else
@@ -657,7 +659,7 @@
SStream *O, A64SE_ShiftExtSpecifiers Ext, bool isHalf)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
+ int64_t Imm = 0;
//assert(MO.isImm() &&
// "Immediate operand required for Neon vector immediate inst.");
@@ -668,7 +670,7 @@
//llvm_unreachable("Invalid shift specifier in movi instruction");
}
- int64_t Imm = MCOperand_getImm(MO);
+ Imm = MCOperand_getImm(MO);
// MSL and LSLH accepts encoded shift amount 0 or 1.
if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1) {
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
index daf52e4..118588f 100644
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@@ -148,16 +148,17 @@
/// take a maximal chunk of bits out of the immediate.
static inline unsigned getSOImmValRotate(unsigned Imm)
{
+ unsigned TZ = 0, RotAmt = 0;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Imm & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
- unsigned TZ = CountTrailingZeros_32(Imm);
+ TZ = CountTrailingZeros_32(Imm);
// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
// not 9.
- unsigned RotAmt = TZ & ~1;
+ RotAmt = TZ & ~1;
// If we can handle this spread, return it.
if ((rotr32(Imm, RotAmt) & ~255U) == 0)
@@ -183,11 +184,12 @@
/// it. If not, return -1.
static inline int getSOImmVal(unsigned Arg)
{
+ unsigned RotAmt = 0;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Arg & ~255U) == 0) return Arg;
- unsigned RotAmt = getSOImmValRotate(Arg);
+ RotAmt = getSOImmValRotate(Arg);
// If this cannot be handled with a single shifter_op, bail out.
if (rotr32(~255U, RotAmt) & Arg)
@@ -337,13 +339,14 @@
/// See ARM Reference Manual A6.3.2.
static inline int getT2SOImmVal(unsigned Arg)
{
+ int Rot = 0;
// If 'Arg' is an 8-bit splat, then get the encoded value.
int Splat = getT2SOImmValSplatVal(Arg);
if (Splat != -1)
return Splat;
// If 'Arg' can be handled with a single shifter_op return the value.
- int Rot = getT2SOImmValRotateVal(Arg);
+ Rot = getT2SOImmValRotateVal(Arg);
if (Rot != -1)
return Rot;
@@ -352,9 +355,10 @@
static inline unsigned getT2SOImmValRotate(unsigned V)
{
+ unsigned RotAmt = 0;
if ((V & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
- unsigned RotAmt = CountTrailingZeros_32(V);
+ RotAmt = CountTrailingZeros_32(V);
return (32 - RotAmt) & 31;
}
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index fa36066..663d9f9 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -437,7 +437,9 @@
static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
uint16_t *Size, uint64_t Address)
{
+ uint32_t insn = 0;
uint8_t bytes[4];
+ DecodeStatus result;
ud->ITBlock.size = 0;
@@ -447,7 +449,6 @@
memcpy(bytes, code, 4);
- uint32_t insn;
if (ud->big_endian)
insn = (bytes[3] << 0) |
(bytes[2] << 8) |
@@ -460,7 +461,7 @@
(bytes[0] << 0);
// Calling the auto-generated decoder function.
- DecodeStatus result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
+ result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
@@ -567,6 +568,7 @@
MCOperandInfo *OpInfo;
unsigned short NumOps;
unsigned int i;
+ unsigned CC;
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
@@ -604,7 +606,6 @@
// If we're in an IT block, base the predicate on that. Otherwise,
// assume a predicate of AL.
- unsigned CC;
CC = ITStatus_getITCC(&(ud->ITBlock));
if (CC == 0xF)
CC = ARMCC_AL;
@@ -670,6 +671,11 @@
uint16_t *Size, uint64_t Address)
{
uint8_t bytes[4];
+ uint16_t insn16 = 0;
+ DecodeStatus result;
+ bool InITBlock;
+ unsigned Firstcond = 0, Mask = 0;
+ uint32_t NEONLdStInsn = 0, insn32 = 0, NEONDataInsn = 0, NEONCryptoInsn = 0, NEONv8Insn = 0;
ud->ITBlock.size = 0;
@@ -680,13 +686,12 @@
memcpy(bytes, code, 2);
- uint16_t insn16;
if (ud->big_endian)
insn16 = (bytes[0] << 8) | bytes[1];
else
insn16 = (bytes[1] << 8) | bytes[0];
- DecodeStatus result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
+ result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
if (result != MCDisassembler_Fail) {
*Size = 2;
Check(&result, AddThumbPredicate(ud, MI));
@@ -697,7 +702,7 @@
result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode);
if (result) {
*Size = 2;
- bool InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
Check(&result, AddThumbPredicate(ud, MI));
AddThumb1SBit(MI, InITBlock);
return result;
@@ -720,8 +725,8 @@
// to the subsequent instructions.
if (MCInst_getOpcode(MI) == ARM_t2IT) {
- unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
- unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
+ Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
+ Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
}
@@ -735,7 +740,6 @@
memcpy(bytes, code, 4);
- uint32_t insn32;
if (ud->big_endian)
insn32 = (bytes[3] << 24) |
(bytes[2] << 16) |
@@ -751,7 +755,7 @@
result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
if (result != MCDisassembler_Fail) {
*Size = 4;
- bool InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
Check(&result, AddThumbPredicate(ud, MI));
AddThumb1SBit(MI, InITBlock);
return result;
@@ -802,7 +806,7 @@
if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
MCInst_clear(MI);
- uint32_t NEONLdStInsn = insn32;
+ NEONLdStInsn = insn32;
NEONLdStInsn &= 0xF0FFFFFF;
NEONLdStInsn |= 0x04000000;
result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode);
@@ -815,7 +819,7 @@
if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
MCInst_clear(MI);
- uint32_t NEONDataInsn = insn32;
+ NEONDataInsn = insn32;
NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
NEONDataInsn |= 0x12000000; // Set bits 28 and 25
@@ -828,7 +832,7 @@
}
MCInst_clear(MI);
- uint32_t NEONCryptoInsn = insn32;
+ NEONCryptoInsn = insn32;
NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
@@ -840,7 +844,7 @@
}
MCInst_clear(MI);
- uint32_t NEONv8Insn = insn32;
+ NEONv8Insn = insn32;
NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode);
if (result != MCDisassembler_Fail) {
@@ -881,10 +885,11 @@
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 15)
return MCDisassembler_Fail;
- unsigned Register = GPRDecoderTable[RegNo];
+ Register = GPRDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -932,6 +937,7 @@
static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned RegisterPair = 0;
DecodeStatus S = MCDisassembler_Success;
if (RegNo > 13)
@@ -940,7 +946,7 @@
if ((RegNo & 1) || RegNo == 0xe)
S = MCDisassembler_SoftFail;
- unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
+ RegisterPair = GPRPairDecoderTable[RegNo/2];
MCInst_addOperand(Inst, MCOperand_CreateReg(RegisterPair));
return S;
}
@@ -1000,10 +1006,11 @@
static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Register = SPRDecoderTable[RegNo];
+ Register = SPRDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -1022,10 +1029,11 @@
static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Register = DPRDecoderTable[RegNo];
+ Register = DPRDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -1057,11 +1065,12 @@
static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 31 || (RegNo & 1) != 0)
return MCDisassembler_Fail;
RegNo >>= 1;
- unsigned Register = QPRDecoderTable[RegNo];
+ Register = QPRDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -1078,10 +1087,11 @@
static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 30)
return MCDisassembler_Fail;
- unsigned Register = DPairDecoderTable[RegNo];
+ Register = DPairDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -1100,10 +1110,11 @@
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, const void *Decoder)
{
+ unsigned Register = 0;
if (RegNo > 29)
return MCDisassembler_Fail;
- unsigned Register = DPairSpacedDecoderTable[RegNo];
+ Register = DPairSpacedDecoderTable[RegNo];
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@@ -1133,7 +1144,7 @@
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_ShiftOpc Shift;
-
+ unsigned Op = 0;
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
unsigned imm = fieldFromInstruction_4(Val, 7, 5);
@@ -1161,7 +1172,7 @@
if (Shift == ARM_AM_ror && imm == 0)
Shift = ARM_AM_rrx;
- unsigned Op = Shift | (imm << 3);
+ Op = Shift | (imm << 3);
MCInst_addOperand(Inst, MCOperand_CreateImm(Op));
return S;
@@ -1207,6 +1218,7 @@
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder)
{
+ unsigned i = 0;
DecodeStatus S = MCDisassembler_Success;
bool NeedDisjointWriteback = false;
@@ -1229,7 +1241,6 @@
// Empty register lists are not allowed.
if (Val == 0) return MCDisassembler_Fail;
- unsigned i;
for (i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
@@ -1247,7 +1258,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned i = 0;
unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
unsigned regs = fieldFromInstruction_4(Val, 0, 8);
@@ -1260,7 +1271,6 @@
if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler_Fail;
- unsigned i;
for (i = 0; i < (regs - 1); ++i) {
if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
return MCDisassembler_Fail;
@@ -1273,7 +1283,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned i = 0;
unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
unsigned regs = fieldFromInstruction_4(Val, 1, 7);
@@ -1287,7 +1297,6 @@
if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler_Fail;
- unsigned i;
for (i = 0; i < (regs - 1); ++i) {
if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
return MCDisassembler_Fail;
@@ -1306,7 +1315,7 @@
// create the final mask.
unsigned msb = fieldFromInstruction_4(Val, 5, 5);
unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
- uint32_t lsb_mask;
+ uint32_t lsb_mask, msb_mask = 0;
DecodeStatus S = MCDisassembler_Success;
if (lsb > msb) {
@@ -1317,7 +1326,7 @@
lsb = msb;
}
- uint32_t msb_mask = 0xFFFFFFFF;
+ msb_mask = 0xFFFFFFFF;
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
lsb_mask = (1U << lsb) - 1;
@@ -1476,7 +1485,7 @@
DecodeStatus S = MCDisassembler_Success;
ARM_AM_AddrOpc Op;
ARM_AM_ShiftOpc Opc;
-
+ bool writeback;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
@@ -1485,6 +1494,7 @@
unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
unsigned P = fieldFromInstruction_4(Insn, 24, 1);
unsigned W = fieldFromInstruction_4(Insn, 21, 1);
+ unsigned idx_mode = 0, amt = 0, tmp = 0;
// On stores, the writeback operand precedes Rt.
switch (MCInst_getOpcode(Inst)) {
@@ -1530,8 +1540,7 @@
if (!fieldFromInstruction_4(Insn, 23, 1))
Op = ARM_AM_sub;
- bool writeback = (P == 0) || (W == 1);
- unsigned idx_mode = 0;
+ writeback = (P == 0) || (W == 1);
if (P && writeback)
idx_mode = ARMII_IndexModePre;
else if (!P && writeback)
@@ -1560,15 +1569,15 @@
default:
return MCDisassembler_Fail;
}
- unsigned amt = fieldFromInstruction_4(Insn, 7, 5);
+ amt = fieldFromInstruction_4(Insn, 7, 5);
if (Opc == ARM_AM_ror && amt == 0)
Opc = ARM_AM_rrx;
- unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
+ imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
MCInst_addOperand(Inst, MCOperand_CreateImm(imm));
} else {
MCInst_addOperand(Inst, MCOperand_CreateReg(0));
- unsigned tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
+ tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
MCInst_addOperand(Inst, MCOperand_CreateImm(tmp));
}
@@ -1583,7 +1592,7 @@
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_ShiftOpc ShOp;
-
+ unsigned shift = 0;
unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
@@ -1613,7 +1622,6 @@
return MCDisassembler_Fail;
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler_Fail;
- unsigned shift;
if (U)
shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0);
else
@@ -2248,13 +2256,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned wb = 0, Rn = 0, Rm = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+ wb = fieldFromInstruction_4(Insn, 16, 4);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
// First output register
switch (MCInst_getOpcode(Inst)) {
@@ -2522,13 +2530,14 @@
static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ unsigned load = 0;
unsigned type = fieldFromInstruction_4(Insn, 8, 4);
unsigned align = fieldFromInstruction_4(Insn, 4, 2);
if (type == 6 && (align & 2)) return MCDisassembler_Fail;
if (type == 7 && (align & 2)) return MCDisassembler_Fail;
if (type == 10 && align == 3) return MCDisassembler_Fail;
- unsigned load = fieldFromInstruction_4(Insn, 21, 1);
+ load = fieldFromInstruction_4(Insn, 21, 1);
return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
@@ -2536,15 +2545,16 @@
static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ unsigned type = 0, align = 0, load = 0;
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
if (size == 3) return MCDisassembler_Fail;
- unsigned type = fieldFromInstruction_4(Insn, 8, 4);
- unsigned align = fieldFromInstruction_4(Insn, 4, 2);
+ type = fieldFromInstruction_4(Insn, 8, 4);
+ align = fieldFromInstruction_4(Insn, 4, 2);
if (type == 8 && align == 3) return MCDisassembler_Fail;
if (type == 9 && align == 3) return MCDisassembler_Fail;
- unsigned load = fieldFromInstruction_4(Insn, 21, 1);
+ load = fieldFromInstruction_4(Insn, 21, 1);
return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
@@ -2552,13 +2562,14 @@
static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ unsigned align = 0, load = 0;
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
if (size == 3) return MCDisassembler_Fail;
- unsigned align = fieldFromInstruction_4(Insn, 4, 2);
+ align = fieldFromInstruction_4(Insn, 4, 2);
if (align & 2) return MCDisassembler_Fail;
- unsigned load = fieldFromInstruction_4(Insn, 21, 1);
+ load = fieldFromInstruction_4(Insn, 21, 1);
return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
@@ -2566,10 +2577,11 @@
static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ unsigned load = 0;
unsigned size = fieldFromInstruction_4(Insn, 6, 2);
if (size == 3) return MCDisassembler_Fail;
- unsigned load = fieldFromInstruction_4(Insn, 21, 1);
+ load = fieldFromInstruction_4(Insn, 21, 1);
return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
}
@@ -2578,13 +2590,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned wb = 0, Rn = 0, Rm = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+ wb = fieldFromInstruction_4(Insn, 16, 4);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
// Writeback Operand
switch (MCInst_getOpcode(Inst)) {
@@ -2850,13 +2862,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rn = 0, Rm = 0, align = 0, size = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
- unsigned align = fieldFromInstruction_4(Insn, 4, 1);
- unsigned size = fieldFromInstruction_4(Insn, 6, 2);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
+ align = fieldFromInstruction_4(Insn, 4, 1);
+ size = fieldFromInstruction_4(Insn, 6, 2);
if (size == 0 && align == 1)
return MCDisassembler_Fail;
@@ -2898,13 +2910,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rn = 0, Rm = 0, align = 0, size = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
- unsigned align = fieldFromInstruction_4(Insn, 4, 1);
- unsigned size = 1 << fieldFromInstruction_4(Insn, 6, 2);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
+ align = fieldFromInstruction_4(Insn, 4, 1);
+ size = 1 << fieldFromInstruction_4(Insn, 6, 2);
align *= 2*size;
switch (MCInst_getOpcode(Inst)) {
@@ -2947,12 +2959,12 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rn = 0, Rm = 0, inc = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
- unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler_Fail;
@@ -2983,14 +2995,14 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rn = 0, Rm = 0, size = 0, inc = 0, align = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
- unsigned size = fieldFromInstruction_4(Insn, 6, 2);
- unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
- unsigned align = fieldFromInstruction_4(Insn, 4, 1);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
+ size = fieldFromInstruction_4(Insn, 6, 2);
+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
+ align = fieldFromInstruction_4(Insn, 4, 1);
if (size == 0x3) {
if (align == 0)
@@ -3037,15 +3049,15 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned imm = 0, Q = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
+ imm = fieldFromInstruction_4(Insn, 0, 4);
imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
- unsigned Q = fieldFromInstruction_4(Insn, 6, 1);
+ Q = fieldFromInstruction_4(Insn, 6, 1);
if (Q) {
if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -3083,12 +3095,12 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rm = 0, size = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 18, 2);
+ size = fieldFromInstruction_4(Insn, 18, 2);
if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler_Fail;
@@ -3131,14 +3143,14 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Rn = 0, Rm = 0, op = 0;
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+ Rn = fieldFromInstruction_4(Insn, 16, 4);
Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
- unsigned op = fieldFromInstruction_4(Insn, 6, 1);
+ op = fieldFromInstruction_4(Insn, 6, 1);
if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler_Fail;
@@ -3294,7 +3306,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned addrmode = 0;
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@@ -3353,7 +3365,7 @@
return MCDisassembler_Fail;
}
- unsigned addrmode = fieldFromInstruction_4(Insn, 4, 2);
+ addrmode = fieldFromInstruction_4(Insn, 4, 2);
addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
@@ -3690,13 +3702,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned load = 0;
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
addr |= Rn << 9;
- unsigned load = fieldFromInstruction_4(Insn, 20, 1);
+ load = fieldFromInstruction_4(Insn, 20, 1);
if (Rn == 15) {
switch (MCInst_getOpcode(Inst)) {
@@ -3890,7 +3902,7 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned imm = 0, brtarget = 0;
unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
if (pred == 0xE || pred == 0xF) {
unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
@@ -3908,11 +3920,11 @@
break;
}
- unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
+ imm = fieldFromInstruction_4(Insn, 0, 4);
return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
}
- unsigned brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
+ brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
@@ -4070,13 +4082,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned pred = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
- unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+ pred = fieldFromInstruction_4(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
@@ -4096,14 +4108,14 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned pred = 0, Rm = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
- unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
- unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+ pred = fieldFromInstruction_4(Insn, 28, 4);
+ Rm = fieldFromInstruction_4(Insn, 0, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
if (Rm == 0xF) S = MCDisassembler_SoftFail;
@@ -4124,13 +4136,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned pred = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
- unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+ pred = fieldFromInstruction_4(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
@@ -4150,13 +4162,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned pred = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
- unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+ pred = fieldFromInstruction_4(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
@@ -4176,15 +4188,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4244,15 +4254,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4310,16 +4318,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4378,16 +4383,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4442,16 +4444,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4513,16 +4512,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4577,16 +4573,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4659,16 +4652,13 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned size = 0, align = 0, index = 0, inc = 1;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
- unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+ size = fieldFromInstruction_4(Insn, 10, 2);
- unsigned align = 0;
- unsigned index = 0;
- unsigned inc = 1;
switch (size) {
default:
return MCDisassembler_Fail;
@@ -4877,11 +4867,12 @@
static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn,
uint64_t Address, const void *Decoder)
{
+ unsigned Val = 0;
unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
if (sign1 != sign2) return MCDisassembler_Fail;
- unsigned Val = fieldFromInstruction_4(Insn, 0, 8);
+ Val = fieldFromInstruction_4(Insn, 0, 8);
Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
Val |= sign1 << 12;
@@ -4934,15 +4925,15 @@
static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ DecodeStatus S = MCDisassembler_Success;
+ unsigned Vm = 0, imm = 0, cmode = 0, op = 0;
unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
- unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
- unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
- unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
- unsigned op = fieldFromInstruction_4(Insn, 5, 1);
-
- DecodeStatus S = MCDisassembler_Success;
+ imm = fieldFromInstruction_4(Insn, 16, 6);
+ cmode = fieldFromInstruction_4(Insn, 8, 4);
+ op = fieldFromInstruction_4(Insn, 5, 1);
// VMOVv2f32 is ambiguous with these decodings.
if (!(imm & 0x38) && cmode == 0xF) {
@@ -4965,15 +4956,15 @@
static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
+ DecodeStatus S = MCDisassembler_Success;
+ unsigned Vm = 0, imm = 0, cmode = 0, op = 0;
unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
- unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
- unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
- unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
- unsigned op = fieldFromInstruction_4(Insn, 5, 1);
-
- DecodeStatus S = MCDisassembler_Success;
+ imm = fieldFromInstruction_4(Insn, 16, 6);
+ cmode = fieldFromInstruction_4(Insn, 8, 4);
+ op = fieldFromInstruction_4(Insn, 5, 1);
// VMOVv4f32 is ambiguous with these decodings.
if (!(imm & 0x38) && cmode == 0xF) {
@@ -4997,12 +4988,12 @@
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
-
+ unsigned Cond = 0;
unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
- unsigned Cond = fieldFromInstruction_4(Val, 28, 4);
+ Cond = fieldFromInstruction_4(Val, 28, 4);
if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
S = MCDisassembler_SoftFail;
diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc
index 84a4d9a..96f7e1f 100644
--- a/arch/ARM/ARMGenDisassemblerTables.inc
+++ b/arch/ARM/ARMGenDisassemblerTables.inc
@@ -13449,48 +13449,48 @@
{ \
uint64_t Bits = getFeatureBits(feature); \
uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
+ uint32_t CurFieldValue = 0, ExpectedValue = 0; \
DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
for (;;) { \
switch (*Ptr) { \
default: \
return MCDisassembler_Fail; \
case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
++Ptr; \
CurFieldValue = fieldname(insn, Start, Len); \
break; \
} \
case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (Val != CurFieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
@@ -13498,21 +13498,19 @@
break; \
} \
case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
+ DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \
S = MCDisassembler_SoftFail; \
break; \
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index aa6bc58..3e6ccdc 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -269,7 +269,7 @@
{
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
- unsigned Opcode = MCInst_getOpcode(MI);
+ unsigned Opcode = MCInst_getOpcode(MI), tmp = 0, i = 0;
switch(Opcode) {
// Check for HINT instructions w/ canonical names.
@@ -374,7 +374,7 @@
}
SStream_concat(O, ", %s", markup("<imm:"));
- unsigned tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
+ tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -518,25 +518,24 @@
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
- if (MCRegisterClass_contains(MRC, Reg)) {
- MCInst NewMI;
- MCOperand *NewReg;
- MCInst_setOpcode(&NewMI, Opcode);
+ if (MCRegisterClass_contains(MRC, Reg)) {
+ MCInst NewMI;
+ MCOperand *NewReg;
+ MCInst_setOpcode(&NewMI, Opcode);
- if (isStore)
- MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
- NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
- MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
- MCInst_addOperand2(&NewMI, NewReg);
- cs_mem_free(NewReg);
+ if (isStore)
+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
+ NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
+ MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
+ MCInst_addOperand2(&NewMI, NewReg);
+ cs_mem_free(NewReg);
- // Copy the rest operands into NewMI.
- unsigned i;
- for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
- MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
- printInstruction(&NewMI, O, MRI);
- return;
- }
+ // Copy the rest operands into NewMI.
+ for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
+ printInstruction(&NewMI, O, MRI);
+ return;
+ }
}
}
@@ -547,6 +546,7 @@
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
+ int32_t imm = 0;
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
@@ -565,7 +565,7 @@
}
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, markup("<imm:"));
- int32_t imm = (int32_t)MCOperand_getImm(Op);
+ imm = (int32_t)MCOperand_getImm(Op);
// relative branch only has relative offset, so we have to update it
// to reflect absolute address.
@@ -618,11 +618,12 @@
static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-
+ int32_t OffImm = 0;
+ bool isSub;
SStream_concat(O, "%s[pc, ", markup("<mem:"));
- int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
- bool isSub = OffImm < 0;
+ OffImm = (int32_t)MCOperand_getImm(MO1);
+ isSub = OffImm < 0;
// Special value for #-0. All others are normal.
if (OffImm == INT32_MIN)
@@ -649,6 +650,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
+ ARM_AM_ShiftOpc ShOpc;
printRegName(MI->csh, O, MCOperand_getReg(MO1));
@@ -661,7 +663,7 @@
}
// Print the shift opc.
- ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
+ ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
if (ShOpc == ARM_AM_rrx)
@@ -838,6 +840,7 @@
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
+ unsigned ImmOffs = 0;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -858,7 +861,7 @@
return;
}
- unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@@ -887,6 +890,7 @@
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
+ unsigned ImmOffs = 0;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -908,7 +912,7 @@
}
//If the op is sub we have to print the immediate even if it is 0
- unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) {
if (ImmOffs > HEX_THRESHOLD)
@@ -933,14 +937,16 @@
static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
bool AlwaysPrintImm0)
{
+ unsigned IdxMode = 0;
+ MCOperand *MO3 = NULL;
MCOperand *MO1 = MCInst_getOperand(MI, Op);
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, Op, O);
return;
}
- MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
- unsigned IdxMode = getAM3IdxMode((unsigned int)MCOperand_getImm(MO3));
+ MO3 = MCInst_getOperand(MI, Op+2);
+ IdxMode = getAM3IdxMode((unsigned int)MCOperand_getImm(MO3));
if (IdxMode == ARMII_IndexModePost) {
printAM3PostIndexOp(MI, Op, O);
@@ -955,6 +961,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO2));
+ unsigned ImmOffs = 0;
if (MCOperand_getReg(MO1)) {
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
@@ -967,7 +974,7 @@
return;
}
- unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@@ -1036,7 +1043,7 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
-
+ unsigned ImmOffs = 0, Op = 0;
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, OpNum, O);
return;
@@ -1045,8 +1052,8 @@
SStream_concat(O, "%s[", markup("<mem:"));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
- unsigned ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
- unsigned Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
+ ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
+ Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
if (ImmOffs * 4 > HEX_THRESHOLD)
SStream_concat(O, ", %s#%s0x%x%s", markup("<imm:"),
@@ -1064,13 +1071,14 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
+ unsigned tmp = 0;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- unsigned tmp = (unsigned int)MCOperand_getImm(MO2);
+ tmp = (unsigned int)MCOperand_getImm(MO2);
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
SStream_concat(O, ":0x%x", (tmp << 3));
@@ -1217,8 +1225,8 @@
// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
{
- SStream_concat(O, "{");
unsigned i, e;
+ SStream_concat(O, "{");
for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
if (i != OpNum) SStream_concat(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
@@ -1548,6 +1556,7 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
+ unsigned RegNum = 0;
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
@@ -1560,7 +1569,7 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- unsigned RegNum = MCOperand_getReg(MO2);
+ RegNum = MCOperand_getReg(MO2);
if (RegNum) {
SStream_concat(O, ", ");
printRegName(MI->csh, O, RegNum);
@@ -1577,6 +1586,7 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
+ unsigned ImmOffs = 0, tmp = 0;
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, Op, O);
@@ -1589,9 +1599,9 @@
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
- unsigned ImmOffs = (unsigned int)MCOperand_getImm(MO2);
+ ImmOffs = (unsigned int)MCOperand_getImm(MO2);
if (ImmOffs) {
- unsigned tmp = ImmOffs * Scale;
+ tmp = ImmOffs * Scale;
SStream_concat(O, ", %s", markup("<imm:"));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
@@ -1782,6 +1792,7 @@
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
+ unsigned tmp = 0;
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
@@ -1792,7 +1803,7 @@
if (MCOperand_getImm(MO2)) {
SStream_concat(O, ", ");
SStream_concat(O, markup("<imm:"));
- unsigned tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
+ tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -1880,6 +1891,7 @@
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
+ unsigned ShAmt = 0;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@@ -1893,7 +1905,7 @@
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
- unsigned ShAmt = (unsigned int)MCOperand_getImm(MO3);
+ ShAmt = (unsigned int)MCOperand_getImm(MO3);
if (ShAmt) {
//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
SStream_concat(O, ", lsl ");
@@ -1972,8 +1984,9 @@
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
{
+ unsigned tmp = 0;
SStream_concat(O, markup("<imm:"));
- unsigned tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@@ -1988,8 +2001,9 @@
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
{
+ unsigned tmp = 0;
SStream_concat(O, markup("<imm:"));
- unsigned tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+ tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index db51f56..36b9344 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -349,10 +349,11 @@
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -360,9 +361,10 @@
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -385,10 +387,11 @@
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -396,10 +399,11 @@
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -407,10 +411,11 @@
static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_FGRH32RegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_FGRH32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -418,10 +423,11 @@
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -429,10 +435,11 @@
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 7)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -570,10 +577,11 @@
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 30 || RegNo %2)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
+ Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -581,10 +589,11 @@
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo >= 4)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -592,10 +601,11 @@
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo >= 4)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -603,10 +613,11 @@
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo >= 4)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
}
@@ -614,10 +625,11 @@
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
@@ -626,10 +638,11 @@
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
@@ -638,10 +651,11 @@
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
@@ -650,10 +664,11 @@
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 31)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
@@ -662,10 +677,11 @@
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
+ unsigned Reg = 0;
if (RegNo > 7)
return MCDisassembler_Fail;
- unsigned Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
+ Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg));
return MCDisassembler_Success;
diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc
index 9309b35..8bc2b88 100644
--- a/arch/Mips/MipsGenAsmWriter.inc
+++ b/arch/Mips/MipsGenAsmWriter.inc
@@ -4408,6 +4408,7 @@
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
const char *AsmString;
+ char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return NULL;
@@ -4586,7 +4587,7 @@
return NULL;
}
- char *tmp = cs_strdup(AsmString), *AsmMnem, *AsmOps;
+ tmp = cs_strdup(AsmString);
AsmMnem = tmp;
AsmOps = strchr(tmp, ' ');
if (AsmOps) {
@@ -4596,7 +4597,6 @@
SStream_concat(OS, "%s", AsmMnem);
if (AsmOps) {
SStream_concat(OS, "\t");
- char *c;
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc
index 2d82b7a..6f63433 100644
--- a/arch/Mips/MipsGenDisassemblerTables.inc
+++ b/arch/Mips/MipsGenDisassemblerTables.inc
@@ -5501,48 +5501,48 @@
{ \
uint64_t Bits = getFeatureBits(feature); \
uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
+ uint32_t CurFieldValue = 0, ExpectedValue = 0; \
DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
for (;;) { \
switch (*Ptr) { \
default: \
return MCDisassembler_Fail; \
case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
++Ptr; \
CurFieldValue = fieldname(insn, Start, Len); \
break; \
} \
case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (Val != CurFieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
@@ -5550,21 +5550,19 @@
break; \
} \
case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
+ DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \
S = MCDisassembler_SoftFail; \
break; \
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index 2d3af70..53ce6ae 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -6,7 +6,7 @@
#include "../../include/mips.h"
#include "../../utils.h"
-
+#include "platform.h"
#include "MipsMapping.h"
#define GET_INSTRINFO_ENUM
@@ -7912,10 +7912,10 @@
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
- insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
- insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
diff --git a/arch/PowerPC/PPCDisassembler.c b/arch/PowerPC/PPCDisassembler.c
index 68e5b6d..ff8c460 100644
--- a/arch/PowerPC/PPCDisassembler.c
+++ b/arch/PowerPC/PPCDisassembler.c
@@ -270,6 +270,8 @@
uint16_t *Size,
uint64_t Address, MCRegisterInfo *MRI)
{
+ uint32_t insn;
+ DecodeStatus result;
// Get the four bytes of the instruction.
if (code_len < 4) {
// not enough data
@@ -278,7 +280,6 @@
}
// The instruction is big-endian encoded.
- uint32_t insn;
if (MI->csh->mode & CS_MODE_BIG_ENDIAN)
insn = (code[0] << 24) | (code[1] << 16) |
(code[2] << 8) | (code[3] << 0);
@@ -286,7 +287,7 @@
insn = (code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
- DecodeStatus result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4);
+ result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
@@ -315,16 +316,16 @@
{
/*
InitMCRegisterInfo( PPCRegDesc, 182, RA, PC,
- PPCMCRegisterClasses, 15,
- PPCRegUnitRoots,
- 138,
- PPCRegDiffLists,
- PPCRegStrings,
- PPCSubRegIdxLists,
- 6,
- PPCSubRegIdxRanges,
- PPCRegEncodingTable);
- */
+ PPCMCRegisterClasses, 15,
+ PPCRegUnitRoots,
+ 138,
+ PPCRegDiffLists,
+ PPCRegStrings,
+ PPCSubRegIdxLists,
+ 6,
+ PPCSubRegIdxRanges,
+ PPCRegEncodingTable);
+ */
MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 182,
0, 0,
diff --git a/arch/PowerPC/PPCGenDisassemblerTables.inc b/arch/PowerPC/PPCGenDisassemblerTables.inc
index ec4ba09..bd53a37 100644
--- a/arch/PowerPC/PPCGenDisassemblerTables.inc
+++ b/arch/PowerPC/PPCGenDisassemblerTables.inc
@@ -2329,48 +2329,48 @@
{ \
uint64_t Bits = getFeatureBits(feature); \
const uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
+ uint32_t CurFieldValue = 0, ExpectedValue = 0; \
DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
for (;;) { \
switch (*Ptr) { \
default: \
return MCDisassembler_Fail; \
case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
++Ptr; \
CurFieldValue = fieldname(insn, Start, Len); \
break; \
} \
case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (Val != CurFieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
@@ -2378,21 +2378,19 @@
break; \
} \
case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
+ DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, 0); \
} \
case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \
S = MCDisassembler_SoftFail; \
break; \
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index 3bd110e..d649e7d 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -374,12 +374,13 @@
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
+ int tmp = 0;
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
printOperand(MI, OpNo, O);
return;
}
- int tmp = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
+ tmp = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (tmp >= 0) {
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
@@ -400,7 +401,7 @@
static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
- unsigned RegNo;
+ unsigned RegNo, tmp;
switch (CCReg) {
default: // llvm_unreachable("Unknown CR register");
case PPC_CR0: RegNo = 0; break;
@@ -413,7 +414,7 @@
case PPC_CR7: RegNo = 7; break;
}
- unsigned tmp= 0x80 >> RegNo;
+ tmp = 0x80 >> RegNo;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
else
diff --git a/arch/Sparc/SparcGenDisassemblerTables.inc b/arch/Sparc/SparcGenDisassemblerTables.inc
index 772e267..d2b7272 100644
--- a/arch/Sparc/SparcGenDisassemblerTables.inc
+++ b/arch/Sparc/SparcGenDisassemblerTables.inc
@@ -9,6 +9,7 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+#include <stdbool.h>
#include "../../MCInst.h"
#include "../../LEB128.h"
@@ -1933,87 +1934,83 @@
} \
}
-#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
-static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
- InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
-{ \
- uint64_t Bits = getFeatureBits(feature); \
- uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
- DecodeStatus S = MCDisassembler_Success; \
- for (;;) { \
- switch (*Ptr) { \
- default: \
- return MCDisassembler_Fail; \
- case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- ++Ptr; \
- CurFieldValue = fieldname(insn, Start, Len); \
- break; \
- } \
- case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
- Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
- NumToSkip |= (*Ptr++) << 8; \
- if (Val != CurFieldValue) \
- Ptr += NumToSkip; \
- break; \
- } \
- case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
- Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
- NumToSkip |= (*Ptr++) << 8; \
- if (ExpectedValue != FieldValue) \
- Ptr += NumToSkip; \
- break; \
- } \
- case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = decodeULEB128(++Ptr, &Len); \
- Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
- NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
- Pred = checkDecoderPredicate(PIdx, Bits); \
- if (!Pred) \
- Ptr += NumToSkip; \
- (void)Pred; \
- break; \
- } \
- case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
- Ptr += Len; \
- unsigned DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
- Ptr += Len; \
- MCInst_setOpcode(MI, Opc); \
- return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
- } \
- case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
- Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
- Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
- if (Fail) \
- S = MCDisassembler_SoftFail; \
- break; \
- } \
- case MCD_OPC_Fail: { \
- return MCDisassembler_Fail; \
- } \
- } \
- } \
-}
-
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
-DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
+//DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
+static DecodeStatus decodeInstruction_4(uint8_t DecodeTable[], MCInst *MI,
+ uint32_t insn, uint64_t Address, MCRegisterInfo *MRI, int feature)
+{
+ uint64_t Bits = getFeatureBits(feature);
+ uint8_t *Ptr = DecodeTable;
+ uint32_t CurFieldValue = 0, ExpectedValue = 0;
+ DecodeStatus S = MCDisassembler_Success;
+ unsigned Start = 0, Len = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0;
+ uint32_t Val, FieldValue, PositiveMask, NegativeMask;
+ bool Pred, Fail;
+ for (;;) {
+ switch (*Ptr) {
+ default:
+ return MCDisassembler_Fail;
+ case MCD_OPC_ExtractField: {
+ Start = *++Ptr;
+ Len = *++Ptr;
+ ++Ptr;
+ CurFieldValue = fieldFromInstruction_4(insn, Start, Len);
+ break;
+ }
+ case MCD_OPC_FilterValue: {
+ Val = (uint32_t)decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ if (Val != CurFieldValue)
+ Ptr += NumToSkip;
+ break;
+ }
+ case MCD_OPC_CheckField: {
+ Start = *++Ptr;
+ Len = *++Ptr;
+ FieldValue = fieldFromInstruction_4(insn, Start, Len);
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ if (ExpectedValue != FieldValue)
+ Ptr += NumToSkip;
+ break;
+ }
+ case MCD_OPC_CheckPredicate: {
+ PIdx = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ Pred = checkDecoderPredicate(PIdx, Bits);
+ if (!Pred)
+ Ptr += NumToSkip;
+ (void)Pred;
+ break;
+ }
+ case MCD_OPC_Decode: {
+ Opc = (unsigned)decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ MCInst_setOpcode(MI, Opc);
+ return decodeToMCInst_4(S, DecodeIdx, insn, MI, Address, MRI);
+ }
+ case MCD_OPC_SoftFail: {
+ PositiveMask = (uint32_t)decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ NegativeMask = (uint32_t)decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask);
+ if (Fail)
+ S = MCDisassembler_SoftFail;
+ break;
+ }
+ case MCD_OPC_Fail: {
+ return MCDisassembler_Fail;
+ }
+ }
+ }
+}
diff --git a/arch/SystemZ/SystemZGenDisassemblerTables.inc b/arch/SystemZ/SystemZGenDisassemblerTables.inc
index 3650ed7..76aab27 100644
--- a/arch/SystemZ/SystemZGenDisassemblerTables.inc
+++ b/arch/SystemZ/SystemZGenDisassemblerTables.inc
@@ -2920,48 +2920,48 @@
{ \
uint64_t Bits = getFeatureBits(feature); \
uint8_t *Ptr = DecodeTable; \
- uint32_t CurFieldValue = 0; \
+ uint32_t CurFieldValue = 0, ExpectedValue = 0; \
DecodeStatus S = MCDisassembler_Success; \
+ unsigned Len = 0, Start = 0, NumToSkip = 0, PIdx = 0, Opc = 0, DecodeIdx = 0; \
+ InsnType FieldValue, Val, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
for (;;) { \
switch (*Ptr) { \
default: \
return MCDisassembler_Fail; \
case MCD_OPC_ExtractField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
++Ptr; \
CurFieldValue = fieldname(insn, Start, Len); \
break; \
} \
case MCD_OPC_FilterValue: { \
- unsigned Len; \
- InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (Val != CurFieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckField: { \
- unsigned Start = *++Ptr; \
- unsigned Len = *++Ptr; \
- InsnType FieldValue = fieldname(insn, Start, Len); \
- uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
case MCD_OPC_CheckPredicate: { \
- unsigned Len; \
- unsigned PIdx = decodeULEB128(++Ptr, &Len); \
+ PIdx = decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned NumToSkip = *Ptr++; \
+ NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
- bool Pred; \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
@@ -2969,21 +2969,19 @@
break; \
} \
case MCD_OPC_Decode: { \
- unsigned Len; \
- unsigned Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- unsigned DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
case MCD_OPC_SoftFail: { \
- unsigned Len; \
- InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
- InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
- bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \
S = MCDisassembler_SoftFail; \
break; \
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 5ca2027..1072ae4 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -428,6 +428,7 @@
MCOperand *IndexReg = MCInst_getOperand(MI, Op+2);
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
+ uint64_t ScaleVal = 0;
if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
@@ -470,7 +471,7 @@
if (MCOperand_getReg(IndexReg)) {
SStream_concat(O, ", ");
_printOperand(MI, Op+2, O);
- uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
+ ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
if (ScaleVal != 1) {
diff --git a/arch/X86/X86Disassembler.c b/arch/X86/X86Disassembler.c
index e04837f..de0763e 100644
--- a/arch/X86/X86Disassembler.c
+++ b/arch/X86/X86Disassembler.c
@@ -67,7 +67,6 @@
/// @param reg - The Reg to append.
static void translateRegister(MCInst *mcInst, Reg reg)
{
-//#define ENTRY(x) X86_x,
#define ENTRY(x) X86_##x,
uint8_t llvmRegnums[] = {
ALL_REGS
@@ -206,8 +205,8 @@
Opcode != X86_VINSERTPSrr &&
#endif
Opcode != X86_INT)
- if(immediate & 0x80)
- immediate |= ~(0xffull);
+ if(immediate & 0x80)
+ immediate |= ~(0xffull);
break;
case ENCODING_IW:
if(immediate & 0x8000)
@@ -320,7 +319,7 @@
MCOperand *indexReg;
MCOperand *displacement;
MCOperand *segmentReg;
- bool IndexIs512;
+ bool IndexIs512, IndexIs128, IndexIs256;
#ifndef CAPSTONE_X86_REDUCE
uint32_t Opcode;
#endif
@@ -350,7 +349,7 @@
#ifndef CAPSTONE_X86_REDUCE
Opcode = MCInst_getOpcode(mcInst);
#endif
- bool IndexIs128 = (
+ IndexIs128 = (
#ifndef CAPSTONE_X86_REDUCE
Opcode == X86_VGATHERDPDrm ||
Opcode == X86_VGATHERDPDYrm ||
@@ -365,7 +364,7 @@
#endif
false
);
- bool IndexIs256 = (
+ IndexIs256 = (
#ifndef CAPSTONE_X86_REDUCE
Opcode == X86_VGATHERQPDYrm ||
Opcode == X86_VGATHERDPSYrm ||
diff --git a/arch/X86/X86GenAsmWriter.inc b/arch/X86/X86GenAsmWriter.inc
index 7b78658..84bc1bd 100644
--- a/arch/X86/X86GenAsmWriter.inc
+++ b/arch/X86/X86GenAsmWriter.inc
@@ -13830,6 +13830,7 @@
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
const char *AsmString;
+ char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL, *c = NULL;
// MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return 0;
@@ -13860,7 +13861,7 @@
return 0;
}
- char *tmp = cs_strdup(AsmString), *AsmMnem, *AsmOps;
+ tmp = cs_strdup(AsmString);
AsmMnem = tmp;
AsmOps = strchr(tmp, ' ');
if (AsmOps) {
@@ -13870,7 +13871,6 @@
SStream_concat(OS, "%s", AsmMnem);
if (AsmOps) {
SStream_concat(OS, "\t");
- char *c;
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
diff --git a/arch/X86/X86GenAsmWriter1.inc b/arch/X86/X86GenAsmWriter1.inc
index 1c288c6..671ed88 100644
--- a/arch/X86/X86GenAsmWriter1.inc
+++ b/arch/X86/X86GenAsmWriter1.inc
@@ -13334,6 +13334,8 @@
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
const char *AsmString;
+ char *c = NULL;
+ char *tmp = NULL, *AsmMnem = NULL, *AsmOps = NULL;
// MCRegisterInfo *MRI = (MCRegisterInfo *)info;
switch (MCInst_getOpcode(MI)) {
default: return 0;
@@ -13364,7 +13366,7 @@
return 0;
}
- char *tmp = cs_strdup(AsmString), *AsmMnem, *AsmOps;
+ tmp = cs_strdup(AsmString);
AsmMnem = tmp;
AsmOps = strchr(tmp, ' ');
if (AsmOps) {
@@ -13374,7 +13376,6 @@
SStream_concat(OS, "%s", AsmMnem);
if (AsmOps) {
SStream_concat(OS, "\t");
- char *c;
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index 44ce21a..9968eb0 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -17,6 +17,7 @@
#include <ctype.h>
#include <inttypes.h>
+#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -210,7 +211,7 @@
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
-
+
SegReg = MCInst_getOperand(MI, Op+1);
// If this has a segment register, print it.
@@ -468,6 +469,7 @@
static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
{
+ bool NeedPlus = false;
MCOperand *BaseReg = MCInst_getOperand(MI, Op);
uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
MCOperand *IndexReg = MCInst_getOperand(MI, Op+2);
@@ -490,7 +492,7 @@
SStream_concat(O, "[");
- bool NeedPlus = false;
+ NeedPlus = false;
if (MCOperand_getReg(BaseReg)) {
_printOperand(MI, Op, O);
NeedPlus = true;
diff --git a/capstone-win32-vc/capstone-test/capstone-test.vcxproj b/capstone-win32-vc/capstone-test/capstone-test.vcxproj
new file mode 100644
index 0000000..4d4725e
--- /dev/null
+++ b/capstone-win32-vc/capstone-test/capstone-test.vcxproj
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <ItemGroup Label="ProjectConfigurations">
+ <ProjectConfiguration Include="Debug|Win32">
+ <Configuration>Debug</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ <ProjectConfiguration Include="Release|Win32">
+ <Configuration>Release</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ </ItemGroup>
+ <PropertyGroup Label="Globals">
+ <ProjectGuid>{B291E0D9-4B39-4AF8-971D-A015B78D54A1}</ProjectGuid>
+ <Keyword>Win32Proj</Keyword>
+ <RootNamespace>capstonetest</RootNamespace>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
+ <ConfigurationType>Application</ConfigurationType>
+ <UseDebugLibraries>true</UseDebugLibraries>
+ <PlatformToolset>v110</PlatformToolset>
+ <CharacterSet>Unicode</CharacterSet>
+ </PropertyGroup>
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
+ <ConfigurationType>Application</ConfigurationType>
+ <UseDebugLibraries>false</UseDebugLibraries>
+ <PlatformToolset>v110</PlatformToolset>
+ <WholeProgramOptimization>true</WholeProgramOptimization>
+ <CharacterSet>Unicode</CharacterSet>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
+ <ImportGroup Label="ExtensionSettings">
+ </ImportGroup>
+ <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ </ImportGroup>
+ <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ </ImportGroup>
+ <PropertyGroup Label="UserMacros" />
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <LinkIncremental>true</LinkIncremental>
+ </PropertyGroup>
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <LinkIncremental>false</LinkIncremental>
+ </PropertyGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <ClCompile>
+ <PrecompiledHeader>
+ </PrecompiledHeader>
+ <WarningLevel>Level3</WarningLevel>
+ <Optimization>Disabled</Optimization>
+ <PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <SDLCheck>true</SDLCheck>
+ </ClCompile>
+ <Link>
+ <SubSystem>Console</SubSystem>
+ <GenerateDebugInformation>true</GenerateDebugInformation>
+ </Link>
+ </ItemDefinitionGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <ClCompile>
+ <WarningLevel>Level3</WarningLevel>
+ <PrecompiledHeader>
+ </PrecompiledHeader>
+ <Optimization>MaxSpeed</Optimization>
+ <FunctionLevelLinking>true</FunctionLevelLinking>
+ <IntrinsicFunctions>true</IntrinsicFunctions>
+ <PreprocessorDefinitions>WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <SDLCheck>true</SDLCheck>
+ <AdditionalIncludeDirectories>D:\Codes\capstone\capstone-win32-vc\headers;D:\Codes\capstone\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ </ClCompile>
+ <Link>
+ <SubSystem>Console</SubSystem>
+ <GenerateDebugInformation>true</GenerateDebugInformation>
+ <EnableCOMDATFolding>true</EnableCOMDATFolding>
+ <OptimizeReferences>true</OptimizeReferences>
+ <AdditionalLibraryDirectories>D:\Codes\capstone\capstone-win32-vc\Release;%(AdditionalLibraryDirectories)</AdditionalLibraryDirectories>
+ <AdditionalDependencies>capstone-win32.lib;%(AdditionalDependencies)</AdditionalDependencies>
+ </Link>
+ </ItemDefinitionGroup>
+ <ItemGroup>
+ <ClCompile Include="..\..\tests\test.c" />
+ </ItemGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
+ <ImportGroup Label="ExtensionTargets">
+ </ImportGroup>
+</Project>
\ No newline at end of file
diff --git a/capstone-win32-vc/capstone-win32/capstone-win32.vcxproj b/capstone-win32-vc/capstone-win32/capstone-win32.vcxproj
new file mode 100644
index 0000000..0157505
--- /dev/null
+++ b/capstone-win32-vc/capstone-win32/capstone-win32.vcxproj
@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+ <ItemGroup Label="ProjectConfigurations">
+ <ProjectConfiguration Include="Debug|Win32">
+ <Configuration>Debug</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ <ProjectConfiguration Include="Release|Win32">
+ <Configuration>Release</Configuration>
+ <Platform>Win32</Platform>
+ </ProjectConfiguration>
+ </ItemGroup>
+ <ItemGroup>
+ <ClCompile Include="..\..\arch\AArch64\AArch64BaseInfo.c" />
+ <ClCompile Include="..\..\arch\AArch64\AArch64Disassembler.c" />
+ <ClCompile Include="..\..\arch\AArch64\AArch64InstPrinter.c" />
+ <ClCompile Include="..\..\arch\AArch64\AArch64Mapping.c" />
+ <ClCompile Include="..\..\arch\AArch64\AArch64Module.c" />
+ <ClCompile Include="..\..\arch\ARM\ARMDisassembler.c" />
+ <ClCompile Include="..\..\arch\ARM\ARMInstPrinter.c" />
+ <ClCompile Include="..\..\arch\ARM\ARMMapping.c" />
+ <ClCompile Include="..\..\arch\ARM\ARMModule.c" />
+ <ClCompile Include="..\..\arch\Mips\MipsDisassembler.c" />
+ <ClCompile Include="..\..\arch\Mips\MipsInstPrinter.c" />
+ <ClCompile Include="..\..\arch\Mips\MipsMapping.c" />
+ <ClCompile Include="..\..\arch\Mips\MipsModule.c" />
+ <ClCompile Include="..\..\arch\PowerPC\PPCDisassembler.c" />
+ <ClCompile Include="..\..\arch\PowerPC\PPCInstPrinter.c" />
+ <ClCompile Include="..\..\arch\PowerPC\PPCMapping.c" />
+ <ClCompile Include="..\..\arch\PowerPC\PPCModule.c" />
+ <ClCompile Include="..\..\arch\Sparc\SparcDisassembler.c" />
+ <ClCompile Include="..\..\arch\Sparc\SparcInstPrinter.c" />
+ <ClCompile Include="..\..\arch\Sparc\SparcMapping.c" />
+ <ClCompile Include="..\..\arch\Sparc\SparcModule.c" />
+ <ClCompile Include="..\..\arch\SystemZ\SystemZDisassembler.c" />
+ <ClCompile Include="..\..\arch\SystemZ\SystemZInstPrinter.c" />
+ <ClCompile Include="..\..\arch\SystemZ\SystemZMapping.c" />
+ <ClCompile Include="..\..\arch\SystemZ\SystemZMCTargetDesc.c" />
+ <ClCompile Include="..\..\arch\SystemZ\SystemZModule.c" />
+ <ClCompile Include="..\..\arch\X86\X86ATTInstPrinter.c" />
+ <ClCompile Include="..\..\arch\X86\X86Disassembler.c" />
+ <ClCompile Include="..\..\arch\X86\X86DisassemblerDecoder.c" />
+ <ClCompile Include="..\..\arch\X86\X86IntelInstPrinter.c" />
+ <ClCompile Include="..\..\arch\X86\X86Mapping.c" />
+ <ClCompile Include="..\..\arch\X86\X86Module.c" />
+ <ClCompile Include="..\..\cs.c" />
+ <ClCompile Include="..\..\MCInst.c" />
+ <ClCompile Include="..\..\MCInstrDesc.c" />
+ <ClCompile Include="..\..\MCRegisterInfo.c" />
+ <ClCompile Include="..\..\SStream.c" />
+ <ClCompile Include="..\..\utils.c" />
+ </ItemGroup>
+ <PropertyGroup Label="Globals">
+ <ProjectGuid>{5B01D900-2359-44CA-9914-6B0C6AFB7BE7}</ProjectGuid>
+ <Keyword>Win32Proj</Keyword>
+ <RootNamespace>capstonewin32</RootNamespace>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
+ <ConfigurationType>StaticLibrary</ConfigurationType>
+ <UseDebugLibraries>true</UseDebugLibraries>
+ <PlatformToolset>v110</PlatformToolset>
+ <CharacterSet>Unicode</CharacterSet>
+ </PropertyGroup>
+ <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
+ <ConfigurationType>StaticLibrary</ConfigurationType>
+ <UseDebugLibraries>false</UseDebugLibraries>
+ <PlatformToolset>v110</PlatformToolset>
+ <WholeProgramOptimization>true</WholeProgramOptimization>
+ <CharacterSet>Unicode</CharacterSet>
+ </PropertyGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
+ <ImportGroup Label="ExtensionSettings">
+ </ImportGroup>
+ <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ </ImportGroup>
+ <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+ </ImportGroup>
+ <PropertyGroup Label="UserMacros" />
+ <PropertyGroup />
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
+ <ClCompile>
+ <PrecompiledHeader>
+ </PrecompiledHeader>
+ <WarningLevel>Level3</WarningLevel>
+ <Optimization>Disabled</Optimization>
+ <PreprocessorDefinitions>WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <SDLCheck>true</SDLCheck>
+ <AdditionalIncludeDirectories>D:\Codes\capstone\capstone-win32-vc\headers;D:\Codes\capstone\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ </ClCompile>
+ <Link>
+ <SubSystem>Windows</SubSystem>
+ <GenerateDebugInformation>true</GenerateDebugInformation>
+ </Link>
+ </ItemDefinitionGroup>
+ <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
+ <ClCompile>
+ <WarningLevel>Level3</WarningLevel>
+ <PrecompiledHeader>
+ </PrecompiledHeader>
+ <Optimization>MaxSpeed</Optimization>
+ <FunctionLevelLinking>true</FunctionLevelLinking>
+ <IntrinsicFunctions>true</IntrinsicFunctions>
+ <PreprocessorDefinitions>WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)</PreprocessorDefinitions>
+ <SDLCheck>true</SDLCheck>
+ <AdditionalIncludeDirectories>D:\Codes\capstone\capstone-win32-vc\headers;D:\Codes\capstone\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ </ClCompile>
+ <Link>
+ <SubSystem>Windows</SubSystem>
+ <GenerateDebugInformation>true</GenerateDebugInformation>
+ <EnableCOMDATFolding>true</EnableCOMDATFolding>
+ <OptimizeReferences>true</OptimizeReferences>
+ </Link>
+ </ItemDefinitionGroup>
+ <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
+ <ImportGroup Label="ExtensionTargets">
+ </ImportGroup>
+</Project>
\ No newline at end of file
diff --git a/capstone-win32-vc/headers/inttypes.h b/capstone-win32-vc/headers/inttypes.h
new file mode 100644
index 0000000..42409c0
--- /dev/null
+++ b/capstone-win32-vc/headers/inttypes.h
@@ -0,0 +1,41 @@
+#pragma once
+
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+
+#define __PRI_8_LENGTH_MODIFIER__ "hh"
+#define __PRI_64_LENGTH_MODIFIER__ "ll"
+
+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
+
+#define PRId16 "hd"
+#define PRIi16 "hi"
+#define PRIo16 "ho"
+#define PRIu16 "hu"
+#define PRIx16 "hx"
+#define PRIX16 "hX"
+
+#define PRId32 "ld"
+#define PRIi32 "li"
+#define PRIo32 "lo"
+#define PRIu32 "lu"
+#define PRIx32 "lx"
+#define PRIX32 "lX"
+
+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
\ No newline at end of file
diff --git a/capstone-win32-vc/headers/platform.h b/capstone-win32-vc/headers/platform.h
new file mode 100644
index 0000000..3c21bbd
--- /dev/null
+++ b/capstone-win32-vc/headers/platform.h
@@ -0,0 +1,5 @@
+#pragma once
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+ #define strcasecmp _stricmp
+#endif
diff --git a/capstone-win32-vc/headers/stdbool.h b/capstone-win32-vc/headers/stdbool.h
new file mode 100644
index 0000000..c38c718
--- /dev/null
+++ b/capstone-win32-vc/headers/stdbool.h
@@ -0,0 +1,8 @@
+#pragma once
+
+#ifndef __cplusplus
+ typedef unsigned int bool;
+
+ #define false 0
+ #define true 1
+#endif
\ No newline at end of file
diff --git a/cs.c b/cs.c
index 3b4a02e..f566af4 100644
--- a/cs.c
+++ b/cs.c
@@ -1,5 +1,15 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+#define _CRT_SECURE_NO_WARNINGS
+
+#define CAPSTONE_HAS_ARM
+#define CAPSTONE_HAS_ARM64
+#define CAPSTONE_HAS_MIPS
+#define CAPSTONE_HAS_POWERPC
+#define CAPSTONE_HAS_SPARC
+#define CAPSTONE_HAS_SYSZ
+#define CAPSTONE_HAS_X86
+#define USE_SYS_DYN_MEM
#include <stddef.h>
#include <stdio.h>
@@ -127,10 +137,11 @@
cs_err cs_errno(csh handle)
{
+ struct cs_struct *ud = NULL;
if (!handle)
return CS_ERR_CSH;
- struct cs_struct *ud = (struct cs_struct *)(uintptr_t)handle;
+ ud = (struct cs_struct *)(uintptr_t)handle;
return ud->errnum;
}
@@ -169,6 +180,8 @@
cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle)
{
+ cs_err err;
+ struct cs_struct *ud = NULL;
if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf)
// Error: before cs_open(), dynamic memory management must be initialized
// with cs_option(CS_OPT_MEM)
@@ -177,8 +190,6 @@
archs_enable();
if (arch < CS_ARCH_MAX && arch_init[arch]) {
- struct cs_struct *ud;
-
ud = cs_mem_calloc(1, sizeof(*ud));
if (!ud) {
// memory insufficient
@@ -195,7 +206,7 @@
// default skipdata setup
ud->skipdata_setup.mnemonic = SKIPDATA_MNEM;
- cs_err err = arch_init[ud->arch](ud);
+ err = arch_init[ud->arch](ud);
if (err) {
cs_mem_free(ud);
*handle = 0;
@@ -213,11 +224,12 @@
cs_err cs_close(csh *handle)
{
+ struct cs_struct *ud = NULL;
if (*handle == 0)
// invalid handle
return CS_ERR_CSH;
- struct cs_struct *ud = (struct cs_struct *)(*handle);
+ ud = (struct cs_struct *)(*handle);
if (ud->printer_info)
cs_mem_free(ud->printer_info);
@@ -239,13 +251,14 @@
static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci,
PostPrinter_t postprinter, const uint8_t *code)
{
+ char *sp = NULL;
if (handle->detail) {
// avoiding copy insn->detail
memcpy(insn, &mci->flat_insn, sizeof(*insn) - sizeof(insn->detail));
// NOTE: copy details in 2 chunks, since union is always put at address divisible by 8
// copy from @regs_read until @arm
- memcpy(insn->detail, (void *)(&(mci->flat_insn)) + offsetof(cs_insn_flat, regs_read),
+ memcpy(insn->detail, (void *)((uintptr_t)(&(mci->flat_insn)) + offsetof(cs_insn_flat, regs_read)),
offsetof(cs_detail, arm) - offsetof(cs_detail, regs_read));
// then copy from @arm until end
memcpy((void *)((uintptr_t)(insn->detail) + offsetof(cs_detail, arm)),
@@ -274,7 +287,7 @@
#ifndef CAPSTONE_DIET
// fill in mnemonic & operands
// find first space or tab
- char *sp = buffer;
+ sp = buffer;
for (sp = buffer; *sp; sp++) {
if (*sp == ' '||*sp == '\t')
break;
@@ -329,6 +342,7 @@
cs_err cs_option(csh ud, cs_opt_type type, size_t value)
{
+ struct cs_struct *handle = NULL;
archs_enable();
// cs_option() can be called with NULL handle just for CS_OPT_MEM
@@ -345,7 +359,7 @@
return CS_ERR_OK;
}
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle)
return CS_ERR_CSH;
@@ -599,10 +613,11 @@
bool cs_insn_group(csh ud, cs_insn *insn, unsigned int group_id)
{
+ struct cs_struct *handle = NULL;
if (!ud)
return false;
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
@@ -624,10 +639,11 @@
bool cs_reg_read(csh ud, cs_insn *insn, unsigned int reg_id)
{
+ struct cs_struct *handle = NULL;
if (!ud)
return false;
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
@@ -649,10 +665,11 @@
bool cs_reg_write(csh ud, cs_insn *insn, unsigned int reg_id)
{
+ struct cs_struct *handle = NULL;
if (!ud)
return false;
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
@@ -674,10 +691,12 @@
int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type)
{
+ struct cs_struct *handle = NULL;
+ unsigned int count = 0, i = 0;
if (!ud)
return -1;
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
@@ -694,8 +713,6 @@
return -1;
}
- unsigned int count = 0, i;
-
handle->errnum = CS_ERR_OK;
switch (handle->arch) {
@@ -745,10 +762,12 @@
int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
unsigned int post)
{
+ struct cs_struct *handle = NULL;
+ unsigned int count = 0, i = 0;
if (!ud)
return -1;
- struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
+ handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
@@ -765,8 +784,6 @@
return -1;
}
- unsigned int count = 0, i;
-
handle->errnum = CS_ERR_OK;
switch (handle->arch) {
diff --git a/tests/test.c b/tests/test.c
index 0261b76..09a4246 100644
--- a/tests/test.c
+++ b/tests/test.c
@@ -50,123 +50,131 @@
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
-
+ struct platform {
+ cs_arch arch;
+ cs_mode mode;
+ unsigned char *code;
+ size_t size;
+ char *comment;
+ cs_opt_type opt_type;
+ cs_opt_value opt_value;
+ };
struct platform platforms[] = {
{
- .arch = CS_ARCH_X86,
- .mode = CS_MODE_16,
- .code = (unsigned char*)X86_CODE16,
- .size = sizeof(X86_CODE16) - 1,
- .comment = "X86 16bit (Intel syntax)"
+ CS_ARCH_X86,
+ CS_MODE_16,
+ (unsigned char*)X86_CODE16,
+ sizeof(X86_CODE16) - 1,
+ "X86 16bit (Intel syntax)"
},
{
- .arch = CS_ARCH_X86,
- .mode = CS_MODE_32,
- .code = (unsigned char*)X86_CODE32,
- .size = sizeof(X86_CODE32) - 1,
- .comment = "X86 32bit (ATT syntax)",
- .opt_type = CS_OPT_SYNTAX,
- .opt_value = CS_OPT_SYNTAX_ATT,
+ CS_ARCH_X86,
+ CS_MODE_32,
+ (unsigned char*)X86_CODE32,
+ sizeof(X86_CODE32) - 1,
+ "X86 32bit (ATT syntax)",
+ CS_OPT_SYNTAX,
+ CS_OPT_SYNTAX_ATT,
},
{
- .arch = CS_ARCH_X86,
- .mode = CS_MODE_32,
- .code = (unsigned char*)X86_CODE32,
- .size = sizeof(X86_CODE32) - 1,
- .comment = "X86 32 (Intel syntax)"
+ CS_ARCH_X86,
+ CS_MODE_32,
+ (unsigned char*)X86_CODE32,
+ sizeof(X86_CODE32) - 1,
+ "X86 32 (Intel syntax)"
},
{
- .arch = CS_ARCH_X86,
- .mode = CS_MODE_64,
- .code = (unsigned char*)X86_CODE64,
- .size = sizeof(X86_CODE64) - 1,
- .comment = "X86 64 (Intel syntax)"
+ CS_ARCH_X86,
+ CS_MODE_64,
+ (unsigned char*)X86_CODE64,
+ sizeof(X86_CODE64) - 1,
+ "X86 64 (Intel syntax)"
},
{
- .arch = CS_ARCH_ARM,
- .mode = CS_MODE_ARM,
- .code = (unsigned char*)ARM_CODE,
- .size = sizeof(ARM_CODE) - 1,
- .comment = "ARM"
+ CS_ARCH_ARM,
+ CS_MODE_ARM,
+ (unsigned char*)ARM_CODE,
+ sizeof(ARM_CODE) - 1,
+ "ARM"
},
{
- .arch = CS_ARCH_ARM,
- .mode = CS_MODE_THUMB,
- .code = (unsigned char*)THUMB_CODE2,
- .size = sizeof(THUMB_CODE2) - 1,
- .comment = "THUMB-2"
+ CS_ARCH_ARM,
+ CS_MODE_THUMB,
+ (unsigned char*)THUMB_CODE2,
+ sizeof(THUMB_CODE2) - 1,
+ "THUMB-2"
},
{
- .arch = CS_ARCH_ARM,
- .mode = CS_MODE_ARM,
- .code = (unsigned char*)ARM_CODE2,
- .size = sizeof(ARM_CODE2) - 1,
- .comment = "ARM: Cortex-A15 + NEON"
+ CS_ARCH_ARM,
+ CS_MODE_ARM,
+ (unsigned char*)ARM_CODE2,
+ sizeof(ARM_CODE2) - 1,
+ "ARM: Cortex-A15 + NEON"
},
{
- .arch = CS_ARCH_ARM,
- .mode = CS_MODE_THUMB,
- .code = (unsigned char*)THUMB_CODE,
- .size = sizeof(THUMB_CODE) - 1,
- .comment = "THUMB"
+ CS_ARCH_ARM,
+ CS_MODE_THUMB,
+ (unsigned char*)THUMB_CODE,
+ sizeof(THUMB_CODE) - 1,
+ "THUMB"
},
{
- .arch = CS_ARCH_MIPS,
- .mode = CS_MODE_32 + CS_MODE_BIG_ENDIAN,
- .code = (unsigned char*)MIPS_CODE,
- .size = sizeof(MIPS_CODE) - 1,
- .comment = "MIPS-32 (Big-endian)"
+ CS_ARCH_MIPS,
+ (cs_mode)(CS_MODE_32 + CS_MODE_BIG_ENDIAN),
+ (unsigned char*)MIPS_CODE,
+ sizeof(MIPS_CODE) - 1,
+ "MIPS-32 (Big-endian)"
},
{
- .arch = CS_ARCH_MIPS,
- .mode = CS_MODE_64+ CS_MODE_LITTLE_ENDIAN,
- .code = (unsigned char*)MIPS_CODE2,
- .size = sizeof(MIPS_CODE2) - 1,
- .comment = "MIPS-64-EL (Little-endian)"
+ CS_ARCH_MIPS,
+ (cs_mode)(CS_MODE_64 + CS_MODE_LITTLE_ENDIAN),
+ (unsigned char*)MIPS_CODE2,
+ sizeof(MIPS_CODE2) - 1,
+ "MIPS-64-EL (Little-endian)"
},
{
- .arch = CS_ARCH_ARM64,
- .mode = CS_MODE_ARM,
- .code = (unsigned char*)ARM64_CODE,
- .size = sizeof(ARM64_CODE) - 1,
- .comment = "ARM-64"
+ CS_ARCH_ARM64,
+ CS_MODE_ARM,
+ (unsigned char*)ARM64_CODE,
+ sizeof(ARM64_CODE) - 1,
+ "ARM-64"
},
{
- .arch = CS_ARCH_PPC,
- .mode = CS_MODE_BIG_ENDIAN,
- .code = (unsigned char*)PPC_CODE,
- .size = sizeof(PPC_CODE) - 1,
- .comment = "PPC-64"
+ CS_ARCH_PPC,
+ CS_MODE_BIG_ENDIAN,
+ (unsigned char*)PPC_CODE,
+ sizeof(PPC_CODE) - 1,
+ "PPC-64"
},
{
- .arch = CS_ARCH_PPC,
- .mode = CS_MODE_BIG_ENDIAN,
- .code = (unsigned char*)PPC_CODE,
- .size = sizeof(PPC_CODE) - 1,
- .opt_type = CS_OPT_SYNTAX,
- .opt_value = CS_OPT_SYNTAX_NOREGNAME,
- .comment = "PPC-64, print register with number only"
+ CS_ARCH_PPC,
+ CS_MODE_BIG_ENDIAN,
+ (unsigned char*)PPC_CODE,
+ sizeof(PPC_CODE) - 1,
+ "PPC-64, print register with number only",
+ CS_OPT_SYNTAX,
+ CS_OPT_SYNTAX_NOREGNAME
},
{
- .arch = CS_ARCH_SPARC,
- .mode = CS_MODE_BIG_ENDIAN,
- .code = (unsigned char*)SPARC_CODE,
- .size = sizeof(SPARC_CODE) - 1,
- .comment = "Sparc"
+ CS_ARCH_SPARC,
+ CS_MODE_BIG_ENDIAN,
+ (unsigned char*)SPARC_CODE,
+ sizeof(SPARC_CODE) - 1,
+ "Sparc"
},
{
- .arch = CS_ARCH_SPARC,
- .mode = CS_MODE_BIG_ENDIAN + CS_MODE_V9,
- .code = (unsigned char*)SPARCV9_CODE,
- .size = sizeof(SPARCV9_CODE) - 1,
- .comment = "SparcV9"
+ CS_ARCH_SPARC,
+ (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
+ (unsigned char*)SPARCV9_CODE,
+ sizeof(SPARCV9_CODE) - 1,
+ "SparcV9"
},
{
- .arch = CS_ARCH_SYSZ,
- .mode = 0,
- .code = (unsigned char*)SYSZ_CODE,
- .size = sizeof(SYSZ_CODE) - 1,
- .comment = "SystemZ"
+ CS_ARCH_SYSZ,
+ (cs_mode)0,
+ (unsigned char*)SYSZ_CODE,
+ sizeof(SYSZ_CODE) - 1,
+ "SystemZ"
},
};
@@ -224,7 +232,7 @@
test();
#if 0
- #define offsetof(st, m) __builtin_offsetof(st, m)
+#define offsetof(st, m) __builtin_offsetof(st, m)
cs_insn insn;
printf("size: %lu\n", sizeof(insn));
diff --git a/utils.c b/utils.c
index 2dbe2ee..fcf40b5 100644
--- a/utils.c
+++ b/utils.c
@@ -5,6 +5,7 @@
#include <string.h>
#include "utils.h"
+#include "platform.h"
// return the position of a string in a list of strings
// or -1 if given string is not in the list