Merge remote-tracking branch 'upstream/next' into next
diff --git a/.travis.yml b/.travis.yml
index bd7085a..aa8f5a1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -5,8 +5,8 @@
script:
- ./make.sh
- make check
- - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so bindings/python/; fi
- - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.dylib bindings/python/; fi
+ - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
+ - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
- cd bindings/python && make check
compiler:
- clang
diff --git a/COMPILE.TXT b/COMPILE.TXT
index e8aa42e..93056ce 100644
--- a/COMPILE.TXT
+++ b/COMPILE.TXT
@@ -7,6 +7,8 @@
To compile using XCode on MacOSX, see xcode/README.md.
+To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md.
+
*-*-*-*-*-*
Capstone requires no prerequisite packages, so it is easy to compile & install.
diff --git a/CREDITS.TXT b/CREDITS.TXT
index bf0d25d..8a3dea5 100644
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@@ -63,3 +63,4 @@
Pranith Kumar: Explicit registers accessed for Arm64.
Xipiter LLC: Capstone logo redesigned.
Satoshi Tanda: Support Windows kernel driver.
+Koutheir Attouchi: Support for Windows CE.
diff --git a/LEB128.h b/LEB128.h
index a5fd9a3..da4140c 100644
--- a/LEB128.h
+++ b/LEB128.h
@@ -18,9 +18,7 @@
#ifndef CS_LLVM_SUPPORT_LEB128_H
#define CS_LLVM_SUPPORT_LEB128_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
+#include "include/capstone/capstone.h"
/// Utility function to decode a ULEB128 value.
static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
diff --git a/MCInst.h b/MCInst.h
index bd2a52f..677fd75 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -19,10 +19,6 @@
#ifndef CS_MCINST_H
#define CS_MCINST_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "include/capstone/capstone.h"
typedef struct MCInst MCInst;
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
index 9e265d1..275ae77 100644
--- a/MCInstrDesc.h
+++ b/MCInstrDesc.h
@@ -18,10 +18,6 @@
#ifndef CS_LLVM_MC_MCINSTRDESC_H
#define CS_LLVM_MC_MCINSTRDESC_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/platform.h"
//===----------------------------------------------------------------------===//
diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h
index 01bc6a7..6d51e19 100644
--- a/MCRegisterInfo.h
+++ b/MCRegisterInfo.h
@@ -19,10 +19,6 @@
#ifndef CS_LLVM_MC_MCREGISTERINFO_H
#define CS_LLVM_MC_MCREGISTERINFO_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/platform.h"
/// An unsigned integer type large enough to represent all physical registers,
diff --git a/Makefile b/Makefile
index e136b2b..73e89ef 100644
--- a/Makefile
+++ b/Makefile
@@ -330,11 +330,11 @@
ifeq ($(CAPSTONE_SHARED),yes)
ifeq ($(IS_MINGW),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
else ifeq ($(IS_CYGWIN),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
else # *nix
-LIBRARY = $(BLDIR)/lib$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
CFLAGS += -fvisibility=hidden
endif
endif
@@ -412,7 +412,7 @@
$(INSTALL_LIB) $(LIBRARY) $(DESTDIR)/$(LIBDIR)
ifneq ($(VERSION_EXT),)
cd $(DESTDIR)/$(LIBDIR) && \
- mv lib$(LIBNAME).$(EXT) lib$(LIBNAME).$(VERSION_EXT) && \
+ rm -f lib$(LIBNAME).$(EXT) && \
ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)
endif
endif
diff --git a/MathExtras.h b/MathExtras.h
index 0d98616..3292f73 100644
--- a/MathExtras.h
+++ b/MathExtras.h
@@ -17,12 +17,10 @@
#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
#define CS_LLVM_SUPPORT_MATHEXTRAS_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
-#ifdef _MSC_VER
-# include <intrin.h>
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/intrin.h"
+#elif defined(_MSC_VER)
+#include <intrin.h>
#endif
#ifndef __cplusplus
diff --git a/SStream.c b/SStream.c
index d12da5e..c90cf1a 100644
--- a/SStream.c
+++ b/SStream.c
@@ -1,9 +1,6 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
diff --git a/SStream.h b/SStream.h
index 5b81310..9ccd351 100644
--- a/SStream.h
+++ b/SStream.h
@@ -4,6 +4,8 @@
#ifndef CS_SSTREAM_H_
#define CS_SSTREAM_H_
+#include "include/capstone/platform.h"
+
typedef struct SStream {
char buffer[512];
int index;
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 73859c1..214cfc3 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -21,9 +21,6 @@
#define CS_LLVM_AARCH64_BASEINFO_H
#include <ctype.h>
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
#include <string.h>
#ifndef __cplusplus
diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h
index c669f4e..153dbca 100644
--- a/arch/AArch64/AArch64Disassembler.h
+++ b/arch/AArch64/AArch64Disassembler.h
@@ -4,10 +4,6 @@
#ifndef CS_AARCH64_DISASSEMBLER_H
#define CS_AARCH64_DISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 7c5a26d..421a48c 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -1642,9 +1642,12 @@
MI->flat_insn->detail->arm64.op_count++;
}
} else {
+#ifndef CAPSTONE_DIET
+ unsigned char access;
+#endif
printInt32Bang(O, Val);
#ifndef CAPSTONE_DIET
- unsigned char access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+ access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
MI->ac_idx++;
#endif
diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c
index faaabc0..ac3ab66 100644
--- a/arch/M68K/M68KDisassembler.c
+++ b/arch/M68K/M68KDisassembler.c
@@ -28,7 +28,7 @@
*/
/* The code bellow is based on MUSASHI but has been heavily modified for capstore by
- * Daniel Collin <daniel@collin.com> 2015 */
+ * Daniel Collin <daniel@collin.com> 2015-2016 */
/* ======================================================================== */
/* ================================ INCLUDES ============================== */
@@ -156,12 +156,11 @@
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
static unsigned int m68k_read_disassembler_16(const m68k_info *info, const uint64_t addr)
{
const uint16_t v0 = info->code[addr + 0];
const uint16_t v1 = info->code[addr + 1];
- return (v0 << 8) | v1;
+ return (v0 << 8) | v1;
}
static unsigned int m68k_read_disassembler_32(const m68k_info *info, const uint64_t addr)
@@ -384,7 +383,7 @@
if (preindex) {
op->address_mode = is_pc ? M68K_AM_PC_MEMI_PRE_INDEX : M68K_AM_MEMI_PRE_INDEX;
- } else if (postindex) {
+ } else if (postindex) {
op->address_mode = is_pc ? M68K_AM_PC_MEMI_POST_INDEX : M68K_AM_MEMI_POST_INDEX;
}
@@ -392,21 +391,21 @@
}
op->mem.index_reg = (EXT_INDEX_AR(extension) ? M68K_REG_A0 : M68K_REG_D0) + EXT_INDEX_REGISTER(extension);
- op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0;
+ op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0;
if (EXT_8BIT_DISPLACEMENT(extension) == 0) {
if (is_pc) {
- op->mem.base_reg = M68K_REG_PC;
+ op->mem.base_reg = M68K_REG_PC;
op->address_mode = M68K_AM_PCI_INDEX_BASE_DISP;
} else {
- op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
+ op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
}
} else {
if (is_pc) {
- op->mem.base_reg = M68K_REG_PC;
+ op->mem.base_reg = M68K_REG_PC;
op->address_mode = M68K_AM_PCI_INDEX_8_BIT_DISP;
} else {
- op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
+ op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
op->address_mode = M68K_AM_AREGI_INDEX_8_BIT_DISP;
}
@@ -513,6 +512,11 @@
}
}
+static void set_insn_group(m68k_info *info, m68k_group_type group)
+{
+ info->groups[info->groups_count++] = (uint8_t)group;
+}
+
static cs_m68k* build_init_op(m68k_info *info, int opcode, int count, int size)
{
cs_m68k* ext;
@@ -625,7 +629,7 @@
op0->type = M68K_OP_IMM;
op0->address_mode = M68K_AM_IMMIDIATE;
- op0->imm = imm;
+ op0->imm = imm;
get_ea_mode_op(info, op1, info->ir, size);
}
@@ -749,10 +753,10 @@
op0->type = M68K_OP_IMM;
op0->address_mode = M68K_AM_IMMIDIATE;
- op0->imm = imm;
+ op0->imm = imm;
op1->address_mode = M68K_AM_NONE;
- op1->reg = reg;
+ op1->reg = reg;
}
static void build_bxx(m68k_info *info, int opcode, int size, int jump_offset)
@@ -765,6 +769,8 @@
op->type = M68K_OP_IMM;
op->address_mode = M68K_AM_IMMIDIATE;
op->imm = jump_offset;
+
+ set_insn_group(info, M68K_GRP_JUMP);
}
static void build_bcc(m68k_info *info, int size, int jump_offset)
@@ -792,6 +798,8 @@
op1->type = M68K_OP_IMM;
op1->address_mode = M68K_AM_IMMIDIATE;
op1->imm = jump_offset;
+
+ set_insn_group(info, M68K_GRP_JUMP);
}
static void build_dbcc(m68k_info *info, int size, int jump_offset)
@@ -871,7 +879,7 @@
uint r = v; // r will be reversed bits of v; first get LSB of v
uint s = 16 - 1; // extra shift needed at end
- for (v >>= 1; v; v >>= 1) {
+ for (v >>= 1; v; v >>= 1) {
r <<= 1;
r |= v & 1;
s--;
@@ -885,7 +893,7 @@
uint r = v; // r will be reversed bits of v; first get LSB of v
uint s = 8 - 1; // extra shift needed at end
- for (v >>= 1; v; v >>= 1) {
+ for (v >>= 1; v; v >>= 1) {
r <<= 1;
r |= v & 1;
s--;
@@ -1060,7 +1068,7 @@
switch ((info->ir >> 3) & 3) { // scope
// Invalid
- case 0:
+ case 0:
d68000_invalid(info);
return;
// Line
@@ -1872,11 +1880,11 @@
get_ea_mode_op(info, op_ea, info->ir, 4);
- if (regsel & 4)
+ if (regsel & 4)
special->reg = M68K_REG_FPCR;
- else if (regsel & 2)
+ else if (regsel & 2)
special->reg = M68K_REG_FPSR;
- else if (regsel & 1)
+ else if (regsel & 1)
special->reg = M68K_REG_FPIAR;
}
@@ -1907,7 +1915,7 @@
op_reglist->reg = M68K_REG_D0 + ((reglist >> 4) & 7);
break;
- case 0 :
+ case 0 :
op_reglist->address_mode = M68K_AM_NONE;
op_reglist->type = M68K_OP_REG_BITS;
op_reglist->register_bits = reglist << 16;
@@ -2022,8 +2030,8 @@
case 0x28: MCInst_setOpcode(info->inst, M68K_INS_FSUB); supports_single_op = false; break;
case 0x38: MCInst_setOpcode(info->inst, M68K_INS_FCMP); supports_single_op = false; break;
case 0x3a: MCInst_setOpcode(info->inst, M68K_INS_FTST); break;
- default:
- break;
+ default:
+ break;
}
// Some trickery here! It's not documented but if bit 6 is set this is a s/d opcode and then
@@ -2054,22 +2062,22 @@
if (rm == 1) {
switch (src) {
- case 0x00 :
+ case 0x00 :
ext->op_size.cpu_size = M68K_CPU_SIZE_LONG;
get_ea_mode_op(info, op0, info->ir, 4);
break;
- case 0x06 :
+ case 0x06 :
ext->op_size.cpu_size = M68K_CPU_SIZE_BYTE;
get_ea_mode_op(info, op0, info->ir, 1);
break;
- case 0x04 :
+ case 0x04 :
ext->op_size.cpu_size = M68K_CPU_SIZE_WORD;
get_ea_mode_op(info, op0, info->ir, 2);
break;
- case 0x01 :
+ case 0x01 :
ext->op_size.type = M68K_SIZE_TYPE_FPU;
ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE;
get_ea_mode_op(info, op0, info->ir, 4);
@@ -2344,12 +2352,14 @@
static void d68000_jmp(m68k_info *info)
{
cs_m68k* ext = build_init_op(info, M68K_INS_JMP, 1, 0);
+ set_insn_group(info, M68K_GRP_JUMP);
get_ea_mode_op(info, &ext->operands[0], info->ir, 4);
}
static void d68000_jsr(m68k_info *info)
{
cs_m68k* ext = build_init_op(info, M68K_INS_JSR, 1, 0);
+ set_insn_group(info, M68K_GRP_JUMP);
get_ea_mode_op(info, &ext->operands[0], info->ir, 4);
}
@@ -2517,16 +2527,12 @@
{
cs_m68k_op* op0;
cs_m68k_op* op1;
- cs_m68k* ext;
-
- LIMIT_CPU_TYPES(info, M68010_PLUS);
-
- ext = build_init_op(info, M68K_INS_MOVE, 2, 2);
+ cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2);
op0 = &ext->operands[0];
op1 = &ext->operands[1];
- get_ea_mode_op(info, op0, info->ir, 1);
+ get_ea_mode_op(info, op0, info->ir, 2);
op1->address_mode = M68K_AM_NONE;
op1->reg = M68K_REG_SR;
@@ -3029,7 +3035,7 @@
static void d68000_roxr_ea(m68k_info *info)
{
- build_ea(info, M68K_INS_ROL, 2);
+ build_ea(info, M68K_INS_ROXR, 2);
}
static void d68000_roxl_s_8(m68k_info *info)
@@ -3069,12 +3075,14 @@
static void d68010_rtd(m68k_info *info)
{
+ set_insn_group(info, M68K_GRP_RET);
LIMIT_CPU_TYPES(info, M68010_PLUS);
build_bxx(info, M68K_INS_RTD, 0, read_imm_16(info));
}
static void d68000_rte(m68k_info *info)
{
+ set_insn_group(info, M68K_GRP_IRET);
MCInst_setOpcode(info->inst, M68K_INS_RTE);
}
@@ -3083,6 +3091,7 @@
cs_m68k* ext;
cs_m68k_op* op;
+ set_insn_group(info, M68K_GRP_RET);
LIMIT_CPU_TYPES(info, M68020_ONLY);
@@ -3103,11 +3112,13 @@
static void d68000_rtr(m68k_info *info)
{
+ set_insn_group(info, M68K_GRP_RET);
MCInst_setOpcode(info->inst, M68K_INS_RTR);
}
static void d68000_rts(m68k_info *info)
{
+ set_insn_group(info, M68K_GRP_RET);
MCInst_setOpcode(info->inst, M68K_INS_RTS);
}
@@ -3865,14 +3876,14 @@
MCInst *inst = info->inst;
cs_m68k* ext = &info->extension;
int i;
-
+
inst->Opcode = M68K_INS_INVALID;
build_opcode_table();
memset(ext, 0, sizeof(cs_m68k));
ext->op_size.type = M68K_SIZE_TYPE_CPU;
-
+
for (i = 0; i < M68K_OPERAND_COUNT; ++i)
ext->operands[i].type = M68K_OP_REG;
@@ -3893,8 +3904,9 @@
int s;
int cpu_type = M68K_CPU_TYPE_68000;
cs_struct* handle = instr->csh;
- m68k_info *info = (m68k_info *)handle->printer_info;
+ m68k_info *info = (m68k_info*)handle->printer_info;
+ info->groups_count = 0;
info->code = code;
info->code_len = code_len;
info->baseAddress = address;
@@ -3923,7 +3935,7 @@
M68K_printInst(instr, &ss, info);
#endif
- // Make sure we always stay within range
+ // Make sure we always stay within range
if (s > (int)code_len)
*size = (uint16_t)code_len;
else
diff --git a/arch/M68K/M68KDisassembler.h b/arch/M68K/M68KDisassembler.h
index 62f4c01..c5f797c 100644
--- a/arch/M68K/M68KDisassembler.h
+++ b/arch/M68K/M68KDisassembler.h
@@ -1,15 +1,11 @@
/* Capstone Disassembly Engine */
-/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
#ifndef CS_M68KDISASSEMBLER_H
#define CS_M68KDISASSEMBLER_H
#include "../../MCInst.h"
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
/* Private, For internal use only */
typedef struct m68k_info {
const uint8_t *code;
@@ -21,6 +17,8 @@
unsigned int type;
unsigned int address_mask; /* Address mask to simulate address lines */
cs_m68k extension;
+ uint8_t groups[8];
+ uint8_t groups_count;
} m68k_info;
bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info);
diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c
index 31b75a7..b56ca3b 100644
--- a/arch/M68K/M68KInstPrinter.c
+++ b/arch/M68K/M68KInstPrinter.c
@@ -1,5 +1,5 @@
/* Capstone Disassembly Engine */
-/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
#ifdef _MSC_VER
// Disable security warnings for strcat & sprintf
@@ -34,7 +34,7 @@
"caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
"dtt1", "mmusr", "urp", "srp",
- "fpcr", "fpsr", "fpiar",
+ "fpcr", "fpsr", "fpiar",
};
static const char* s_instruction_names[] = {
@@ -49,15 +49,15 @@
"fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne",
"fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne",
"fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove",
- "fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
+ "fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
"fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle",
- "fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
- "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
- "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
- "ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
- "movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
- "pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
+ "fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
+ "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
+ "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
+ "ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
+ "movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
+ "pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
"roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi",
"sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls",
"trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk",
@@ -100,7 +100,7 @@
static void registerBits(SStream* O, const cs_m68k_op* op)
{
char buffer[128];
- unsigned int data = op->register_bits;
+ unsigned int data = op->register_bits;
buffer[0] = 0;
@@ -113,7 +113,7 @@
static void registerPair(SStream* O, const cs_m68k_op* op)
{
- SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + (op->register_bits >> 4)],
+ SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + (op->register_bits >> 4)],
s_reg_names[M68K_REG_D0 + (op->register_bits & 0xf)]);
}
@@ -143,8 +143,8 @@
case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break;
case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "$%x(a%d)", op->mem.disp, (op->reg - M68K_REG_A0)); break;
case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", op->mem.disp); break;
- case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
- case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
+ case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
+ case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
case M68K_AM_IMMIDIATE:
if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
@@ -158,10 +158,10 @@
SStream_concat(O, "#$%x", op->imm);
break;
case M68K_AM_PCI_INDEX_8_BIT_DISP:
- SStream_concat(O, "$%x(pc,%s%s)", op->mem.disp, s_spacing, getRegName(op->mem.index_reg));
+ SStream_concat(O, "$%x(pc,%s%s.%c)", op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
break;
case M68K_AM_AREGI_INDEX_8_BIT_DISP:
- SStream_concat(O, "$%x(%s,%s%s.%c)", op->mem.disp, getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+ SStream_concat(O, "$%x(%s,%s%s.%c)", op->mem.disp, getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
break;
case M68K_AM_PCI_INDEX_BASE_DISP:
case M68K_AM_AREGI_INDEX_BASE_DISP:
@@ -171,7 +171,7 @@
SStream_concat(O, "(");
if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
- SStream_concat(O, "pc,%s%s.%c", getRegName(op->mem.index_reg), s_spacing, op->mem.index_size ? 'l' : 'w');
+ SStream_concat(O, "pc,%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
} else {
if (op->mem.base_reg != M68K_REG_INVALID)
SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing);
@@ -196,9 +196,9 @@
if (op->mem.base_reg != M68K_REG_INVALID) {
if (op->mem.in_disp > 0)
- SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
+ SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
else
- SStream_concat(O, "%s", getRegName(op->mem.base_reg));
+ SStream_concat(O, "%s", getRegName(op->mem.base_reg));
}
if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
@@ -238,9 +238,10 @@
detail = MI->flat_insn->detail;
if (detail) {
memcpy(&detail->m68k, ext, sizeof(cs_m68k));
+ memcpy(&detail->groups, &info->groups, info->groups_count);
+ detail->groups_count = info->groups_count;
detail->regs_read_count = 0;
detail->regs_write_count = 0;
- detail->groups_count = 0;
}
if (MI->Opcode == M68K_INS_INVALID) {
@@ -262,7 +263,7 @@
case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break;
case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break;
case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break;
- case M68K_CPU_SIZE_NONE: break;
+ case M68K_CPU_SIZE_NONE: break;
}
break;
@@ -271,14 +272,14 @@
case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break;
case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break;
case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break;
- case M68K_FPU_SIZE_NONE: break;
+ case M68K_FPU_SIZE_NONE: break;
}
break;
}
SStream_concat0(O, " ");
- // this one is a bit spacial so we do spacial things
+ // this one is a bit spacial so we do special things
if (MI->Opcode == M68K_INS_CAS2) {
int reg_value_0, reg_value_1;
@@ -286,7 +287,7 @@
printAddressingMode(O, ext, &ext->operands[1]); SStream_concat0(O, ",");
reg_value_0 = ext->operands[2].register_bits >> 4;
reg_value_1 = ext->operands[2].register_bits & 0xf;
- SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
+ SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
return;
}
@@ -321,9 +322,21 @@
#endif
}
-const char* M68K_group_name(csh handle, unsigned int id)
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+ { M68K_GRP_INVALID , NULL },
+ { M68K_GRP_JUMP, "jump" },
+ { M68K_GRP_RET , "ret" },
+ { M68K_GRP_IRET, "iret" },
+};
+#endif
+
+const char *M68K_group_name(csh handle, unsigned int id)
{
- // TODO: Implement group names in m68k
+#ifndef CAPSTONE_DIET
+ return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
return NULL;
+#endif
}
diff --git a/arch/M68K/M68KInstPrinter.h b/arch/M68K/M68KInstPrinter.h
index ac96afd..d5f1e9b 100644
--- a/arch/M68K/M68KInstPrinter.h
+++ b/arch/M68K/M68KInstPrinter.h
@@ -4,10 +4,6 @@
#ifndef CS_M68KINSTPRINTER_H
#define CS_M68KINSTPRINTER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/arch/PowerPC/PPCDisassembler.h b/arch/PowerPC/PPCDisassembler.h
index 946f3f7..5ffab28 100644
--- a/arch/PowerPC/PPCDisassembler.h
+++ b/arch/PowerPC/PPCDisassembler.h
@@ -4,10 +4,6 @@
#ifndef CS_PPCDISASSEMBLER_H
#define CS_PPCDISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/arch/Sparc/SparcDisassembler.h b/arch/Sparc/SparcDisassembler.h
index 49ac375..eccb3cb 100644
--- a/arch/Sparc/SparcDisassembler.h
+++ b/arch/Sparc/SparcDisassembler.h
@@ -4,10 +4,6 @@
#ifndef CS_SPARCDISASSEMBLER_H
#define CS_SPARCDISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/arch/Sparc/SparcInstPrinter.c b/arch/Sparc/SparcInstPrinter.c
index ba2a315..c5f1e2c 100644
--- a/arch/Sparc/SparcInstPrinter.c
+++ b/arch/Sparc/SparcInstPrinter.c
@@ -195,7 +195,7 @@
// backward, so they need to be multiplied by 4
switch (MI->Opcode) {
case SP_CALL:
- Imm = SignExtend32(Imm, 30);
+ // Imm = SignExtend32(Imm, 30);
Imm += (uint32_t)MI->address;
break;
diff --git a/arch/SystemZ/SystemZDisassembler.h b/arch/SystemZ/SystemZDisassembler.h
index 6785d7c..8b6e540 100644
--- a/arch/SystemZ/SystemZDisassembler.h
+++ b/arch/SystemZ/SystemZDisassembler.h
@@ -4,10 +4,6 @@
#ifndef CS_SYSZDISASSEMBLER_H
#define CS_SYSZDISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 0e82273..9ab89ee 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -174,6 +174,21 @@
// TODO: fix this in tablegen instead
MI->x86opsize = 10;
break;
+ case X86_FSTENVm:
+ case X86_FLDENVm:
+ // TODO: fix this in tablegen instead
+ switch(MI->csh->mode) {
+ default: // never reach
+ break;
+ case CS_MODE_16:
+ MI->x86opsize = 14;
+ break;
+ case CS_MODE_32:
+ case CS_MODE_64:
+ MI->x86opsize = 28;
+ break;
+ }
+ break;
}
printMemReference(MI, OpNo, O);
}
diff --git a/arch/X86/X86Disassembler.h b/arch/X86/X86Disassembler.h
index 10bdeb8..8be8cc9 100644
--- a/arch/X86/X86Disassembler.h
+++ b/arch/X86/X86Disassembler.h
@@ -77,10 +77,6 @@
#ifndef CS_X86_DISASSEMBLER_H
#define CS_X86_DISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCInst.h"
diff --git a/arch/X86/X86DisassemblerDecoder.h b/arch/X86/X86DisassemblerDecoder.h
index 777fb90..8b3e5ba 100644
--- a/arch/X86/X86DisassemblerDecoder.h
+++ b/arch/X86/X86DisassemblerDecoder.h
@@ -24,9 +24,6 @@
#else
#include <stdio.h>
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
#include "X86DisassemblerDecoderCommon.h"
diff --git a/arch/X86/X86DisassemblerDecoderCommon.h b/arch/X86/X86DisassemblerDecoderCommon.h
index cc1549a..aade4f9 100644
--- a/arch/X86/X86DisassemblerDecoderCommon.h
+++ b/arch/X86/X86DisassemblerDecoderCommon.h
@@ -25,10 +25,6 @@
#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H
#define CS_X86_DISASSEMBLERDECODERCOMMON_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
#define CONTEXTS_SYM x86DisassemblerContexts
#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
index 247ab3a..b7ca409 100644
--- a/arch/X86/X86IntelInstPrinter.c
+++ b/arch/X86/X86IntelInstPrinter.c
@@ -64,6 +64,7 @@
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O)
{
// FIXME: do this with autogen
+ // printf(">>> ID = %u\n", MI->flat_insn->id);
switch(MI->flat_insn->id) {
default:
SStream_concat0(O, "ptr ");
@@ -72,6 +73,10 @@
case X86_INS_SIDT:
case X86_INS_LGDT:
case X86_INS_LIDT:
+ case X86_INS_FXRSTOR:
+ case X86_INS_FXSAVE:
+ case X86_INS_LJMP:
+ case X86_INS_LCALL:
// do not print "ptr"
break;
}
@@ -194,6 +199,21 @@
SStream_concat0(O, "tbyte ptr ");
MI->x86opsize = 10;
break;
+ case X86_FSTENVm:
+ case X86_FLDENVm:
+ // TODO: fix this in tablegen instead
+ switch(MI->csh->mode) {
+ default: // never reach
+ break;
+ case CS_MODE_16:
+ MI->x86opsize = 14;
+ break;
+ case CS_MODE_32:
+ case CS_MODE_64:
+ MI->x86opsize = 28;
+ break;
+ }
+ break;
}
printMemReference(MI, OpNo, O);
diff --git a/arch/XCore/XCoreDisassembler.h b/arch/XCore/XCoreDisassembler.h
index e50fc55..a747800 100644
--- a/arch/XCore/XCoreDisassembler.h
+++ b/arch/XCore/XCoreDisassembler.h
@@ -4,10 +4,6 @@
#ifndef CS_XCOREDISASSEMBLER_H
#define CS_XCOREDISASSEMBLER_H
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
diff --git a/bindings/java/TestX86.java b/bindings/java/TestX86.java
index e2894b5..72e401e 100644
--- a/bindings/java/TestX86.java
+++ b/bindings/java/TestX86.java
@@ -103,8 +103,6 @@
System.out.printf("\t\toperands[%d].type: REG = %s\n", c, ins.regName(i.value.reg));
if (i.type == X86_OP_IMM)
System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
- if (i.type == X86_OP_FP)
- System.out.printf("\t\toperands[%d].type: FP = %f\n", c, i.value.fp);
if (i.type == X86_OP_MEM) {
System.out.printf("\t\toperands[%d].type: MEM\n",c);
String segment = ins.regName(i.value.mem.segment);
diff --git a/bindings/java/capstone/M68k_const.java b/bindings/java/capstone/M68k_const.java
index a56e811..39402f2 100644
--- a/bindings/java/capstone/M68k_const.java
+++ b/bindings/java/capstone/M68k_const.java
@@ -478,4 +478,13 @@
public static final int M68K_INS_TST = 372;
public static final int M68K_INS_UNLK = 373;
public static final int M68K_INS_UNPK = 374;
+ public static final int M68K_INS_ENDING = 375;
+
+ // Group of M68K instructions
+
+ public static final int M68K_GRP_INVALID = 0;
+ public static final int M68K_GRP_JUMP = 1;
+ public static final int M68K_GRP_RET = 3;
+ public static final int M68K_GRP_IRET = 5;
+ public static final int M68K_GRP_ENDING = 6;
}
\ No newline at end of file
diff --git a/bindings/java/capstone/X86.java b/bindings/java/capstone/X86.java
index 19ed8af..fffbbe2 100644
--- a/bindings/java/capstone/X86.java
+++ b/bindings/java/capstone/X86.java
@@ -29,12 +29,11 @@
public static class OpValue extends Union {
public int reg;
public long imm;
- public double fp;
public MemType mem;
@Override
public List getFieldOrder() {
- return Arrays.asList("reg", "imm", "fp", "mem");
+ return Arrays.asList("reg", "imm", "mem");
}
}
@@ -50,8 +49,6 @@
super.read();
if (type == X86_OP_MEM)
value.setType(MemType.class);
- if (type == X86_OP_FP)
- value.setType(Double.TYPE);
if (type == X86_OP_IMM)
value.setType(Long.TYPE);
if (type == X86_OP_REG)
diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
index c135813..850e8a4 100644
--- a/bindings/java/capstone/X86_const.java
+++ b/bindings/java/capstone/X86_const.java
@@ -303,7 +303,6 @@
public static final int X86_OP_REG = 1;
public static final int X86_OP_IMM = 2;
public static final int X86_OP_MEM = 3;
- public static final int X86_OP_FP = 4;
// XOP Code Condition type
diff --git a/bindings/ocaml/m68k_const.ml b/bindings/ocaml/m68k_const.ml
index 9e0b785..09919bc 100644
--- a/bindings/ocaml/m68k_const.ml
+++ b/bindings/ocaml/m68k_const.ml
@@ -475,3 +475,12 @@
let _M68K_INS_TST = 372;;
let _M68K_INS_UNLK = 373;;
let _M68K_INS_UNPK = 374;;
+let _M68K_INS_ENDING = 375;;
+
+(* Group of M68K instructions *)
+
+let _M68K_GRP_INVALID = 0;;
+let _M68K_GRP_JUMP = 1;;
+let _M68K_GRP_RET = 3;;
+let _M68K_GRP_IRET = 5;;
+let _M68K_GRP_ENDING = 6;;
diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c
index f333cec..038daf8 100644
--- a/bindings/ocaml/ocaml.c
+++ b/bindings/ocaml/ocaml.c
@@ -376,12 +376,8 @@
tmp = caml_alloc(5, 2);
Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm));
break;
- case X86_OP_FP:
- tmp = caml_alloc(5, 3);
- Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->x86.operands[i].fp));
- break;
case X86_OP_MEM:
- tmp = caml_alloc(5, 4);
+ tmp = caml_alloc(5, 3);
tmp2 = caml_alloc(5, 0);
Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment));
Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base));
diff --git a/bindings/ocaml/test_x86.ml b/bindings/ocaml/test_x86.ml
index 4b2409a..ce343e4 100644
--- a/bindings/ocaml/test_x86.ml
+++ b/bindings/ocaml/test_x86.ml
@@ -32,7 +32,6 @@
| X86_OP_INVALID _ -> (); (* this would never happens *)
| X86_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg);
| X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm;
- | X86_OP_FP fp -> printf "\t\top[%d]: FP = %f\n" i fp;
| X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i;
if mem.base != 0 then
printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base);
diff --git a/bindings/ocaml/x86.ml b/bindings/ocaml/x86.ml
index 84b0a29..9e97794 100644
--- a/bindings/ocaml/x86.ml
+++ b/bindings/ocaml/x86.ml
@@ -16,7 +16,6 @@
| X86_OP_INVALID of int
| X86_OP_REG of int
| X86_OP_IMM of int
- | X86_OP_FP of float
| X86_OP_MEM of x86_op_mem
type x86_op = {
diff --git a/bindings/ocaml/x86_const.ml b/bindings/ocaml/x86_const.ml
index 9c2addf..805bf4b 100644
--- a/bindings/ocaml/x86_const.ml
+++ b/bindings/ocaml/x86_const.ml
@@ -300,7 +300,6 @@
let _X86_OP_REG = 1;;
let _X86_OP_IMM = 2;;
let _X86_OP_MEM = 3;;
-let _X86_OP_FP = 4;;
(* XOP Code Condition type *)
diff --git a/bindings/python/Makefile b/bindings/python/Makefile
index 0977218..d63247d 100644
--- a/bindings/python/Makefile
+++ b/bindings/python/Makefile
@@ -132,6 +132,6 @@
check:
@for t in $(TESTS); do \
echo Check $$t ... ; \
- ./$$t > /dev/null && echo OK || echo FAILED; \
+ ./$$t > /dev/null && echo OK || (echo FAILED; exit 1;) \
done
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index cba23d7..851aa90 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -617,12 +617,12 @@
attr = object.__getattribute__
if not attr(self, '_cs')._detail:
- return None
+ raise AttributeError(name)
_dict = attr(self, '__dict__')
if 'operands' not in _dict:
self.__gen_detail()
if name not in _dict:
- return None
+ raise AttributeError(name)
return _dict[name]
# get the last error code
diff --git a/bindings/python/capstone/arm64.py b/bindings/python/capstone/arm64.py
index e33c7df..4ab31b7 100644
--- a/bindings/python/capstone/arm64.py
+++ b/bindings/python/capstone/arm64.py
@@ -38,6 +38,7 @@
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('value', Arm64OpValue),
+ ('access', ctypes.c_uint8),
)
@property
diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py
index 3d11211..1d18349 100644
--- a/bindings/python/capstone/m68k_const.py
+++ b/bindings/python/capstone/m68k_const.py
@@ -475,3 +475,12 @@
M68K_INS_TST = 372
M68K_INS_UNLK = 373
M68K_INS_UNPK = 374
+M68K_INS_ENDING = 375
+
+# Group of M68K instructions
+
+M68K_GRP_INVALID = 0
+M68K_GRP_JUMP = 1
+M68K_GRP_RET = 3
+M68K_GRP_IRET = 5
+M68K_GRP_ENDING = 6
diff --git a/bindings/python/capstone/x86.py b/bindings/python/capstone/x86.py
index 51ba707..f2569cd 100644
--- a/bindings/python/capstone/x86.py
+++ b/bindings/python/capstone/x86.py
@@ -17,7 +17,6 @@
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
- ('fp', ctypes.c_double),
('mem', X86OpMem),
)
@@ -40,10 +39,6 @@
return self.value.reg
@property
- def fp(self):
- return self.value.fp
-
- @property
def mem(self):
return self.value.mem
diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
index 00a7424..943a7e2 100644
--- a/bindings/python/capstone/x86_const.py
+++ b/bindings/python/capstone/x86_const.py
@@ -300,7 +300,6 @@
X86_OP_REG = 1
X86_OP_IMM = 2
X86_OP_MEM = 3
-X86_OP_FP = 4
# XOP Code Condition type
diff --git a/bindings/python/test_arm64.py b/bindings/python/test_arm64.py
index 2950a7f..f6c7a42 100755
--- a/bindings/python/test_arm64.py
+++ b/bindings/python/test_arm64.py
@@ -75,6 +75,14 @@
if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
+ if i.access == CS_AC_READ:
+ print("\t\toperands[%u].access: READ\n" % (c))
+ elif i.access == CS_AC_WRITE:
+ print("\t\toperands[%u].access: WRITE\n" % (c))
+ elif i.access == CS_AC_READ | CS_AC_WRITE:
+ print("\t\toperands[%u].access: READ | WRITE\n" % (c))
+
+
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
@@ -82,6 +90,20 @@
if insn.update_flags:
print("\tUpdate-flags: True")
+ (regs_read, regs_write) = insn.regs_access()
+
+ if len(regs_read) > 0:
+ print("\tRegisters read:", end="")
+ for r in regs_read:
+ print(" %s" %(insn.reg_name(r)), end="")
+ print("")
+
+ if len(regs_write) > 0:
+ print("\tRegisters modified:", end="")
+ for r in regs_write:
+ print(" %s" %(insn.reg_name(r)), end="")
+ print("")
+
# ## Test class Cs
def test_class():
diff --git a/bindings/python/test_m68k.py b/bindings/python/test_m68k.py
index f462c52..8ae1f58 100755
--- a/bindings/python/test_m68k.py
+++ b/bindings/python/test_m68k.py
@@ -6,7 +6,7 @@
from capstone.m68k import *
from xprint import to_hex, to_x
-M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
+M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
all_tests = (
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"),
@@ -40,11 +40,12 @@
16: "Absolute Data Addressing - Short",
17: "Absolute Data Addressing - Long",
18: "Immidate value",
-}
+}
def print_insn_detail(insn):
if len(insn.operands) > 0:
print("\top_count: %u" % (len(insn.operands)))
+ print("\tgroups_count: %u" % len(insn.groups))
for i, op in enumerate(insn.operands):
if op.type == M68K_OP_REG:
diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py
index b1ba8f8..3b77c75 100755
--- a/bindings/python/test_x86.py
+++ b/bindings/python/test_x86.py
@@ -99,8 +99,6 @@
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == X86_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
- if i.type == X86_OP_FP:
- print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == X86_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.segment != 0:
diff --git a/contrib/objdump/objdump-m68k.py b/contrib/objdump/objdump-m68k.py
index fd2be31..fd59d7c 100644
--- a/contrib/objdump/objdump-m68k.py
+++ b/contrib/objdump/objdump-m68k.py
@@ -149,14 +149,14 @@
if op.address_mode in [ M68K_AM_PCI_INDEX_8_BIT_DISP, M68K_AM_AREGI_INDEX_8_BIT_DISP ]:
disp = op.mem.disp
- if op.mem.register_bits == 2:
+ if op.register_bits == 2:
disp = extsign8(op.mem.disp)
- if op.mem.register_bits == 4:
+ if op.register_bits == 4:
disp = extsign1632(op.mem.disp)
str = dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016x}".format(disp) + "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size]
- if op.mem.register_bits:
- str += format(":%u" % (op.mem.register_bits))
+ if op.register_bits:
+ str += format(":%u" % (op.register_bits))
return str + ")"
@@ -165,8 +165,8 @@
str += format("@(%016x)@(%016x" % (extsign1632(op.mem.in_disp), extsign1632(op.mem.out_disp)))
if op.mem.index_reg:
str += "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size]
- if op.mem.register_bits:
- str += format(":%u" % (op.mem.register_bits))
+ if op.register_bits:
+ str += format(":%u" % (op.register_bits))
str += ")"
return str
diff --git a/cs.c b/cs.c
index e668932..b57d02f 100644
--- a/cs.c
+++ b/cs.c
@@ -88,18 +88,27 @@
#if defined(CAPSTONE_USE_SYS_DYN_MEM)
#if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE)
+// default
cs_malloc_t cs_mem_malloc = malloc;
cs_calloc_t cs_mem_calloc = calloc;
cs_realloc_t cs_mem_realloc = realloc;
cs_free_t cs_mem_free = free;
+#if defined(_WIN32_WCE)
+cs_vsnprintf_t cs_vsnprintf = _vsnprintf;
+#else
cs_vsnprintf_t cs_vsnprintf = vsnprintf;
+#endif // defined(_WIN32_WCE)
+
#elif defined(_KERNEL_MODE)
+// Windows driver
cs_malloc_t cs_mem_malloc = cs_winkernel_malloc;
cs_calloc_t cs_mem_calloc = cs_winkernel_calloc;
cs_realloc_t cs_mem_realloc = cs_winkernel_realloc;
cs_free_t cs_mem_free = cs_winkernel_free;
cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf;
+
#else
+// OSX kernel
extern void* kern_os_malloc(size_t size);
extern void kern_os_free(void* addr);
extern void* kern_os_realloc(void* addr, size_t nsize);
@@ -114,14 +123,17 @@
cs_realloc_t cs_mem_realloc = kern_os_realloc;
cs_free_t cs_mem_free = kern_os_free;
cs_vsnprintf_t cs_vsnprintf = vsnprintf;
-#endif
+
+#endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE)
#else
+// User-defined
cs_malloc_t cs_mem_malloc = NULL;
cs_calloc_t cs_mem_calloc = NULL;
cs_realloc_t cs_mem_realloc = NULL;
cs_free_t cs_mem_free = NULL;
cs_vsnprintf_t cs_vsnprintf = NULL;
-#endif
+
+#endif // defined(CAPSTONE_USE_SYS_DYN_MEM)
CAPSTONE_EXPORT
unsigned int CAPSTONE_API cs_version(int *major, int *minor)
@@ -577,6 +589,10 @@
handle->errnum = CS_ERR_OK;
+ // reset IT block of ARM structure
+ if (handle->arch == CS_ARCH_ARM)
+ handle->ITBlock.size = 0;
+
#ifdef CAPSTONE_USE_SYS_DYN_MEM
if (count > 0 && count <= INSN_CACHE_SIZE)
cache_size = (unsigned int) count;
diff --git a/include/capstone/arm.h b/include/capstone/arm.h
index 40fa593..5cfc0c9 100644
--- a/include/capstone/arm.h
+++ b/include/capstone/arm.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -252,67 +248,6 @@
ARM_VECTORDATA_F64U32, // f64.u32
} arm_vectordata_type;
-// Instruction's operand referring to memory
-// This is associated with ARM_OP_MEM operand type above
-typedef struct arm_op_mem {
- unsigned int base; // base register
- unsigned int index; // index register
- int scale; // scale for index register (can be 1, or -1)
- int disp; // displacement/offset value
- int lshift; // left-shift on index register, or 0 if irrelevant.
-} arm_op_mem;
-
-// Instruction operand
-typedef struct cs_arm_op {
- int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
-
- struct {
- arm_shifter type;
- unsigned int value;
- } shift;
-
- arm_op_type type; // operand type
-
- union {
- unsigned int reg; // register value for REG/SYSREG operand
- int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand
- double fp; // floating point value for FP operand
- arm_op_mem mem; // base/index/scale/disp value for MEM operand
- arm_setend_type setend; // SETEND instruction's operand type
- };
-
- // in some instructions, an operand can be subtracted or added to
- // the base register,
- bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added.
-
- // How is this operand accessed? (READ, WRITE or READ|WRITE)
- // This field is combined of cs_ac_type.
- // NOTE: this field is irrelevant if engine is compiled in DIET mode.
- uint8_t access;
-
- // Neon lane index for NEON instructions (or -1 if irrelevant)
- int8_t neon_lane;
-} cs_arm_op;
-
-// Instruction structure
-typedef struct cs_arm {
- bool usermode; // User-mode registers to be loaded (for LDM/STM instructions)
- int vector_size; // Scalar size for vector instructions
- arm_vectordata_type vector_data; // Data type for elements of vector instructions
- arm_cpsmode_type cps_mode; // CPS mode for CPS instruction
- arm_cpsflag_type cps_flag; // CPS mode for CPS instruction
- arm_cc cc; // conditional code for this insn
- bool update_flags; // does this insn update flags?
- bool writeback; // does this insn write-back?
- arm_mem_barrier mem_barrier; // Option for some memory barrier instructions
-
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
-
- cs_arm_op operands[36]; // operands for this instruction.
-} cs_arm;
-
//> ARM registers
typedef enum arm_reg {
ARM_REG_INVALID = 0,
@@ -440,6 +375,67 @@
ARM_REG_IP = ARM_REG_R12,
} arm_reg;
+// Instruction's operand referring to memory
+// This is associated with ARM_OP_MEM operand type above
+typedef struct arm_op_mem {
+ arm_reg base; // base register
+ arm_reg index; // index register
+ int scale; // scale for index register (can be 1, or -1)
+ int disp; // displacement/offset value
+ int lshift; // left-shift on index register, or 0 if irrelevant.
+} arm_op_mem;
+
+// Instruction operand
+typedef struct cs_arm_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
+
+ struct {
+ arm_shifter type;
+ unsigned int value;
+ } shift;
+
+ arm_op_type type; // operand type
+
+ union {
+ int reg; // register value for REG/SYSREG operand
+ int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand
+ double fp; // floating point value for FP operand
+ arm_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm_setend_type setend; // SETEND instruction's operand type
+ };
+
+ // in some instructions, an operand can be subtracted or added to
+ // the base register,
+ bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added.
+
+ // How is this operand accessed? (READ, WRITE or READ|WRITE)
+ // This field is combined of cs_ac_type.
+ // NOTE: this field is irrelevant if engine is compiled in DIET mode.
+ uint8_t access;
+
+ // Neon lane index for NEON instructions (or -1 if irrelevant)
+ int8_t neon_lane;
+} cs_arm_op;
+
+// Instruction structure
+typedef struct cs_arm {
+ bool usermode; // User-mode registers to be loaded (for LDM/STM instructions)
+ int vector_size; // Scalar size for vector instructions
+ arm_vectordata_type vector_data; // Data type for elements of vector instructions
+ arm_cpsmode_type cps_mode; // CPS mode for CPS instruction
+ arm_cpsflag_type cps_flag; // CPS mode for CPS instruction
+ arm_cc cc; // conditional code for this insn
+ bool update_flags; // does this insn update flags?
+ bool writeback; // does this insn write-back?
+ arm_mem_barrier mem_barrier; // Option for some memory barrier instructions
+
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+
+ cs_arm_op operands[36]; // operands for this instruction.
+} cs_arm;
+
//> ARM instruction
typedef enum arm_insn {
ARM_INS_INVALID = 0,
diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h
index afd6292..5811a6b 100644
--- a/include/capstone/arm64.h
+++ b/include/capstone/arm64.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -346,54 +342,6 @@
ARM64_PRFM_PSTL3STRM = 0x15 + 1,
} arm64_prefetch_op;
-// Instruction's operand referring to memory
-// This is associated with ARM64_OP_MEM operand type above
-typedef struct arm64_op_mem {
- unsigned int base; // base register
- unsigned int index; // index register
- int32_t disp; // displacement/offset value
-} arm64_op_mem;
-
-// Instruction operand
-typedef struct cs_arm64_op {
- int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
- arm64_vas vas; // Vector Arrangement Specifier
- arm64_vess vess; // Vector Element Size Specifier
- struct {
- arm64_shifter type; // shifter type of this operand
- unsigned int value; // shifter value of this operand
- } shift;
- arm64_extender ext; // extender type of this operand
- arm64_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int64_t imm; // immediate value, or index for C-IMM or IMM operand
- double fp; // floating point value for FP operand
- arm64_op_mem mem; // base/index/scale/disp value for MEM operand
- arm64_pstate pstate; // PState field of MSR instruction.
- unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
- arm64_prefetch_op prefetch; // PRFM operation.
- arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions).
- };
-
- // How is this operand accessed? (READ, WRITE or READ|WRITE)
- // This field is combined of cs_ac_type.
- // NOTE: this field is irrelevant if engine is compiled in DIET mode.
- cs_ac_type access;
-} cs_arm64_op;
-
-// Instruction structure
-typedef struct cs_arm64 {
- arm64_cc cc; // conditional code for this insn
- bool update_flags; // does this insn update flags?
- bool writeback; // does this insn request writeback? 'True' means 'yes'
-
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
-
- cs_arm64_op operands[8]; // operands for this instruction.
-} cs_arm64;
//> ARM64 registers
typedef enum arm64_reg {
@@ -670,6 +618,55 @@
ARM64_REG_LR = ARM64_REG_X30,
} arm64_reg;
+// Instruction's operand referring to memory
+// This is associated with ARM64_OP_MEM operand type above
+typedef struct arm64_op_mem {
+ arm64_reg base; // base register
+ arm64_reg index; // index register
+ int32_t disp; // displacement/offset value
+} arm64_op_mem;
+
+// Instruction operand
+typedef struct cs_arm64_op {
+ int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
+ arm64_vas vas; // Vector Arrangement Specifier
+ arm64_vess vess; // Vector Element Size Specifier
+ struct {
+ arm64_shifter type; // shifter type of this operand
+ unsigned int value; // shifter value of this operand
+ } shift;
+ arm64_extender ext; // extender type of this operand
+ arm64_op_type type; // operand type
+ union {
+ arm64_reg reg; // register value for REG operand
+ int64_t imm; // immediate value, or index for C-IMM or IMM operand
+ double fp; // floating point value for FP operand
+ arm64_op_mem mem; // base/index/scale/disp value for MEM operand
+ arm64_pstate pstate; // PState field of MSR instruction.
+ unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
+ arm64_prefetch_op prefetch; // PRFM operation.
+ arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions).
+ };
+
+ // How is this operand accessed? (READ, WRITE or READ|WRITE)
+ // This field is combined of cs_ac_type.
+ // NOTE: this field is irrelevant if engine is compiled in DIET mode.
+ uint8_t access;
+} cs_arm64_op;
+
+// Instruction structure
+typedef struct cs_arm64 {
+ arm64_cc cc; // conditional code for this insn
+ bool update_flags; // does this insn update flags?
+ bool writeback; // does this insn request writeback? 'True' means 'yes'
+
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+
+ cs_arm64_op operands[8]; // operands for this instruction.
+} cs_arm64;
+
//> ARM64 instruction
typedef enum arm64_insn {
ARM64_INS_INVALID = 0,
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index 61bb35e..11eb8b4 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h
index eb86889..91f69e5 100644
--- a/include/capstone/m68k.h
+++ b/include/capstone/m68k.h
@@ -2,16 +2,12 @@
#define CAPSTONE_M68K_H
/* Capstone Disassembly Engine */
-/* By Daniel Collin <daniel@collin.com>, 2015 */
+/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
#ifdef __cplusplus
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -80,7 +76,7 @@
} m68k_reg;
//> M68K Addressing Modes
-typedef enum m68k_adress_mode {
+typedef enum m68k_address_mode {
M68K_AM_NONE = 0, // No address mode.
M68K_AM_REG_DIRECT_DATA, // Register Direct - Data
@@ -107,8 +103,8 @@
M68K_AM_ABSOLUTE_DATA_SHORT, // Absolute Data Addressing - Short
M68K_AM_ABSOLUTE_DATA_LONG, // Absolute Data Addressing - Long
- M68K_AM_IMMIDIATE, // Immidate value
-} m68k_adress_mode;
+ M68K_AM_IMMIDIATE, // Immediate value
+} m68k_address_mode;
//> Operand type for instruction's operands
typedef enum m68k_op_type {
@@ -117,7 +113,7 @@
M68K_OP_IMM, // = CS_OP_IMM (Immediate operand).
M68K_OP_MEM, // = CS_OP_MEM (Memory operand).
M68K_OP_FP, // = CS_OP_FP (Floating-Point operand)
- M68K_OP_REG_BITS, // Registes bits movem
+ M68K_OP_REG_BITS, // Register bits move
M68K_OP_REG_PAIR, // Register pair in the same op (upper 4 bits for first reg, lower for second)
} m68k_op_type;
@@ -128,11 +124,11 @@
m68k_reg index_reg; // index register (or M68K_REG_INVALID if irrelevant)
m68k_reg in_base_reg; // indirect base register (or M68K_REG_INVALID if irrelevant)
uint32_t in_disp; // indirect displacement
- uint32_t out_disp; // outher displacement
+ uint32_t out_disp; // other displacement
uint16_t disp; // displacement value
uint8_t scale; // scale for index register
- uint8_t bitfield; // set to true if the two values bellow should be used
- uint8_t width; // used for bf* instructions
+ uint8_t bitfield; // set to true if the two values below should be used
+ uint8_t width; // used for bf* instructions
uint8_t offset; // used for bf* instructions
uint8_t index_size; // 0 = w, 1 = l
} m68k_op_mem;
@@ -148,10 +144,10 @@
uint32_t register_bits; // register bits for movem/cas2/etc (always in d0-d7, a0-a7, fp0 - fp7 order)
};
m68k_op_type type;
- m68k_adress_mode address_mode; // M68K addressing mode for this op
+ m68k_address_mode address_mode; // M68K addressing mode for this op
} cs_m68k_op;
-// Operation size of the CPU instructions
+// Operation size of the CPU instructions
typedef enum m68k_cpu_size {
M68K_CPU_SIZE_NONE = 0, // unsized or unspecified
M68K_CPU_SIZE_BYTE = 1, // 1 byte in size
@@ -162,8 +158,8 @@
// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
typedef enum m68k_fpu_size {
M68K_FPU_SIZE_NONE = 0, // unsized like fsave/frestore
- M68K_FPU_SIZE_SINGLE = 4, // 4 byte in size (single float)
- M68K_FPU_SIZE_DOUBLE = 8, // 8 byte in size (double)
+ M68K_FPU_SIZE_SINGLE = 4, // 4 byte in size (single float)
+ M68K_FPU_SIZE_DOUBLE = 8, // 8 byte in size (double)
M68K_FPU_SIZE_EXTENDED = 12, // 12 byte in size (extended real format)
} m68k_fpu_size;
@@ -570,8 +566,20 @@
M68K_INS_TST,
M68K_INS_UNLK,
M68K_INS_UNPK,
+ M68K_INS_ENDING, // <-- mark the end of the list of instructions
+
} m68k_insn;
+//> Group of M68K instructions
+typedef enum m68k_group_type {
+ M68K_GRP_INVALID = 0, // CS_GRUP_INVALID
+ M68K_GRP_JUMP, // = CS_GRP_JUMP
+ M68K_GRP_RET = 3, // = CS_GRP_RET
+ M68K_GRP_IRET = 5, // = CS_GRP_IRET
+
+ M68K_GRP_ENDING,// <-- mark the end of the list of groups
+} m68k_group_type;
+
#ifdef __cplusplus
}
#endif
diff --git a/include/capstone/mips.h b/include/capstone/mips.h
index 2e43512..2c1282a 100644
--- a/include/capstone/mips.h
+++ b/include/capstone/mips.h
@@ -8,10 +8,13 @@
extern "C" {
#endif
+<<<<<<< HEAD
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
+=======
+>>>>>>> upstream/next
#include "platform.h"
// GCC MIPS toolchain has a default macro called "mips" which breaks
@@ -30,31 +33,6 @@
MIPS_OP_MEM, // = CS_OP_MEM (Memory operand).
} mips_op_type;
-// Instruction's operand referring to memory
-// This is associated with MIPS_OP_MEM operand type above
-typedef struct mips_op_mem {
- unsigned int base; // base register
- int64_t disp; // displacement/offset value
-} mips_op_mem;
-
-// Instruction operand
-typedef struct cs_mips_op {
- mips_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int64_t imm; // immediate value for IMM operand
- mips_op_mem mem; // base/index/scale/disp value for MEM operand
- };
-} cs_mips_op;
-
-// Instruction structure
-typedef struct cs_mips {
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
- cs_mips_op operands[8]; // operands for this instruction.
-} cs_mips;
-
//> MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
@@ -258,6 +236,31 @@
MIPS_REG_LO3 = MIPS_REG_HI3,
} mips_reg;
+// Instruction's operand referring to memory
+// This is associated with MIPS_OP_MEM operand type above
+typedef struct mips_op_mem {
+ mips_reg base; // base register
+ int64_t disp; // displacement/offset value
+} mips_op_mem;
+
+// Instruction operand
+typedef struct cs_mips_op {
+ mips_op_type type; // operand type
+ union {
+ mips_reg reg; // register value for REG operand
+ int64_t imm; // immediate value for IMM operand
+ mips_op_mem mem; // base/index/scale/disp value for MEM operand
+ };
+} cs_mips_op;
+
+// Instruction structure
+typedef struct cs_mips {
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_mips_op operands[8]; // operands for this instruction.
+} cs_mips;
+
//> MIPS instruction
typedef enum mips_insn {
MIPS_INS_INVALID = 0,
diff --git a/include/capstone/platform.h b/include/capstone/platform.h
index 2ff28d3..7455b8a 100644
--- a/include/capstone/platform.h
+++ b/include/capstone/platform.h
@@ -4,6 +4,7 @@
#ifndef CAPSTONE_PLATFORM_H
#define CAPSTONE_PLATFORM_H
+
// handle C99 issue (for pre-2013 VisualStudio)
#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
// MSVC
@@ -15,20 +16,24 @@
typedef unsigned char bool;
#define false 0
#define true 1
-#endif
+#endif // __cplusplus
#else
// VisualStudio 2013+ -> C99 is supported
#include <stdbool.h>
-#endif
+#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
#else
// not MSVC -> C99 is supported
#include <stdbool.h>
-#endif
+#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
-// handle C99 issue (for pre-2013 VisualStudio)
+// handle inttypes.h / stdint.h compatibility
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/stdint.h"
+#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+
#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
// this system does not have inttypes.h
@@ -55,7 +60,7 @@
#define UINT16_MAX 0xffffui16
#define UINT32_MAX 0xffffffffui32
#define UINT64_MAX 0xffffffffffffffffui64
-#endif
+#endif // defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))
#define __PRI_8_LENGTH_MODIFIER__ "hh"
#define __PRI_64_LENGTH_MODIFIER__ "ll"
@@ -88,7 +93,7 @@
#define PRIu32 "u"
#define PRIx32 "x"
#define PRIX32 "X"
-#endif
+#endif // defined(_MSC_VER) && _MSC_VER <= 1700
#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
@@ -100,6 +105,6 @@
#else
// this system has inttypes.h by default
#include <inttypes.h>
-#endif
+#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
#endif
diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h
index c9add21..996eb45 100644
--- a/include/capstone/ppc.h
+++ b/include/capstone/ppc.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -51,47 +47,6 @@
PPC_OP_CRX = 64, // Condition Register field
} ppc_op_type;
-// Instruction's operand referring to memory
-// This is associated with PPC_OP_MEM operand type above
-typedef struct ppc_op_mem {
- unsigned int base; // base register
- int32_t disp; // displacement/offset value
-} ppc_op_mem;
-
-typedef struct ppc_op_crx {
- unsigned int scale;
- unsigned int reg;
- ppc_bc cond;
-} ppc_op_crx;
-
-// Instruction operand
-typedef struct cs_ppc_op {
- ppc_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int64_t imm; // immediate value for IMM operand
- ppc_op_mem mem; // base/disp value for MEM operand
- ppc_op_crx crx; // operand with condition register
- };
-} cs_ppc_op;
-
-// Instruction structure
-typedef struct cs_ppc {
- // branch code for branch instructions
- ppc_bc bc;
-
- // branch hint for branch instructions
- ppc_bh bh;
-
- // if update_cr0 = True, then this 'dot' insn updates CR0
- bool update_cr0;
-
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
- cs_ppc_op operands[8]; // operands for this instruction.
-} cs_ppc;
-
//> PPC registers
typedef enum ppc_reg {
PPC_REG_INVALID = 0,
@@ -311,6 +266,47 @@
PPC_REG_ENDING, // <-- mark the end of the list of registers
} ppc_reg;
+// Instruction's operand referring to memory
+// This is associated with PPC_OP_MEM operand type above
+typedef struct ppc_op_mem {
+ ppc_reg base; // base register
+ int32_t disp; // displacement/offset value
+} ppc_op_mem;
+
+typedef struct ppc_op_crx {
+ unsigned int scale;
+ ppc_reg reg;
+ ppc_bc cond;
+} ppc_op_crx;
+
+// Instruction operand
+typedef struct cs_ppc_op {
+ ppc_op_type type; // operand type
+ union {
+ ppc_reg reg; // register value for REG operand
+ int64_t imm; // immediate value for IMM operand
+ ppc_op_mem mem; // base/disp value for MEM operand
+ ppc_op_crx crx; // operand with condition register
+ };
+} cs_ppc_op;
+
+// Instruction structure
+typedef struct cs_ppc {
+ // branch code for branch instructions
+ ppc_bc bc;
+
+ // branch hint for branch instructions
+ ppc_bh bh;
+
+ // if update_cr0 = True, then this 'dot' insn updates CR0
+ bool update_cr0;
+
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_ppc_op operands[8]; // operands for this instruction.
+} cs_ppc;
+
//> PPC instruction
typedef enum ppc_insn {
PPC_INS_INVALID = 0,
diff --git a/include/capstone/sparc.h b/include/capstone/sparc.h
index 343c845..2154314 100644
--- a/include/capstone/sparc.h
+++ b/include/capstone/sparc.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
// GCC SPARC toolchain has a default macro called "sparc" which breaks
@@ -78,34 +74,6 @@
SPARC_OP_MEM, // = CS_OP_MEM (Memory operand).
} sparc_op_type;
-// Instruction's operand referring to memory
-// This is associated with SPARC_OP_MEM operand type above
-typedef struct sparc_op_mem {
- uint8_t base; // base register
- uint8_t index; // index register
- int32_t disp; // displacement/offset value
-} sparc_op_mem;
-
-// Instruction operand
-typedef struct cs_sparc_op {
- sparc_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int32_t imm; // immediate value for IMM operand
- sparc_op_mem mem; // base/disp value for MEM operand
- };
-} cs_sparc_op;
-
-// Instruction structure
-typedef struct cs_sparc {
- sparc_cc cc; // code condition for this insn
- sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint.
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
- cs_sparc_op operands[4]; // operands for this instruction.
-} cs_sparc;
-
//> SPARC registers
typedef enum sparc_reg {
SPARC_REG_INVALID = 0,
@@ -207,6 +175,36 @@
SPARC_REG_I6 = SPARC_REG_FP,
} sparc_reg;
+// Instruction's operand referring to memory
+// This is associated with SPARC_OP_MEM operand type above
+typedef struct sparc_op_mem {
+ uint8_t base; // base register, can be safely interpreted as
+ // a value of type `sparc_reg`, but it is only
+ // one byte wide
+ uint8_t index; // index register, same conditions apply here
+ int32_t disp; // displacement/offset value
+} sparc_op_mem;
+
+// Instruction operand
+typedef struct cs_sparc_op {
+ sparc_op_type type; // operand type
+ union {
+ sparc_reg reg; // register value for REG operand
+ int32_t imm; // immediate value for IMM operand
+ sparc_op_mem mem; // base/disp value for MEM operand
+ };
+} cs_sparc_op;
+
+// Instruction structure
+typedef struct cs_sparc {
+ sparc_cc cc; // code condition for this insn
+ sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint.
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_sparc_op operands[4]; // operands for this instruction.
+} cs_sparc;
+
//> SPARC instruction
typedef enum sparc_insn {
SPARC_INS_INVALID = 0,
diff --git a/include/capstone/systemz.h b/include/capstone/systemz.h
index d91706e..d9c151a 100644
--- a/include/capstone/systemz.h
+++ b/include/capstone/systemz.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -47,34 +43,6 @@
SYSZ_OP_ACREG = 64, // Access register operand.
} sysz_op_type;
-// Instruction's operand referring to memory
-// This is associated with SYSZ_OP_MEM operand type above
-typedef struct sysz_op_mem {
- uint8_t base; // base register
- uint8_t index; // index register
- uint64_t length; // BDLAddr operand
- int64_t disp; // displacement/offset value
-} sysz_op_mem;
-
-// Instruction operand
-typedef struct cs_sysz_op {
- sysz_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int64_t imm; // immediate value for IMM operand
- sysz_op_mem mem; // base/disp value for MEM operand
- };
-} cs_sysz_op;
-
-// Instruction structure
-typedef struct cs_sysz {
- sysz_cc cc; // Code condition
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
- cs_sysz_op operands[6]; // operands for this instruction.
-} cs_sysz;
-
//> SystemZ registers
typedef enum sysz_reg {
SYSZ_REG_INVALID = 0,
@@ -118,6 +86,36 @@
SYSZ_REG_ENDING,
} sysz_reg;
+// Instruction's operand referring to memory
+// This is associated with SYSZ_OP_MEM operand type above
+typedef struct sysz_op_mem {
+ uint8_t base; // base register, can be safely interpreted as
+ // a value of type `sysz_reg`, but it is only
+ // one byte wide
+ uint8_t index; // index register, same conditions apply here
+ uint64_t length; // BDLAddr operand
+ int64_t disp; // displacement/offset value
+} sysz_op_mem;
+
+// Instruction operand
+typedef struct cs_sysz_op {
+ sysz_op_type type; // operand type
+ union {
+ sysz_reg reg; // register value for REG operand
+ int64_t imm; // immediate value for IMM operand
+ sysz_op_mem mem; // base/disp value for MEM operand
+ };
+} cs_sysz_op;
+
+// Instruction structure
+typedef struct cs_sysz {
+ sysz_cc cc; // Code condition
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_sysz_op operands[6]; // operands for this instruction.
+} cs_sysz;
+
//> SystemZ instruction
typedef enum sysz_insn {
SYSZ_INS_INVALID = 0,
diff --git a/include/capstone/x86.h b/include/capstone/x86.h
index 17ad3bd..dbabbe6 100644
--- a/include/capstone/x86.h
+++ b/include/capstone/x86.h
@@ -8,9 +8,7 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
+#include "platform.h"
// Calculate relative address for X86-64, given cs_insn structure
#define X86_REL_ADDR(insn) (insn.address + insn.size + insn.detail->x86.disp)
@@ -125,7 +123,6 @@
X86_OP_REG, // = CS_OP_REG (Register operand).
X86_OP_IMM, // = CS_OP_IMM (Immediate operand).
X86_OP_MEM, // = CS_OP_MEM (Memory operand).
- X86_OP_FP, // = CS_OP_FP (Floating-Point operand).
} x86_op_type;
//> XOP Code Condition type
@@ -243,7 +240,6 @@
union {
x86_reg reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
- double fp; // floating point value for FP operand
x86_op_mem mem; // base/index/scale/disp value for MEM operand
};
diff --git a/include/capstone/xcore.h b/include/capstone/xcore.h
index 6376662..13c383b 100644
--- a/include/capstone/xcore.h
+++ b/include/capstone/xcore.h
@@ -8,10 +8,6 @@
extern "C" {
#endif
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
#include "platform.h"
#ifdef _MSC_VER
@@ -26,33 +22,6 @@
XCORE_OP_MEM, // = CS_OP_MEM (Memory operand).
} xcore_op_type;
-// Instruction's operand referring to memory
-// This is associated with XCORE_OP_MEM operand type above
-typedef struct xcore_op_mem {
- uint8_t base; // base register
- uint8_t index; // index register
- int32_t disp; // displacement/offset value
- int direct; // +1: forward, -1: backward
-} xcore_op_mem;
-
-// Instruction operand
-typedef struct cs_xcore_op {
- xcore_op_type type; // operand type
- union {
- unsigned int reg; // register value for REG operand
- int32_t imm; // immediate value for IMM operand
- xcore_op_mem mem; // base/disp value for MEM operand
- };
-} cs_xcore_op;
-
-// Instruction structure
-typedef struct cs_xcore {
- // Number of operands of this instruction,
- // or 0 when instruction has no operand.
- uint8_t op_count;
- cs_xcore_op operands[8]; // operands for this instruction.
-} cs_xcore;
-
//> XCore registers
typedef enum xcore_reg {
XCORE_REG_INVALID = 0,
@@ -91,6 +60,35 @@
XCORE_REG_ENDING, // <-- mark the end of the list of registers
} xcore_reg;
+// Instruction's operand referring to memory
+// This is associated with XCORE_OP_MEM operand type above
+typedef struct xcore_op_mem {
+ uint8_t base; // base register, can be safely interpreted as
+ // a value of type `xcore_reg`, but it is only
+ // one byte wide
+ uint8_t index; // index register, same conditions apply here
+ int32_t disp; // displacement/offset value
+ int direct; // +1: forward, -1: backward
+} xcore_op_mem;
+
+// Instruction operand
+typedef struct cs_xcore_op {
+ xcore_op_type type; // operand type
+ union {
+ xcore_reg reg; // register value for REG operand
+ int32_t imm; // immediate value for IMM operand
+ xcore_op_mem mem; // base/disp value for MEM operand
+ };
+} cs_xcore_op;
+
+// Instruction structure
+typedef struct cs_xcore {
+ // Number of operands of this instruction,
+ // or 0 when instruction has no operand.
+ uint8_t op_count;
+ cs_xcore_op operands[8]; // operands for this instruction.
+} cs_xcore;
+
//> XCore instruction
typedef enum xcore_insn {
XCORE_INS_INVALID = 0,
diff --git a/include/windowsce/intrin.h b/include/windowsce/intrin.h
new file mode 100644
index 0000000..e9cdc59
--- /dev/null
+++ b/include/windowsce/intrin.h
@@ -0,0 +1,12 @@
+
+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN)
+#define _STDINT
+
+#ifdef _M_ARM
+#include <armintr.h>
+#if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#include <arm_neon.h>
+#endif
+#endif // _M_ARM
+
+#endif
diff --git a/include/windowsce/stdint.h b/include/windowsce/stdint.h
new file mode 100644
index 0000000..014a163
--- /dev/null
+++ b/include/windowsce/stdint.h
@@ -0,0 +1,133 @@
+
+#if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT)
+#define _STDINT
+
+typedef __int8
+ int8_t,
+ int_least8_t;
+
+typedef __int16
+ int16_t,
+ int_least16_t;
+
+typedef __int32
+ int32_t,
+ int_least32_t,
+ int_fast8_t,
+ int_fast16_t,
+ int_fast32_t;
+
+typedef __int64
+ int64_t,
+ intmax_t,
+ int_least64_t,
+ int_fast64_t;
+
+typedef unsigned __int8
+ uint8_t,
+ uint_least8_t;
+
+typedef unsigned __int16
+ uint16_t,
+ uint_least16_t;
+
+typedef unsigned __int32
+ uint32_t,
+ uint_least32_t,
+ uint_fast8_t,
+ uint_fast16_t,
+ uint_fast32_t;
+
+typedef unsigned __int64
+ uint64_t,
+ uintmax_t,
+ uint_least64_t,
+ uint_fast64_t;
+
+#ifndef _INTPTR_T_DEFINED
+#define _INTPTR_T_DEFINED
+typedef __int32 intptr_t;
+#endif
+
+#ifndef _UINTPTR_T_DEFINED
+#define _UINTPTR_T_DEFINED
+typedef unsigned __int32 uintptr_t;
+#endif
+
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
+
+#define INT_LEAST8_MIN INT8_MIN
+#define INT_LEAST16_MIN INT16_MIN
+#define INT_LEAST32_MIN INT32_MIN
+#define INT_LEAST64_MIN INT64_MIN
+#define INT_LEAST8_MAX INT8_MAX
+#define INT_LEAST16_MAX INT16_MAX
+#define INT_LEAST32_MAX INT32_MAX
+#define INT_LEAST64_MAX INT64_MAX
+#define UINT_LEAST8_MAX UINT8_MAX
+#define UINT_LEAST16_MAX UINT16_MAX
+#define UINT_LEAST32_MAX UINT32_MAX
+#define UINT_LEAST64_MAX UINT64_MAX
+
+#define INT_FAST8_MIN INT8_MIN
+#define INT_FAST16_MIN INT32_MIN
+#define INT_FAST32_MIN INT32_MIN
+#define INT_FAST64_MIN INT64_MIN
+#define INT_FAST8_MAX INT8_MAX
+#define INT_FAST16_MAX INT32_MAX
+#define INT_FAST32_MAX INT32_MAX
+#define INT_FAST64_MAX INT64_MAX
+#define UINT_FAST8_MAX UINT8_MAX
+#define UINT_FAST16_MAX UINT32_MAX
+#define UINT_FAST32_MAX UINT32_MAX
+#define UINT_FAST64_MAX UINT64_MAX
+
+#define INTPTR_MIN INT32_MIN
+#define INTPTR_MAX INT32_MAX
+#define UINTPTR_MAX UINT32_MAX
+
+#define INTMAX_MIN INT64_MIN
+#define INTMAX_MAX INT64_MAX
+#define UINTMAX_MAX UINT64_MAX
+
+#define PTRDIFF_MIN INTPTR_MIN
+#define PTRDIFF_MAX INTPTR_MAX
+
+#ifndef SIZE_MAX
+#define SIZE_MAX UINTPTR_MAX
+#endif
+
+#define SIG_ATOMIC_MIN INT32_MIN
+#define SIG_ATOMIC_MAX INT32_MAX
+
+#define WCHAR_MIN 0x0000
+#define WCHAR_MAX 0xffff
+
+#define WINT_MIN 0x0000
+#define WINT_MAX 0xffff
+
+#define INT8_C(x) (x)
+#define INT16_C(x) (x)
+#define INT32_C(x) (x)
+#define INT64_C(x) (x ## LL)
+
+#define UINT8_C(x) (x)
+#define UINT16_C(x) (x)
+#define UINT32_C(x) (x ## U)
+#define UINT64_C(x) (x ## ULL)
+
+#define INTMAX_C(x) INT64_C(x)
+#define UINTMAX_C(x) UINT64_C(x)
+
+#endif
diff --git a/tests/test_m68k.c b/tests/test_m68k.c
index 557a062..ead076a 100644
--- a/tests/test_m68k.c
+++ b/tests/test_m68k.c
@@ -56,21 +56,25 @@
"Absolute Data Addressing - Short",
"Absolute Data Addressing - Long",
"Immidate value",
-};
+};
static void print_insn_detail(cs_insn *ins)
{
cs_m68k* m68k;
+ cs_detail* detail;
int i;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
- m68k = &(ins->detail->m68k);
+ detail = ins->detail;
+ m68k = &detail->m68k;
if (m68k->op_count)
printf("\top_count: %u\n", m68k->op_count);
+ printf("\tgroups_count: %u\n", detail->groups_count);
+
for (i = 0; i < m68k->op_count; i++) {
cs_m68k_op* op = &(m68k->operands[i]);
@@ -121,7 +125,7 @@
static void test()
{
-#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
+#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
struct platform platforms[] = {
{
diff --git a/tests/test_x86.c b/tests/test_x86.c
index 13329a3..f3b7350 100644
--- a/tests/test_x86.c
+++ b/tests/test_x86.c
@@ -214,9 +214,6 @@
case X86_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
break;
- case X86_OP_FP:
- printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
- break;
case X86_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.segment != X86_REG_INVALID)
diff --git a/windowsce/.gitignore b/windowsce/.gitignore
new file mode 100644
index 0000000..49fbbf5
--- /dev/null
+++ b/windowsce/.gitignore
@@ -0,0 +1,13 @@
+# Object files
+*.obj
+
+# Libraries
+*.lib
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+
+# VisualStudio
+*.exp
+*.map
+*.pdb
diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md
new file mode 100644
index 0000000..b41dcb7
--- /dev/null
+++ b/windowsce/COMPILE.md
@@ -0,0 +1,124 @@
+This documentation explains how to compile Capstone for:
+- Windows CE 7, a.k.a, [Windows Embedded Compact 7](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-7.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html).
+- Windows CE 8, a.k.a, [Windows Embedded Compact 2013](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-2013.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html).
+
+To build Capstone for a different platform, please refer to `COMPILE.TXT`.
+
+# Prerequisites
+
+We support the following scenario regarding the build machine:
+- Build running on Microsoft Windows.
+- The C Software Develepment Kit of the target Windows CE **device** installed.
+- Only for Windows CE 7:
+ - C compiler toolchain installed, targetting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old.
+
+Before building Capstone for Windows CE 7 (respectively, Windows CE 8), the build script `windowsce/make_windowsce7-armv7.bat` (respectively, `windowsce/make_windowsce8-armv7.bat`) needs to be modified. The variables specified in the rest of this section are set in this script file.
+
+# Toolchain specification
+
+The following information need to be specified in the build script in order to perform the build:
+- `set WINCE_TOOLCHAIN_ROOT=` is the path of the root directory of the Windows CE toolchain. To build for Windows CE 7, this should be set to the Windows Embedded Compact 7 toolchain. To build for Windows CE 8, this should be set to the device toolchain.
+Examples:
+ - For Windows CE 7:
+ ```bat
+ set WINCE_TOOLCHAIN_ROOT=C:\WINCE700\sdk
+ ```
+ - For Windows CE 8:
+ ```bat
+ set WINCE_TOOLCHAIN_ROOT=C:\Windows_CE_Tools\SDKs\SDK_HW90270\Sdk
+ ```
+
+- `set TOOLCHAIN=` is a semicolon-separated list of the paths of the directories containing the binaries of the Windows CE toolchain.
+For example:
+```bat
+set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386
+```
+
+- `set INCLUDE=` is a semicolon-separated list of the paths of the directories containing the C header files of the Windows CE device SDK. To build for Windows CE 7, this should also include the directories containing the C header files of the Windows Embedded Compact 7 toolchain.
+Examples:
+ - For Windows CE 7:
+ ```bat
+ set INCLUDE=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Include\Armv4i;C:\WINCE700\public\common\sdk\inc
+ ```
+ - For Windows CE 8:
+ ```bat
+ set INCLUDE=%WINCE_TOOLCHAIN_ROOT%\Inc;%WINCE_TOOLCHAIN_ROOT%\crt\Include
+ ```
+
+- `set LIBPATH=` is a semicolon-separated list of the paths of the directories containing the library (i.e., `.LIB`) files of the Windows CE 7 device SDK.
+Examples:
+ - For Windows CE 7:
+ ```bat
+ set LIBPATH=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Lib\ARMv4I
+ ```
+ - For Windows CE 8:
+ ```bat
+ set LIBPATH=%WINCE_TOOLCHAIN_ROOT%\Lib\ARMV7\retail;%WINCE_TOOLCHAIN_ROOT%\Crt\Lib\ARM
+ ```
+
+- `set LIBS=` is a space-separated list of linker directives controlling library search.
+Examples:
+ - For Windows CE 7:
+ ```bat
+ set LIBS=-nodefaultlib:oldnames.lib -nodefaultlib:libcmtd.lib -nodefaultlib:libcmt.lib coredll.lib corelibc.lib
+ ```
+ - For Windows CE 8:
+ ```bat
+ set LIBS=coredll.lib
+ ```
+
+# Capstone binary format
+
+By default, the build script produces a **dynamic link library** (i.e., `.DLL`). In order to produce a **static library** (i.e., `.LIB`) instead, the `SHARED` variable needs to be set to `0`, i.e.:
+```bat
+set SHARED=0
+```
+
+# Architectures supported at runtime
+
+Capstone supports the following architectures: ARM, ARM64 (AArch64), M68K, MIPS, PowerPC, Sparc, SystemZ, x86 and XCore. However, Capstone can be configured in order to select which architectures need to be supported **at runtime**. This is controlled via the variable `DISASM_ARCH_LIST`, which is a space-separated list that is a combination of the following names:
+- `ARM`
+- `ARM64`
+- `M68K`
+- `MIPS`
+- `POWERPC`
+- `SPARC`
+- `SYSZ`
+- `X86`
+- `XCORE`.
+
+By default, `DISASM_ARCH_LIST` includes support for **all** architectures supported by Capstone.
+For example:
+```bat
+set DISASM_ARCH_LIST=ARM ARM64 X86
+```
+will produce a Capstone binary that supports the following architectures: ARM, ARM64 and x86.
+
+## Features customization
+
+Capstone has a list of features that can be controlled when needed. Each feature is controlled through setting a variable from the following list:
+
+- In order to produce a smaller binary that provides a **subset** of the features of Capstone, but still supports all the selected architectures, please specify the following:
+ ```bat
+ set DIET_MODE=1
+ ```
+ By default, this variable is set to `0`.
+
+- By default, Capstone uses the default system-provided **dynamic memory management** functions (e.g., `malloc()`, `realloc()`, `free()`) for its internal memory management. However, Capstone can instead be configured to call **custom** memory management functions provided by client applications. In order to enable this behavior, set the following:
+ ```bat
+ set USE_SYS_DYN_MEM=0
+ ```
+
+- In order to produce a **smaller** Capstone binary, support for the `x86` architecture can be more **limited**. In order to do so, set the following:
+ ```bat
+ set X86_REDUCE=1
+ ```
+ By default, this is set to `0`.
+
+- If the **AT&T** disassembly style of the `x86` architecture is never needed at runtime, then disabling support for it can produce a **smaller** Capstone binary. To do this, please set the following:
+ ```bat
+ set X86_ATT_DISABLE=1
+ ```
+ By default, this is set to `0`.
+
+Please refer to `docs/README` for more details on these features.
diff --git a/windowsce/make_windowsce7-armv7.bat b/windowsce/make_windowsce7-armv7.bat
new file mode 100644
index 0000000..35427e4
--- /dev/null
+++ b/windowsce/make_windowsce7-armv7.bat
@@ -0,0 +1,179 @@
+@echo off
+
+rem ***************************************************************************
+rem * VARIABLES TO SET FOR BUILDING *
+rem ***************************************************************************
+
+set WINCE_TOOLCHAIN_ROOT=C:\WINCE700\sdk
+set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386
+set INCLUDE=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Include\Armv4i;C:\WINCE700\public\common\sdk\inc
+set LIBPATH=C:\Program Files (x86)\Windows CE Tools\SDKs\Symbol MC3200c70 Windows CE 7.0 PSDK\Lib\ARMv4I
+set LIBS=-nodefaultlib:oldnames.lib -nodefaultlib:libcmtd.lib -nodefaultlib:libcmt.lib coredll.lib corelibc.lib
+
+rem ***************************************************************************
+rem * CAPSTONE CONFIGURATION *
+rem ***************************************************************************
+
+set SHARED=1
+set DIET_MODE=0
+set USE_SYS_DYN_MEM=1
+set X86_REDUCE=0
+set X86_ATT_DISABLE=0
+set DISASM_ARCH_LIST=ARM ARM64 M68K MIPS POWERPC SPARC SYSZ X86 XCORE
+
+rem ***************************************************************************
+rem * SANITY CHECKS *
+rem ***************************************************************************
+
+setlocal ENABLEDELAYEDEXPANSION
+
+if "%WINCE_TOOLCHAIN_ROOT%"=="" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT
+if not exist "%WINCE_TOOLCHAIN_ROOT%" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT
+
+if "%TOOLCHAIN%"=="" goto check_dir_exist_TOOLCHAIN
+
+set CC=
+set LD=
+set AR=
+for /f "tokens=1-8 delims=;" %%a in ("%TOOLCHAIN%") do (
+ for %%i in (%%a %%b %%c %%d %%e %%f %%g %%h) do (
+ if not "%%i"=="" (
+ if not exist "%%i" goto check_dir_exist_TOOLCHAIN
+ if "%CC%"=="" if exist "%%i\cl.exe" set CC=%%i\cl.exe
+ if "%LD%"=="" if exist "%%i\link.exe" set LD=%%i\link.exe
+ if "%AR%"=="" if exist "%%i\lib.exe" set AR=%%i\lib.exe
+ )
+ )
+)
+
+if "%CC%"=="" goto check_dir_exist_CC_LD_AR
+if "%LD%"=="" goto check_dir_exist_CC_LD_AR
+if "%AR%"=="" goto check_dir_exist_CC_LD_AR
+
+if "%INCLUDE%"=="" goto check_dir_exist_INCLUDE
+
+set WINDOWS_H=
+
+set INCLUDE_SC=%INCLUDE%
+set INCLUDE=
+for /f "tokens=1-8 delims=;" %%a in ("%INCLUDE_SC%") do (
+ for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do (
+ if not %%i=="" (
+ set INCLUDE=!INCLUDE! -I %%i
+ )
+ )
+)
+
+if "%LIBPATH%"=="" goto check_dir_exist_LIBPATH
+
+set LIBPATH_SC=%LIBPATH%
+set LIBPATH=
+for /f "tokens=1-8 delims=;" %%a in ("%LIBPATH_SC%") do (
+ for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do (
+ if not %%i=="" (
+ set LIBPATH=!LIBPATH! -libpath:%%i
+ )
+ )
+)
+
+rem ***************************************************************************
+rem * COMPILATION OPTIONS *
+rem ***************************************************************************
+
+set OS=windowsce
+set OS_VERSION=7.0
+set OS_VERSION_NUMBER=0x700
+set LIBARCH=arm
+set MACH=THUMB
+
+for /f "delims=" %%i in ('cd') do set THIS_DIR=%%i
+
+set SOURCES_ROOT=%THIS_DIR%\..
+set TARGET_DIR=%THIS_DIR%\bin\%OS%_%OS_VERSION%_%LIBARCH%
+
+for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MAJOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MAJOR=%%i
+for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MINOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MINOR=%%i
+
+set TARGET_VERSION=%CS_API_MAJOR%.%CS_API_MINOR%
+set TAREGET_NAME=capstone-%TARGET_VERSION%
+
+set CPPFLAGS=-D LIBARCH_%LIBARCH% -D LIBARCH=L\"%LIBARCH%\"
+set CPPFLAGS=%CPPFLAGS% -D _CRT_SECURE_NO_DEPRECATE -D _WINDOWS -D WINVER=%OS_VERSION_NUMBER% -D UNDER_CE=%OS_VERSION_NUMBER% -D _WIN32_WCE=%OS_VERSION_NUMBER% -D WINCE -D _UNICODE -D UNICODE -D STANDARDSHELL_UI_MODEL -D _USE_MATH_DEFINES -D ARM -D _ARM -D _ARM_ -D __ARM_ARCH_7__ -D __ARM_ARCH_7A__ -D __VFP_FP__=1
+
+for %%a in (%DISASM_ARCH_LIST%) do set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_HAS_%%a
+
+if %SHARED%==0 (
+ set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_STATIC -D LIB_EXT=L\".lib\"
+) else (
+ set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_SHARED -D LIB_EXT=L\".dll\"
+)
+
+if not %USE_SYS_DYN_MEM%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_USE_SYS_DYN_MEM )
+if not %DIET_MODE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_DIET )
+if not %X86_REDUCE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_REDUCE )
+if not %X86_ATT_DISABLE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_ATT_DISABLE )
+
+set INCLUDE=-I %SOURCES_ROOT%\include -I %SOURCES_ROOT% %INCLUDE%
+
+set CFLAGS=%CPPFLAGS% %INCLUDE% -nologo -Zi -MT -Oi -GS -GF -QRarch7 -arch:VFPv3-D32 -QRfpe- -fp:fast -Oy- -W3 -WX
+
+set LDFLAGS=-nologo -debug -incremental:no -manifest:no -version:%TARGET_VERSION% -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS%
+
+set ARFLAGS=-nologo -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS%
+
+set SOURCES=
+for %%f in (%SOURCES_ROOT%\*.c) do set SOURCES=!SOURCES! %%f
+for /d %%a in (%SOURCES_ROOT%\arch\*) do for %%f in (%%a\*.c) do set SOURCES=!SOURCES! %%f
+
+rem ***************************************************************************
+rem * COMPILATION COMMANDS *
+rem ***************************************************************************
+
+rd /q /s "%TARGET_DIR%"
+md "%TARGET_DIR%"
+
+set PATH=%TOOLCHAIN%;%PATH%
+
+rem %CC% -c %CFLAGS% -D DEBUG -D _DEBUG -Od -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES%
+%CC% -c %CFLAGS% -D NDEBUG -Ox -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES%
+if errorlevel 1 goto compilation_failed
+
+if %SHARED%==0 (
+ %AR% -out:%TARGET_DIR%\%TAREGET_NAME%.lib %ARFLAGS% %TARGET_DIR%\*.obj
+) else (
+ %LD% -dll -out:%TARGET_DIR%\%TAREGET_NAME%.dll -map:"%TARGET_DIR%\%TAREGET_NAME%.map" -pdb:"%TARGET_DIR%\%TAREGET_NAME%.pdb" %LDFLAGS% -opt:REF -opt:ICF %TARGET_DIR%\*.obj
+)
+
+endlocal
+goto done
+
+rem ***************************************************************************
+rem * ERROR REPORTING *
+rem ***************************************************************************
+
+:check_dir_exist_WINCE_TOOLCHAIN_ROOT
+echo ERROR: WINCE_TOOLCHAIN_ROOT does not specify an existing directory.
+goto done
+
+:check_dir_exist_TOOLCHAIN
+echo ERROR: TOOLCHAIN does not specify an existing directory.
+goto done
+
+:check_dir_exist_CC_LD_AR
+echo ERROR: TOOLCHAIN does not specify a valid toolchain directory.
+goto done
+
+:check_dir_exist_INCLUDE
+echo ERROR: INCLUDE does not specify an existing directory.
+goto done
+
+:check_dir_exist_LIBPATH
+echo ERROR: LIBPATH does not specify an existing directory.
+goto done
+
+:compilation_failed
+echo ERROR: Compilation failed.
+goto done
+
+:done
+pause
diff --git a/windowsce/make_windowsce8-armv7.bat b/windowsce/make_windowsce8-armv7.bat
new file mode 100644
index 0000000..b905dc5
--- /dev/null
+++ b/windowsce/make_windowsce8-armv7.bat
@@ -0,0 +1,179 @@
+@echo off
+
+rem ***************************************************************************
+rem * VARIABLES TO SET FOR BUILDING *
+rem ***************************************************************************
+
+set WINCE_TOOLCHAIN_ROOT=C:\Windows_CE_Tools\SDKs\SDK_HW90270\Sdk
+set TOOLCHAIN=%WINCE_TOOLCHAIN_ROOT%\Bin\i386\Arm;%WINCE_TOOLCHAIN_ROOT%\Bin\i386
+set INCLUDE=%WINCE_TOOLCHAIN_ROOT%\Inc;%WINCE_TOOLCHAIN_ROOT%\crt\Include
+set LIBPATH=%WINCE_TOOLCHAIN_ROOT%\Lib\ARMV7\retail;%WINCE_TOOLCHAIN_ROOT%\Crt\Lib\ARM
+set LIBS=coredll.lib
+
+rem ***************************************************************************
+rem * CAPSTONE CONFIGURATION *
+rem ***************************************************************************
+
+set SHARED=1
+set DIET_MODE=0
+set USE_SYS_DYN_MEM=1
+set X86_REDUCE=0
+set X86_ATT_DISABLE=0
+set DISASM_ARCH_LIST=ARM ARM64 M68K MIPS POWERPC SPARC SYSZ X86 XCORE
+
+rem ***************************************************************************
+rem * SANITY CHECKS *
+rem ***************************************************************************
+
+setlocal ENABLEDELAYEDEXPANSION
+
+if "%WINCE_TOOLCHAIN_ROOT%"=="" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT
+if not exist "%WINCE_TOOLCHAIN_ROOT%" goto check_dir_exist_WINCE_TOOLCHAIN_ROOT
+
+if "%TOOLCHAIN%"=="" goto check_dir_exist_TOOLCHAIN
+
+set CC=
+set LD=
+set AR=
+for /f "tokens=1-8 delims=;" %%a in ("%TOOLCHAIN%") do (
+ for %%i in (%%a %%b %%c %%d %%e %%f %%g %%h) do (
+ if not "%%i"=="" (
+ if not exist "%%i" goto check_dir_exist_TOOLCHAIN
+ if "%CC%"=="" if exist "%%i\cl.exe" set CC=%%i\cl.exe
+ if "%LD%"=="" if exist "%%i\link.exe" set LD=%%i\link.exe
+ if "%AR%"=="" if exist "%%i\lib.exe" set AR=%%i\lib.exe
+ )
+ )
+)
+
+if "%CC%"=="" goto check_dir_exist_CC_LD_AR
+if "%LD%"=="" goto check_dir_exist_CC_LD_AR
+if "%AR%"=="" goto check_dir_exist_CC_LD_AR
+
+if "%INCLUDE%"=="" goto check_dir_exist_INCLUDE
+
+set WINDOWS_H=
+
+set INCLUDE_SC=%INCLUDE%
+set INCLUDE=
+for /f "tokens=1-8 delims=;" %%a in ("%INCLUDE_SC%") do (
+ for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do (
+ if not %%i=="" (
+ set INCLUDE=!INCLUDE! -I %%i
+ )
+ )
+)
+
+if "%LIBPATH%"=="" goto check_dir_exist_LIBPATH
+
+set LIBPATH_SC=%LIBPATH%
+set LIBPATH=
+for /f "tokens=1-8 delims=;" %%a in ("%LIBPATH_SC%") do (
+ for %%i in ("%%a" "%%b" "%%c" "%%d" "%%e" "%%f" "%%g" "%%h") do (
+ if not %%i=="" (
+ set LIBPATH=!LIBPATH! -libpath:%%i
+ )
+ )
+)
+
+rem ***************************************************************************
+rem * COMPILATION OPTIONS *
+rem ***************************************************************************
+
+set OS=windowsce
+set OS_VERSION=8.0
+set OS_VERSION_NUMBER=0x800
+set LIBARCH=arm
+set MACH=ARM
+
+for /f "delims=" %%i in ('cd') do set THIS_DIR=%%i
+
+set SOURCES_ROOT=%THIS_DIR%\..
+set TARGET_DIR=%THIS_DIR%\bin\%OS%_%OS_VERSION%_%LIBARCH%
+
+for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MAJOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MAJOR=%%i
+for /f "tokens=3" %%i in ('findstr /c:"#define CS_API_MINOR" "%SOURCES_ROOT%\include\capstone\capstone.h"') do set CS_API_MINOR=%%i
+
+set TARGET_VERSION=%CS_API_MAJOR%.%CS_API_MINOR%
+set TAREGET_NAME=capstone-%TARGET_VERSION%
+
+set CPPFLAGS=-D LIBARCH_%LIBARCH% -D LIBARCH=L\"%LIBARCH%\"
+set CPPFLAGS=%CPPFLAGS% -D _CRT_SECURE_NO_DEPRECATE -D _WINDOWS -D WINVER=%OS_VERSION_NUMBER% -D UNDER_CE=%OS_VERSION_NUMBER% -D _WIN32_WCE=%OS_VERSION_NUMBER% -D WINCE -D _UNICODE -D UNICODE -D STANDARDSHELL_UI_MODEL -D _USE_MATH_DEFINES -D ARM -D _ARM -D _ARM_ -D __ARM_ARCH_7__ -D __ARM_ARCH_7A__ -D __VFP_FP__=1
+
+for %%a in (%DISASM_ARCH_LIST%) do set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_HAS_%%a
+
+if %SHARED%==0 (
+ set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_STATIC -D LIB_EXT=L\".lib\"
+) else (
+ set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_SHARED -D LIB_EXT=L\".dll\"
+)
+
+if not %USE_SYS_DYN_MEM%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_USE_SYS_DYN_MEM )
+if not %DIET_MODE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_DIET )
+if not %X86_REDUCE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_REDUCE )
+if not %X86_ATT_DISABLE%==0 ( set CPPFLAGS=!CPPFLAGS! -D CAPSTONE_X86_ATT_DISABLE )
+
+set INCLUDE=-I %SOURCES_ROOT%\include -I %SOURCES_ROOT% %INCLUDE%
+
+set CFLAGS=%CPPFLAGS% %INCLUDE% -nologo -MP -Zi -MT -Oi -GS -fp:fast -Oy- -W3 -WX
+
+set LDFLAGS=-nologo -debug -incremental:no -manifest:no -version:%TARGET_VERSION% -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS%
+
+set ARFLAGS=-nologo -machine:%MACH% -subsystem:WINDOWSCE,%OS_VERSION% %LIBPATH% %LIBS%
+
+set SOURCES=
+for %%f in (%SOURCES_ROOT%\*.c) do set SOURCES=!SOURCES! %%f
+for /d %%a in (%SOURCES_ROOT%\arch\*) do for %%f in (%%a\*.c) do set SOURCES=!SOURCES! %%f
+
+rem ***************************************************************************
+rem * COMPILATION COMMANDS *
+rem ***************************************************************************
+
+rd /q /s "%TARGET_DIR%"
+md "%TARGET_DIR%"
+
+set PATH=%TOOLCHAIN%;%PATH%
+
+rem %CC% -c %CFLAGS% -D DEBUG -D _DEBUG -Od -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES%
+%CC% -c %CFLAGS% -D NDEBUG -Ox -Fo"%TARGET_DIR%\\" -Fd"%TARGET_DIR%\%TAREGET_NAME%.pdb" %SOURCES%
+if errorlevel 1 goto compilation_failed
+
+if %SHARED%==0 (
+ %AR% -out:%TARGET_DIR%\%TAREGET_NAME%.lib %ARFLAGS% %TARGET_DIR%\*.obj
+) else (
+ %LD% -dll -out:%TARGET_DIR%\%TAREGET_NAME%.dll -map:"%TARGET_DIR%\%TAREGET_NAME%.map" -pdb:"%TARGET_DIR%\%TAREGET_NAME%.pdb" %LDFLAGS% -opt:REF -opt:ICF %TARGET_DIR%\*.obj
+)
+
+endlocal
+goto done
+
+rem ***************************************************************************
+rem * ERROR REPORTING *
+rem ***************************************************************************
+
+:check_dir_exist_WINCE_TOOLCHAIN_ROOT
+echo ERROR: WINCE_TOOLCHAIN_ROOT does not specify an existing directory.
+goto done
+
+:check_dir_exist_TOOLCHAIN
+echo ERROR: TOOLCHAIN does not specify an existing directory.
+goto done
+
+:check_dir_exist_CC_LD_AR
+echo ERROR: TOOLCHAIN does not specify a valid toolchain directory.
+goto done
+
+:check_dir_exist_INCLUDE
+echo ERROR: INCLUDE does not specify an existing directory.
+goto done
+
+:check_dir_exist_LIBPATH
+echo ERROR: LIBPATH does not specify an existing directory.
+goto done
+
+:compilation_failed
+echo ERROR: Compilation failed.
+goto done
+
+:done
+pause