python: update to the newly added cs_option() API
diff --git a/bindings/python/__init__.py b/bindings/python/__init__.py
index 0aa23fc..46463a3 100644
--- a/bindings/python/__init__.py
+++ b/bindings/python/__init__.py
@@ -1 +1 @@
-from capstone import cs, cs_disasm_quick, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_MODE_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_SYNTAX_ATT, CS_MODE_BIG_ENDIAN
+from capstone import cs, cs_disasm_quick, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_X86_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_OPT_X86_ATT, CS_MODE_BIG_ENDIAN
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 83c299d..84aedd6 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -1 +1 @@
-from capstone import cs, cs_disasm_quick, cs_version, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_MODE_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_SYNTAX_ATT, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
+from capstone import cs, cs_disasm_quick, cs_version, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_X86_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_OPT_X86_ATT, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
diff --git a/bindings/python/capstone/capstone.py b/bindings/python/capstone/capstone.py
index 1c20bbc..7f67903 100644
--- a/bindings/python/capstone/capstone.py
+++ b/bindings/python/capstone/capstone.py
@@ -14,8 +14,6 @@
'CS_MODE_LITTLE_ENDIAN',
'CS_MODE_BIG_ENDIAN',
- 'CS_MODE_SYNTAX_INTEL',
- 'CS_MODE_SYNTAX_ATT',
'CS_MODE_16',
'CS_MODE_32',
'CS_MODE_64',
@@ -24,6 +22,9 @@
'CS_MODE_MICRO',
'CS_MODE_N64',
+ 'CS_OPT_X86_INTEL',
+ 'CS_OPT_X86_ATT',
+
'CS_ERR_OK',
'CS_ERR_MEM',
'CS_ERR_ARCH',
@@ -32,7 +33,7 @@
'CS_ERR_MODE',
]
-# capstone C interface
+# Capstone C interface
# architectures
CS_ARCH_ARM = 0
CS_ARCH_ARM64 = 1
@@ -41,7 +42,6 @@
# disasm mode
CS_MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
-CS_MODE_SYNTAX_INTEL = 0 # Intel X86 asm syntax (default for CS_ARCH_X86)
CS_MODE_ARM = 0 # ARM mode
CS_MODE_16 = (1 << 1) # 16-bit mode (for X86, Mips)
CS_MODE_32 = (1 << 2) # 32-bit mode (for X86, Mips)
@@ -49,10 +49,13 @@
CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_N64 = (1 << 5) # Nintendo-64 mode (MIPS architecture)
-CS_MODE_SYNTAX_ATT = (1 << 30) # X86 ATT asm syntax (for CS_ARCH_X86 only)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
-# capstone error type
+# Capstone option type
+CS_OPT_X86_INTEL = 1 << 0 # Intel X86 asm syntax (CS_ARCH_X86 arch)
+CS_OPT_X86_ATT = 1 << 1 # ATT asm syntax (CS_ARCH_X86 arch)
+
+# Capstone error type
CS_ERR_OK = 0 # No error: everything was fine
CS_ERR_MEM = 1 # Out-Of-Memory error
CS_ERR_ARCH = 2 # Unsupported architecture
@@ -149,7 +152,8 @@
_setup_prototype(_cs, "cs_op_count", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint)
_setup_prototype(_cs, "cs_op_index", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint, ctypes.c_uint)
_setup_prototype(_cs, "cs_version", None, ctypes.POINTER(ctypes.c_int), ctypes.POINTER(ctypes.c_int))
-_setup_prototype(_cs, "cs_errno", ctypes.c_int, ctypes.c_int64)
+_setup_prototype(_cs, "cs_errno", ctypes.c_int, ctypes.c_size_t)
+_setup_prototype(_cs, "cs_option", ctypes.c_int, ctypes.c_size_t, ctypes.c_int)
def cs_version():
@@ -259,6 +263,9 @@
if self.csh:
_cs.cs_close(self.csh)
+ def option(self, option):
+ return _cs.cs_option(self.csh, option)
+
def disasm(self, code, offset, count = 0):
if self.csh is None:
raise ValueError("Error: Failed to initialize!")
diff --git a/bindings/python/test.py b/bindings/python/test.py
index 19a9d11..8ca8256 100755
--- a/bindings/python/test.py
+++ b/bindings/python/test.py
@@ -16,17 +16,17 @@
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
- (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
- (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
- (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_X86_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
+ (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
+ (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
+ (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
)
@@ -48,7 +48,7 @@
### Test class cs
def test_class():
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, option) in all_tests:
print('*' * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
@@ -56,6 +56,10 @@
try:
md = cs(arch, mode)
+
+ if option != 0:
+ md.option(option)
+
all_ins = list(md.disasm(code, 0x1000))
for insn in all_ins:
print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py
index b36f7d0..c8c19f1 100755
--- a/bindings/python/test_detail.py
+++ b/bindings/python/test_detail.py
@@ -16,17 +16,17 @@
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
- (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
- (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
- (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_X86_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0),
+ (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
+ (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
+ (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
)
@@ -52,13 +52,16 @@
print
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, option) in all_tests:
print('*' * 40)
print("Platform: %s" %comment)
print("Disasm:")
try:
md = cs(arch, mode)
+ if option != 0:
+ md.option(option)
+
for insn in md.disasm(code, 0x1000):
print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \
%(insn.address, insn.mnemonic, insn.op_str, insn.id, \
diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py
index a3ec0b2..29b749e 100755
--- a/bindings/python/test_x86.py
+++ b/bindings/python/test_x86.py
@@ -10,10 +10,10 @@
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32 (AT&T syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_X86_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
)
def to_hex(s):
@@ -102,13 +102,16 @@
print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.value.mem.disp)))
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, option) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
md = cs(arch, mode)
+ if option != 0:
+ md.option(option)
+
last = None
for insn in md.disasm(code, 0x1000):
print_insn_detail(mode, insn)