bindings: support newly added field @xop_cc in the last commit (Java, Ocaml, Python)
diff --git a/bindings/java/TestX86.java b/bindings/java/TestX86.java
index d9480ef..e2894b5 100644
--- a/bindings/java/TestX86.java
+++ b/bindings/java/TestX86.java
@@ -70,6 +70,9 @@
ins.regName(operands.sibBase), ins.regName(operands.sibIndex), operands.sibScale);
}
+ if (operands.xopCC != 0)
+ System.out.printf("\txop_cc: %u\n", operands.xopCC);
+
if (operands.sseCC != 0)
System.out.printf("\tsse_cc: %u\n", operands.sseCC);
diff --git a/bindings/java/capstone/X86.java b/bindings/java/capstone/X86.java
index 8f69ee1..17745bf 100644
--- a/bindings/java/capstone/X86.java
+++ b/bindings/java/capstone/X86.java
@@ -77,6 +77,7 @@
public int sib_index;
public byte sib_scale;
public int sib_base;
+ public int xop_cc;
public int sse_cc;
public int avx_cc;
public byte avx_sae;
@@ -95,7 +96,7 @@
@Override
public List getFieldOrder() {
return Arrays.asList("prefix", "opcode", "rex", "addr_size",
- "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "op_count", "op");
+ "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "xop_cc", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "op_count", "op");
}
}
@@ -131,6 +132,7 @@
sibIndex = e.sib_index;
sibScale = e.sib_scale;
sibBase = e.sib_base;
+ xopCC = e.xop_cc;
sseCC = e.sse_cc;
avxCC = e.avx_cc;
avxSae = e.avx_sae > 0;
diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
index 91a4135..0f5bf54 100644
--- a/bindings/java/capstone/X86_const.java
+++ b/bindings/java/capstone/X86_const.java
@@ -257,6 +257,18 @@
public static final int X86_OP_MEM = 3;
public static final int X86_OP_FP = 4;
+ // XOP Code Condition type
+
+ public static final int X86_XOP_CC_INVALID = 0;
+ public static final int X86_XOP_CC_LT = 1;
+ public static final int X86_XOP_CC_LE = 2;
+ public static final int X86_XOP_CC_GT = 3;
+ public static final int X86_XOP_CC_GE = 4;
+ public static final int X86_XOP_CC_EQ = 5;
+ public static final int X86_XOP_CC_NEQ = 6;
+ public static final int X86_XOP_CC_FALSE = 7;
+ public static final int X86_XOP_CC_TRUE = 8;
+
// AVX broadcast type
public static final int X86_AVX_BCAST_INVALID = 0;
diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c
index f088a62..be11237 100644
--- a/bindings/ocaml/ocaml.c
+++ b/bindings/ocaml/ocaml.c
@@ -314,7 +314,7 @@
case CS_ARCH_X86:
arch_info = caml_alloc(1, 3);
- op_info_val = caml_alloc(15, 0);
+ op_info_val = caml_alloc(16, 0);
// fill prefix
lcount = list_count(insn[j-1].detail->x86.prefix, ARR_SIZE(insn[j-1].detail->x86.prefix));
@@ -354,10 +354,11 @@
Store_field(op_info_val, 9, Val_int(insn[j-1].detail->x86.sib_base));
- Store_field(op_info_val, 10, Val_int(insn[j-1].detail->x86.sse_cc));
- Store_field(op_info_val, 11, Val_int(insn[j-1].detail->x86.avx_cc));
- Store_field(op_info_val, 12, Val_int(insn[j-1].detail->x86.avx_sae));
- Store_field(op_info_val, 13, Val_int(insn[j-1].detail->x86.avx_rm));
+ Store_field(op_info_val, 10, Val_int(insn[j-1].detail->x86.xop_cc));
+ Store_field(op_info_val, 11, Val_int(insn[j-1].detail->x86.sse_cc));
+ Store_field(op_info_val, 12, Val_int(insn[j-1].detail->x86.avx_cc));
+ Store_field(op_info_val, 13, Val_int(insn[j-1].detail->x86.avx_sae));
+ Store_field(op_info_val, 14, Val_int(insn[j-1].detail->x86.avx_rm));
lcount = insn[j-1].detail->x86.op_count;
if (lcount > 0) {
@@ -399,7 +400,7 @@
}
} else // empty array
array = Atom(0);
- Store_field(op_info_val, 14, array);
+ Store_field(op_info_val, 15, array);
// finally, insert this into arch_info
Store_field(arch_info, 0, op_info_val);
diff --git a/bindings/ocaml/x86.ml b/bindings/ocaml/x86.ml
index 8616754..c178460 100644
--- a/bindings/ocaml/x86.ml
+++ b/bindings/ocaml/x86.ml
@@ -37,6 +37,7 @@
sib_index: int;
sib_scale: int;
sib_base: int;
+ xop_cc: int;
sse_cc: int;
avx_cc: int;
avx_sae: int;
diff --git a/bindings/ocaml/x86_const.ml b/bindings/ocaml/x86_const.ml
index 85a6abd..55d4f5d 100644
--- a/bindings/ocaml/x86_const.ml
+++ b/bindings/ocaml/x86_const.ml
@@ -254,6 +254,18 @@
let _X86_OP_MEM = 3;;
let _X86_OP_FP = 4;;
+(* XOP Code Condition type *)
+
+let _X86_XOP_CC_INVALID = 0;;
+let _X86_XOP_CC_LT = 1;;
+let _X86_XOP_CC_LE = 2;;
+let _X86_XOP_CC_GT = 3;;
+let _X86_XOP_CC_GE = 4;;
+let _X86_XOP_CC_EQ = 5;;
+let _X86_XOP_CC_NEQ = 6;;
+let _X86_XOP_CC_FALSE = 7;;
+let _X86_XOP_CC_TRUE = 8;;
+
(* AVX broadcast type *)
let _X86_AVX_BCAST_INVALID = 0;;
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index a019703..5995898 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -519,7 +519,7 @@
elif arch == CS_ARCH_X86:
(self.prefix, self.opcode, self.rex, self.addr_size, \
self.modrm, self.sib, self.disp, \
- self.sib_index, self.sib_scale, self.sib_base, self.sse_cc, \
+ self.sib_index, self.sib_scale, self.sib_base, self.xop_cc, self.sse_cc, \
self.avx_cc, self.avx_sae, self.avx_rm, self.operands) = x86.get_arch_info(self._detail.arch.x86)
elif arch == CS_ARCH_MIPS:
self.operands = mips.get_arch_info(self._detail.arch.mips)
diff --git a/bindings/python/capstone/x86.py b/bindings/python/capstone/x86.py
index 97c7898..bef4773 100644
--- a/bindings/python/capstone/x86.py
+++ b/bindings/python/capstone/x86.py
@@ -59,6 +59,7 @@
('sib_index', ctypes.c_uint),
('sib_scale', ctypes.c_int8),
('sib_base', ctypes.c_uint),
+ ('xop_cc', ctypes.c_uint),
('sse_cc', ctypes.c_uint),
('avx_cc', ctypes.c_uint),
('avx_sae', ctypes.c_bool),
@@ -70,6 +71,6 @@
def get_arch_info(a):
return (a.prefix[:], a.opcode[:], a.rex, a.addr_size, \
a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, \
- a.sib_base, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, \
+ a.sib_base, a.xop_cc, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, \
copy.deepcopy(a.operands[:a.op_count]))
diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
index 49b2f9e..01f81ad 100644
--- a/bindings/python/capstone/x86_const.py
+++ b/bindings/python/capstone/x86_const.py
@@ -254,6 +254,18 @@
X86_OP_MEM = 3
X86_OP_FP = 4
+# XOP Code Condition type
+
+X86_XOP_CC_INVALID = 0
+X86_XOP_CC_LT = 1
+X86_XOP_CC_LE = 2
+X86_XOP_CC_GT = 3
+X86_XOP_CC_GE = 4
+X86_XOP_CC_EQ = 5
+X86_XOP_CC_NEQ = 6
+X86_XOP_CC_FALSE = 7
+X86_XOP_CC_TRUE = 8
+
# AVX broadcast type
X86_AVX_BCAST_INVALID = 0
diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py
index 6d2aa50..380b029 100755
--- a/bindings/python/test_x86.py
+++ b/bindings/python/test_x86.py
@@ -7,7 +7,7 @@
from xprint import to_hex, to_x, to_x_32
-X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
+X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\x8f\xe8\x60\xcd\xe2\x07"
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
@@ -63,6 +63,10 @@
if insn.sib_scale != 0:
print("\t\tsib_scale: %d" % (insn.sib_scale))
+ # XOP CC type
+ if insn.xop_cc != X86_XOP_CC_INVALID:
+ print("\txop_cc: %u" % (insn.xop_cc))
+
# SSE CC type
if insn.sse_cc != X86_SSE_CC_INVALID:
print("\tsse_cc: %u" % (insn.sse_cc))