/* Capstone Unified Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */

#include <stdio.h>	// debug
#include <string.h>

#include "../../include/arm64.h"
#include "../../utils.h"

#include "mapping.h"

#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"

static name_map reg_name_maps[] = {
	{ ARM64_REG_INVALID, NULL },
	{ ARM64_REG_NZCV, "nzcv"},
	{ ARM64_REG_WSP, "wsp"},
	{ ARM64_REG_WZR, "wzr"},
	{ ARM64_REG_SP, "sp"},
	{ ARM64_REG_XZR, "xzr"},
	{ ARM64_REG_B0, "b0"},
	{ ARM64_REG_B1, "b1"},
	{ ARM64_REG_B2, "b2"},
	{ ARM64_REG_B3, "b3"},
	{ ARM64_REG_B4, "b4"},
	{ ARM64_REG_B5, "b5"},
	{ ARM64_REG_B6, "b6"},
	{ ARM64_REG_B7, "b7"},
	{ ARM64_REG_B8, "b8"},
	{ ARM64_REG_B9, "b9"},
	{ ARM64_REG_B10, "b10"},
	{ ARM64_REG_B11, "b11"},
	{ ARM64_REG_B12, "b12"},
	{ ARM64_REG_B13, "b13"},
	{ ARM64_REG_B14, "b14"},
	{ ARM64_REG_B15, "b15"},
	{ ARM64_REG_B16, "b16"},
	{ ARM64_REG_B17, "b17"},
	{ ARM64_REG_B18, "b18"},
	{ ARM64_REG_B19, "b19"},
	{ ARM64_REG_B20, "b20"},
	{ ARM64_REG_B21, "b21"},
	{ ARM64_REG_B22, "b22"},
	{ ARM64_REG_B23, "b23"},
	{ ARM64_REG_B24, "b24"},
	{ ARM64_REG_B25, "b25"},
	{ ARM64_REG_B26, "b26"},
	{ ARM64_REG_B27, "b27"},
	{ ARM64_REG_B28, "b28"},
	{ ARM64_REG_B29, "b29"},
	{ ARM64_REG_B30, "b30"},
	{ ARM64_REG_B31, "b31"},
	{ ARM64_REG_D0, "d0"},
	{ ARM64_REG_D1, "d1"},
	{ ARM64_REG_D2, "d2"},
	{ ARM64_REG_D3, "d3"},
	{ ARM64_REG_D4, "d4"},
	{ ARM64_REG_D5, "d5"},
	{ ARM64_REG_D6, "d6"},
	{ ARM64_REG_D7, "d7"},
	{ ARM64_REG_D8, "d8"},
	{ ARM64_REG_D9, "d9"},
	{ ARM64_REG_D10, "d10"},
	{ ARM64_REG_D11, "d11"},
	{ ARM64_REG_D12, "d12"},
	{ ARM64_REG_D13, "d13"},
	{ ARM64_REG_D14, "d14"},
	{ ARM64_REG_D15, "d15"},
	{ ARM64_REG_D16, "d16"},
	{ ARM64_REG_D17, "d17"},
	{ ARM64_REG_D18, "d18"},
	{ ARM64_REG_D19, "d19"},
	{ ARM64_REG_D20, "d20"},
	{ ARM64_REG_D21, "d21"},
	{ ARM64_REG_D22, "d22"},
	{ ARM64_REG_D23, "d23"},
	{ ARM64_REG_D24, "d24"},
	{ ARM64_REG_D25, "d25"},
	{ ARM64_REG_D26, "d26"},
	{ ARM64_REG_D27, "d27"},
	{ ARM64_REG_D28, "d28"},
	{ ARM64_REG_D29, "d29"},
	{ ARM64_REG_D30, "d30"},
	{ ARM64_REG_D31, "d31"},
	{ ARM64_REG_H0, "h0"},
	{ ARM64_REG_H1, "h1"},
	{ ARM64_REG_H2, "h2"},
	{ ARM64_REG_H3, "h3"},
	{ ARM64_REG_H4, "h4"},
	{ ARM64_REG_H5, "h5"},
	{ ARM64_REG_H6, "h6"},
	{ ARM64_REG_H7, "h7"},
	{ ARM64_REG_H8, "h8"},
	{ ARM64_REG_H9, "h9"},
	{ ARM64_REG_H10, "h10"},
	{ ARM64_REG_H11, "h11"},
	{ ARM64_REG_H12, "h12"},
	{ ARM64_REG_H13, "h13"},
	{ ARM64_REG_H14, "h14"},
	{ ARM64_REG_H15, "h15"},
	{ ARM64_REG_H16, "h16"},
	{ ARM64_REG_H17, "h17"},
	{ ARM64_REG_H18, "h18"},
	{ ARM64_REG_H19, "h19"},
	{ ARM64_REG_H20, "h20"},
	{ ARM64_REG_H21, "h21"},
	{ ARM64_REG_H22, "h22"},
	{ ARM64_REG_H23, "h23"},
	{ ARM64_REG_H24, "h24"},
	{ ARM64_REG_H25, "h25"},
	{ ARM64_REG_H26, "h26"},
	{ ARM64_REG_H27, "h27"},
	{ ARM64_REG_H28, "h28"},
	{ ARM64_REG_H29, "h29"},
	{ ARM64_REG_H30, "h30"},
	{ ARM64_REG_H31, "h31"},
	{ ARM64_REG_Q0, "q0"},
	{ ARM64_REG_Q1, "q1"},
	{ ARM64_REG_Q2, "q2"},
	{ ARM64_REG_Q3, "q3"},
	{ ARM64_REG_Q4, "q4"},
	{ ARM64_REG_Q5, "q5"},
	{ ARM64_REG_Q6, "q6"},
	{ ARM64_REG_Q7, "q7"},
	{ ARM64_REG_Q8, "q8"},
	{ ARM64_REG_Q9, "q9"},
	{ ARM64_REG_Q10, "q10"},
	{ ARM64_REG_Q11, "q11"},
	{ ARM64_REG_Q12, "q12"},
	{ ARM64_REG_Q13, "q13"},
	{ ARM64_REG_Q14, "q14"},
	{ ARM64_REG_Q15, "q15"},
	{ ARM64_REG_Q16, "q16"},
	{ ARM64_REG_Q17, "q17"},
	{ ARM64_REG_Q18, "q18"},
	{ ARM64_REG_Q19, "q19"},
	{ ARM64_REG_Q20, "q20"},
	{ ARM64_REG_Q21, "q21"},
	{ ARM64_REG_Q22, "q22"},
	{ ARM64_REG_Q23, "q23"},
	{ ARM64_REG_Q24, "q24"},
	{ ARM64_REG_Q25, "q25"},
	{ ARM64_REG_Q26, "q26"},
	{ ARM64_REG_Q27, "q27"},
	{ ARM64_REG_Q28, "q28"},
	{ ARM64_REG_Q29, "q29"},
	{ ARM64_REG_Q30, "q30"},
	{ ARM64_REG_Q31, "q31"},
	{ ARM64_REG_S0, "s0"},
	{ ARM64_REG_S1, "s1"},
	{ ARM64_REG_S2, "s2"},
	{ ARM64_REG_S3, "s3"},
	{ ARM64_REG_S4, "s4"},
	{ ARM64_REG_S5, "s5"},
	{ ARM64_REG_S6, "s6"},
	{ ARM64_REG_S7, "s7"},
	{ ARM64_REG_S8, "s8"},
	{ ARM64_REG_S9, "s9"},
	{ ARM64_REG_S10, "s10"},
	{ ARM64_REG_S11, "s11"},
	{ ARM64_REG_S12, "s12"},
	{ ARM64_REG_S13, "s13"},
	{ ARM64_REG_S14, "s14"},
	{ ARM64_REG_S15, "s15"},
	{ ARM64_REG_S16, "s16"},
	{ ARM64_REG_S17, "s17"},
	{ ARM64_REG_S18, "s18"},
	{ ARM64_REG_S19, "s19"},
	{ ARM64_REG_S20, "s20"},
	{ ARM64_REG_S21, "s21"},
	{ ARM64_REG_S22, "s22"},
	{ ARM64_REG_S23, "s23"},
	{ ARM64_REG_S24, "s24"},
	{ ARM64_REG_S25, "s25"},
	{ ARM64_REG_S26, "s26"},
	{ ARM64_REG_S27, "s27"},
	{ ARM64_REG_S28, "s28"},
	{ ARM64_REG_S29, "s29"},
	{ ARM64_REG_S30, "s30"},
	{ ARM64_REG_S31, "s31"},
	{ ARM64_REG_W0, "w0"},
	{ ARM64_REG_W1, "w1"},
	{ ARM64_REG_W2, "w2"},
	{ ARM64_REG_W3, "w3"},
	{ ARM64_REG_W4, "w4"},
	{ ARM64_REG_W5, "w5"},
	{ ARM64_REG_W6, "w6"},
	{ ARM64_REG_W7, "w7"},
	{ ARM64_REG_W8, "w8"},
	{ ARM64_REG_W9, "w9"},
	{ ARM64_REG_W10, "w10"},
	{ ARM64_REG_W11, "w11"},
	{ ARM64_REG_W12, "w12"},
	{ ARM64_REG_W13, "w13"},
	{ ARM64_REG_W14, "w14"},
	{ ARM64_REG_W15, "w15"},
	{ ARM64_REG_W16, "w16"},
	{ ARM64_REG_W17, "w17"},
	{ ARM64_REG_W18, "w18"},
	{ ARM64_REG_W19, "w19"},
	{ ARM64_REG_W20, "w20"},
	{ ARM64_REG_W21, "w21"},
	{ ARM64_REG_W22, "w22"},
	{ ARM64_REG_W23, "w23"},
	{ ARM64_REG_W24, "w24"},
	{ ARM64_REG_W25, "w25"},
	{ ARM64_REG_W26, "w26"},
	{ ARM64_REG_W27, "w27"},
	{ ARM64_REG_W28, "w28"},
	{ ARM64_REG_W29, "w29"},
	{ ARM64_REG_W30, "w30"},
	{ ARM64_REG_X0, "x0"},
	{ ARM64_REG_X1, "x1"},
	{ ARM64_REG_X2, "x2"},
	{ ARM64_REG_X3, "x3"},
	{ ARM64_REG_X4, "x4"},
	{ ARM64_REG_X5, "x5"},
	{ ARM64_REG_X6, "x6"},
	{ ARM64_REG_X7, "x7"},
	{ ARM64_REG_X8, "x8"},
	{ ARM64_REG_X9, "x9"},
	{ ARM64_REG_X10, "x10"},
	{ ARM64_REG_X11, "x11"},
	{ ARM64_REG_X12, "x12"},
	{ ARM64_REG_X13, "x13"},
	{ ARM64_REG_X14, "x14"},
	{ ARM64_REG_X15, "x15"},
	{ ARM64_REG_X16, "x16"},
	{ ARM64_REG_X17, "x17"},
	{ ARM64_REG_X18, "x18"},
	{ ARM64_REG_X19, "x19"},
	{ ARM64_REG_X20, "x20"},
	{ ARM64_REG_X21, "x21"},
	{ ARM64_REG_X22, "x22"},
	{ ARM64_REG_X23, "x23"},
	{ ARM64_REG_X24, "x24"},
	{ ARM64_REG_X25, "x25"},
	{ ARM64_REG_X26, "x26"},
	{ ARM64_REG_X27, "x27"},
	{ ARM64_REG_X28, "x28"},
	{ ARM64_REG_X29, "x29"},
	{ ARM64_REG_X30, "x30"},
};

char *AArch64_reg_name(unsigned int reg)
{
	if (reg >= ARM64_REG_MAX)
		return NULL;

	return reg_name_maps[reg].name;
}

static insn_map insns[] = {
	{ AArch64_ADCSwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADCSxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADCwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_ADCxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_16B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_2S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_4H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_4S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_8B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDP_8H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDSwww_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSwww_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxx_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxx_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxx_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDddd, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_16B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_2D, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_2S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_4H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_4S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_8B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDvvv_8H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDwww_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxw_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxx_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxx_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxx_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxx_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADDxxx_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADRPxi, ARM64_INS_ADRP, { 0 }, { 0 }, { 0 } },
	{ AArch64_ADRxi, ARM64_INS_ADR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDSwwi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSwww_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSwww_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSwww_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSwww_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSxxi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSxxx_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSxxx_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSxxx_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDSxxx_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_ANDvvv_16B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ANDvvv_8B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ANDwwi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDwww_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDwww_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDwww_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDwww_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDxxi, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDxxx_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDxxx_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDxxx_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ANDxxx_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 } },
	{ AArch64_ASRVwww, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ASRVxxx, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ASRwwi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ASRxxi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ATix, ARM64_INS_AT, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFIwwii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFIxxii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFMwwii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFMxxii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFXILwwii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } },
	{ AArch64_BFXILxxii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICSwww_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSwww_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSwww_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSwww_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSxxx_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSxxx_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSxxx_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICSxxx_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_BICvi_lsl_2S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICvi_lsl_4H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICvi_lsl_4S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICvi_lsl_8H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICvvv_16B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICvvv_8B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BICwww_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICwww_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICwww_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICwww_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICxxx_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICxxx_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICxxx_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BICxxx_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 } },
	{ AArch64_BIFvvv_16B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BIFvvv_8B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BITvvv_16B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BITvvv_8B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BLRx, ARM64_INS_BLR, { 0 }, { ARM64_REG_X30, 0 }, { 0 } },
	{ AArch64_BLimm, ARM64_INS_BL, { 0 }, { ARM64_REG_X30, 0 }, { 0 } },
	{ AArch64_BRKi, ARM64_INS_BRK, { 0 }, { 0 }, { 0 } },
	{ AArch64_BRx, ARM64_INS_BR, { 0 }, { 0 }, { 0 } },
	{ AArch64_BSLvvv_16B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_BSLvvv_8B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_Bcc, ARM64_INS_B, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_Bimm, ARM64_INS_B, { 0 }, { 0 }, { 0 } },
	{ AArch64_CBNZw, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CBNZx, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CBZw, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CBZx, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CCMNwi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMNww, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMNxi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMNxx, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMPwi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMPww, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMPxi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CCMPxx, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CLREXi, ARM64_INS_CLREX, { 0 }, { 0 }, { 0 } },
	{ AArch64_CLSww, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } },
	{ AArch64_CLSxx, ARM64_INS_CLS, { 0 }, { 0 }, { 0 } },
	{ AArch64_CLZww, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CLZxx, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvi_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGEvvv_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvi_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMGTvvv_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_16B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_2D, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_2S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_4H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_4S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_8B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHIvvv_8H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_16B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_2D, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_2S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_4H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_4S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_8B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMHSvvv_8H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_16B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_2D, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_2S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_4H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_4S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_8B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLEvvi_8H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_16B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_2D, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_2S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_4H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_4S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_8B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMLTvvi_8H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMNww_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNww_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxw_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxx_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxx_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxx_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxx_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMNxx_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPww_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxw_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxx_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxx_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxx_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxx_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMPxx_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_CRC32B_www, ARM64_INS_CRC32B, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32CB_www, ARM64_INS_CRC32CB, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32CH_www, ARM64_INS_CRC32CH, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32CW_www, ARM64_INS_CRC32CW, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32H_www, ARM64_INS_CRC32H, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32W_www, ARM64_INS_CRC32W, { 0 }, { 0 }, { 0 } },
	{ AArch64_CRC32X_wwx, ARM64_INS_CRC32X, { 0 }, { 0 }, { 0 } },
	{ AArch64_CSELwwwc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSELxxxc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSINCwwwc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSINCxxxc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSINVwwwc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSINVxxxc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSNEGwwwc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_CSNEGxxxc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_DCPS1i, ARM64_INS_DCPS1, { 0 }, { 0 }, { 0 } },
	{ AArch64_DCPS2i, ARM64_INS_DCPS2, { 0 }, { 0 }, { 0 } },
	{ AArch64_DCPS3i, ARM64_INS_DCPS3, { 0 }, { 0 }, { 0 } },
	{ AArch64_DCix, ARM64_INS_DC, { 0 }, { 0 }, { 0 } },
	{ AArch64_DMBi, ARM64_INS_DMB, { 0 }, { 0 }, { 0 } },
	{ AArch64_DRPS, ARM64_INS_DRPS, { 0 }, { 0 }, { 0 } },
	{ AArch64_DSBi, ARM64_INS_DSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONwww_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONwww_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONwww_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONwww_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONxxx_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONxxx_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONxxx_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EONxxx_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORvvv_16B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_EORvvv_8B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_EORwwi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORwww_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORwww_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORwww_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORwww_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORxxi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORxxx_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORxxx_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORxxx_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EORxxx_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ERET, ARM64_INS_ERET, { 0 }, { 0 }, { 0 } },
	{ AArch64_EXTRwwwi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_EXTRxxxi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_FABDvvv_2D, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FABDvvv_2S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FABDvvv_4S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FABSdd, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FABSss, ARM64_INS_FABS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FACGEvvv_2D, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FACGEvvv_2S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FACGEvvv_4S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FACGTvvv_2D, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FACGTvvv_2S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FACGTvvv_4S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDP_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDP_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDP_4S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDddd, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FADDsss, ARM64_INS_FADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FADDvvv_2D, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDvvv_2S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FADDvvv_4S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCCMPEdd, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCCMPEss, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCCMPdd, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCCMPss, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FCMPdd_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPdd_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPdi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPdi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPsi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPsi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPss_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCMPss_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_FCSELdddc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_FCSELsssc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTASwd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTASws, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTASxd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTASxs, ARM64_INS_FCVTAS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTAUwd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTAUws, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTAUxd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTAUxs, ARM64_INS_FCVTAU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMSwd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMSws, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMSxd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMSxs, ARM64_INS_FCVTMS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMUwd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMUws, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMUxd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTMUxs, ARM64_INS_FCVTMU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNSwd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNSws, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNSxd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNSxs, ARM64_INS_FCVTNS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNUwd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNUws, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNUxd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTNUxs, ARM64_INS_FCVTNU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPSwd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPSws, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPSxd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPSxs, ARM64_INS_FCVTPS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPUwd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPUws, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPUxd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTPUxs, ARM64_INS_FCVTPU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSwd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSws, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSxd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSxs, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUwd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUws, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUxd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUxs, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTdh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTds, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVThd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVThs, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTsd, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FCVTsh, ARM64_INS_FCVT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FDIVddd, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FDIVsss, ARM64_INS_FDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FDIVvvv_2D, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FDIVvvv_2S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FDIVvvv_4S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMADDdddd, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMADDssss, ARM64_INS_FMADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXNMddd, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMAXNMsss, ARM64_INS_FMAXNM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXddd, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMAXsss, ARM64_INS_FMAX, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMAXvvv_2D, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXvvv_2S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMAXvvv_4S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMddd, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMINNMsss, ARM64_INS_FMINNM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINPvvv_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINPvvv_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINPvvv_4S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINddd, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMINsss, ARM64_INS_FMIN, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMINvvv_2D, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINvvv_2S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMINvvv_4S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLAvvv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLAvvv_2S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLAvvv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLSvvv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLSvvv_2S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMLSvvv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMOVdd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVdi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVdx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVsi, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVss, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVsw, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVvi_2D, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMOVvi_2S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMOVvi_4S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMOVvx, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVws, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVxd, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMOVxv, ARM64_INS_FMOV, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMSUBdddd, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMSUBssss, ARM64_INS_FMSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMULXvvv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMULXvvv_2S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMULXvvv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMULddd, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMULsss, ARM64_INS_FMUL, { 0 }, { 0 }, { 0 } },
	{ AArch64_FMULvvv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMULvvv_2S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FMULvvv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FNEGdd, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNEGss, ARM64_INS_FNEG, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMADDdddd, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMADDssss, ARM64_INS_FNMADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMSUBssss, ARM64_INS_FNMSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMULddd, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } },
	{ AArch64_FNMULsss, ARM64_INS_FNMUL, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FRINTAdd, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTAss, ARM64_INS_FRINTA, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTIdd, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTIss, ARM64_INS_FRINTI, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTMdd, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTMss, ARM64_INS_FRINTM, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTNdd, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTNss, ARM64_INS_FRINTN, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTPdd, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTPss, ARM64_INS_FRINTP, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTXdd, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTXss, ARM64_INS_FRINTX, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTZdd, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRINTZss, ARM64_INS_FRINTZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FSQRTdd, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FSQRTss, ARM64_INS_FSQRT, { 0 }, { 0 }, { 0 } },
	{ AArch64_FSUBddd, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FSUBsss, ARM64_INS_FSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_FSUBvvv_2D, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FSUBvvv_2S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_FSUBvvv_4S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_HINTi, ARM64_INS_HINT, { 0 }, { 0 }, { 0 } },
	{ AArch64_HLTi, ARM64_INS_HLT, { 0 }, { 0 }, { 0 } },
	{ AArch64_HVCi, ARM64_INS_HVC, { 0 }, { 0 }, { 0 } },
	{ AArch64_ICi, ARM64_INS_IC, { 0 }, { 0 }, { 0 } },
	{ AArch64_ICix, ARM64_INS_IC, { 0 }, { 0 }, { 0 } },
	{ AArch64_INSELb, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSELd, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSELh, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSELs, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSbw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSdx, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INShw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_INSsw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ISBi, ARM64_INS_ISB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAR_byte, ARM64_INS_LDARB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAR_dword, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAR_hword, ARM64_INS_LDARH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAR_word, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXP_dword, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXP_word, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXR_byte, ARM64_INS_LDAXRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXR_dword, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXR_hword, ARM64_INS_LDAXRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDAXR_word, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDPSWx, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRSWx_lit, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRd_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRq_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRs_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRw_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDRx_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDTRSBw, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDTRSBx, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDTRSHw, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDTRSHx, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDTRSWx, ARM64_INS_LDTRSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDURSWx, ARM64_INS_LDURSW, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXP_dword, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXP_word, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXR_byte, ARM64_INS_LDXRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXR_dword, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXR_hword, ARM64_INS_LDXRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LDXR_word, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_LDUR, ARM64_INS_LDURH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_PostInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_PreInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_STUR, ARM64_INS_STURH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_LDUR, ARM64_INS_LDURB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_PostInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_PreInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_STUR, ARM64_INS_STURB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair128_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSFPPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSLVwww, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSLVxxx, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSLwwi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSLxxi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSRVwww, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSRVxxx, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSRwwi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_LSRxxi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_MADDwwww, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_MADDxxxx, ARM64_INS_MADD, { 0 }, { 0 }, { 0 } },
	{ AArch64_MLAvvv_16B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLAvvv_2S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLAvvv_4H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLAvvv_4S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLAvvv_8B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLAvvv_8H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_16B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_2S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_4H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_4S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_8B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MLSvvv_8H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIdi, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_16B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_2D, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_8B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MOVKwii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } },
	{ AArch64_MOVKxii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 } },
	{ AArch64_MOVNwii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MOVNxii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MOVZwii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_MOVZxii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_MRSxi, ARM64_INS_MRS, { 0 }, { 0 }, { 0 } },
	{ AArch64_MSRii, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_MSRix, ARM64_INS_MSR, { 0 }, { 0 }, { 0 } },
	{ AArch64_MSUBwwww, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_MSUBxxxx, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_MULvvv_16B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MULvvv_2S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MULvvv_4H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MULvvv_4S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MULvvv_8B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MULvvv_8H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_MVNww_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNww_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNww_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNww_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNxx_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNxx_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNxx_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_MVNxx_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNvvv_16B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORNvvv_8B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORNwww_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNwww_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNwww_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNwww_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNxxx_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNxxx_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNxxx_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORNxxx_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRvvv_16B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRvvv_8B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_ORRwwi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRwww_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRwww_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRwww_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRwww_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRxxi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRxxx_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRxxx_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRxxx_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_ORRxxx_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 } },
	{ AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_PMULvvv_16B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_PMULvvv_8B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_PRFM, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_PRFM_lit, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_PRFUM, ARM64_INS_PRFUM, { 0 }, { 0 }, { 0 } },
	{ AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RBITww, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } },
	{ AArch64_RBITxx, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 } },
	{ AArch64_RETx, ARM64_INS_RET, { 0 }, { 0 }, { 0 } },
	{ AArch64_REV16ww, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } },
	{ AArch64_REV16xx, ARM64_INS_REV16, { 0 }, { 0 }, { 0 } },
	{ AArch64_REV32xx, ARM64_INS_REV32, { 0 }, { 0 }, { 0 } },
	{ AArch64_REVww, ARM64_INS_REV, { 0 }, { 0 }, { 0 } },
	{ AArch64_REVxx, ARM64_INS_REV, { 0 }, { 0 }, { 0 } },
	{ AArch64_RORVwww, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } },
	{ AArch64_RORVxxx, ARM64_INS_ROR, { 0 }, { 0 }, { 0 } },
	{ AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_16B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_2S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_4H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_4S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_8B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABAvvv_8H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_16B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_2S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_4H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_4S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_8B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SABDvvv_8H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SBCSwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SBCSxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SBCwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_SBCxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 } },
	{ AArch64_SBFIZwwii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_SBFIZxxii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_SBFMwwii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_SBFMxxii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_SBFXwwii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } },
	{ AArch64_SBFXxxii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFdw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFdwi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFdx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFdxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFsw, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFswi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFsx, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SCVTFsxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_SDIVwww, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_SDIVxxx, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_SHADDvvv_16B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHADDvvv_2S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHADDvvv_4H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHADDvvv_4S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHADDvvv_8B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHADDvvv_8H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_16B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_2D, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_2S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_4H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_4S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_8B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHLvvi_8H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_2S, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_4H, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_8B, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_16B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_2D, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_2S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_4H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_4S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_8B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SLIvvi_8H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMADDLxwwx, ARM64_INS_SMADDL, { 0 }, { 0 }, { 0 } },
	{ AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_16B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_2S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_4H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_4S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_8B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMAXvvv_8H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMCi, ARM64_INS_SMC, { 0 }, { 0 }, { 0 } },
	{ AArch64_SMINPvvv_16B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINPvvv_2S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINPvvv_4H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINPvvv_4S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINPvvv_8B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINPvvv_8H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_16B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_2S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_4H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_4S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_8B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMINvvv_8H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMOVwb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMOVwh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMOVxb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMOVxh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMOVxs, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, { 0 }, { 0 }, { 0 } },
	{ AArch64_SMULHxxx, ARM64_INS_SMULH, { 0 }, { 0 }, { 0 } },
	{ AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDbbb, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDddd, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDhhh, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDsss, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_16B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_2D, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_2S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_4H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_4S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_8B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQADDvvv_8H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLddd, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLsss, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLbbb, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLddd, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLhhh, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLsss, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBbbb, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBddd, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBhhh, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBsss, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_16B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_2D, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_2S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_4H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_4S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_8B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRIvvi_8H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLddd, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLddd, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_16B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_2D, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_2S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_4H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_4S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_8B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHLvvv_8H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_16B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_2D, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_2S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_4H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_4S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_8B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSHRvvi_8H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_16B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_2D, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_2S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_4H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_4S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_8B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSRAvvi_8H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_STLR_byte, ARM64_INS_STLRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLR_dword, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLR_hword, ARM64_INS_STLRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLR_word, ARM64_INS_STLR, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXP_dword, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXP_word, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXR_byte, ARM64_INS_STLXRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXR_dword, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXR_hword, ARM64_INS_STLXRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_STLXR_word, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXP_dword, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXP_word, ARM64_INS_STXP, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXR_byte, ARM64_INS_STXRB, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXR_dword, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXR_hword, ARM64_INS_STXRH, { 0 }, { 0 }, { 0 } },
	{ AArch64_STXR_word, ARM64_INS_STXR, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBSwww_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSwww_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxx_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxx_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxx_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBddd, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_16B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_2D, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_2S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_4H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_4S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_8B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBvvv_8H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBwww_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxw_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxx_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxx_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxx_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxx_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SUBxxx_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SVCi, ARM64_INS_SVC, { 0 }, { 0 }, { 0 } },
	{ AArch64_SXTBww, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SXTBxw, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 } },
	{ AArch64_SXTHww, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } },
	{ AArch64_SXTHxw, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 } },
	{ AArch64_SXTWxw, ARM64_INS_SXTW, { 0 }, { 0 }, { 0 } },
	{ AArch64_SYSLxicci, ARM64_INS_SYSL, { 0 }, { 0 }, { 0 } },
	{ AArch64_SYSiccix, ARM64_INS_SYS, { 0 }, { 0 }, { 0 } },
	{ AArch64_TBNZwii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_TBNZxii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_TBZwii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_TBZxii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_TLBIi, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } },
	{ AArch64_TLBIix, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 } },
	{ AArch64_TSTww_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTww_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTww_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTww_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTxx_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTxx_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTxx_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_TSTxx_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
	{ AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_16B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_2S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_4H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_4S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_8B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABAvvv_8H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_16B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_2S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_4H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_4S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_8B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UABDvvv_8H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UBFIZwwii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_UBFIZxxii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 } },
	{ AArch64_UBFMwwii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_UBFMxxii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 } },
	{ AArch64_UBFXwwii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } },
	{ AArch64_UBFXxxii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFdw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFdwi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFdx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFdxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFsw, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFswi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFsx, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UCVTFsxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { 0 } },
	{ AArch64_UDIVwww, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_UDIVxxx, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 } },
	{ AArch64_UHADDvvv_16B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHADDvvv_2S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHADDvvv_4H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHADDvvv_4S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHADDvvv_8B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHADDvvv_8H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMADDLxwwx, ARM64_INS_UMADDL, { 0 }, { 0 }, { 0 } },
	{ AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_16B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_2S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_4H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_4S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_8B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMAXvvv_8H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_16B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_2S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_4H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_4S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_8B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINPvvv_8H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_16B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_2S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_4H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_4S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_8B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMINvvv_8H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMOVwb, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMOVwh, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMOVws, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMOVxd, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, { 0 }, { 0 }, { 0 } },
	{ AArch64_UMULHxxx, ARM64_INS_UMULH, { 0 }, { 0 }, { 0 } },
	{ AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDbbb, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDddd, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDhhh, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDsss, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_16B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_2D, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_2S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_4H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_4S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_8B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQADDvvv_8H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLddd, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLsss, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLbbb, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLddd, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLhhh, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLsss, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBbbb, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBddd, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBhhh, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBsss, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_16B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_2S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_4H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_4S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_8B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URHADDvvv_8H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLddd, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_16B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_2D, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_2S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_4H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_4S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_8B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHLvvv_8H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_16B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_2D, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_2S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_4H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_4S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_8B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSHRvvi_8H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_16B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_2D, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_2S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_4H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_4S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_8B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_URSRAvvi_8H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_2S, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_4H, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_8B, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLddd, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_16B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_2D, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_2S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_4H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_4S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_8B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHLvvv_8H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_16B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_2D, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_2S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_4H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_4S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_8B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USHRvvi_8H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_16B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_2D, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_2S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_4H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_4S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_8B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USRAvvi_8H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_UXTBww, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } },
	{ AArch64_UXTBxw, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 } },
	{ AArch64_UXTHww, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } },
	{ AArch64_UXTHxw, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 } },
	{ AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
	{ AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 } },
};

void AArch64_get_insn_id(cs_insn *insn, unsigned int id)
{
	int i = insn_find(insns, ARR_SIZE(insns), id);
	if (i != -1) {
		insn->id = insns[i].mapid;
		memcpy(insn->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
		memcpy(insn->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
		memcpy(insn->groups, insns[i].groups, sizeof(insns[i].groups));
		insn->arm64.update_flags = cs_reg_write(1, insn, ARM64_REG_NZCV);
	}
}

// given public insn id, return internal instruction ID
unsigned int AArch64_get_insn_id2(unsigned int id)
{
	return insn_reverse_id(insns, ARR_SIZE(insns), id);
}

static name_map insn_name_maps[] = {
	{ ARM64_INS_INVALID, NULL },
	{ ARM64_INS_ADC, "ADC" },
	{ ARM64_INS_ADDHN2, "ADDHN2" },
	{ ARM64_INS_ADDHN, "ADDHN" },
	{ ARM64_INS_ADDP, "ADDP" },
	{ ARM64_INS_ADD, "ADD" },
	{ ARM64_INS_CMN, "CMN" },
	{ ARM64_INS_ADRP, "ADRP" },
	{ ARM64_INS_ADR, "ADR" },
	{ ARM64_INS_AND, "AND" },
	{ ARM64_INS_ASR, "ASR" },
	{ ARM64_INS_AT, "AT" },
	{ ARM64_INS_BFI, "BFI" },
	{ ARM64_INS_BFM, "BFM" },
	{ ARM64_INS_BFXIL, "BFXIL" },
	{ ARM64_INS_BIC, "BIC" },
	{ ARM64_INS_BIF, "BIF" },
	{ ARM64_INS_BIT, "BIT" },
	{ ARM64_INS_BLR, "BLR" },
	{ ARM64_INS_BL, "BL" },
	{ ARM64_INS_BRK, "BRK" },
	{ ARM64_INS_BR, "BR" },
	{ ARM64_INS_BSL, "BSL" },
	{ ARM64_INS_B, "B" },
	{ ARM64_INS_CBNZ, "CBNZ" },
	{ ARM64_INS_CBZ, "CBZ" },
	{ ARM64_INS_CCMN, "CCMN" },
	{ ARM64_INS_CCMP, "CCMP" },
	{ ARM64_INS_CLREX, "CLREX" },
	{ ARM64_INS_CLS, "CLS" },
	{ ARM64_INS_CLZ, "CLZ" },
	{ ARM64_INS_CMEQ, "CMEQ" },
	{ ARM64_INS_CMGE, "CMGE" },
	{ ARM64_INS_CMGT, "CMGT" },
	{ ARM64_INS_CMHI, "CMHI" },
	{ ARM64_INS_CMHS, "CMHS" },
	{ ARM64_INS_CMLE, "CMLE" },
	{ ARM64_INS_CMLT, "CMLT" },
	{ ARM64_INS_CMP, "CMP" },
	{ ARM64_INS_CMTST, "CMTST" },
	{ ARM64_INS_CRC32B, "CRC32B" },
	{ ARM64_INS_CRC32CB, "CRC32CB" },
	{ ARM64_INS_CRC32CH, "CRC32CH" },
	{ ARM64_INS_CRC32CW, "CRC32CW" },
	{ ARM64_INS_CRC32CX, "CRC32CX" },
	{ ARM64_INS_CRC32H, "CRC32H" },
	{ ARM64_INS_CRC32W, "CRC32W" },
	{ ARM64_INS_CRC32X, "CRC32X" },
	{ ARM64_INS_CSEL, "CSEL" },
	{ ARM64_INS_CSINC, "CSINC" },
	{ ARM64_INS_CSINV, "CSINV" },
	{ ARM64_INS_CSNEG, "CSNEG" },
	{ ARM64_INS_DCPS1, "DCPS1" },
	{ ARM64_INS_DCPS2, "DCPS2" },
	{ ARM64_INS_DCPS3, "DCPS3" },
	{ ARM64_INS_DC, "DC" },
	{ ARM64_INS_DMB, "DMB" },
	{ ARM64_INS_DRPS, "DRPS" },
	{ ARM64_INS_DSB, "DSB" },
	{ ARM64_INS_EON, "EON" },
	{ ARM64_INS_EOR, "EOR" },
	{ ARM64_INS_ERET, "ERET" },
	{ ARM64_INS_EXTR, "EXTR" },
	{ ARM64_INS_FABD, "FABD" },
	{ ARM64_INS_FABS, "FABS" },
	{ ARM64_INS_FACGE, "FACGE" },
	{ ARM64_INS_FACGT, "FACGT" },
	{ ARM64_INS_FADDP, "FADDP" },
	{ ARM64_INS_FADD, "FADD" },
	{ ARM64_INS_FCCMPE, "FCCMPE" },
	{ ARM64_INS_FCCMP, "FCCMP" },
	{ ARM64_INS_FCMEQ, "FCMEQ" },
	{ ARM64_INS_FCMGE, "FCMGE" },
	{ ARM64_INS_FCMGT, "FCMGT" },
	{ ARM64_INS_FCMLE, "FCMLE" },
	{ ARM64_INS_FCMLT, "FCMLT" },
	{ ARM64_INS_FCMP, "FCMP" },
	{ ARM64_INS_FCMPE, "FCMPE" },
	{ ARM64_INS_FCSEL, "FCSEL" },
	{ ARM64_INS_FCVTAS, "FCVTAS" },
	{ ARM64_INS_FCVTAU, "FCVTAU" },
	{ ARM64_INS_FCVTMS, "FCVTMS" },
	{ ARM64_INS_FCVTMU, "FCVTMU" },
	{ ARM64_INS_FCVTNS, "FCVTNS" },
	{ ARM64_INS_FCVTNU, "FCVTNU" },
	{ ARM64_INS_FCVTPS, "FCVTPS" },
	{ ARM64_INS_FCVTPU, "FCVTPU" },
	{ ARM64_INS_FCVTZS, "FCVTZS" },
	{ ARM64_INS_FCVTZU, "FCVTZU" },
	{ ARM64_INS_FCVT, "FCVT" },
	{ ARM64_INS_FDIV, "FDIV" },
	{ ARM64_INS_FMADD, "FMADD" },
	{ ARM64_INS_FMAXNMP, "FMAXNMP" },
	{ ARM64_INS_FMAXNM, "FMAXNM" },
	{ ARM64_INS_FMAXP, "FMAXP" },
	{ ARM64_INS_FMAX, "FMAX" },
	{ ARM64_INS_FMINNMP, "FMINNMP" },
	{ ARM64_INS_FMINNM, "FMINNM" },
	{ ARM64_INS_FMINP, "FMINP" },
	{ ARM64_INS_FMIN, "FMIN" },
	{ ARM64_INS_FMLA, "FMLA" },
	{ ARM64_INS_FMLS, "FMLS" },
	{ ARM64_INS_FMOV, "FMOV" },
	{ ARM64_INS_FMSUB, "FMSUB" },
	{ ARM64_INS_FMULX, "FMULX" },
	{ ARM64_INS_FMUL, "FMUL" },
	{ ARM64_INS_FNEG, "FNEG" },
	{ ARM64_INS_FNMADD, "FNMADD" },
	{ ARM64_INS_FNMSUB, "FNMSUB" },
	{ ARM64_INS_FNMUL, "FNMUL" },
	{ ARM64_INS_FRECPS, "FRECPS" },
	{ ARM64_INS_FRINTA, "FRINTA" },
	{ ARM64_INS_FRINTI, "FRINTI" },
	{ ARM64_INS_FRINTM, "FRINTM" },
	{ ARM64_INS_FRINTN, "FRINTN" },
	{ ARM64_INS_FRINTP, "FRINTP" },
	{ ARM64_INS_FRINTX, "FRINTX" },
	{ ARM64_INS_FRINTZ, "FRINTZ" },
	{ ARM64_INS_FRSQRTS, "FRSQRTS" },
	{ ARM64_INS_FSQRT, "FSQRT" },
	{ ARM64_INS_FSUB, "FSUB" },
	{ ARM64_INS_HINT, "HINT" },
	{ ARM64_INS_HLT, "HLT" },
	{ ARM64_INS_HVC, "HVC" },
	{ ARM64_INS_IC, "IC" },
	{ ARM64_INS_INS, "INS" },
	{ ARM64_INS_ISB, "ISB" },
	{ ARM64_INS_LDARB, "LDARB" },
	{ ARM64_INS_LDAR, "LDAR" },
	{ ARM64_INS_LDARH, "LDARH" },
	{ ARM64_INS_LDAXP, "LDAXP" },
	{ ARM64_INS_LDAXRB, "LDAXRB" },
	{ ARM64_INS_LDAXR, "LDAXR" },
	{ ARM64_INS_LDAXRH, "LDAXRH" },
	{ ARM64_INS_LDPSW, "LDPSW" },
	{ ARM64_INS_LDRSB, "LDRSB" },
	{ ARM64_INS_LDURSB, "LDURSB" },
	{ ARM64_INS_LDRSH, "LDRSH" },
	{ ARM64_INS_LDURSH, "LDURSH" },
	{ ARM64_INS_LDRSW, "LDRSW" },
	{ ARM64_INS_LDR, "LDR" },
	{ ARM64_INS_LDTRSB, "LDTRSB" },
	{ ARM64_INS_LDTRSH, "LDTRSH" },
	{ ARM64_INS_LDTRSW, "LDTRSW" },
	{ ARM64_INS_LDURSW, "LDURSW" },
	{ ARM64_INS_LDXP, "LDXP" },
	{ ARM64_INS_LDXRB, "LDXRB" },
	{ ARM64_INS_LDXR, "LDXR" },
	{ ARM64_INS_LDXRH, "LDXRH" },
	{ ARM64_INS_LDRH, "LDRH" },
	{ ARM64_INS_LDURH, "LDURH" },
	{ ARM64_INS_STRH, "STRH" },
	{ ARM64_INS_STURH, "STURH" },
	{ ARM64_INS_LDTRH, "LDTRH" },
	{ ARM64_INS_STTRH, "STTRH" },
	{ ARM64_INS_LDUR, "LDUR" },
	{ ARM64_INS_STR, "STR" },
	{ ARM64_INS_STUR, "STUR" },
	{ ARM64_INS_LDTR, "LDTR" },
	{ ARM64_INS_STTR, "STTR" },
	{ ARM64_INS_LDRB, "LDRB" },
	{ ARM64_INS_LDURB, "LDURB" },
	{ ARM64_INS_STRB, "STRB" },
	{ ARM64_INS_STURB, "STURB" },
	{ ARM64_INS_LDTRB, "LDTRB" },
	{ ARM64_INS_STTRB, "STTRB" },
	{ ARM64_INS_LDP, "LDP" },
	{ ARM64_INS_LDNP, "LDNP" },
	{ ARM64_INS_STNP, "STNP" },
	{ ARM64_INS_STP, "STP" },
	{ ARM64_INS_LSL, "LSL" },
	{ ARM64_INS_LSR, "LSR" },
	{ ARM64_INS_MADD, "MADD" },
	{ ARM64_INS_MLA, "MLA" },
	{ ARM64_INS_MLS, "MLS" },
	{ ARM64_INS_MOVI, "MOVI" },
	{ ARM64_INS_MOVK, "MOVK" },
	{ ARM64_INS_MOVN, "MOVN" },
	{ ARM64_INS_MOVZ, "MOVZ" },
	{ ARM64_INS_MRS, "MRS" },
	{ ARM64_INS_MSR, "MSR" },
	{ ARM64_INS_MSUB, "MSUB" },
	{ ARM64_INS_MUL, "MUL" },
	{ ARM64_INS_MVNI, "MVNI" },
	{ ARM64_INS_MVN, "MVN" },
	{ ARM64_INS_ORN, "ORN" },
	{ ARM64_INS_ORR, "ORR" },
	{ ARM64_INS_PMULL2, "PMULL2" },
	{ ARM64_INS_PMULL, "PMULL" },
	{ ARM64_INS_PMUL, "PMUL" },
	{ ARM64_INS_PRFM, "PRFM" },
	{ ARM64_INS_PRFUM, "PRFUM" },
	{ ARM64_INS_SQRSHRUN2, "SQRSHRUN2" },
	{ ARM64_INS_SQRSHRUN, "SQRSHRUN" },
	{ ARM64_INS_SQSHRUN2, "SQSHRUN2" },
	{ ARM64_INS_SQSHRUN, "SQSHRUN" },
	{ ARM64_INS_RADDHN2, "RADDHN2" },
	{ ARM64_INS_RADDHN, "RADDHN" },
	{ ARM64_INS_RBIT, "RBIT" },
	{ ARM64_INS_RET, "RET" },
	{ ARM64_INS_REV16, "REV16" },
	{ ARM64_INS_REV32, "REV32" },
	{ ARM64_INS_REV, "REV" },
	{ ARM64_INS_ROR, "ROR" },
	{ ARM64_INS_RSHRN2, "RSHRN2" },
	{ ARM64_INS_RSHRN, "RSHRN" },
	{ ARM64_INS_RSUBHN2, "RSUBHN2" },
	{ ARM64_INS_RSUBHN, "RSUBHN" },
	{ ARM64_INS_SABAL2, "SABAL2" },
	{ ARM64_INS_SABAL, "SABAL" },
	{ ARM64_INS_SABA, "SABA" },
	{ ARM64_INS_SABDL2, "SABDL2" },
	{ ARM64_INS_SABDL, "SABDL" },
	{ ARM64_INS_SABD, "SABD" },
	{ ARM64_INS_SADDL2, "SADDL2" },
	{ ARM64_INS_SADDL, "SADDL" },
	{ ARM64_INS_SADDW2, "SADDW2" },
	{ ARM64_INS_SADDW, "SADDW" },
	{ ARM64_INS_SBC, "SBC" },
	{ ARM64_INS_SBFIZ, "SBFIZ" },
	{ ARM64_INS_SBFM, "SBFM" },
	{ ARM64_INS_SBFX, "SBFX" },
	{ ARM64_INS_SCVTF, "SCVTF" },
	{ ARM64_INS_SDIV, "SDIV" },
	{ ARM64_INS_SHADD, "SHADD" },
	{ ARM64_INS_SHL, "SHL" },
	{ ARM64_INS_SHRN2, "SHRN2" },
	{ ARM64_INS_SHRN, "SHRN" },
	{ ARM64_INS_SHSUB, "SHSUB" },
	{ ARM64_INS_SLI, "SLI" },
	{ ARM64_INS_SMADDL, "SMADDL" },
	{ ARM64_INS_SMAXP, "SMAXP" },
	{ ARM64_INS_SMAX, "SMAX" },
	{ ARM64_INS_SMC, "SMC" },
	{ ARM64_INS_SMINP, "SMINP" },
	{ ARM64_INS_SMIN, "SMIN" },
	{ ARM64_INS_SMLAL2, "SMLAL2" },
	{ ARM64_INS_SMLAL, "SMLAL" },
	{ ARM64_INS_SMLSL2, "SMLSL2" },
	{ ARM64_INS_SMLSL, "SMLSL" },
	{ ARM64_INS_SMOV, "SMOV" },
	{ ARM64_INS_SMSUBL, "SMSUBL" },
	{ ARM64_INS_SMULH, "SMULH" },
	{ ARM64_INS_SMULL2, "SMULL2" },
	{ ARM64_INS_SMULL, "SMULL" },
	{ ARM64_INS_SQADD, "SQADD" },
	{ ARM64_INS_SQDMLAL2, "SQDMLAL2" },
	{ ARM64_INS_SQDMLAL, "SQDMLAL" },
	{ ARM64_INS_SQDMLSL2, "SQDMLSL2" },
	{ ARM64_INS_SQDMLSL, "SQDMLSL" },
	{ ARM64_INS_SQDMULH, "SQDMULH" },
	{ ARM64_INS_SQDMULL2, "SQDMULL2" },
	{ ARM64_INS_SQDMULL, "SQDMULL" },
	{ ARM64_INS_SQRDMULH, "SQRDMULH" },
	{ ARM64_INS_SQRSHL, "SQRSHL" },
	{ ARM64_INS_SQRSHRN2, "SQRSHRN2" },
	{ ARM64_INS_SQRSHRN, "SQRSHRN" },
	{ ARM64_INS_SQSHLU, "SQSHLU" },
	{ ARM64_INS_SQSHL, "SQSHL" },
	{ ARM64_INS_SQSHRN2, "SQSHRN2" },
	{ ARM64_INS_SQSHRN, "SQSHRN" },
	{ ARM64_INS_SQSUB, "SQSUB" },
	{ ARM64_INS_SRHADD, "SRHADD" },
	{ ARM64_INS_SRI, "SRI" },
	{ ARM64_INS_SRSHL, "SRSHL" },
	{ ARM64_INS_SRSHR, "SRSHR" },
	{ ARM64_INS_SRSRA, "SRSRA" },
	{ ARM64_INS_SSHLL2, "SSHLL2" },
	{ ARM64_INS_SSHLL, "SSHLL" },
	{ ARM64_INS_SSHL, "SSHL" },
	{ ARM64_INS_SSHR, "SSHR" },
	{ ARM64_INS_SSRA, "SSRA" },
	{ ARM64_INS_SSUBL2, "SSUBL2" },
	{ ARM64_INS_SSUBL, "SSUBL" },
	{ ARM64_INS_SSUBW2, "SSUBW2" },
	{ ARM64_INS_SSUBW, "SSUBW" },
	{ ARM64_INS_STLRB, "STLRB" },
	{ ARM64_INS_STLR, "STLR" },
	{ ARM64_INS_STLRH, "STLRH" },
	{ ARM64_INS_STLXP, "STLXP" },
	{ ARM64_INS_STLXRB, "STLXRB" },
	{ ARM64_INS_STLXR, "STLXR" },
	{ ARM64_INS_STLXRH, "STLXRH" },
	{ ARM64_INS_STXP, "STXP" },
	{ ARM64_INS_STXRB, "STXRB" },
	{ ARM64_INS_STXR, "STXR" },
	{ ARM64_INS_STXRH, "STXRH" },
	{ ARM64_INS_SUBHN2, "SUBHN2" },
	{ ARM64_INS_SUBHN, "SUBHN" },
	{ ARM64_INS_SUB, "SUB" },
	{ ARM64_INS_SVC, "SVC" },
	{ ARM64_INS_SXTB, "SXTB" },
	{ ARM64_INS_SXTH, "SXTH" },
	{ ARM64_INS_SXTW, "SXTW" },
	{ ARM64_INS_SYSL, "SYSL" },
	{ ARM64_INS_SYS, "SYS" },
	{ ARM64_INS_TBNZ, "TBNZ" },
	{ ARM64_INS_TBZ, "TBZ" },
	{ ARM64_INS_TLBI, "TLBI" },
	{ ARM64_INS_TST, "TST" },
	{ ARM64_INS_UABAL2, "UABAL2" },
	{ ARM64_INS_UABAL, "UABAL" },
	{ ARM64_INS_UABA, "UABA" },
	{ ARM64_INS_UABDL2, "UABDL2" },
	{ ARM64_INS_UABDL, "UABDL" },
	{ ARM64_INS_UABD, "UABD" },
	{ ARM64_INS_UADDL2, "UADDL2" },
	{ ARM64_INS_UADDL, "UADDL" },
	{ ARM64_INS_UADDW2, "UADDW2" },
	{ ARM64_INS_UADDW, "UADDW" },
	{ ARM64_INS_UBFIZ, "UBFIZ" },
	{ ARM64_INS_UBFM, "UBFM" },
	{ ARM64_INS_UBFX, "UBFX" },
	{ ARM64_INS_UCVTF, "UCVTF" },
	{ ARM64_INS_UDIV, "UDIV" },
	{ ARM64_INS_UHADD, "UHADD" },
	{ ARM64_INS_UHSUB, "UHSUB" },
	{ ARM64_INS_UMADDL, "UMADDL" },
	{ ARM64_INS_UMAXP, "UMAXP" },
	{ ARM64_INS_UMAX, "UMAX" },
	{ ARM64_INS_UMINP, "UMINP" },
	{ ARM64_INS_UMIN, "UMIN" },
	{ ARM64_INS_UMLAL2, "UMLAL2" },
	{ ARM64_INS_UMLAL, "UMLAL" },
	{ ARM64_INS_UMLSL2, "UMLSL2" },
	{ ARM64_INS_UMLSL, "UMLSL" },
	{ ARM64_INS_UMOV, "UMOV" },
	{ ARM64_INS_UMSUBL, "UMSUBL" },
	{ ARM64_INS_UMULH, "UMULH" },
	{ ARM64_INS_UMULL2, "UMULL2" },
	{ ARM64_INS_UMULL, "UMULL" },
	{ ARM64_INS_UQADD, "UQADD" },
	{ ARM64_INS_UQRSHL, "UQRSHL" },
	{ ARM64_INS_UQRSHRN2, "UQRSHRN2" },
	{ ARM64_INS_UQRSHRN, "UQRSHRN" },
	{ ARM64_INS_UQSHL, "UQSHL" },
	{ ARM64_INS_UQSHRN2, "UQSHRN2" },
	{ ARM64_INS_UQSHRN, "UQSHRN" },
	{ ARM64_INS_UQSUB, "UQSUB" },
	{ ARM64_INS_URHADD, "URHADD" },
	{ ARM64_INS_URSHL, "URSHL" },
	{ ARM64_INS_URSHR, "URSHR" },
	{ ARM64_INS_URSRA, "URSRA" },
	{ ARM64_INS_USHLL2, "USHLL2" },
	{ ARM64_INS_USHLL, "USHLL" },
	{ ARM64_INS_USHL, "USHL" },
	{ ARM64_INS_USHR, "USHR" },
	{ ARM64_INS_USRA, "USRA" },
	{ ARM64_INS_USUBL2, "USUBL2" },
	{ ARM64_INS_USUBL, "USUBL" },
	{ ARM64_INS_USUBW2, "USUBW2" },
	{ ARM64_INS_USUBW, "USUBW" },
	{ ARM64_INS_UXTB, "UXTB" },
	{ ARM64_INS_UXTH, "UXTH" },
};

char *AArch64_insn_name(unsigned int id)
{
	if (id >= ARM64_INS_MAX)
		return NULL;

	return insn_name_maps[id].name;
}

// map instruction name to public instruction ID
arm64_reg AArch64_map_insn(char *name)
{
	// map *S instructions back to original id
	name_map insn_name_maps2[] = {
		{ ARM64_INS_ADC, "ADCS" },
		{ ARM64_INS_AND, "ANDS" },
		{ ARM64_INS_ADD, "ADDS" },
		{ ARM64_INS_BIC, "BICS" },
		{ ARM64_INS_SBC, "SBCS" },
		{ ARM64_INS_SUB, "SUBS" },

		// alias insn
		{ ARM64_INS_MNEG, "MNEG" },
		{ ARM64_INS_UMNEGL, "UMNEGL" },
		{ ARM64_INS_SMNEGL, "SMNEGL" },
		{ ARM64_INS_MOV, "MOV" },
		{ ARM64_INS_NOP, "NOP" },
		{ ARM64_INS_YIELD, "YIELD" },
		{ ARM64_INS_WFE, "WFE" },
		{ ARM64_INS_WFI, "WFI" },
		{ ARM64_INS_SEV, "SEV" },
		{ ARM64_INS_SEVL, "SEVL" },
		{ ARM64_INS_NGC, "NGC" },
		{ ARM64_INS_NEG, "NEG" },

		// FIXME: map these with flag updated
		{ ARM64_INS_NEG, "NEGS" },
		{ ARM64_INS_NGC, "NGCS" },
	};

	// NOTE: skip first NULL name in insn_name_maps
	int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);

	if (i == -1)
		// try again with 'special' insn that is not available in insn_name_maps
		i = name2id(insn_name_maps2, ARR_SIZE(insn_name_maps2), name);

	return (i != -1)? i : ARM64_REG_INVALID;
}