merge with option branch
diff --git a/MCInst.c b/MCInst.c
index e63e55c..f911257 100644
--- a/MCInst.c
+++ b/MCInst.c
@@ -18,6 +18,7 @@
inst->size = 0;
}
+// NOTE: this will free @Op argument
void MCInst_insert(MCInst *inst, int index, MCOperand *Op)
{
int i;
@@ -28,6 +29,8 @@
inst->Operands[index] = *Op;
inst->size++;
+
+ free(Op);
}
void MCInst_setOpcode(MCInst *inst, unsigned Op)
@@ -60,6 +63,7 @@
return inst->size;
}
+// NOTE: this will free @Op argument
int MCInst_addOperand(MCInst *inst, MCOperand *Op)
{
if (inst->size == ARR_SIZE(inst->Operands))
diff --git a/bindings/python/__init__.py b/bindings/python/__init__.py
index 0aa23fc..5cbebaf 100644
--- a/bindings/python/__init__.py
+++ b/bindings/python/__init__.py
@@ -1 +1 @@
-from capstone import cs, cs_disasm_quick, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_MODE_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_SYNTAX_ATT, CS_MODE_BIG_ENDIAN
+from capstone import cs, cs_disasm_quick, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_OPT_SYNTAX_ATT, CS_MODE_BIG_ENDIAN
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 83c299d..56cfaa4 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -1 +1 @@
-from capstone import cs, cs_disasm_quick, cs_version, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_MODE_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_SYNTAX_ATT, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
+from capstone import cs, cs_disasm_quick, cs_version, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_OPT_SYNTAX_ATT, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
diff --git a/bindings/python/capstone/capstone.py b/bindings/python/capstone/capstone.py
index 1c20bbc..84e65fc 100644
--- a/bindings/python/capstone/capstone.py
+++ b/bindings/python/capstone/capstone.py
@@ -14,8 +14,6 @@
'CS_MODE_LITTLE_ENDIAN',
'CS_MODE_BIG_ENDIAN',
- 'CS_MODE_SYNTAX_INTEL',
- 'CS_MODE_SYNTAX_ATT',
'CS_MODE_16',
'CS_MODE_32',
'CS_MODE_64',
@@ -24,6 +22,10 @@
'CS_MODE_MICRO',
'CS_MODE_N64',
+ 'CS_OPT_SYNTAX',
+ 'CS_OPT_SYNTAX_INTEL',
+ 'CS_OPT_SYNTAX_ATT',
+
'CS_ERR_OK',
'CS_ERR_MEM',
'CS_ERR_ARCH',
@@ -32,7 +34,7 @@
'CS_ERR_MODE',
]
-# capstone C interface
+# Capstone C interface
# architectures
CS_ARCH_ARM = 0
CS_ARCH_ARM64 = 1
@@ -41,7 +43,6 @@
# disasm mode
CS_MODE_LITTLE_ENDIAN = 0 # little-endian mode (default mode)
-CS_MODE_SYNTAX_INTEL = 0 # Intel X86 asm syntax (default for CS_ARCH_X86)
CS_MODE_ARM = 0 # ARM mode
CS_MODE_16 = (1 << 1) # 16-bit mode (for X86, Mips)
CS_MODE_32 = (1 << 2) # 32-bit mode (for X86, Mips)
@@ -49,10 +50,16 @@
CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_N64 = (1 << 5) # Nintendo-64 mode (MIPS architecture)
-CS_MODE_SYNTAX_ATT = (1 << 30) # X86 ATT asm syntax (for CS_ARCH_X86 only)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
-# capstone error type
+# Capstone option type
+CS_OPT_SYNTAX = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)
+
+# Capstone option value
+CS_OPT_SYNTAX_INTEL = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)
+CS_OPT_SYNTAX_ATT = 2 # ATT asm syntax (CS_ARCH_X86 arch)
+
+# Capstone error type
CS_ERR_OK = 0 # No error: everything was fine
CS_ERR_MEM = 1 # Out-Of-Memory error
CS_ERR_ARCH = 2 # Unsupported architecture
@@ -149,7 +156,8 @@
_setup_prototype(_cs, "cs_op_count", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint)
_setup_prototype(_cs, "cs_op_index", ctypes.c_int, ctypes.c_size_t, ctypes.POINTER(_cs_insn), ctypes.c_uint, ctypes.c_uint)
_setup_prototype(_cs, "cs_version", None, ctypes.POINTER(ctypes.c_int), ctypes.POINTER(ctypes.c_int))
-_setup_prototype(_cs, "cs_errno", ctypes.c_int, ctypes.c_int64)
+_setup_prototype(_cs, "cs_errno", ctypes.c_int, ctypes.c_size_t)
+_setup_prototype(_cs, "cs_option", ctypes.c_int, ctypes.c_size_t, ctypes.c_int, ctypes.c_size_t)
def cs_version():
@@ -170,10 +178,11 @@
if res > 0:
for i in xrange(res):
yield all_insn[i]
+
+ _cs.cs_free(all_insn)
else:
yield []
- _cs.cs_free(all_insn)
_cs.cs_close(csh)
@@ -259,6 +268,9 @@
if self.csh:
_cs.cs_close(self.csh)
+ def option(self, opt_type, opt_value):
+ return _cs.cs_option(self.csh, opt_type, opt_value)
+
def disasm(self, code, offset, count = 0):
if self.csh is None:
raise ValueError("Error: Failed to initialize!")
diff --git a/bindings/python/test.py b/bindings/python/test.py
index 19a9d11..766619e 100755
--- a/bindings/python/test.py
+++ b/bindings/python/test.py
@@ -16,17 +16,17 @@
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
- (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
- (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
- (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0, 0),
+ (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0, 0),
+ (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0, 0),
+ (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0, 0),
)
@@ -48,7 +48,7 @@
### Test class cs
def test_class():
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, opt_type, opt_value) in all_tests:
print('*' * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
@@ -56,6 +56,10 @@
try:
md = cs(arch, mode)
+
+ if opt_type != 0:
+ md.option(opt_type, opt_value)
+
all_ins = list(md.disasm(code, 0x1000))
for insn in all_ins:
print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py
index b36f7d0..acb18e3 100755
--- a/bindings/python/test_detail.py
+++ b/bindings/python/test_detail.py
@@ -16,17 +16,17 @@
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
- (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
- (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
- (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
- (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
- (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0, 0),
+ (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0, 0),
+ (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0, 0),
+ (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0, 0),
+ (CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0, 0),
)
@@ -52,13 +52,18 @@
print
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, opt_type, opt_value) in all_tests:
print('*' * 40)
print("Platform: %s" %comment)
print("Disasm:")
try:
md = cs(arch, mode)
+
+ if opt_type != 0:
+ md.option(opt_type, opt_value)
+
+
for insn in md.disasm(code, 0x1000):
print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \
%(insn.address, insn.mnemonic, insn.op_str, insn.id, \
diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py
index a3ec0b2..ed307e5 100755
--- a/bindings/python/test_x86.py
+++ b/bindings/python/test_x86.py
@@ -10,10 +10,10 @@
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
all_tests = (
- (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32 (AT&T syntax)"),
- (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
- (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
+ (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT),
+ (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0, 0),
+ (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0, 0),
)
def to_hex(s):
@@ -102,13 +102,17 @@
print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.value.mem.disp)))
- for (arch, mode, code, comment) in all_tests:
+ for (arch, mode, code, comment, opt_type, opt_value) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
md = cs(arch, mode)
+
+ if opt_type != 0:
+ md.option(opt_type, opt_value)
+
last = None
for insn in md.disasm(code, 0x1000):
print_insn_detail(mode, insn)
diff --git a/cs.c b/cs.c
index 5e1e68f..461e63b 100644
--- a/cs.c
+++ b/cs.c
@@ -70,10 +70,8 @@
switch (ud->arch) {
case CS_ARCH_X86:
- if (ud->mode & CS_MODE_SYNTAX_ATT)
- ud->printer = X86_ATT_printInst;
- else
- ud->printer = X86_Intel_printInst;
+ // by default, we use Intel syntax
+ ud->printer = X86_Intel_printInst;
ud->printer_info = NULL;
ud->disasm = X86_getInstruction;
ud->reg_name = X86_reg_name;
@@ -198,6 +196,34 @@
insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0';
}
+cs_err cs_option(csh ud, cs_opt_type type, size_t value)
+{
+ cs_struct *handle = (cs_struct *)(uintptr_t)ud;
+ if (!handle)
+ return CS_ERR_CSH;
+
+ switch (handle->arch) {
+ default:
+ break;
+ case CS_ARCH_X86:
+ if (type & CS_OPT_SYNTAX) {
+ switch(value) {
+ default:
+ break;
+ case CS_OPT_SYNTAX_INTEL:
+ handle->printer = X86_Intel_printInst;
+ break;
+ case CS_OPT_SYNTAX_ATT:
+ handle->printer = X86_ATT_printInst;
+ break;
+ }
+ }
+ break;
+ }
+
+ return CS_ERR_OK;
+}
+
size_t cs_disasm(csh ud, unsigned char *buffer, size_t size, uint64_t offset, size_t count, cs_insn *insn)
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
diff --git a/include/capstone.h b/include/capstone.h
index a2f5a44..f04af71 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -26,7 +26,6 @@
// Mode type
typedef enum cs_mode {
CS_MODE_LITTLE_ENDIAN = 0, // little endian mode (default mode)
- CS_MODE_SYNTAX_INTEL = 0, // Intel X86 asm syntax (CS_ARCH_X86 architecture)
CS_MODE_ARM = 0, // 32-bit ARM
CS_MODE_16 = 1 << 1, // 16-bit mode
CS_MODE_32 = 1 << 2, // 32-bit mode
@@ -34,11 +33,22 @@
CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
- CS_MODE_SYNTAX_ATT = 1 << 30, // ATT asm syntax (CS_ARCH_X86 architecture)
CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
} cs_mode;
+// Option type
+typedef enum cs_opt_type {
+ CS_OPT_SYNTAX = 1, // Asssembly syntax option
+} cs_opt_type;
+
+// Option value
+typedef enum cs_opt_value {
+ CS_OPT_SYNTAX_INTEL = 1, // X86 Intel asm syntax (CS_OPT_SYNTAX)
+ CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX)
+} cs_opt_value;
+
+
#include "arm.h"
#include "arm64.h"
#include "mips.h"
@@ -125,6 +135,18 @@
cs_err cs_close(csh handle);
/*
+ Set option for disassembling
+
+ @handle: handle returned by cs_open()
+ @type: type of option to be set
+ @value: option value for corresponding , which can be OR by several cs_opt enums
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+cs_err cs_option(csh handle, cs_opt_type type, size_t value);
+
+/*
Report the last error number when some API function fail.
Like glibc's errno, cs_errno might not retain its old value once accessed.
diff --git a/tests/test.c b/tests/test.c
index d6ab076..721ce8f 100644
--- a/tests/test.c
+++ b/tests/test.c
@@ -13,6 +13,8 @@
unsigned char *code;
size_t size;
char *comment;
+ cs_opt_type opt_type;
+ cs_opt_value opt_value;
};
static void print_string_hex(unsigned char *str, int len)
@@ -54,10 +56,12 @@
},
{
.arch = CS_ARCH_X86,
- .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .mode = CS_MODE_32,
.code = (unsigned char*)X86_CODE32,
.size = sizeof(X86_CODE32) - 1,
- .comment = "X86 32bit (ATT syntax)"
+ .comment = "X86 32bit (ATT syntax)",
+ .opt_type = CS_OPT_SYNTAX,
+ .opt_value = CS_OPT_SYNTAX_ATT,
},
{
.arch = CS_ARCH_X86,
@@ -137,6 +141,9 @@
return;
}
+ if (platforms[i].opt_type)
+ cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
+
//size_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
size_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
if (count) {
diff --git a/tests/test_detail.c b/tests/test_detail.c
index 48bddfa..3963db6 100644
--- a/tests/test_detail.c
+++ b/tests/test_detail.c
@@ -13,6 +13,8 @@
unsigned char *code;
size_t size;
char *comment;
+ cs_opt_type opt_type;
+ cs_opt_value opt_value;
};
static void print_string_hex(unsigned char *str, int len)
@@ -59,10 +61,12 @@
},
{
.arch = CS_ARCH_X86,
- .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .mode = CS_MODE_32,
.code = (unsigned char *)X86_CODE32,
.size = sizeof(X86_CODE32) - 1,
- .comment = "X86 32bit (ATT syntax)"
+ .comment = "X86 32bit (ATT syntax)",
+ .opt_type = CS_OPT_SYNTAX,
+ .opt_value = CS_OPT_SYNTAX_ATT,
},
{
.arch = CS_ARCH_X86,
@@ -139,6 +143,9 @@
if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
return;
+ if (platforms[i].opt_type)
+ cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
+
//size_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, all_insn);
size_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
if (count) {
diff --git a/tests/test_x86.c b/tests/test_x86.c
index 9b085bd..e766248 100644
--- a/tests/test_x86.c
+++ b/tests/test_x86.c
@@ -15,6 +15,8 @@
unsigned char *code;
size_t size;
char *comment;
+ cs_opt_type opt_type;
+ cs_opt_value opt_value;
};
static void print_string_hex(char *comment, unsigned char *str, int len)
@@ -131,10 +133,12 @@
},
{
.arch = CS_ARCH_X86,
- .mode = CS_MODE_32 + CS_MODE_SYNTAX_ATT,
+ .mode = CS_MODE_32,
.code = (unsigned char *)X86_CODE32,
.size = sizeof(X86_CODE32) - 1,
- .comment = "X86 32 (AT&T syntax)"
+ .comment = "X86 32 (AT&T syntax)",
+ .opt_type = CS_OPT_SYNTAX,
+ .opt_value = CS_OPT_SYNTAX_ATT,
},
{
.arch = CS_ARCH_X86,
@@ -161,6 +165,9 @@
if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
return;
+ if (platforms[i].opt_type)
+ cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
+
//size_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
size_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
if (count) {