arm64: the left-over fix of the last commit
diff --git a/arch/AArch64/mapping.c b/arch/AArch64/mapping.c
index dff0de9..d4eb255 100644
--- a/arch/AArch64/mapping.c
+++ b/arch/AArch64/mapping.c
@@ -17,9 +17,9 @@
//=========
{ ARM64_REG_NZCV, "nzcv"},
{ ARM64_REG_WSP, "wsp"},
- { ARM64_REG_WZR, "wzr"},
+ { ARM64_REG_WZR, "wzr"}, // dummy data for array mapping order only
{ ARM64_REG_SP, "sp"},
- { ARM64_REG_XZR, "xzr"},
+ { ARM64_REG_XZR, "xzr"}, // dummy data for array mapping order only
{ ARM64_REG_B0, "b0"},
{ ARM64_REG_B1, "b1"},
{ ARM64_REG_B2, "b2"},
@@ -242,198 +242,6 @@
{ ARM64_REG_X28, "x28"},
{ ARM64_REG_X29, "x29"},
{ ARM64_REG_X30, "x30"},
- { ARM64_REG_D0_D1, "d0_d1"},
- { ARM64_REG_D1_D2, "d1_d2"},
- { ARM64_REG_D2_D3, "d2_d3"},
- { ARM64_REG_D3_D4, "d3_d4"},
- { ARM64_REG_D4_D5, "d4_d5"},
- { ARM64_REG_D5_D6, "d5_d6"},
- { ARM64_REG_D6_D7, "d6_d7"},
- { ARM64_REG_D7_D8, "d7_d8"},
- { ARM64_REG_D8_D9, "d8_d9"},
- { ARM64_REG_D9_D10, "d9_d10"},
- { ARM64_REG_D10_D11, "d10_d11"},
- { ARM64_REG_D11_D12, "d11_d12"},
- { ARM64_REG_D12_D13, "d12_d13"},
- { ARM64_REG_D13_D14, "d13_d14"},
- { ARM64_REG_D14_D15, "d14_d15"},
- { ARM64_REG_D15_D16, "d15_d16"},
- { ARM64_REG_D16_D17, "d16_d17"},
- { ARM64_REG_D17_D18, "d17_d18"},
- { ARM64_REG_D18_D19, "d18_d19"},
- { ARM64_REG_D19_D20, "d19_d20"},
- { ARM64_REG_D20_D21, "d20_d21"},
- { ARM64_REG_D21_D22, "d21_d22"},
- { ARM64_REG_D22_D23, "d22_d23"},
- { ARM64_REG_D23_D24, "d23_d24"},
- { ARM64_REG_D24_D25, "d24_d25"},
- { ARM64_REG_D25_D26, "d25_d26"},
- { ARM64_REG_D26_D27, "d26_d27"},
- { ARM64_REG_D27_D28, "d27_d28"},
- { ARM64_REG_D28_D29, "d28_d29"},
- { ARM64_REG_D29_D30, "d29_d30"},
- { ARM64_REG_D30_D31, "d30_d31"},
- { ARM64_REG_D31_D0, "d31_d0"},
- { ARM64_REG_Q0_Q1, "q0_q1"},
- { ARM64_REG_Q1_Q2, "q1_q2"},
- { ARM64_REG_Q2_Q3, "q2_q3"},
- { ARM64_REG_Q3_Q4, "q3_q4"},
- { ARM64_REG_Q4_Q5, "q4_q5"},
- { ARM64_REG_Q5_Q6, "q5_q6"},
- { ARM64_REG_Q6_Q7, "q6_q7"},
- { ARM64_REG_Q7_Q8, "q7_q8"},
- { ARM64_REG_Q8_Q9, "q8_q9"},
- { ARM64_REG_Q9_Q10, "q9_q10"},
- { ARM64_REG_Q10_Q11, "q10_q11"},
- { ARM64_REG_Q11_Q12, "q11_q12"},
- { ARM64_REG_Q12_Q13, "q12_q13"},
- { ARM64_REG_Q13_Q14, "q13_q14"},
- { ARM64_REG_Q14_Q15, "q14_q15"},
- { ARM64_REG_Q15_Q16, "q15_q16"},
- { ARM64_REG_Q16_Q17, "q16_q17"},
- { ARM64_REG_Q17_Q18, "q17_q18"},
- { ARM64_REG_Q18_Q19, "q18_q19"},
- { ARM64_REG_Q19_Q20, "q19_q20"},
- { ARM64_REG_Q20_Q21, "q20_q21"},
- { ARM64_REG_Q21_Q22, "q21_q22"},
- { ARM64_REG_Q22_Q23, "q22_q23"},
- { ARM64_REG_Q23_Q24, "q23_q24"},
- { ARM64_REG_Q24_Q25, "q24_q25"},
- { ARM64_REG_Q25_Q26, "q25_q26"},
- { ARM64_REG_Q26_Q27, "q26_q27"},
- { ARM64_REG_Q27_Q28, "q27_q28"},
- { ARM64_REG_Q28_Q29, "q28_q29"},
- { ARM64_REG_Q29_Q30, "q29_q30"},
- { ARM64_REG_Q30_Q31, "q30_q31"},
- { ARM64_REG_Q31_Q0, "q31_q0"},
- { ARM64_REG_D0_D1_D2, "d0_d1_d2"},
- { ARM64_REG_D1_D2_D3, "d1_d2_d3"},
- { ARM64_REG_D2_D3_D4, "d2_d3_d4"},
- { ARM64_REG_D3_D4_D5, "d3_d4_d5"},
- { ARM64_REG_D4_D5_D6, "d4_d5_d6"},
- { ARM64_REG_D5_D6_D7, "d5_d6_d7"},
- { ARM64_REG_D6_D7_D8, "d6_d7_d8"},
- { ARM64_REG_D7_D8_D9, "d7_d8_d9"},
- { ARM64_REG_D8_D9_D10, "d8_d9_d10"},
- { ARM64_REG_D9_D10_D11, "d9_d10_d11"},
- { ARM64_REG_D10_D11_D12, "d10_d11_d12"},
- { ARM64_REG_D11_D12_D13, "d11_d12_d13"},
- { ARM64_REG_D12_D13_D14, "d12_d13_d14"},
- { ARM64_REG_D13_D14_D15, "d13_d14_d15"},
- { ARM64_REG_D14_D15_D16, "d14_d15_d16"},
- { ARM64_REG_D15_D16_D17, "d15_d16_d17"},
- { ARM64_REG_D16_D17_D18, "d16_d17_d18"},
- { ARM64_REG_D17_D18_D19, "d17_d18_d19"},
- { ARM64_REG_D18_D19_D20, "d18_d19_d20"},
- { ARM64_REG_D19_D20_D21, "d19_d20_d21"},
- { ARM64_REG_D20_D21_D22, "d20_d21_d22"},
- { ARM64_REG_D21_D22_D23, "d21_d22_d23"},
- { ARM64_REG_D22_D23_D24, "d22_d23_d24"},
- { ARM64_REG_D23_D24_D25, "d23_d24_d25"},
- { ARM64_REG_D24_D25_D26, "d24_d25_d26"},
- { ARM64_REG_D25_D26_D27, "d25_d26_d27"},
- { ARM64_REG_D26_D27_D28, "d26_d27_d28"},
- { ARM64_REG_D27_D28_D29, "d27_d28_d29"},
- { ARM64_REG_D28_D29_D30, "d28_d29_d30"},
- { ARM64_REG_D29_D30_D31, "d29_d30_d31"},
- { ARM64_REG_D30_D31_D0, "d30_d31_d0"},
- { ARM64_REG_D31_D0_D1, "d31_d0_d1"},
- { ARM64_REG_Q0_Q1_Q2, "q0_q1_q2"},
- { ARM64_REG_Q1_Q2_Q3, "q1_q2_q3"},
- { ARM64_REG_Q2_Q3_Q4, "q2_q3_q4"},
- { ARM64_REG_Q3_Q4_Q5, "q3_q4_q5"},
- { ARM64_REG_Q4_Q5_Q6, "q4_q5_q6"},
- { ARM64_REG_Q5_Q6_Q7, "q5_q6_q7"},
- { ARM64_REG_Q6_Q7_Q8, "q6_q7_q8"},
- { ARM64_REG_Q7_Q8_Q9, "q7_q8_q9"},
- { ARM64_REG_Q8_Q9_Q10, "q8_q9_q10"},
- { ARM64_REG_Q9_Q10_Q11, "q9_q10_q11"},
- { ARM64_REG_Q10_Q11_Q12, "q10_q11_q12"},
- { ARM64_REG_Q11_Q12_Q13, "q11_q12_q13"},
- { ARM64_REG_Q12_Q13_Q14, "q12_q13_q14"},
- { ARM64_REG_Q13_Q14_Q15, "q13_q14_q15"},
- { ARM64_REG_Q14_Q15_Q16, "q14_q15_q16"},
- { ARM64_REG_Q15_Q16_Q17, "q15_q16_q17"},
- { ARM64_REG_Q16_Q17_Q18, "q16_q17_q18"},
- { ARM64_REG_Q17_Q18_Q19, "q17_q18_q19"},
- { ARM64_REG_Q18_Q19_Q20, "q18_q19_q20"},
- { ARM64_REG_Q19_Q20_Q21, "q19_q20_q21"},
- { ARM64_REG_Q20_Q21_Q22, "q20_q21_q22"},
- { ARM64_REG_Q21_Q22_Q23, "q21_q22_q23"},
- { ARM64_REG_Q22_Q23_Q24, "q22_q23_q24"},
- { ARM64_REG_Q23_Q24_Q25, "q23_q24_q25"},
- { ARM64_REG_Q24_Q25_Q26, "q24_q25_q26"},
- { ARM64_REG_Q25_Q26_Q27, "q25_q26_q27"},
- { ARM64_REG_Q26_Q27_Q28, "q26_q27_q28"},
- { ARM64_REG_Q27_Q28_Q29, "q27_q28_q29"},
- { ARM64_REG_Q28_Q29_Q30, "q28_q29_q30"},
- { ARM64_REG_Q29_Q30_Q31, "q29_q30_q31"},
- { ARM64_REG_Q30_Q31_Q0, "q30_q31_q0"},
- { ARM64_REG_Q31_Q0_Q1, "q31_q0_q1"},
- { ARM64_REG_D0_D1_D2_D3, "d0_d1_d2_d3"},
- { ARM64_REG_D1_D2_D3_D4, "d1_d2_d3_d4"},
- { ARM64_REG_D2_D3_D4_D5, "d2_d3_d4_d5"},
- { ARM64_REG_D3_D4_D5_D6, "d3_d4_d5_d6"},
- { ARM64_REG_D4_D5_D6_D7, "d4_d5_d6_d7"},
- { ARM64_REG_D5_D6_D7_D8, "d5_d6_d7_d8"},
- { ARM64_REG_D6_D7_D8_D9, "d6_d7_d8_d9"},
- { ARM64_REG_D7_D8_D9_D10, "d7_d8_d9_d10"},
- { ARM64_REG_D8_D9_D10_D11, "d8_d9_d10_d11"},
- { ARM64_REG_D9_D10_D11_D12, "d9_d10_d11_d12"},
- { ARM64_REG_D10_D11_D12_D13, "d10_d11_d12_d13"},
- { ARM64_REG_D11_D12_D13_D14, "d11_d12_d13_d14"},
- { ARM64_REG_D12_D13_D14_D15, "d12_d13_d14_d15"},
- { ARM64_REG_D13_D14_D15_D16, "d13_d14_d15_d16"},
- { ARM64_REG_D14_D15_D16_D17, "d14_d15_d16_d17"},
- { ARM64_REG_D15_D16_D17_D18, "d15_d16_d17_d18"},
- { ARM64_REG_D16_D17_D18_D19, "d16_d17_d18_d19"},
- { ARM64_REG_D17_D18_D19_D20, "d17_d18_d19_d20"},
- { ARM64_REG_D18_D19_D20_D21, "d18_d19_d20_d21"},
- { ARM64_REG_D19_D20_D21_D22, "d19_d20_d21_d22"},
- { ARM64_REG_D20_D21_D22_D23, "d20_d21_d22_d23"},
- { ARM64_REG_D21_D22_D23_D24, "d21_d22_d23_d24"},
- { ARM64_REG_D22_D23_D24_D25, "d22_d23_d24_d25"},
- { ARM64_REG_D23_D24_D25_D26, "d23_d24_d25_d26"},
- { ARM64_REG_D24_D25_D26_D27, "d24_d25_d26_d27"},
- { ARM64_REG_D25_D26_D27_D28, "d25_d26_d27_d28"},
- { ARM64_REG_D26_D27_D28_D29, "d26_d27_d28_d29"},
- { ARM64_REG_D27_D28_D29_D30, "d27_d28_d29_d30"},
- { ARM64_REG_D28_D29_D30_D31, "d28_d29_d30_d31"},
- { ARM64_REG_D29_D30_D31_D0, "d29_d30_d31_d0"},
- { ARM64_REG_D30_D31_D0_D1, "d30_d31_d0_d1"},
- { ARM64_REG_D31_D0_D1_D2, "d31_d0_d1_d2"},
- { ARM64_REG_Q0_Q1_Q2_Q3, "q0_q1_q2_q3"},
- { ARM64_REG_Q1_Q2_Q3_Q4, "q1_q2_q3_q4"},
- { ARM64_REG_Q2_Q3_Q4_Q5, "q2_q3_q4_q5"},
- { ARM64_REG_Q3_Q4_Q5_Q6, "q3_q4_q5_q6"},
- { ARM64_REG_Q4_Q5_Q6_Q7, "q4_q5_q6_q7"},
- { ARM64_REG_Q5_Q6_Q7_Q8, "q5_q6_q7_q8"},
- { ARM64_REG_Q6_Q7_Q8_Q9, "q6_q7_q8_q9"},
- { ARM64_REG_Q7_Q8_Q9_Q10, "q7_q8_q9_q10"},
- { ARM64_REG_Q8_Q9_Q10_Q11, "q8_q9_q10_q11"},
- { ARM64_REG_Q9_Q10_Q11_Q12, "q9_q10_q11_q12"},
- { ARM64_REG_Q10_Q11_Q12_Q13, "q10_q11_q12_q13"},
- { ARM64_REG_Q11_Q12_Q13_Q14, "q11_q12_q13_q14"},
- { ARM64_REG_Q12_Q13_Q14_Q15, "q12_q13_q14_q15"},
- { ARM64_REG_Q13_Q14_Q15_Q16, "q13_q14_q15_q16"},
- { ARM64_REG_Q14_Q15_Q16_Q17, "q14_q15_q16_q17"},
- { ARM64_REG_Q15_Q16_Q17_Q18, "q15_q16_q17_q18"},
- { ARM64_REG_Q16_Q17_Q18_Q19, "q16_q17_q18_q19"},
- { ARM64_REG_Q17_Q18_Q19_Q20, "q17_q18_q19_q20"},
- { ARM64_REG_Q18_Q19_Q20_Q21, "q18_q19_q20_q21"},
- { ARM64_REG_Q19_Q20_Q21_Q22, "q19_q20_q21_q22"},
- { ARM64_REG_Q20_Q21_Q22_Q23, "q20_q21_q22_q23"},
- { ARM64_REG_Q21_Q22_Q23_Q24, "q21_q22_q23_q24"},
- { ARM64_REG_Q22_Q23_Q24_Q25, "q22_q23_q24_q25"},
- { ARM64_REG_Q23_Q24_Q25_Q26, "q23_q24_q25_q26"},
- { ARM64_REG_Q24_Q25_Q26_Q27, "q24_q25_q26_q27"},
- { ARM64_REG_Q25_Q26_Q27_Q28, "q25_q26_q27_q28"},
- { ARM64_REG_Q26_Q27_Q28_Q29, "q26_q27_q28_q29"},
- { ARM64_REG_Q27_Q28_Q29_Q30, "q27_q28_q29_q30"},
- { ARM64_REG_Q28_Q29_Q30_Q31, "q28_q29_q30_q31"},
- { ARM64_REG_Q29_Q30_Q31_Q0, "q29_q30_q31_q0"},
- { ARM64_REG_Q30_Q31_Q0_Q1, "q30_q31_q0_q1"},
- { ARM64_REG_Q31_Q0_Q1_Q2, "q31_q0_q1_q2"},
};
const char *AArch64_reg_name(csh handle, unsigned int reg)