commit ec58a02c6daeb5696c4c097fa02df89c679f2f97
author Nguyen Anh Quynh <aquynh@gmail.com> Thu Nov 13 11:42:38 2014 +0800
committer Nguyen Anh Quynh <aquynh@gmail.com> Thu Nov 13 11:42:38 2014 +0800
tree 0851d23310e88b59c5038a2fad0ec32a6842d85c
parent 952da90e5b98fcb42e153d19e400c17e3b4a50d5

python: update Mips modes to CS_MODE_MIPS32 & CS_MODE_MIPS64

bindings/python/test_lite.py

diff --git a/bindings/python/test_lite.py b/bindings/python/test_lite.py
index 0e04262..6f592e1 100755
--- a/bindings/python/test_lite.py
+++ b/bindings/python/test_lite.py
@@ -28,8 +28,8 @@
         (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0),
         (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0),
         (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
-        (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
-        (CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
+        (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
+        (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
         (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
         (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
         (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),