add diet compile option (CAPSTONE_DIET option in config.mk). This reduces binary size by around 40%
diff --git a/Makefile b/Makefile
index 8e69e7f..40b0281 100644
--- a/Makefile
+++ b/Makefile
@@ -126,15 +126,28 @@
VERSION=$(shell echo `grep -e PKG_MAJOR -e PKG_MINOR CONFIG | grep -v = | awk '{print $$3}'` | awk '{print $$1"."$$2}')
-.PHONY: all clean install uninstall
+.PHONY: all clean install uninstall diet
all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
$(MAKE) -C tests
$(INSTALL_DATA) lib$(LIBNAME).$(EXT) tests
-$(LIBRARY): $(LIBOBJ)
+$(LIBRARY): diet $(LIBOBJ)
$(CC) $(LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+# generate include/diet.h
+diet:
+ @echo "#ifndef CAPSTONE_DIET_H" > include/diet.h
+ @echo "#define CAPSTONE_DIET_H" >> include/diet.h
+ @echo "" >> include/diet.h
+ @echo "// File auto-generated by Makefile for Capstone framework. DO NOT MODIFY!" >> include/diet.h
+ @echo "" >> include/diet.h
+ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
+ @echo "#define CAPSTONE_DIET" >> include/diet.h
+ @echo "" >> include/diet.h
+endif
+ @echo "#endif" >> include/diet.h
+
$(ARCHIVE): $(LIBOBJ)
rm -f $(ARCHIVE)
$(AR) q $(ARCHIVE) $(LIBOBJ)
diff --git a/SStream.c b/SStream.c
index 5d9dda1..380a1f6 100644
--- a/SStream.c
+++ b/SStream.c
@@ -16,12 +16,14 @@
void SStream_concat(SStream *ss, const char *fmt, ...)
{
+#ifndef CAPSTONE_DIET
va_list ap;
va_start(ap, fmt);
int ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
va_end(ap);
ss->index += ret;
+#endif
}
/*
diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc
index 87d6ae9..0de6bf8 100644
--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@@ -5587,6 +5587,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0,
/* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0,
@@ -5994,13 +5995,16 @@
/* 2804 */ 'd', 'r', 'p', 's', 0,
/* 2809 */ 'e', 'r', 'e', 't', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 4095)-1);
+#endif
// Fragment 0 encoded into 8 bits for 159 unique commands.
@@ -8523,6 +8527,7 @@
{
// assert(RegNo && RegNo < 420 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
/* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
@@ -8854,6 +8859,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index e2563d5..3af4a2e 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -12,6 +12,7 @@
#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"
+#ifndef CAPSTONE_DIET
static name_map reg_name_maps[] = {
{ ARM64_REG_INVALID, NULL },
//=========
@@ -243,2724 +244,16265 @@
{ ARM64_REG_X29, "x29"},
{ ARM64_REG_X30, "x30"},
};
+#endif
const char *AArch64_reg_name(csh handle, unsigned int reg)
{
+#ifndef CAPSTONE_DIET
if (reg >= ARM64_REG_MAX)
return NULL;
return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
}
static insn_map insns[] = {
- { 0, 0, { 0 }, { 0 }, { 0 }, 0, 0 }, // dummy item
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
- { AArch64_ABS16b, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS2d, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS2s, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS4h, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS4s, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS8b, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABS8h, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ABSdd, ARM64_INS_ABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADCSwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADCSxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADCwww, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADCxxx, ARM64_INS_ADC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_16B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_2S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_4H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_4S, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_8B, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDP_8H, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDPvv_D_2D, ARM64_INS_ADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDSwww_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSwww_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_sxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_sxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_sxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_uxtb, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_uxth, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxw_uxtw, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxx_asr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxx_lsl, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxx_lsr, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxx_sxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDSxxx_uxtx, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDV_1b16b, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDV_1b8b, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDV_1h4h, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDV_1h8h, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDV_1s4s, ARM64_INS_ADDV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDddd, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_16B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_2D, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_2S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_4H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_4S, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_8B, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDvvv_8H, ARM64_INS_ADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDwww_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_sxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_sxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_sxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_uxtb, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_uxth, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxw_uxtw, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxx_asr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxx_lsl, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxx_lsr, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxx_sxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADDxxx_uxtx, ARM64_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADRPxi, ARM64_INS_ADRP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ADRxi, ARM64_INS_ADR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_AESD, ARM64_INS_AESD, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_AESE, ARM64_INS_AESE, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_AESIMC, ARM64_INS_AESIMC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_AESMC, ARM64_INS_AESMC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ANDSwwi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSwww_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSwww_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSwww_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSwww_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSxxi, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSxxx_asr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSxxx_lsl, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSxxx_lsr, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDSxxx_ror, ARM64_INS_AND, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_ANDvvv_16B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ANDvvv_8B, ARM64_INS_AND, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ANDwwi, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDwww_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDwww_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDwww_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDwww_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDxxi, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDxxx_asr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDxxx_lsl, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDxxx_lsr, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ANDxxx_ror, ARM64_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ASRVwww, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ASRVxxx, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ASRwwi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ASRxxi, ARM64_INS_ASR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ATix, ARM64_INS_AT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFIwwii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFIxxii, ARM64_INS_BFI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFMwwii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFMxxii, ARM64_INS_BFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFXILwwii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BFXILxxii, ARM64_INS_BFXIL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICSwww_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSwww_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSwww_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSwww_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSxxx_asr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSxxx_lsl, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSxxx_lsr, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICSxxx_ror, ARM64_INS_BIC, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_BICvi_lsl_2S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICvi_lsl_4H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICvi_lsl_4S, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICvi_lsl_8H, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICvvv_16B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICvvv_8B, ARM64_INS_BIC, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BICwww_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICwww_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICwww_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICwww_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICxxx_asr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICxxx_lsl, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICxxx_lsr, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BICxxx_ror, ARM64_INS_BIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_BIFvvv_16B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BIFvvv_8B, ARM64_INS_BIF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BITvvv_16B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BITvvv_8B, ARM64_INS_BIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BLRx, ARM64_INS_BLR, { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 1 },
- { AArch64_BLimm, ARM64_INS_BL, { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 0 },
- { AArch64_BRKi, ARM64_INS_BRK, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_BRx, ARM64_INS_BR, { 0 }, { 0 }, { 0 }, 1, 1 },
- { AArch64_BSLvvv_16B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_BSLvvv_8B, ARM64_INS_BSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_Bcc, ARM64_INS_B, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_Bimm, ARM64_INS_B, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_CBNZw, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_CBNZx, ARM64_INS_CBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_CBZw, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_CBZx, ARM64_INS_CBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_CCMNwi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMNww, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMNxi, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMNxx, ARM64_INS_CCMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMPwi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMPww, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMPxi, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CCMPxx, ARM64_INS_CCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CLREXi, ARM64_INS_CLREX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CLS16b, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLS2s, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLS4h, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLS4s, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLS8b, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLS8h, ARM64_INS_CLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLSww, ARM64_INS_CLS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CLSxx, ARM64_INS_CLS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CLZ16b, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZ2s, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZ4h, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZ4s, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZ8b, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZ8h, ARM64_INS_CLZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CLZww, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CLZxx, ARM64_INS_CLZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CMEQddd, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQddi, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvi_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_16B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_2D, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_2S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_4H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_4S, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_8B, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMEQvvv_8H, ARM64_INS_CMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEddd, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEddi, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvi_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_16B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_2D, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_2S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_4H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_4S, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_8B, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGEvvv_8H, ARM64_INS_CMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTddd, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTddi, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvi_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_16B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_2D, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_2S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_4H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_4S, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_8B, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMGTvvv_8H, ARM64_INS_CMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIddd, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_16B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_2D, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_2S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_4H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_4S, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_8B, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHIvvv_8H, ARM64_INS_CMHI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSddd, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_16B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_2D, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_2S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_4H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_4S, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_8B, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMHSvvv_8H, ARM64_INS_CMHS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEddi, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_16B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_2D, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_2S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_4H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_4S, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_8B, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLEvvi_8H, ARM64_INS_CMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTddi, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_16B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_2D, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_2S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_4H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_4S, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_8B, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMLTvvi_8H, ARM64_INS_CMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMNww_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNww_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_sxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_sxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_sxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_uxtb, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_uxth, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxw_uxtw, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxx_asr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxx_lsl, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxx_lsr, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxx_sxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMNxx_uxtx, ARM64_INS_CMN, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPww_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_sxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_sxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_sxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_uxtb, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_uxth, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxw_uxtw, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxx_asr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxx_lsl, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxx_lsr, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxx_sxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMPxx_uxtx, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_CMTSTddd, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_16B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_2D, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_2S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_4H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_4S, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_8B, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CMTSTvvv_8H, ARM64_INS_CMTST, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CNT16b, ARM64_INS_CNT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CNT8b, ARM64_INS_CNT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_CRC32B_www, ARM64_INS_CRC32B, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32CB_www, ARM64_INS_CRC32CB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32CH_www, ARM64_INS_CRC32CH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32CW_www, ARM64_INS_CRC32CW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32H_www, ARM64_INS_CRC32H, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32W_www, ARM64_INS_CRC32W, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CRC32X_wwx, ARM64_INS_CRC32X, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSELwwwc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSELxxxc, ARM64_INS_CSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSINCwwwc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSINCxxxc, ARM64_INS_CSINC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSINVwwwc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSINVxxxc, ARM64_INS_CSINV, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSNEGwwwc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_CSNEGxxxc, ARM64_INS_CSNEG, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_DCPS1i, ARM64_INS_DCPS1, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_DCPS2i, ARM64_INS_DCPS2, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_DCPS3i, ARM64_INS_DCPS3, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_DCix, ARM64_INS_DC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_DMBi, ARM64_INS_DMB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_DRPS, ARM64_INS_DRPS, { 0 }, { 0 }, { 0 }, 1, 1 },
- { AArch64_DSBi, ARM64_INS_DSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_DUP16b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP2d, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP2s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP4h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP4s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP8b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUP8h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT16b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT2d, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT2s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT4h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT4s, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT8b, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPELT8h, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPbv_B, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPdv_D, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPhv_H, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_DUPsv_S, ARM64_INS_DUP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_EONwww_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONwww_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONwww_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONwww_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONxxx_asr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONxxx_lsl, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONxxx_lsr, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EONxxx_ror, ARM64_INS_EON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORvvv_16B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_EORvvv_8B, ARM64_INS_EOR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_EORwwi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORwww_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORwww_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORwww_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORwww_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORxxi, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORxxx_asr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORxxx_lsl, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORxxx_lsr, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EORxxx_ror, ARM64_INS_EOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ERET, ARM64_INS_ERET, { 0 }, { 0 }, { 0 }, 1, 1 },
- { AArch64_EXTRwwwi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EXTRxxxi, ARM64_INS_EXTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_EXTvvvi_16b, ARM64_INS_EXT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_EXTvvvi_8b, ARM64_INS_EXT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABDddd, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABDsss, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABDvvv_2D, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABDvvv_2S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABDvvv_4S, ARM64_INS_FABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABS2d, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABS2s, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABS4s, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FABSdd, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FABSss, ARM64_INS_FABS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FACGEddd, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGEsss, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGEvvv_2D, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGEvvv_2S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGEvvv_4S, ARM64_INS_FACGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGTddd, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGTsss, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGTvvv_2D, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGTvvv_2S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FACGTvvv_4S, ARM64_INS_FACGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDP_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDP_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDP_4S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDPvv_D_2D, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDPvv_S_2S, ARM64_INS_FADDP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDddd, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FADDsss, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FADDvvv_2D, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDvvv_2S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FADDvvv_4S, ARM64_INS_FADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCCMPEdd, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCCMPEss, ARM64_INS_FCCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCCMPdd, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCCMPss, ARM64_INS_FCCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMEQZddi, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQZssi, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQddd, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQsss, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEZddi, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEZssi, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEddd, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEsss, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTZddi, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTZssi, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTddd, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTsss, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLEZddi, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLEZssi, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLTZddi, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLTZssi, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCMPdd_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPdd_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPdi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPdi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPsi_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPsi_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPss_quiet, ARM64_INS_FCMP, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCMPss_sig, ARM64_INS_FCMPE, { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCSELdddc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCSELsssc, ARM64_INS_FCSEL, { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTAS_2d, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAS_2s, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAS_4s, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTASdd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTASss, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTASwd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTASws, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTASxd, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTASxs, ARM64_INS_FCVTAS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTAU_2d, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAU_2s, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAU_4s, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAUdd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAUss, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTAUwd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTAUws, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTAUxd, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTAUxs, ARM64_INS_FCVTAU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTL2s2d, ARM64_INS_FCVTL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTL4h4s, ARM64_INS_FCVTL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTL4s2d, ARM64_INS_FCVTL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTL8h4s, ARM64_INS_FCVTL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMS_2d, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMS_2s, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMS_4s, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMSdd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMSss, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMSwd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMSws, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMSxd, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMSxs, ARM64_INS_FCVTMS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMU_2d, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMU_2s, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMU_4s, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMUdd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMUss, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTMUwd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMUws, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMUxd, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTMUxs, ARM64_INS_FCVTMU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTN2d2s, ARM64_INS_FCVTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTN2d4s, ARM64_INS_FCVTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTN4s4h, ARM64_INS_FCVTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTN4s8h, ARM64_INS_FCVTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNS_2d, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNS_2s, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNS_4s, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNSdd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNSss, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNSwd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNSws, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNSxd, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNSxs, ARM64_INS_FCVTNS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNU_2d, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNU_2s, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNU_4s, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNUdd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNUss, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTNUwd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNUws, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNUxd, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTNUxs, ARM64_INS_FCVTNU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPS_2d, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPS_2s, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPS_4s, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPSdd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPSss, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPSwd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPSws, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPSxd, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPSxs, ARM64_INS_FCVTPS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPU_2d, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPU_2s, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPU_4s, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPUdd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPUss, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTPUwd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPUws, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPUxd, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTPUxs, ARM64_INS_FCVTPU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTXN, ARM64_INS_FCVTXN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTXN2d2s, ARM64_INS_FCVTXN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTXN2d4s, ARM64_INS_FCVTXN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZS_2d, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZS_2s, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZS_4s, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZS_Nddi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZS_Nssi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZSdd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZSss, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZSwd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSwdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSws, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSwsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSxd, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSxdi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSxs, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZSxsi, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZU_2d, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZU_2s, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZU_4s, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZU_Nddi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZU_Nssi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZUdd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZUss, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FCVTZUwd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUwdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUws, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUwsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUxd, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUxdi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUxs, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTZUxsi, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTdh, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTds, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVThd, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVThs, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTsd, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FCVTsh, ARM64_INS_FCVT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FDIVddd, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FDIVsss, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FDIVvvv_2D, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FDIVvvv_2S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FDIVvvv_4S, ARM64_INS_FDIV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMADDdddd, ARM64_INS_FMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMADDssss, ARM64_INS_FMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMAXNMPvv_D_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMPvv_S_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMV_1s4s, ARM64_INS_FMAXNMV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMddd, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMAXNMsss, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXPvv_D_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXPvv_S_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXV_1s4s, ARM64_INS_FMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXddd, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMAXsss, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMAXvvv_2D, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXvvv_2S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMAXvvv_4S, ARM64_INS_FMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMPvv_D_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMPvv_S_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMV_1s4s, ARM64_INS_FMINNMV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMddd, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMINNMsss, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINPvv_D_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINPvv_S_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINPvvv_2D, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINPvvv_2S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINPvvv_4S, ARM64_INS_FMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINV_1s4s, ARM64_INS_FMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINddd, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMINsss, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMINvvv_2D, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINvvv_2S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMINvvv_4S, ARM64_INS_FMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAddv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAssv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvve_2d2d, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvve_2s4s, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvve_4s4s, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvvv_2D, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvvv_2S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLAvvv_4S, ARM64_INS_FMLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSddv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSssv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvve_2d2d, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvve_2s4s, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvve_4s4s, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvvv_2D, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvvv_2S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMLSvvv_4S, ARM64_INS_FMLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMOVdd, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVdi, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVdx, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVsi, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVss, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVsw, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVvi_2D, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMOVvi_2S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMOVvi_4S, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMOVvx, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVws, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVxd, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMOVxv, ARM64_INS_FMOV, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMSUBdddd, ARM64_INS_FMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMSUBssss, ARM64_INS_FMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMULXddd, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXddv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXsss, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXssv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXve_2d2d, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXve_2s4s, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXve_4s4s, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXvvv_2D, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXvvv_2S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULXvvv_4S, ARM64_INS_FMULX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULddd, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMULddv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULsss, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FMULssv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULve_2d2d, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULve_2s4s, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULve_4s4s, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULvvv_2D, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULvvv_2S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FMULvvv_4S, ARM64_INS_FMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FNEG2d, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FNEG2s, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FNEG4s, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FNEGdd, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNEGss, ARM64_INS_FNEG, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMADDdddd, ARM64_INS_FNMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMADDssss, ARM64_INS_FNMADD, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMSUBdddd, ARM64_INS_FNMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMSUBssss, ARM64_INS_FNMSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMULddd, ARM64_INS_FNMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FNMULsss, ARM64_INS_FNMUL, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRECPE_2d, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPE_2s, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPE_4s, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPEdd, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPEss, ARM64_INS_FRECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPSddd, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPSsss, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPXdd, ARM64_INS_FRECPX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRECPXss, ARM64_INS_FRECPX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTA_2d, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTA_2s, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTA_4s, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTAdd, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTAss, ARM64_INS_FRINTA, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTI_2d, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTI_2s, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTI_4s, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTIdd, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTIss, ARM64_INS_FRINTI, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTM_2d, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTM_2s, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTM_4s, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTMdd, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTMss, ARM64_INS_FRINTM, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTN_2d, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTN_2s, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTN_4s, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTNdd, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTNss, ARM64_INS_FRINTN, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTP_2d, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTP_2s, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTP_4s, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTPdd, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTPss, ARM64_INS_FRINTP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTX_2d, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTX_2s, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTX_4s, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTXdd, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTXss, ARM64_INS_FRINTX, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTZ_2d, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTZ_2s, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTZ_4s, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRINTZdd, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRINTZss, ARM64_INS_FRINTZ, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FRSQRTE_2d, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTE_2s, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTE_4s, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTEdd, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTEss, ARM64_INS_FRSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTSddd, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTSsss, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSQRT_2d, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSQRT_2s, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSQRT_4s, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSQRTdd, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FSQRTss, ARM64_INS_FSQRT, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FSUBddd, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FSUBsss, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_FSUBvvv_2D, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSUBvvv_2S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_FSUBvvv_4S, ARM64_INS_FSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_HINTi, ARM64_INS_HINT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_HLTi, ARM64_INS_HLT, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_HVCi, ARM64_INS_HVC, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_ICi, ARM64_INS_IC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ICix, ARM64_INS_IC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_INSELb, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSELd, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSELh, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSELs, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSbw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSdx, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INShw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_INSsw, ARM64_INS_INS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ISBi, ARM64_INS_ISB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LD1LN_B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1LN_WB_S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_16B, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_1D, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_2D, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_2S, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_4H, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_4S, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_8B, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_8H, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_16B_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_16B_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_1D_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_1D_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_2D_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_2D_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_2S_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_2S_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_4H_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_4H_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_4S_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_4S_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_8B_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_8B_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_8H_fixed, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1R_WB_8H_register, ARM64_INS_LD1R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x2_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x3_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_16B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_16B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_1D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_1D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_2D_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_2D_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_2S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_2S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_4H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_4H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_4S_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_4S_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_8B_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_8B_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_8H_fixed, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4WB_8H_register, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_16B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_1D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_2D, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_2S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_4H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_4S, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_8B, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD1x4_8H, ARM64_INS_LD1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_D, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_D_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_D_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2LN_WB_S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_16B, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_1D, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_2D, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_2S, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_4H, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_4S, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_8B, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_8H, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_16B_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_16B_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_1D_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_1D_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_2D_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_2D_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_2S_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_2S_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_4H_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_4H_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_4S_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_4S_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_8B_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_8B_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_8H_fixed, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2R_WB_8H_register, ARM64_INS_LD2R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_16B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_16B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_2D_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_2D_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_2S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_2S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_4H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_4H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_4S_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_4S_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_8B_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_8B_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_8H_fixed, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2WB_8H_register, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_16B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_2D, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_2S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_4H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_4S, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_8B, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD2_8H, ARM64_INS_LD2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_D, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_D_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_D_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3LN_WB_S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_16B, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_1D, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_2D, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_2S, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_4H, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_4S, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_8B, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_8H, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_16B_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_16B_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_1D_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_1D_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_2D_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_2D_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_2S_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_2S_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_4H_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_4H_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_4S_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_4S_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_8B_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_8B_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_8H_fixed, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3R_WB_8H_register, ARM64_INS_LD3R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_16B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_16B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_2D_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_2D_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_2S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_2S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_4H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_4H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_4S_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_4S_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_8B_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_8B_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_8H_fixed, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3WB_8H_register, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_16B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_2D, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_2S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_4H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_4S, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_8B, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD3_8H, ARM64_INS_LD3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_D, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_D_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_D_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4LN_WB_S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_16B, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_1D, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_2D, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_2S, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_4H, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_4S, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_8B, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_8H, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_16B_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_16B_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_1D_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_1D_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_2D_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_2D_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_2S_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_2S_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_4H_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_4H_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_4S_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_4S_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_8B_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_8B_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_8H_fixed, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4R_WB_8H_register, ARM64_INS_LD4R, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_16B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_16B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_2D_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_2D_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_2S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_2S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_4H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_4H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_4S_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_4S_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_8B_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_8B_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_8H_fixed, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4WB_8H_register, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_16B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_2D, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_2S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_4H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_4S, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_8B, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LD4_8H, ARM64_INS_LD4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_LDAR_byte, ARM64_INS_LDARB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAR_dword, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAR_hword, ARM64_INS_LDARH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAR_word, ARM64_INS_LDAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXP_dword, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXP_word, ARM64_INS_LDAXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXR_byte, ARM64_INS_LDAXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXR_dword, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXR_hword, ARM64_INS_LDAXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDAXR_word, ARM64_INS_LDAXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDPSWx, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx_U, ARM64_INS_LDURSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx_U, ARM64_INS_LDURSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRSWx_lit, ARM64_INS_LDRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRd_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LDRq_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LDRs_lit, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LDRw_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDRx_lit, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDTRSBw, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDTRSBx, ARM64_INS_LDTRSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDTRSHw, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDTRSHx, ARM64_INS_LDTRSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDTRSWx, ARM64_INS_LDTRSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDURSWx, ARM64_INS_LDURSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXP_dword, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXP_word, ARM64_INS_LDXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXR_byte, ARM64_INS_LDXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXR_dword, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXR_hword, ARM64_INS_LDXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LDXR_word, ARM64_INS_LDXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_LDUR, ARM64_INS_LDURH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_PostInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_PreInd_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_STUR, ARM64_INS_STURH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_UnPriv_STR, ARM64_INS_STTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_LDUR, ARM64_INS_LDURB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_PostInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_PreInd_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_STUR, ARM64_INS_STURB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSFP128_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_LDUR, ARM64_INS_LDUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_PostInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_PreInd_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_STUR, ARM64_INS_STUR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair128_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSFPPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_LSLVwww, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSLVxxx, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSLwwi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSLxxi, ARM64_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair32_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_PostInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_PreInd_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSPair64_STR, ARM64_INS_STP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSRVwww, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSRVxxx, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSRwwi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_LSRxxi, ARM64_INS_LSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MADDwwww, ARM64_INS_MADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MADDxxxx, ARM64_INS_MADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MLAvve_2s4s, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvve_4h8h, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvve_4s4s, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvve_8h8h, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_16B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_2S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_4H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_4S, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_8B, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLAvvv_8H, ARM64_INS_MLA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvve_2s4s, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvve_4h8h, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvve_4s4s, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvve_8h8h, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_16B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_2S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_4H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_4S, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_8B, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MLSvvv_8H, ARM64_INS_MLS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIdi, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_16B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_2D, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_8B, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MOVKwii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MOVKxii, ARM64_INS_MOVK, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MOVNwii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MOVNxii, ARM64_INS_MOVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MOVZwii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MOVZxii, ARM64_INS_MOVZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MRSxi, ARM64_INS_MRS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MSRii, ARM64_INS_MSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MSRix, ARM64_INS_MSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MSUBwwww, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MSUBxxxx, ARM64_INS_MSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MULve_2s4s, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULve_4h8h, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULve_4s4s, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULve_8h8h, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_16B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_2S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_4H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_4S, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_8B, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MULvvv_8H, ARM64_INS_MUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_MVNww_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNww_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNww_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNww_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNxx_asr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNxx_lsl, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNxx_lsr, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_MVNxx_ror, ARM64_INS_MVN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_NEG16b, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG2d, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG2s, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG4h, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG4s, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG8b, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEG8h, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NEGdd, ARM64_INS_NEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NOT16b, ARM64_INS_NOT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_NOT8b, ARM64_INS_NOT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORNvvv_16B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORNvvv_8B, ARM64_INS_ORN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORNwww_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNwww_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNwww_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNwww_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNxxx_asr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNxxx_lsl, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNxxx_lsr, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORNxxx_ror, ARM64_INS_ORN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRvi_lsl_2S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRvi_lsl_4H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRvi_lsl_4S, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRvi_lsl_8H, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRvvv_16B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRvvv_8B, ARM64_INS_ORR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ORRwwi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRwww_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRwww_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRwww_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRwww_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRxxi, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRxxx_asr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRxxx_lsl, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRxxx_lsr, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_ORRxxx_ror, ARM64_INS_ORR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_PMULL2vvv_1q2d, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PMULLvvv_1q1d, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PMULvvv_16B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PMULvvv_8B, ARM64_INS_PMUL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_PRFM, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_PRFM_lit, ARM64_INS_PRFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_PRFUM, ARM64_INS_PRFUM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RBIT16b, ARM64_INS_RBIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RBIT8b, ARM64_INS_RBIT, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RBITww, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_RBITxx, ARM64_INS_RBIT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_RETx, ARM64_INS_RET, { 0 }, { 0 }, { 0 }, 1, 1 },
- { AArch64_REV16_16b, ARM64_INS_REV16, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV16_8b, ARM64_INS_REV16, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV16ww, ARM64_INS_REV16, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_REV16xx, ARM64_INS_REV16, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_REV32_16b, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV32_4h, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV32_8b, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV32_8h, ARM64_INS_REV32, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV32xx, ARM64_INS_REV32, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_REV64_16b, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV64_2s, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV64_4h, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV64_4s, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV64_8b, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REV64_8h, ARM64_INS_REV64, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_REVww, ARM64_INS_REV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_REVxx, ARM64_INS_REV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_RORVwww, ARM64_INS_ROR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_RORVxxx, ARM64_INS_ROR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABALvvv_2d2s, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABALvvv_4s4h, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABALvvv_8h8b, ARM64_INS_SABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_16B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_2S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_4H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_4S, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_8B, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABAvvv_8H, ARM64_INS_SABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_16B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_2S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_4H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_4S, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_8B, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SABDvvv_8H, ARM64_INS_SABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP16b8h, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP2s1d, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP4h2s, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP4s2d, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP8b4h, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADALP8h4s, ARM64_INS_SADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP16b8h, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP2s1d, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP4h2s, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP4s2d, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP8b4h, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLP8h4s, ARM64_INS_SADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLV_1d4s, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLV_1h16b, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLV_1h8b, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLV_1s4h, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLV_1s8h, ARM64_INS_SADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SBCSwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SBCSxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SBCwww, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBCxxx, ARM64_INS_SBC, { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFIZwwii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFIZxxii, ARM64_INS_SBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFMwwii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFMxxii, ARM64_INS_SBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFXwwii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SBFXxxii, ARM64_INS_SBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SCVTF_2d, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTF_2s, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTF_4s, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTF_Nddi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTF_Nssi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTFdd, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTFdw, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFdwi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFdx, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFdxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFss, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SCVTFsw, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFswi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFsx, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SCVTFsxi, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_SDIVwww, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SDIVxxx, ARM64_INS_SDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SHA1C, ARM64_INS_SHA1C, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA1H, ARM64_INS_SHA1H, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA1M, ARM64_INS_SHA1M, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA1P, ARM64_INS_SHA1P, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA1SU0, ARM64_INS_SHA1SU0, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA1SU1, ARM64_INS_SHA1SU1, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA256H, ARM64_INS_SHA256H, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA256H2, ARM64_INS_SHA256H2, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA256SU0, ARM64_INS_SHA256SU0, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHA256SU1, ARM64_INS_SHA256SU1, { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0 },
- { AArch64_SHADDvvv_16B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHADDvvv_2S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHADDvvv_4H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHADDvvv_4S, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHADDvvv_8B, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHADDvvv_8H, ARM64_INS_SHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL16b8h, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL2s2d, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL4h4s, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL4s2d, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL8b8h, ARM64_INS_SHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLL8h4s, ARM64_INS_SHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLddi, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_16B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_2D, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_2S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_4H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_4S, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_8B, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHLvvi_8H, ARM64_INS_SHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_16B, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_2S, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_4H, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_4S, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_8B, ARM64_INS_SHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHRNvvi_8H, ARM64_INS_SHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLI, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_16B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_2D, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_2S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_4H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_4S, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_8B, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SLIvvi_8H, ARM64_INS_SLI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMADDLxwwx, ARM64_INS_SMADDL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXV_1b16b, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXV_1b8b, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXV_1h4h, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXV_1h8h, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXV_1s4s, ARM64_INS_SMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_16B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_2S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_4H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_4S, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_8B, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMAXvvv_8H, ARM64_INS_SMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMCi, ARM64_INS_SMC, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_SMINPvvv_16B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINPvvv_2S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINPvvv_4H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINPvvv_4S, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINPvvv_8B, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINPvvv_8H, ARM64_INS_SMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINV_1b16b, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINV_1b8b, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINV_1h4h, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINV_1h8h, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINV_1s4s, ARM64_INS_SMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_16B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_2S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_4H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_4S, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_8B, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMINvvv_8H, ARM64_INS_SMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvve_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvve_2d4s, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvve_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvve_4s8h, ARM64_INS_SMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvve_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvve_2d4s, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvve_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvve_4s8h, ARM64_INS_SMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMOVwb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMOVwh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMOVxb, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMOVxh, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMOVxs, ARM64_INS_SMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SMULHxxx, ARM64_INS_SMULH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLve_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLve_2d4s, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLve_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLve_4s8h, ARM64_INS_SMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS16b, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS2d, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS2s, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS4h, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS4s, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS8b, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABS8h, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABSbb, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABSdd, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABShh, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQABSss, ARM64_INS_SQABS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDbbb, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDddd, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDhhh, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDsss, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_16B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_2D, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_2S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_4H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_4S, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_8B, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQADDvvv_8H, ARM64_INS_SQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALdss, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALdsv_2S, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALdsv_4S, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALshh, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALshv_4H, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALshv_8H, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvve_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvve_2d4s, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvve_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvve_4s8h, ARM64_INS_SQDMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLdss, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLdsv_2S, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLdsv_4S, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLshh, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLshv_4H, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLshv_8H, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvve_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvve_2d4s, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvve_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvve_4s8h, ARM64_INS_SQDMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHhhh, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHhhv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHhhv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHsss, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHssv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHssv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHve_2s4s, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHve_4h8h, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHve_4s4s, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHve_8h8h, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLdss, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLdsv_2S, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLdsv_4S, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLshh, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLshv_4H, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLshv_8H, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLve_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLve_2d4s, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLve_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLve_4s8h, ARM64_INS_SQDMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG16b, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG2d, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG2s, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG4h, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG4s, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG8b, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEG8h, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEGbb, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEGdd, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEGhh, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQNEGss, ARM64_INS_SQNEG, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHhhh, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHhhv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHhhv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHsss, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHssv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHssv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHve_2s4s, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHve_4h8h, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHve_4s4s, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHve_8h8h, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLbbb, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLddd, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLhhh, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLsss, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNbhi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNhsi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNsdi, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRUNbhi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRUNhsi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQRSHRUNsdi, ARM64_INS_SQRSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUbbi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUddi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUhhi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUssi, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLbbb, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLbbi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLddd, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLddi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLhhh, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLhhi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLssi, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLsss, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNbhi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNhsi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNsdi, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRUNbhi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRUNhsi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSHRUNsdi, ARM64_INS_SQSHRUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBbbb, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBddd, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBhhh, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBsss, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN2d2s, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN2d4s, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN4s4h, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN4s8h, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN8h16b, ARM64_INS_SQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTN8h8b, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTNbh, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTNhs, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTNsd, ARM64_INS_SQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN2d2s, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN2d4s, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN4s4h, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN4s8h, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN8h16b, ARM64_INS_SQXTUN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUN8h8b, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUNbh, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUNhs, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SQXTUNsd, ARM64_INS_SQXTUN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRI, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_16B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_2D, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_2S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_4H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_4S, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_8B, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRIvvi_8H, ARM64_INS_SRI, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLddd, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRddi, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRA, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLddd, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_16B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_2D, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_2S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_4H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_4S, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_8B, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHLvvv_8H, ARM64_INS_SSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRddi, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_16B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_2D, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_2S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_4H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_4S, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_8B, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSHRvvi_8H, ARM64_INS_SSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRA, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_16B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_2D, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_2S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_4H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_4S, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_8B, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSRAvvi_8H, ARM64_INS_SSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1LN_WB_S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x2_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x3_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_16B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_16B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_1D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_1D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_2D_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_2D_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_2S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_2S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_4H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_4H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_4S_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_4S_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_8B_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_8B_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_8H_fixed, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4WB_8H_register, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_16B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_1D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_2D, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_2S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_4H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_4S, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_8B, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST1x4_8H, ARM64_INS_ST1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_D, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_D_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_D_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2LN_WB_S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_16B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_16B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_2D_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_2D_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_2S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_2S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_4H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_4H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_4S_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_4S_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_8B_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_8B_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_8H_fixed, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2WB_8H_register, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_16B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_2D, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_2S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_4H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_4S, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_8B, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST2_8H, ARM64_INS_ST2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_D, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_D_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_D_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3LN_WB_S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_16B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_16B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_2D_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_2D_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_2S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_2S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_4H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_4H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_4S_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_4S_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_8B_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_8B_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_8H_fixed, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3WB_8H_register, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_16B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_2D, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_2S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_4H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_4S, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_8B, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST3_8H, ARM64_INS_ST3, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_D, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_D_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_D_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4LN_WB_S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_16B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_16B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_2D_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_2D_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_2S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_2S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_4H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_4H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_4S_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_4S_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_8B_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_8B_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_8H_fixed, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4WB_8H_register, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_16B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_2D, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_2S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_4H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_4S, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_8B, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ST4_8H, ARM64_INS_ST4, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_STLR_byte, ARM64_INS_STLRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLR_dword, ARM64_INS_STLR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLR_hword, ARM64_INS_STLRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLR_word, ARM64_INS_STLR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXP_dword, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXP_word, ARM64_INS_STLXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXR_byte, ARM64_INS_STLXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXR_dword, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXR_hword, ARM64_INS_STLXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STLXR_word, ARM64_INS_STLXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXP_dword, ARM64_INS_STXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXP_word, ARM64_INS_STXP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXR_byte, ARM64_INS_STXRB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXR_dword, ARM64_INS_STXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXR_hword, ARM64_INS_STXRH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_STXR_word, ARM64_INS_STXR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBSwww_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSwww_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_sxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_sxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_sxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_uxtb, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_uxth, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxw_uxtw, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxx_asr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxx_lsl, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxx_lsr, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxx_sxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBSxxx_uxtx, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBddd, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_16B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_2D, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_2S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_4H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_4S, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_8B, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBvvv_8H, ARM64_INS_SUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBwww_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_sxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_sxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_sxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_uxtb, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_uxth, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxw_uxtw, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxx_asr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxx_lsl, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxx_lsr, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxx_sxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUBxxx_uxtx, ARM64_INS_SUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SUQADD16b, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD2d, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD2s, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD4h, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD4s, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD8b, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADD8h, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADDbb, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADDdd, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADDhh, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SUQADDss, ARM64_INS_SUQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_SVCi, ARM64_INS_SVC, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_SXTBww, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SXTBxw, ARM64_INS_SXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SXTHww, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SXTHxw, ARM64_INS_SXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SXTWxw, ARM64_INS_SXTW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SYSLxicci, ARM64_INS_SYSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_SYSiccix, ARM64_INS_SYS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_TBL1_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL1_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL2_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL2_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL3_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL3_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL4_16b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBL4_8b, ARM64_INS_TBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBNZwii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_TBNZxii, ARM64_INS_TBNZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_TBX1_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX1_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX2_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX2_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX3_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX3_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX4_16b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBX4_8b, ARM64_INS_TBX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TBZwii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_TBZxii, ARM64_INS_TBZ, { 0 }, { 0 }, { 0 }, 1, 0 },
- { AArch64_TLBIi, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_TLBIix, ARM64_INS_TLBI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_TRN1vvv_16b, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_2d, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_2s, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_4h, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_4s, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_8b, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN1vvv_8h, ARM64_INS_TRN1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_16b, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_2d, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_2s, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_4h, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_4s, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_8b, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TRN2vvv_8h, ARM64_INS_TRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_TSTww_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTww_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTww_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTww_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTxx_asr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTxx_lsl, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTxx_lsr, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_TSTxx_ror, ARM64_INS_TST, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 },
- { AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABALvvv_2d2s, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABALvvv_4s4h, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABALvvv_8h8b, ARM64_INS_UABAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_16B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_2S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_4H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_4S, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_8B, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABAvvv_8H, ARM64_INS_UABA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_16B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_2S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_4H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_4S, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_8B, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UABDvvv_8H, ARM64_INS_UABD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP16b8h, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP2s1d, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP4h2s, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP4s2d, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP8b4h, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADALP8h4s, ARM64_INS_UADALP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP16b8h, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP2s1d, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP4h2s, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP4s2d, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP8b4h, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLP8h4s, ARM64_INS_UADDLP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLV_1d4s, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLV_1h16b, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLV_1h8b, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLV_1s4h, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLV_1s8h, ARM64_INS_UADDLV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UBFIZwwii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UBFIZxxii, ARM64_INS_UBFIZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UBFMwwii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UBFMxxii, ARM64_INS_UBFM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UBFXwwii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UBFXxxii, ARM64_INS_UBFX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UCVTF_2d, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTF_2s, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTF_4s, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTF_Nddi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTF_Nssi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTFdd, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTFdw, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFdwi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFdx, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFdxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFss, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UCVTFsw, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFswi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFsx, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UCVTFsxi, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 },
- { AArch64_UDIVwww, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UDIVxxx, ARM64_INS_UDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UHADDvvv_16B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHADDvvv_2S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHADDvvv_4H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHADDvvv_4S, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHADDvvv_8B, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHADDvvv_8H, ARM64_INS_UHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMADDLxwwx, ARM64_INS_UMADDL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXV_1b16b, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXV_1b8b, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXV_1h4h, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXV_1h8h, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXV_1s4s, ARM64_INS_UMAXV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_16B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_2S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_4H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_4S, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_8B, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMAXvvv_8H, ARM64_INS_UMAX, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_16B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_2S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_4H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_4S, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_8B, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINPvvv_8H, ARM64_INS_UMINP, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINV_1b16b, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINV_1b8b, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINV_1h4h, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINV_1h8h, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINV_1s4s, ARM64_INS_UMINV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_16B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_2S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_4H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_4S, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_8B, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMINvvv_8H, ARM64_INS_UMIN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvve_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvve_2d4s, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvve_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvve_4s8h, ARM64_INS_UMLAL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvve_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvve_2d4s, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvve_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvve_4s8h, ARM64_INS_UMLSL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMOVwb, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMOVwh, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMOVws, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMOVxd, ARM64_INS_UMOV, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UMULHxxx, ARM64_INS_UMULH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLve_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLve_2d4s, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLve_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLve_4s8h, ARM64_INS_UMULL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDbbb, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDddd, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDhhh, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDsss, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_16B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_2D, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_2S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_4H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_4S, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_8B, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQADDvvv_8H, ARM64_INS_UQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLbbb, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLddd, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLhhh, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLsss, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNbhi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNhsi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNsdi, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLbbb, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLbbi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLddd, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLddi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLhhh, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLhhi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLssi, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLsss, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNbhi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNhsi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNsdi, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBbbb, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBddd, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBhhh, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBsss, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN2d2s, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN2d4s, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN4s4h, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN4s8h, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN8h16b, ARM64_INS_UQXTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTN8h8b, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTNbh, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTNhs, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UQXTNsd, ARM64_INS_UQXTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URECPE2s, ARM64_INS_URECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URECPE4s, ARM64_INS_URECPE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_16B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_2S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_4H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_4S, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_8B, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URHADDvvv_8H, ARM64_INS_URHADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLddd, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_16B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_2D, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_2S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_4H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_4S, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_8B, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHLvvv_8H, ARM64_INS_URSHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRddi, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_16B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_2D, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_2S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_4H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_4S, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_8B, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSHRvvi_8H, ARM64_INS_URSHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSQRTE2s, ARM64_INS_URSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSQRTE4s, ARM64_INS_URSQRTE, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRA, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_16B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_2D, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_2S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_4H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_4S, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_8B, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_URSRAvvi_8H, ARM64_INS_URSRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_16B, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_2S, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_4H, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_4S, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_8B, ARM64_INS_USHLL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLLvvi_8H, ARM64_INS_USHLL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLddd, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_16B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_2D, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_2S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_4H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_4S, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_8B, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHLvvv_8H, ARM64_INS_USHL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRddi, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_16B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_2D, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_2S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_4H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_4S, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_8B, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USHRvvi_8H, ARM64_INS_USHR, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD16b, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD2d, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD2s, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD4h, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD4s, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD8b, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADD8h, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADDbb, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADDdd, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADDhh, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USQADDss, ARM64_INS_USQADD, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRA, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_16B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_2D, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_2S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_4H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_4S, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_8B, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USRAvvi_8H, ARM64_INS_USRA, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UXTBww, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UXTBxw, ARM64_INS_UXTB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UXTHww, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UXTHxw, ARM64_INS_UXTH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { AArch64_UZP1vvv_16b, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_2d, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_2s, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_4h, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_4s, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_8b, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP1vvv_8h, ARM64_INS_UZP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_16b, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_2d, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_2s, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_4h, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_4s, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_8b, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_UZP2vvv_8h, ARM64_INS_UZP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN2d2s, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN2d4s, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN4s4h, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN4s8h, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN8h16b, ARM64_INS_XTN2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_XTN8h8b, ARM64_INS_XTN, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_16b, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_2d, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_2s, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_4h, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_4s, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_8b, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP1vvv_8h, ARM64_INS_ZIP1, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_16b, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_2d, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_2s, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_4h, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_4s, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_8b, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
- { AArch64_ZIP2vvv_8h, ARM64_INS_ZIP2, { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 },
+ {
+ AArch64_ABS16b, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS2d, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS2s, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS4h, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS4s, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS8b, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABS8h, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ABSdd, ARM64_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADCSwww, ARM64_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADCSxxx, ARM64_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADCwww, ARM64_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADCxxx, ARM64_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHN2vvv_16b8h, ARM64_INS_ADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHN2vvv_4s2d, ARM64_INS_ADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHN2vvv_8h4s, ARM64_INS_ADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHNvvv_2s2d, ARM64_INS_ADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHNvvv_4h4s, ARM64_INS_ADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDHNvvv_8b8h, ARM64_INS_ADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_16B, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_2D, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_2S, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_4H, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_4S, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_8B, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDP_8H, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDPvv_D_2D, ARM64_INS_ADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_asr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_lsl, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_lsr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_sxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_sxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_sxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_sxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_uxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_uxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_uxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSwww_uxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_sxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_sxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_sxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_uxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_uxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxw_uxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxx_asr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxx_lsl, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxx_lsr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxx_sxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDSxxx_uxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDV_1b16b, ARM64_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDV_1b8b, ARM64_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDV_1h4h, ARM64_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDV_1h8h, ARM64_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDV_1s4s, ARM64_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDddd, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_16B, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_2D, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_2S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_4H, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_4S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_8B, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDvvv_8H, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl0_S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl0_cmp, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl0_s, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl12_S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl12_cmp, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwwi_lsl12_s, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_asr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_lsl, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_lsr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_sxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_sxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_sxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_sxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_uxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_uxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_uxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDwww_uxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl0_S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl0_cmp, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl0_s, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl12_S, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl12_cmp, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxi_lsl12_s, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_sxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_sxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_sxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_uxtb, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_uxth, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxw_uxtw, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxx_asr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxx_lsl, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxx_lsr, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxx_sxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADDxxx_uxtx, ARM64_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADRPxi, ARM64_INS_ADRP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ADRxi, ARM64_INS_ADR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_AESD, ARM64_INS_AESD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_AESE, ARM64_INS_AESE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_AESIMC, ARM64_INS_AESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_AESMC, ARM64_INS_AESMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSwwi, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSwww_asr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSwww_lsl, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSwww_lsr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSwww_ror, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSxxi, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSxxx_asr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSxxx_lsl, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSxxx_lsr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDSxxx_ror, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDvvv_16B, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDvvv_8B, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDwwi, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDwww_asr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDwww_lsl, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDwww_lsr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDwww_ror, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDxxi, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDxxx_asr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDxxx_lsl, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDxxx_lsr, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ANDxxx_ror, ARM64_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ASRVwww, ARM64_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ASRVxxx, ARM64_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ASRwwi, ARM64_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ASRxxi, ARM64_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ATix, ARM64_INS_AT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFIwwii, ARM64_INS_BFI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFIxxii, ARM64_INS_BFI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFMwwii, ARM64_INS_BFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFMxxii, ARM64_INS_BFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFXILwwii, ARM64_INS_BFXIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BFXILxxii, ARM64_INS_BFXIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSwww_asr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSwww_lsl, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSwww_lsr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSwww_ror, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSxxx_asr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSxxx_lsl, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSxxx_lsr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICSxxx_ror, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvi_lsl_2S, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvi_lsl_4H, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvi_lsl_4S, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvi_lsl_8H, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvvv_16B, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICvvv_8B, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICwww_asr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICwww_lsl, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICwww_lsr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICwww_ror, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICxxx_asr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICxxx_lsl, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICxxx_lsr, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BICxxx_ror, ARM64_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BIFvvv_16B, ARM64_INS_BIF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BIFvvv_8B, ARM64_INS_BIF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BITvvv_16B, ARM64_INS_BIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BITvvv_8B, ARM64_INS_BIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BLRx, ARM64_INS_BLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ AArch64_BLimm, ARM64_INS_BL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_X30, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_BRKi, ARM64_INS_BRK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_BRx, ARM64_INS_BR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ AArch64_BSLvvv_16B, ARM64_INS_BSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_BSLvvv_8B, ARM64_INS_BSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_Bcc, ARM64_INS_B,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_Bimm, ARM64_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_CBNZw, ARM64_INS_CBNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_CBNZx, ARM64_INS_CBNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_CBZw, ARM64_INS_CBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_CBZx, ARM64_INS_CBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_CCMNwi, ARM64_INS_CCMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMNww, ARM64_INS_CCMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMNxi, ARM64_INS_CCMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMNxx, ARM64_INS_CCMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMPwi, ARM64_INS_CCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMPww, ARM64_INS_CCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMPxi, ARM64_INS_CCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CCMPxx, ARM64_INS_CCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLREXi, ARM64_INS_CLREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS16b, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS2s, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS4h, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS4s, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS8b, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLS8h, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLSww, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLSxx, ARM64_INS_CLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ16b, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ2s, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ4h, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ4s, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ8b, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZ8h, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZww, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CLZxx, ARM64_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQddd, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQddi, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_16B, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_2D, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_2S, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_4H, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_4S, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_8B, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvi_8H, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_16B, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_2D, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_2S, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_4H, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_4S, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_8B, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMEQvvv_8H, ARM64_INS_CMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEddd, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEddi, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_16B, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_2D, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_2S, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_4H, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_4S, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_8B, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvi_8H, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_16B, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_2D, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_2S, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_4H, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_4S, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_8B, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGEvvv_8H, ARM64_INS_CMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTddd, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTddi, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_16B, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_2D, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_2S, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_4H, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_4S, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_8B, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvi_8H, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_16B, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_2D, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_2S, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_4H, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_4S, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_8B, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMGTvvv_8H, ARM64_INS_CMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIddd, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_16B, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_2D, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_2S, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_4H, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_4S, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_8B, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHIvvv_8H, ARM64_INS_CMHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSddd, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_16B, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_2D, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_2S, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_4H, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_4S, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_8B, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMHSvvv_8H, ARM64_INS_CMHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEddi, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_16B, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_2D, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_2S, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_4H, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_4S, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_8B, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLEvvi_8H, ARM64_INS_CMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTddi, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_16B, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_2D, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_2S, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_4H, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_4S, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_8B, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMLTvvi_8H, ARM64_INS_CMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_asr, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_lsl, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_lsr, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_sxtb, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_sxth, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_sxtw, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_sxtx, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_uxtb, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_uxth, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_uxtw, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNww_uxtx, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_sxtb, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_sxth, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_sxtw, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_uxtb, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_uxth, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxw_uxtw, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxx_asr, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxx_lsl, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxx_lsr, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxx_sxtx, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMNxx_uxtx, ARM64_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_asr, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_lsl, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_lsr, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_sxtb, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_sxth, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_sxtw, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_sxtx, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_uxtb, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_uxth, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_uxtw, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPww_uxtx, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_sxtb, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_sxth, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_sxtw, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_uxtb, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_uxth, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxw_uxtw, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxx_asr, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxx_lsl, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxx_lsr, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxx_sxtx, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMPxx_uxtx, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTddd, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_16B, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_2D, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_2S, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_4H, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_4S, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_8B, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CMTSTvvv_8H, ARM64_INS_CMTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CNT16b, ARM64_INS_CNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CNT8b, ARM64_INS_CNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32B_www, ARM64_INS_CRC32B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32CB_www, ARM64_INS_CRC32CB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32CH_www, ARM64_INS_CRC32CH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32CW_www, ARM64_INS_CRC32CW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32CX_wwx, ARM64_INS_CRC32CX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32H_www, ARM64_INS_CRC32H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32W_www, ARM64_INS_CRC32W,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CRC32X_wwx, ARM64_INS_CRC32X,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSELwwwc, ARM64_INS_CSEL,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSELxxxc, ARM64_INS_CSEL,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSINCwwwc, ARM64_INS_CSINC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSINCxxxc, ARM64_INS_CSINC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSINVwwwc, ARM64_INS_CSINV,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSINVxxxc, ARM64_INS_CSINV,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSNEGwwwc, ARM64_INS_CSNEG,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_CSNEGxxxc, ARM64_INS_CSNEG,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DCPS1i, ARM64_INS_DCPS1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_DCPS2i, ARM64_INS_DCPS2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_DCPS3i, ARM64_INS_DCPS3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_DCix, ARM64_INS_DC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DMBi, ARM64_INS_DMB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DRPS, ARM64_INS_DRPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ AArch64_DSBi, ARM64_INS_DSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP16b, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP2d, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP2s, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP4h, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP4s, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP8b, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUP8h, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT16b, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT2d, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT2s, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT4h, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT4s, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT8b, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPELT8h, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPbv_B, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPdv_D, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPhv_H, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_DUPsv_S, ARM64_INS_DUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONwww_asr, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONwww_lsl, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONwww_lsr, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONwww_ror, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONxxx_asr, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONxxx_lsl, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONxxx_lsr, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EONxxx_ror, ARM64_INS_EON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORvvv_16B, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORvvv_8B, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORwwi, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORwww_asr, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORwww_lsl, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORwww_lsr, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORwww_ror, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORxxi, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORxxx_asr, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORxxx_lsl, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORxxx_lsr, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EORxxx_ror, ARM64_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ERET, ARM64_INS_ERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ AArch64_EXTRwwwi, ARM64_INS_EXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EXTRxxxi, ARM64_INS_EXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EXTvvvi_16b, ARM64_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_EXTvvvi_8b, ARM64_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABDddd, ARM64_INS_FABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABDsss, ARM64_INS_FABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABDvvv_2D, ARM64_INS_FABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABDvvv_2S, ARM64_INS_FABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABDvvv_4S, ARM64_INS_FABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABS2d, ARM64_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABS2s, ARM64_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABS4s, ARM64_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABSdd, ARM64_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FABSss, ARM64_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGEddd, ARM64_INS_FACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGEsss, ARM64_INS_FACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGEvvv_2D, ARM64_INS_FACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGEvvv_2S, ARM64_INS_FACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGEvvv_4S, ARM64_INS_FACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGTddd, ARM64_INS_FACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGTsss, ARM64_INS_FACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGTvvv_2D, ARM64_INS_FACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGTvvv_2S, ARM64_INS_FACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FACGTvvv_4S, ARM64_INS_FACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDP_2D, ARM64_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDP_2S, ARM64_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDP_4S, ARM64_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDPvv_D_2D, ARM64_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDPvv_S_2S, ARM64_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDddd, ARM64_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDsss, ARM64_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDvvv_2D, ARM64_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDvvv_2S, ARM64_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FADDvvv_4S, ARM64_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCCMPEdd, ARM64_INS_FCCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCCMPEss, ARM64_INS_FCCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCCMPdd, ARM64_INS_FCCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCCMPss, ARM64_INS_FCCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQZddi, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQZssi, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQddd, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQsss, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvi_2D, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvi_2S, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvi_4S, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvv_2D, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvv_2S, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMEQvvv_4S, ARM64_INS_FCMEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEZddi, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEZssi, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEddd, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEsss, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvi_2D, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvi_2S, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvi_4S, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvv_2D, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvv_2S, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGEvvv_4S, ARM64_INS_FCMGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTZddi, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTZssi, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTddd, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTsss, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvi_2D, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvi_2S, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvi_4S, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvv_2D, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvv_2S, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMGTvvv_4S, ARM64_INS_FCMGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLEZddi, ARM64_INS_FCMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLEZssi, ARM64_INS_FCMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLEvvi_2D, ARM64_INS_FCMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLEvvi_2S, ARM64_INS_FCMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLEvvi_4S, ARM64_INS_FCMLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLTZddi, ARM64_INS_FCMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLTZssi, ARM64_INS_FCMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLTvvi_2D, ARM64_INS_FCMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLTvvi_2S, ARM64_INS_FCMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMLTvvi_4S, ARM64_INS_FCMLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPdd_quiet, ARM64_INS_FCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPdd_sig, ARM64_INS_FCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPdi_quiet, ARM64_INS_FCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPdi_sig, ARM64_INS_FCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPsi_quiet, ARM64_INS_FCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPsi_sig, ARM64_INS_FCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPss_quiet, ARM64_INS_FCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCMPss_sig, ARM64_INS_FCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCSELdddc, ARM64_INS_FCSEL,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCSELsssc, ARM64_INS_FCSEL,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAS_2d, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAS_2s, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAS_4s, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASdd, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASss, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASwd, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASws, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASxd, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTASxs, ARM64_INS_FCVTAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAU_2d, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAU_2s, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAU_4s, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUdd, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUss, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUwd, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUws, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUxd, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTAUxs, ARM64_INS_FCVTAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTL2s2d, ARM64_INS_FCVTL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTL4h4s, ARM64_INS_FCVTL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTL4s2d, ARM64_INS_FCVTL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTL8h4s, ARM64_INS_FCVTL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMS_2d, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMS_2s, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMS_4s, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSdd, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSss, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSwd, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSws, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSxd, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMSxs, ARM64_INS_FCVTMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMU_2d, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMU_2s, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMU_4s, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUdd, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUss, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUwd, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUws, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUxd, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTMUxs, ARM64_INS_FCVTMU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTN2d2s, ARM64_INS_FCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTN2d4s, ARM64_INS_FCVTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTN4s4h, ARM64_INS_FCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTN4s8h, ARM64_INS_FCVTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNS_2d, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNS_2s, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNS_4s, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSdd, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSss, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSwd, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSws, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSxd, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNSxs, ARM64_INS_FCVTNS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNU_2d, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNU_2s, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNU_4s, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUdd, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUss, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUwd, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUws, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUxd, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTNUxs, ARM64_INS_FCVTNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPS_2d, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPS_2s, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPS_4s, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSdd, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSss, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSwd, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSws, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSxd, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPSxs, ARM64_INS_FCVTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPU_2d, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPU_2s, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPU_4s, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUdd, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUss, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUwd, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUws, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUxd, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTPUxs, ARM64_INS_FCVTPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTXN, ARM64_INS_FCVTXN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTXN2d2s, ARM64_INS_FCVTXN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTXN2d4s, ARM64_INS_FCVTXN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZS_2d, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZS_2s, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZS_4s, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZS_Nddi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZS_Nssi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSdd, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSss, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSwd, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSwdi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSws, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSwsi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSxd, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSxdi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSxs, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZSxsi, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZU_2d, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZU_2s, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZU_4s, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZU_Nddi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZU_Nssi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUdd, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUss, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUwd, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUwdi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUws, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUwsi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUxd, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUxdi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUxs, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTZUxsi, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTdh, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTds, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVThd, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVThs, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTsd, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FCVTsh, ARM64_INS_FCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FDIVddd, ARM64_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FDIVsss, ARM64_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FDIVvvv_2D, ARM64_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FDIVvvv_2S, ARM64_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FDIVvvv_4S, ARM64_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMADDdddd, ARM64_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMADDssss, ARM64_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMPvv_D_2D, ARM64_INS_FMAXNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMPvv_S_2S, ARM64_INS_FMAXNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMPvvv_2D, ARM64_INS_FMAXNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMPvvv_2S, ARM64_INS_FMAXNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMPvvv_4S, ARM64_INS_FMAXNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMV_1s4s, ARM64_INS_FMAXNMV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMddd, ARM64_INS_FMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMsss, ARM64_INS_FMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMvvv_2D, ARM64_INS_FMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMvvv_2S, ARM64_INS_FMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXNMvvv_4S, ARM64_INS_FMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXPvv_D_2D, ARM64_INS_FMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXPvv_S_2S, ARM64_INS_FMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXPvvv_2D, ARM64_INS_FMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXPvvv_2S, ARM64_INS_FMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXPvvv_4S, ARM64_INS_FMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXV_1s4s, ARM64_INS_FMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXddd, ARM64_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXsss, ARM64_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXvvv_2D, ARM64_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXvvv_2S, ARM64_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMAXvvv_4S, ARM64_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMPvv_D_2D, ARM64_INS_FMINNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMPvv_S_2S, ARM64_INS_FMINNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMPvvv_2D, ARM64_INS_FMINNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMPvvv_2S, ARM64_INS_FMINNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMPvvv_4S, ARM64_INS_FMINNMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMV_1s4s, ARM64_INS_FMINNMV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMddd, ARM64_INS_FMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMsss, ARM64_INS_FMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMvvv_2D, ARM64_INS_FMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMvvv_2S, ARM64_INS_FMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINNMvvv_4S, ARM64_INS_FMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINPvv_D_2D, ARM64_INS_FMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINPvv_S_2S, ARM64_INS_FMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINPvvv_2D, ARM64_INS_FMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINPvvv_2S, ARM64_INS_FMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINPvvv_4S, ARM64_INS_FMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINV_1s4s, ARM64_INS_FMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINddd, ARM64_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINsss, ARM64_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINvvv_2D, ARM64_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINvvv_2S, ARM64_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMINvvv_4S, ARM64_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAddv_2D, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAssv_4S, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvve_2d2d, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvve_2s4s, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvve_4s4s, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvvv_2D, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvvv_2S, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLAvvv_4S, ARM64_INS_FMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSddv_2D, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSssv_4S, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvve_2d2d, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvve_2s4s, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvve_4s4s, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvvv_2D, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvvv_2S, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMLSvvv_4S, ARM64_INS_FMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVdd, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVdi, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVdx, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVsi, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVss, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVsw, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVvi_2D, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVvi_2S, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVvi_4S, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVvx, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVws, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVxd, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMOVxv, ARM64_INS_FMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMSUBdddd, ARM64_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMSUBssss, ARM64_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXddd, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXddv_2D, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXsss, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXssv_4S, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXve_2d2d, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXve_2s4s, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXve_4s4s, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXvvv_2D, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXvvv_2S, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULXvvv_4S, ARM64_INS_FMULX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULddd, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULddv_2D, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULsss, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULssv_4S, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULve_2d2d, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULve_2s4s, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULve_4s4s, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULvvv_2D, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULvvv_2S, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FMULvvv_4S, ARM64_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNEG2d, ARM64_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNEG2s, ARM64_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNEG4s, ARM64_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNEGdd, ARM64_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNEGss, ARM64_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMADDdddd, ARM64_INS_FNMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMADDssss, ARM64_INS_FNMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMSUBdddd, ARM64_INS_FNMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMSUBssss, ARM64_INS_FNMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMULddd, ARM64_INS_FNMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FNMULsss, ARM64_INS_FNMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPE_2d, ARM64_INS_FRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPE_2s, ARM64_INS_FRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPE_4s, ARM64_INS_FRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPEdd, ARM64_INS_FRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPEss, ARM64_INS_FRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPSddd, ARM64_INS_FRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPSsss, ARM64_INS_FRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPSvvv_2D, ARM64_INS_FRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPSvvv_2S, ARM64_INS_FRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPSvvv_4S, ARM64_INS_FRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPXdd, ARM64_INS_FRECPX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRECPXss, ARM64_INS_FRECPX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTA_2d, ARM64_INS_FRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTA_2s, ARM64_INS_FRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTA_4s, ARM64_INS_FRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTAdd, ARM64_INS_FRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTAss, ARM64_INS_FRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTI_2d, ARM64_INS_FRINTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTI_2s, ARM64_INS_FRINTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTI_4s, ARM64_INS_FRINTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTIdd, ARM64_INS_FRINTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTIss, ARM64_INS_FRINTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTM_2d, ARM64_INS_FRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTM_2s, ARM64_INS_FRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTM_4s, ARM64_INS_FRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTMdd, ARM64_INS_FRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTMss, ARM64_INS_FRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTN_2d, ARM64_INS_FRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTN_2s, ARM64_INS_FRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTN_4s, ARM64_INS_FRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTNdd, ARM64_INS_FRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTNss, ARM64_INS_FRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTP_2d, ARM64_INS_FRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTP_2s, ARM64_INS_FRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTP_4s, ARM64_INS_FRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTPdd, ARM64_INS_FRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTPss, ARM64_INS_FRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTX_2d, ARM64_INS_FRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTX_2s, ARM64_INS_FRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTX_4s, ARM64_INS_FRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTXdd, ARM64_INS_FRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTXss, ARM64_INS_FRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTZ_2d, ARM64_INS_FRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTZ_2s, ARM64_INS_FRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTZ_4s, ARM64_INS_FRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTZdd, ARM64_INS_FRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRINTZss, ARM64_INS_FRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTE_2d, ARM64_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTE_2s, ARM64_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTE_4s, ARM64_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTEdd, ARM64_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTEss, ARM64_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTSddd, ARM64_INS_FRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTSsss, ARM64_INS_FRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTSvvv_2D, ARM64_INS_FRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTSvvv_2S, ARM64_INS_FRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FRSQRTSvvv_4S, ARM64_INS_FRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSQRT_2d, ARM64_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSQRT_2s, ARM64_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSQRT_4s, ARM64_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSQRTdd, ARM64_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSQRTss, ARM64_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSUBddd, ARM64_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSUBsss, ARM64_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSUBvvv_2D, ARM64_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSUBvvv_2S, ARM64_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_FSUBvvv_4S, ARM64_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_HINTi, ARM64_INS_HINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_HLTi, ARM64_INS_HLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_HVCi, ARM64_INS_HVC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_ICi, ARM64_INS_IC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ICix, ARM64_INS_IC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSELb, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSELd, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSELh, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSELs, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSbw, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSdx, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INShw, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_INSsw, ARM64_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ISBi, ARM64_INS_ISB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1LN_WB_S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_16B, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_1D, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_2D, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_2S, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_4H, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_4S, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_8B, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_8H, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_16B_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_16B_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_1D_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_1D_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_2D_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_2D_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_2S_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_2S_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_4H_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_4H_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_4S_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_4S_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_8B_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_8B_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_8H_fixed, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1R_WB_8H_register, ARM64_INS_LD1R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_16B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_16B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_1D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_1D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_2D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_2D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_2S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_2S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_4H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_4H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_4S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_4S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_8B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_8B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_8H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1WB_8H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_16B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_1D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_2D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_2S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_4H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_4S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_8B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1_8H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_16B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_16B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_1D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_1D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_2D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_2D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_2S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_2S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_4H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_4H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_4S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_4S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_8B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_8B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_8H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2WB_8H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_16B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_1D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_2D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_2S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_4H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_4S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_8B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x2_8H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_16B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_16B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_1D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_1D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_2D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_2D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_2S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_2S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_4H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_4H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_4S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_4S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_8B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_8B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_8H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3WB_8H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_16B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_1D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_2D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_2S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_4H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_4S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_8B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x3_8H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_16B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_16B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_1D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_1D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_2D_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_2D_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_2S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_2S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_4H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_4H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_4S_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_4S_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_8B_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_8B_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_8H_fixed, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4WB_8H_register, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_16B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_1D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_2D, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_2S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_4H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_4S, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_8B, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD1x4_8H, ARM64_INS_LD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_B, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_D, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_H, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_S, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_B_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_B_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_D_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_D_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_H_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_H_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_S_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2LN_WB_S_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_16B, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_1D, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_2D, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_2S, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_4H, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_4S, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_8B, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_8H, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_16B_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_16B_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_1D_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_1D_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_2D_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_2D_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_2S_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_2S_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_4H_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_4H_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_4S_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_4S_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_8B_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_8B_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_8H_fixed, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2R_WB_8H_register, ARM64_INS_LD2R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_16B_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_16B_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_2D_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_2D_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_2S_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_2S_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_4H_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_4H_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_4S_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_4S_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_8B_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_8B_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_8H_fixed, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2WB_8H_register, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_16B, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_2D, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_2S, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_4H, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_4S, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_8B, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD2_8H, ARM64_INS_LD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_B, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_D, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_H, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_S, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_B_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_B_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_D_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_D_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_H_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_H_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_S_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3LN_WB_S_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_16B, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_1D, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_2D, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_2S, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_4H, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_4S, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_8B, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_8H, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_16B_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_16B_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_1D_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_1D_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_2D_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_2D_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_2S_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_2S_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_4H_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_4H_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_4S_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_4S_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_8B_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_8B_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_8H_fixed, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3R_WB_8H_register, ARM64_INS_LD3R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_16B_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_16B_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_2D_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_2D_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_2S_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_2S_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_4H_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_4H_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_4S_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_4S_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_8B_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_8B_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_8H_fixed, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3WB_8H_register, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_16B, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_2D, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_2S, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_4H, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_4S, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_8B, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD3_8H, ARM64_INS_LD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_B, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_D, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_H, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_S, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_B_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_B_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_D_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_D_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_H_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_H_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_S_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4LN_WB_S_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_16B, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_1D, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_2D, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_2S, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_4H, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_4S, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_8B, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_8H, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_16B_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_16B_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_1D_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_1D_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_2D_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_2D_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_2S_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_2S_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_4H_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_4H_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_4S_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_4S_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_8B_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_8B_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_8H_fixed, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4R_WB_8H_register, ARM64_INS_LD4R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_16B_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_16B_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_2D_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_2D_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_2S_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_2S_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_4H_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_4H_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_4S_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_4S_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_8B_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_8B_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_8H_fixed, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4WB_8H_register, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_16B, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_2D, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_2S, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_4H, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_4S, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_8B, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LD4_8H, ARM64_INS_LD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAR_byte, ARM64_INS_LDARB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAR_dword, ARM64_INS_LDAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAR_hword, ARM64_INS_LDARH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAR_word, ARM64_INS_LDAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXP_dword, ARM64_INS_LDAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXP_word, ARM64_INS_LDAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXR_byte, ARM64_INS_LDAXRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXR_dword, ARM64_INS_LDAXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXR_hword, ARM64_INS_LDAXRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDAXR_word, ARM64_INS_LDAXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDPSWx, ARM64_INS_LDPSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDPSWx_PostInd, ARM64_INS_LDPSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDPSWx_PreInd, ARM64_INS_LDPSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw_PostInd, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw_PreInd, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw_U, ARM64_INS_LDURSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw_Wm_RegOffset, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBw_Xm_RegOffset, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx_PostInd, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx_PreInd, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx_U, ARM64_INS_LDURSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx_Wm_RegOffset, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSBx_Xm_RegOffset, ARM64_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw_PostInd, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw_PreInd, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw_U, ARM64_INS_LDURSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw_Wm_RegOffset, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHw_Xm_RegOffset, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx_PostInd, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx_PreInd, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx_U, ARM64_INS_LDURSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx_Wm_RegOffset, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSHx_Xm_RegOffset, ARM64_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx_PostInd, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx_PreInd, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx_Wm_RegOffset, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx_Xm_RegOffset, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRSWx_lit, ARM64_INS_LDRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRd_lit, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRq_lit, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRs_lit, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRw_lit, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDRx_lit, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDTRSBw, ARM64_INS_LDTRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDTRSBx, ARM64_INS_LDTRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDTRSHw, ARM64_INS_LDTRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDTRSHx, ARM64_INS_LDTRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDTRSWx, ARM64_INS_LDTRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDURSWx, ARM64_INS_LDURSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXP_dword, ARM64_INS_LDXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXP_word, ARM64_INS_LDXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXR_byte, ARM64_INS_LDXRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXR_dword, ARM64_INS_LDXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXR_hword, ARM64_INS_LDXRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LDXR_word, ARM64_INS_LDXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_LDR, ARM64_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_LDUR, ARM64_INS_LDURH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_PostInd_LDR, ARM64_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_PostInd_STR, ARM64_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_PreInd_LDR, ARM64_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_PreInd_STR, ARM64_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_STR, ARM64_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_STUR, ARM64_INS_STURH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_UnPriv_LDR, ARM64_INS_LDTRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_UnPriv_STR, ARM64_INS_STTRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_Wm_RegOffset_LDR, ARM64_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_Wm_RegOffset_STR, ARM64_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_Xm_RegOffset_LDR, ARM64_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS16_Xm_RegOffset_STR, ARM64_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_UnPriv_LDR, ARM64_INS_LDTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_UnPriv_STR, ARM64_INS_STTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS32_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_UnPriv_LDR, ARM64_INS_LDTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_UnPriv_STR, ARM64_INS_STTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS64_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_LDR, ARM64_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_LDUR, ARM64_INS_LDURB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_PostInd_LDR, ARM64_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_PostInd_STR, ARM64_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_PreInd_LDR, ARM64_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_PreInd_STR, ARM64_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_STR, ARM64_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_STUR, ARM64_INS_STURB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_UnPriv_LDR, ARM64_INS_LDTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_UnPriv_STR, ARM64_INS_STTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_Wm_RegOffset_LDR, ARM64_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_Wm_RegOffset_STR, ARM64_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_Xm_RegOffset_LDR, ARM64_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LS8_Xm_RegOffset_STR, ARM64_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP128_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP16_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP32_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP64_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_LDUR, ARM64_INS_LDUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_PostInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_PostInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_PreInd_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_PreInd_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_STUR, ARM64_INS_STUR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_Wm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_Wm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_Xm_RegOffset_LDR, ARM64_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFP8_Xm_RegOffset_STR, ARM64_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_NonTemp_LDR, ARM64_INS_LDNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_NonTemp_STR, ARM64_INS_STNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_PostInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_PostInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_PreInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_PreInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair128_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_NonTemp_LDR, ARM64_INS_LDNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_NonTemp_STR, ARM64_INS_STNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_PostInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_PostInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_PreInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_PreInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair32_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_NonTemp_LDR, ARM64_INS_LDNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_NonTemp_STR, ARM64_INS_STNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_PostInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_PostInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_PreInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_PreInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSFPPair64_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSLVwww, ARM64_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSLVxxx, ARM64_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSLwwi, ARM64_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSLxxi, ARM64_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_NonTemp_LDR, ARM64_INS_LDNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_NonTemp_STR, ARM64_INS_STNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_PostInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_PostInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_PreInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_PreInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair32_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_NonTemp_LDR, ARM64_INS_LDNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_NonTemp_STR, ARM64_INS_STNP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_PostInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_PostInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_PreInd_LDR, ARM64_INS_LDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_PreInd_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSPair64_STR, ARM64_INS_STP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSRVwww, ARM64_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSRVxxx, ARM64_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSRwwi, ARM64_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_LSRxxi, ARM64_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MADDwwww, ARM64_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MADDxxxx, ARM64_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvve_2s4s, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvve_4h8h, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvve_4s4s, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvve_8h8h, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_16B, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_2S, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_4H, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_4S, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_8B, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLAvvv_8H, ARM64_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvve_2s4s, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvve_4h8h, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvve_4s4s, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvve_8h8h, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_16B, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_2S, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_4H, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_4S, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_8B, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MLSvvv_8H, ARM64_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIdi, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_16B, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_2D, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_8B, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_lsl_2S, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_lsl_4H, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_lsl_4S, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_lsl_8H, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_msl_2S, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVIvi_msl_4S, ARM64_INS_MOVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVKwii, ARM64_INS_MOVK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVKxii, ARM64_INS_MOVK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVNwii, ARM64_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVNxii, ARM64_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVZwii, ARM64_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MOVZxii, ARM64_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MRSxi, ARM64_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MSRii, ARM64_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MSRix, ARM64_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MSUBwwww, ARM64_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MSUBxxxx, ARM64_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULve_2s4s, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULve_4h8h, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULve_4s4s, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULve_8h8h, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_16B, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_2S, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_4H, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_4S, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_8B, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MULvvv_8H, ARM64_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_lsl_2S, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_lsl_4H, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_lsl_4S, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_lsl_8H, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_msl_2S, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNIvi_msl_4S, ARM64_INS_MVNI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNww_asr, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNww_lsl, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNww_lsr, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNww_ror, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNxx_asr, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNxx_lsl, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNxx_lsr, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_MVNxx_ror, ARM64_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG16b, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG2d, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG2s, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG4h, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG4s, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG8b, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEG8h, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NEGdd, ARM64_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NOT16b, ARM64_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_NOT8b, ARM64_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNvvv_16B, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNvvv_8B, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNwww_asr, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNwww_lsl, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNwww_lsr, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNwww_ror, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNxxx_asr, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNxxx_lsl, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNxxx_lsr, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORNxxx_ror, ARM64_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvi_lsl_2S, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvi_lsl_4H, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvi_lsl_4S, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvi_lsl_8H, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvvv_16B, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRvvv_8B, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRwwi, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRwww_asr, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRwww_lsl, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRwww_lsr, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRwww_ror, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRxxi, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRxxx_asr, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRxxx_lsl, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRxxx_lsr, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ORRxxx_ror, ARM64_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULL2vvv_1q2d, ARM64_INS_PMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULL2vvv_8h16b, ARM64_INS_PMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULLvvv_1q1d, ARM64_INS_PMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULLvvv_8h8b, ARM64_INS_PMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULvvv_16B, ARM64_INS_PMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PMULvvv_8B, ARM64_INS_PMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PRFM, ARM64_INS_PRFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PRFM_Wm_RegOffset, ARM64_INS_PRFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PRFM_Xm_RegOffset, ARM64_INS_PRFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PRFM_lit, ARM64_INS_PRFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_PRFUM, ARM64_INS_PRFUM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_16B, ARM64_INS_SQRSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_2S, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_4H, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_4S, ARM64_INS_SQRSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_8B, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QRSHRUNvvi_8H, ARM64_INS_SQRSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_16B, ARM64_INS_SQSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_2S, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_4H, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_4S, ARM64_INS_SQSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_8B, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_QSHRUNvvi_8H, ARM64_INS_SQSHRUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHN2vvv_16b8h, ARM64_INS_RADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHN2vvv_4s2d, ARM64_INS_RADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHN2vvv_8h4s, ARM64_INS_RADDHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHNvvv_2s2d, ARM64_INS_RADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHNvvv_4h4s, ARM64_INS_RADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RADDHNvvv_8b8h, ARM64_INS_RADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RBIT16b, ARM64_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RBIT8b, ARM64_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RBITww, ARM64_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RBITxx, ARM64_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RETx, ARM64_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ AArch64_REV16_16b, ARM64_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV16_8b, ARM64_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV16ww, ARM64_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV16xx, ARM64_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV32_16b, ARM64_INS_REV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV32_4h, ARM64_INS_REV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV32_8b, ARM64_INS_REV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV32_8h, ARM64_INS_REV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV32xx, ARM64_INS_REV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_16b, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_2s, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_4h, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_4s, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_8b, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REV64_8h, ARM64_INS_REV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REVww, ARM64_INS_REV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_REVxx, ARM64_INS_REV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RORVwww, ARM64_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RORVxxx, ARM64_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_16B, ARM64_INS_RSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_2S, ARM64_INS_RSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_4H, ARM64_INS_RSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_4S, ARM64_INS_RSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_8B, ARM64_INS_RSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSHRNvvi_8H, ARM64_INS_RSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHN2vvv_16b8h, ARM64_INS_RSUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHN2vvv_4s2d, ARM64_INS_RSUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHN2vvv_8h4s, ARM64_INS_RSUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHNvvv_2s2d, ARM64_INS_RSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHNvvv_4h4s, ARM64_INS_RSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_RSUBHNvvv_8b8h, ARM64_INS_RSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAL2vvv_2d2s, ARM64_INS_SABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAL2vvv_4s4h, ARM64_INS_SABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAL2vvv_8h8b, ARM64_INS_SABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABALvvv_2d2s, ARM64_INS_SABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABALvvv_4s4h, ARM64_INS_SABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABALvvv_8h8b, ARM64_INS_SABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_16B, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_2S, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_4H, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_4S, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_8B, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABAvvv_8H, ARM64_INS_SABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDL2vvv_2d2s, ARM64_INS_SABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDL2vvv_4s4h, ARM64_INS_SABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDL2vvv_8h8b, ARM64_INS_SABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDLvvv_2d2s, ARM64_INS_SABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDLvvv_4s4h, ARM64_INS_SABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDLvvv_8h8b, ARM64_INS_SABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_16B, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_2S, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_4H, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_4S, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_8B, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SABDvvv_8H, ARM64_INS_SABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP16b8h, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP2s1d, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP4h2s, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP4s2d, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP8b4h, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADALP8h4s, ARM64_INS_SADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDL2vvv_2d4s, ARM64_INS_SADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDL2vvv_4s8h, ARM64_INS_SADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDL2vvv_8h16b, ARM64_INS_SADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP16b8h, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP2s1d, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP4h2s, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP4s2d, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP8b4h, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLP8h4s, ARM64_INS_SADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLV_1d4s, ARM64_INS_SADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLV_1h16b, ARM64_INS_SADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLV_1h8b, ARM64_INS_SADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLV_1s4h, ARM64_INS_SADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLV_1s8h, ARM64_INS_SADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLvvv_2d2s, ARM64_INS_SADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLvvv_4s4h, ARM64_INS_SADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDLvvv_8h8b, ARM64_INS_SADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDW2vvv_2d4s, ARM64_INS_SADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDW2vvv_4s8h, ARM64_INS_SADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDW2vvv_8h16b, ARM64_INS_SADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDWvvv_2d2s, ARM64_INS_SADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDWvvv_4s4h, ARM64_INS_SADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SADDWvvv_8h8b, ARM64_INS_SADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBCSwww, ARM64_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBCSxxx, ARM64_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBCwww, ARM64_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBCxxx, ARM64_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFIZwwii, ARM64_INS_SBFIZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFIZxxii, ARM64_INS_SBFIZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFMwwii, ARM64_INS_SBFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFMxxii, ARM64_INS_SBFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFXwwii, ARM64_INS_SBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SBFXxxii, ARM64_INS_SBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTF_2d, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTF_2s, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTF_4s, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTF_Nddi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTF_Nssi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFdd, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFdw, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFdwi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFdx, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFdxi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFss, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFsw, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFswi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFsx, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SCVTFsxi, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SDIVwww, ARM64_INS_SDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SDIVxxx, ARM64_INS_SDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1C, ARM64_INS_SHA1C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1H, ARM64_INS_SHA1H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1M, ARM64_INS_SHA1M,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1P, ARM64_INS_SHA1P,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1SU0, ARM64_INS_SHA1SU0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA1SU1, ARM64_INS_SHA1SU1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA256H, ARM64_INS_SHA256H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA256H2, ARM64_INS_SHA256H2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA256SU0, ARM64_INS_SHA256SU0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHA256SU1, ARM64_INS_SHA256SU1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, ARM64_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_16B, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_2S, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_4H, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_4S, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_8B, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHADDvvv_8H, ARM64_INS_SHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL16b8h, ARM64_INS_SHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL2s2d, ARM64_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL4h4s, ARM64_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL4s2d, ARM64_INS_SHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL8b8h, ARM64_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLL8h4s, ARM64_INS_SHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLddi, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_16B, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_2D, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_2S, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_4H, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_4S, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_8B, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHLvvi_8H, ARM64_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_16B, ARM64_INS_SHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_2S, ARM64_INS_SHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_4H, ARM64_INS_SHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_4S, ARM64_INS_SHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_8B, ARM64_INS_SHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHRNvvi_8H, ARM64_INS_SHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_16B, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_2S, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_4H, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_4S, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_8B, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SHSUBvvv_8H, ARM64_INS_SHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLI, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_16B, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_2D, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_2S, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_4H, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_4S, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_8B, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SLIvvi_8H, ARM64_INS_SLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMADDLxwwx, ARM64_INS_SMADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_16B, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_2S, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_4H, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_4S, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_8B, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXPvvv_8H, ARM64_INS_SMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXV_1b16b, ARM64_INS_SMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXV_1b8b, ARM64_INS_SMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXV_1h4h, ARM64_INS_SMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXV_1h8h, ARM64_INS_SMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXV_1s4s, ARM64_INS_SMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_16B, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_2S, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_4H, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_4S, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_8B, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMAXvvv_8H, ARM64_INS_SMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMCi, ARM64_INS_SMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_16B, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_2S, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_4H, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_4S, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_8B, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINPvvv_8H, ARM64_INS_SMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINV_1b16b, ARM64_INS_SMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINV_1b8b, ARM64_INS_SMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINV_1h4h, ARM64_INS_SMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINV_1h8h, ARM64_INS_SMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINV_1s4s, ARM64_INS_SMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_16B, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_2S, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_4H, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_4S, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_8B, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMINvvv_8H, ARM64_INS_SMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLAL2vvv_2d4s, ARM64_INS_SMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLAL2vvv_4s8h, ARM64_INS_SMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLAL2vvv_8h16b, ARM64_INS_SMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvve_2d2s, ARM64_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvve_2d4s, ARM64_INS_SMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvve_4s4h, ARM64_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvve_4s8h, ARM64_INS_SMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvvv_2d2s, ARM64_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvvv_4s4h, ARM64_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLALvvv_8h8b, ARM64_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSL2vvv_2d4s, ARM64_INS_SMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSL2vvv_4s8h, ARM64_INS_SMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSL2vvv_8h16b, ARM64_INS_SMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvve_2d2s, ARM64_INS_SMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvve_2d4s, ARM64_INS_SMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvve_4s4h, ARM64_INS_SMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvve_4s8h, ARM64_INS_SMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvvv_2d2s, ARM64_INS_SMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvvv_4s4h, ARM64_INS_SMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMLSLvvv_8h8b, ARM64_INS_SMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMOVwb, ARM64_INS_SMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMOVwh, ARM64_INS_SMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMOVxb, ARM64_INS_SMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMOVxh, ARM64_INS_SMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMOVxs, ARM64_INS_SMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMSUBLxwwx, ARM64_INS_SMSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULHxxx, ARM64_INS_SMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULL2vvv_2d4s, ARM64_INS_SMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULL2vvv_4s8h, ARM64_INS_SMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULL2vvv_8h16b, ARM64_INS_SMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLve_2d2s, ARM64_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLve_2d4s, ARM64_INS_SMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLve_4s4h, ARM64_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLve_4s8h, ARM64_INS_SMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLvvv_2d2s, ARM64_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLvvv_4s4h, ARM64_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SMULLvvv_8h8b, ARM64_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS16b, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS2d, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS2s, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS4h, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS4s, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS8b, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABS8h, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABSbb, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABSdd, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABShh, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQABSss, ARM64_INS_SQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDbbb, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDddd, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDhhh, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDsss, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_16B, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_2D, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_2S, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_4H, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_4S, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_8B, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQADDvvv_8H, ARM64_INS_SQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLAL2vvv_2d4s, ARM64_INS_SQDMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLAL2vvv_4s8h, ARM64_INS_SQDMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALdss, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALdsv_2S, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALdsv_4S, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALshh, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALshv_4H, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALshv_8H, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvve_2d2s, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvve_2d4s, ARM64_INS_SQDMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvve_4s4h, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvve_4s8h, ARM64_INS_SQDMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvvv_2d2s, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLALvvv_4s4h, ARM64_INS_SQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSL2vvv_2d4s, ARM64_INS_SQDMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSL2vvv_4s8h, ARM64_INS_SQDMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLdss, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLdsv_2S, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLdsv_4S, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLshh, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLshv_4H, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLshv_8H, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvve_2d2s, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvve_2d4s, ARM64_INS_SQDMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvve_4s4h, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvve_4s8h, ARM64_INS_SQDMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvvv_2d2s, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMLSLvvv_4s4h, ARM64_INS_SQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHhhh, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHhhv_4H, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHhhv_8H, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHsss, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHssv_2S, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHssv_4S, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHve_2s4s, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHve_4h8h, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHve_4s4s, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHve_8h8h, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHvvv_2S, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHvvv_4H, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHvvv_4S, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULHvvv_8H, ARM64_INS_SQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULL2vvv_2d4s, ARM64_INS_SQDMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULL2vvv_4s8h, ARM64_INS_SQDMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLdss, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLdsv_2S, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLdsv_4S, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLshh, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLshv_4H, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLshv_8H, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLve_2d2s, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLve_2d4s, ARM64_INS_SQDMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLve_4s4h, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLve_4s8h, ARM64_INS_SQDMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLvvv_2d2s, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQDMULLvvv_4s4h, ARM64_INS_SQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG16b, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG2d, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG2s, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG4h, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG4s, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG8b, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEG8h, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEGbb, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEGdd, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEGhh, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQNEGss, ARM64_INS_SQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHhhh, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHhhv_4H, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHhhv_8H, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHsss, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHssv_2S, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHssv_4S, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHve_2s4s, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHve_4h8h, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHve_4s4s, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHve_8h8h, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHvvv_2S, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHvvv_4H, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHvvv_4S, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRDMULHvvv_8H, ARM64_INS_SQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLbbb, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLddd, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLhhh, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLsss, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_16B, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_2D, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_2S, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_4H, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_4S, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_8B, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHLvvv_8H, ARM64_INS_SQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNbhi, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNhsi, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNsdi, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_16B, ARM64_INS_SQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_2S, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_4H, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_4S, ARM64_INS_SQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_8B, ARM64_INS_SQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRNvvi_8H, ARM64_INS_SQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRUNbhi, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRUNhsi, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQRSHRUNsdi, ARM64_INS_SQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUbbi, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUddi, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUhhi, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUssi, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_16B, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_2D, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_2S, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_4H, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_4S, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_8B, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLUvvi_8H, ARM64_INS_SQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLbbb, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLbbi, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLddd, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLddi, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLhhh, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLhhi, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLssi, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLsss, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_16B, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_2D, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_2S, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_4H, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_4S, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_8B, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvi_8H, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_16B, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_2D, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_2S, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_4H, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_4S, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_8B, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHLvvv_8H, ARM64_INS_SQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNbhi, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNhsi, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNsdi, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_16B, ARM64_INS_SQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_2S, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_4H, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_4S, ARM64_INS_SQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_8B, ARM64_INS_SQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRNvvi_8H, ARM64_INS_SQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRUNbhi, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRUNhsi, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSHRUNsdi, ARM64_INS_SQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBbbb, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBddd, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBhhh, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBsss, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_16B, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_2D, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_2S, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_4H, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_4S, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_8B, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQSUBvvv_8H, ARM64_INS_SQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN2d2s, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN2d4s, ARM64_INS_SQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN4s4h, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN4s8h, ARM64_INS_SQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN8h16b, ARM64_INS_SQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTN8h8b, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTNbh, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTNhs, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTNsd, ARM64_INS_SQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN2d2s, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN2d4s, ARM64_INS_SQXTUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN4s4h, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN4s8h, ARM64_INS_SQXTUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN8h16b, ARM64_INS_SQXTUN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUN8h8b, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUNbh, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUNhs, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SQXTUNsd, ARM64_INS_SQXTUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_16B, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_2S, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_4H, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_4S, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_8B, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRHADDvvv_8H, ARM64_INS_SRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRI, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_16B, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_2D, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_2S, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_4H, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_4S, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_8B, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRIvvi_8H, ARM64_INS_SRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLddd, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_16B, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_2D, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_2S, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_4H, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_4S, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_8B, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHLvvv_8H, ARM64_INS_SRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRddi, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_16B, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_2D, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_2S, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_4H, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_4S, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_8B, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSHRvvi_8H, ARM64_INS_SRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRA, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_16B, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_2D, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_2S, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_4H, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_4S, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_8B, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SRSRAvvi_8H, ARM64_INS_SRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_16B, ARM64_INS_SSHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_2S, ARM64_INS_SSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_4H, ARM64_INS_SSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_4S, ARM64_INS_SSHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_8B, ARM64_INS_SSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLLvvi_8H, ARM64_INS_SSHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLddd, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_16B, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_2D, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_2S, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_4H, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_4S, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_8B, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHLvvv_8H, ARM64_INS_SSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRddi, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_16B, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_2D, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_2S, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_4H, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_4S, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_8B, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSHRvvi_8H, ARM64_INS_SSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRA, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_16B, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_2D, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_2S, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_4H, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_4S, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_8B, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSRAvvi_8H, ARM64_INS_SSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBL2vvv_2d4s, ARM64_INS_SSUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBL2vvv_4s8h, ARM64_INS_SSUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBL2vvv_8h16b, ARM64_INS_SSUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBLvvv_2d2s, ARM64_INS_SSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBLvvv_4s4h, ARM64_INS_SSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBLvvv_8h8b, ARM64_INS_SSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBW2vvv_2d4s, ARM64_INS_SSUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBW2vvv_4s8h, ARM64_INS_SSUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBW2vvv_8h16b, ARM64_INS_SSUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBWvvv_2d2s, ARM64_INS_SSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBWvvv_4s4h, ARM64_INS_SSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SSUBWvvv_8h8b, ARM64_INS_SSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1LN_WB_S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_16B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_16B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_1D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_1D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_2D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_2D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_2S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_2S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_4H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_4H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_4S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_4S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_8B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_8B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_8H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1WB_8H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_16B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_1D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_2D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_2S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_4H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_4S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_8B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1_8H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_16B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_16B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_1D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_1D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_2D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_2D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_2S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_2S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_4H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_4H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_4S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_4S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_8B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_8B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_8H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2WB_8H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_16B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_1D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_2D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_2S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_4H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_4S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_8B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x2_8H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_16B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_16B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_1D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_1D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_2D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_2D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_2S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_2S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_4H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_4H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_4S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_4S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_8B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_8B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_8H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3WB_8H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_16B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_1D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_2D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_2S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_4H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_4S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_8B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x3_8H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_16B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_16B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_1D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_1D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_2D_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_2D_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_2S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_2S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_4H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_4H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_4S_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_4S_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_8B_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_8B_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_8H_fixed, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4WB_8H_register, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_16B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_1D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_2D, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_2S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_4H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_4S, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_8B, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST1x4_8H, ARM64_INS_ST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_B, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_D, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_H, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_S, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_B_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_B_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_D_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_D_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_H_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_H_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_S_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2LN_WB_S_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_16B_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_16B_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_2D_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_2D_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_2S_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_2S_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_4H_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_4H_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_4S_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_4S_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_8B_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_8B_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_8H_fixed, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2WB_8H_register, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_16B, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_2D, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_2S, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_4H, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_4S, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_8B, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST2_8H, ARM64_INS_ST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_B, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_D, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_H, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_S, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_B_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_B_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_D_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_D_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_H_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_H_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_S_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3LN_WB_S_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_16B_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_16B_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_2D_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_2D_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_2S_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_2S_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_4H_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_4H_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_4S_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_4S_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_8B_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_8B_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_8H_fixed, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3WB_8H_register, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_16B, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_2D, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_2S, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_4H, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_4S, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_8B, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST3_8H, ARM64_INS_ST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_B, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_D, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_H, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_S, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_B_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_B_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_D_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_D_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_H_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_H_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_S_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4LN_WB_S_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_16B_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_16B_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_2D_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_2D_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_2S_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_2S_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_4H_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_4H_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_4S_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_4S_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_8B_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_8B_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_8H_fixed, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4WB_8H_register, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_16B, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_2D, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_2S, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_4H, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_4S, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_8B, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ST4_8H, ARM64_INS_ST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLR_byte, ARM64_INS_STLRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLR_dword, ARM64_INS_STLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLR_hword, ARM64_INS_STLRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLR_word, ARM64_INS_STLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXP_dword, ARM64_INS_STLXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXP_word, ARM64_INS_STLXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXR_byte, ARM64_INS_STLXRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXR_dword, ARM64_INS_STLXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXR_hword, ARM64_INS_STLXRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STLXR_word, ARM64_INS_STLXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXP_dword, ARM64_INS_STXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXP_word, ARM64_INS_STXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXR_byte, ARM64_INS_STXRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXR_dword, ARM64_INS_STXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXR_hword, ARM64_INS_STXRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_STXR_word, ARM64_INS_STXR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHN2vvv_16b8h, ARM64_INS_SUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHN2vvv_4s2d, ARM64_INS_SUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHN2vvv_8h4s, ARM64_INS_SUBHN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHNvvv_2s2d, ARM64_INS_SUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHNvvv_4h4s, ARM64_INS_SUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBHNvvv_8b8h, ARM64_INS_SUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_asr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_lsl, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_lsr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_sxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_sxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_sxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_sxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_uxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_uxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_uxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSwww_uxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_sxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_sxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_sxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_uxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_uxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxw_uxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxx_asr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxx_lsl, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxx_lsr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxx_sxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBSxxx_uxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBddd, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_16B, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_2D, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_2S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_4H, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_4S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_8B, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBvvv_8H, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl0_S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl0_cmp, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl0_s, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl12_S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl12_cmp, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwwi_lsl12_s, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_asr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_lsl, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_lsr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_sxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_sxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_sxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_sxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_uxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_uxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_uxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBwww_uxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl0_S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl0_cmp, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl0_s, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl12_S, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl12_cmp, ARM64_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxi_lsl12_s, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_sxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_sxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_sxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_uxtb, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_uxth, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxw_uxtw, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxx_asr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxx_lsl, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxx_lsr, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxx_sxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUBxxx_uxtx, ARM64_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD16b, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD2d, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD2s, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD4h, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD4s, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD8b, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADD8h, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADDbb, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADDdd, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADDhh, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SUQADDss, ARM64_INS_SUQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SVCi, ARM64_INS_SVC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_SXTBww, ARM64_INS_SXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SXTBxw, ARM64_INS_SXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SXTHww, ARM64_INS_SXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SXTHxw, ARM64_INS_SXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SXTWxw, ARM64_INS_SXTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SYSLxicci, ARM64_INS_SYSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_SYSiccix, ARM64_INS_SYS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL1_16b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL1_8b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL2_16b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL2_8b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL3_16b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL3_8b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL4_16b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBL4_8b, ARM64_INS_TBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBNZwii, ARM64_INS_TBNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_TBNZxii, ARM64_INS_TBNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_TBX1_16b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX1_8b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX2_16b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX2_8b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX3_16b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX3_8b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX4_16b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBX4_8b, ARM64_INS_TBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TBZwii, ARM64_INS_TBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_TBZxii, ARM64_INS_TBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ AArch64_TLBIi, ARM64_INS_TLBI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TLBIix, ARM64_INS_TLBI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_16b, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_2d, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_2s, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_4h, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_4s, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_8b, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN1vvv_8h, ARM64_INS_TRN1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_16b, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_2d, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_2s, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_4h, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_4s, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_8b, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TRN2vvv_8h, ARM64_INS_TRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTww_asr, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTww_lsl, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTww_lsr, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTww_ror, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTxx_asr, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTxx_lsl, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTxx_lsr, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_TSTxx_ror, ARM64_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAL2vvv_2d2s, ARM64_INS_UABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAL2vvv_4s4h, ARM64_INS_UABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAL2vvv_8h8b, ARM64_INS_UABAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABALvvv_2d2s, ARM64_INS_UABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABALvvv_4s4h, ARM64_INS_UABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABALvvv_8h8b, ARM64_INS_UABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_16B, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_2S, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_4H, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_4S, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_8B, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABAvvv_8H, ARM64_INS_UABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDL2vvv_2d2s, ARM64_INS_UABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDL2vvv_4s4h, ARM64_INS_UABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDL2vvv_8h8b, ARM64_INS_UABDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDLvvv_2d2s, ARM64_INS_UABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDLvvv_4s4h, ARM64_INS_UABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDLvvv_8h8b, ARM64_INS_UABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_16B, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_2S, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_4H, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_4S, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_8B, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UABDvvv_8H, ARM64_INS_UABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP16b8h, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP2s1d, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP4h2s, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP4s2d, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP8b4h, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADALP8h4s, ARM64_INS_UADALP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDL2vvv_2d4s, ARM64_INS_UADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDL2vvv_4s8h, ARM64_INS_UADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDL2vvv_8h16b, ARM64_INS_UADDL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP16b8h, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP2s1d, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP4h2s, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP4s2d, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP8b4h, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLP8h4s, ARM64_INS_UADDLP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLV_1d4s, ARM64_INS_UADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLV_1h16b, ARM64_INS_UADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLV_1h8b, ARM64_INS_UADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLV_1s4h, ARM64_INS_UADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLV_1s8h, ARM64_INS_UADDLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLvvv_2d2s, ARM64_INS_UADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLvvv_4s4h, ARM64_INS_UADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDLvvv_8h8b, ARM64_INS_UADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDW2vvv_2d4s, ARM64_INS_UADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDW2vvv_4s8h, ARM64_INS_UADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDW2vvv_8h16b, ARM64_INS_UADDW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDWvvv_2d2s, ARM64_INS_UADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDWvvv_4s4h, ARM64_INS_UADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UADDWvvv_8h8b, ARM64_INS_UADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFIZwwii, ARM64_INS_UBFIZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFIZxxii, ARM64_INS_UBFIZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFMwwii, ARM64_INS_UBFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFMxxii, ARM64_INS_UBFM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFXwwii, ARM64_INS_UBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UBFXxxii, ARM64_INS_UBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTF_2d, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTF_2s, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTF_4s, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTF_Nddi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTF_Nssi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFdd, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFdw, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFdwi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFdx, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFdxi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFss, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFsw, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFswi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFsx, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UCVTFsxi, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UDIVwww, ARM64_INS_UDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UDIVxxx, ARM64_INS_UDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_16B, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_2S, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_4H, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_4S, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_8B, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHADDvvv_8H, ARM64_INS_UHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_16B, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_2S, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_4H, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_4S, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_8B, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UHSUBvvv_8H, ARM64_INS_UHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMADDLxwwx, ARM64_INS_UMADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_16B, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_2S, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_4H, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_4S, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_8B, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXPvvv_8H, ARM64_INS_UMAXP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXV_1b16b, ARM64_INS_UMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXV_1b8b, ARM64_INS_UMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXV_1h4h, ARM64_INS_UMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXV_1h8h, ARM64_INS_UMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXV_1s4s, ARM64_INS_UMAXV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_16B, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_2S, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_4H, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_4S, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_8B, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMAXvvv_8H, ARM64_INS_UMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_16B, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_2S, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_4H, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_4S, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_8B, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINPvvv_8H, ARM64_INS_UMINP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINV_1b16b, ARM64_INS_UMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINV_1b8b, ARM64_INS_UMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINV_1h4h, ARM64_INS_UMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINV_1h8h, ARM64_INS_UMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINV_1s4s, ARM64_INS_UMINV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_16B, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_2S, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_4H, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_4S, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_8B, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMINvvv_8H, ARM64_INS_UMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLAL2vvv_2d4s, ARM64_INS_UMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLAL2vvv_4s8h, ARM64_INS_UMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLAL2vvv_8h16b, ARM64_INS_UMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvve_2d2s, ARM64_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvve_2d4s, ARM64_INS_UMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvve_4s4h, ARM64_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvve_4s8h, ARM64_INS_UMLAL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvvv_2d2s, ARM64_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvvv_4s4h, ARM64_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLALvvv_8h8b, ARM64_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSL2vvv_2d4s, ARM64_INS_UMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSL2vvv_4s8h, ARM64_INS_UMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSL2vvv_8h16b, ARM64_INS_UMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvve_2d2s, ARM64_INS_UMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvve_2d4s, ARM64_INS_UMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvve_4s4h, ARM64_INS_UMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvve_4s8h, ARM64_INS_UMLSL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvvv_2d2s, ARM64_INS_UMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvvv_4s4h, ARM64_INS_UMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMLSLvvv_8h8b, ARM64_INS_UMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMOVwb, ARM64_INS_UMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMOVwh, ARM64_INS_UMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMOVws, ARM64_INS_UMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMOVxd, ARM64_INS_UMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMSUBLxwwx, ARM64_INS_UMSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULHxxx, ARM64_INS_UMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULL2vvv_2d4s, ARM64_INS_UMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULL2vvv_4s8h, ARM64_INS_UMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULL2vvv_8h16b, ARM64_INS_UMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLve_2d2s, ARM64_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLve_2d4s, ARM64_INS_UMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLve_4s4h, ARM64_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLve_4s8h, ARM64_INS_UMULL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLvvv_2d2s, ARM64_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLvvv_4s4h, ARM64_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UMULLvvv_8h8b, ARM64_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDbbb, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDddd, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDhhh, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDsss, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_16B, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_2D, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_2S, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_4H, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_4S, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_8B, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQADDvvv_8H, ARM64_INS_UQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLbbb, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLddd, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLhhh, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLsss, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_16B, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_2D, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_2S, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_4H, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_4S, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_8B, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHLvvv_8H, ARM64_INS_UQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNbhi, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNhsi, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNsdi, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_16B, ARM64_INS_UQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_2S, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_4H, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_4S, ARM64_INS_UQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_8B, ARM64_INS_UQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQRSHRNvvi_8H, ARM64_INS_UQRSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLbbb, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLbbi, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLddd, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLddi, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLhhh, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLhhi, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLssi, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLsss, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_16B, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_2D, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_2S, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_4H, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_4S, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_8B, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvi_8H, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_16B, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_2D, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_2S, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_4H, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_4S, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_8B, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHLvvv_8H, ARM64_INS_UQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNbhi, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNhsi, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNsdi, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_16B, ARM64_INS_UQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_2S, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_4H, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_4S, ARM64_INS_UQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_8B, ARM64_INS_UQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSHRNvvi_8H, ARM64_INS_UQSHRN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBbbb, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBddd, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBhhh, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBsss, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_16B, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_2D, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_2S, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_4H, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_4S, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_8B, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQSUBvvv_8H, ARM64_INS_UQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN2d2s, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN2d4s, ARM64_INS_UQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN4s4h, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN4s8h, ARM64_INS_UQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN8h16b, ARM64_INS_UQXTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTN8h8b, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTNbh, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTNhs, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UQXTNsd, ARM64_INS_UQXTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URECPE2s, ARM64_INS_URECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URECPE4s, ARM64_INS_URECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_16B, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_2S, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_4H, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_4S, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_8B, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URHADDvvv_8H, ARM64_INS_URHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLddd, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_16B, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_2D, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_2S, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_4H, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_4S, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_8B, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHLvvv_8H, ARM64_INS_URSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRddi, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_16B, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_2D, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_2S, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_4H, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_4S, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_8B, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSHRvvi_8H, ARM64_INS_URSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSQRTE2s, ARM64_INS_URSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSQRTE4s, ARM64_INS_URSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRA, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_16B, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_2D, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_2S, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_4H, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_4S, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_8B, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_URSRAvvi_8H, ARM64_INS_URSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_16B, ARM64_INS_USHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_2S, ARM64_INS_USHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_4H, ARM64_INS_USHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_4S, ARM64_INS_USHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_8B, ARM64_INS_USHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLLvvi_8H, ARM64_INS_USHLL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLddd, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_16B, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_2D, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_2S, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_4H, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_4S, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_8B, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHLvvv_8H, ARM64_INS_USHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRddi, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_16B, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_2D, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_2S, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_4H, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_4S, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_8B, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USHRvvi_8H, ARM64_INS_USHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD16b, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD2d, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD2s, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD4h, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD4s, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD8b, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADD8h, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADDbb, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADDdd, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADDhh, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USQADDss, ARM64_INS_USQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRA, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_16B, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_2D, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_2S, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_4H, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_4S, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_8B, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USRAvvi_8H, ARM64_INS_USRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBL2vvv_2d4s, ARM64_INS_USUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBL2vvv_4s8h, ARM64_INS_USUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBL2vvv_8h16b, ARM64_INS_USUBL2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBLvvv_2d2s, ARM64_INS_USUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBLvvv_4s4h, ARM64_INS_USUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBLvvv_8h8b, ARM64_INS_USUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBW2vvv_2d4s, ARM64_INS_USUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBW2vvv_4s8h, ARM64_INS_USUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBW2vvv_8h16b, ARM64_INS_USUBW2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBWvvv_2d2s, ARM64_INS_USUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBWvvv_4s4h, ARM64_INS_USUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_USUBWvvv_8h8b, ARM64_INS_USUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UXTBww, ARM64_INS_UXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UXTBxw, ARM64_INS_UXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UXTHww, ARM64_INS_UXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UXTHxw, ARM64_INS_UXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_16b, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_2d, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_2s, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_4h, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_4s, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_8b, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP1vvv_8h, ARM64_INS_UZP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_16b, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_2d, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_2s, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_4h, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_4s, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_8b, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_UZP2vvv_8h, ARM64_INS_UZP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xs_2D, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xs_2S, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xs_4S, ARM64_INS_FCVTZS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xu_2D, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xu_2S, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTf2xu_4S, ARM64_INS_FCVTZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxs2f_2D, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxs2f_2S, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxs2f_4S, ARM64_INS_SCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxu2f_2D, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxu2f_2S, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_VCVTxu2f_4S, ARM64_INS_UCVTF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN2d2s, ARM64_INS_XTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN2d4s, ARM64_INS_XTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN4s4h, ARM64_INS_XTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN4s8h, ARM64_INS_XTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN8h16b, ARM64_INS_XTN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_XTN8h8b, ARM64_INS_XTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_16b, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_2d, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_2s, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_4h, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_4s, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_8b, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP1vvv_8h, ARM64_INS_ZIP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_16b, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_2d, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_2s, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_4h, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_4s, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_8b, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ AArch64_ZIP2vvv_8h, ARM64_INS_ZIP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
+#endif
+ },
};
// some alias instruction only need to be defined locally to satisfy
@@ -2977,6 +16519,7 @@
insn->id = insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
cs_struct handle;
handle.detail = h->detail;
@@ -2996,6 +16539,7 @@
insn->detail->groups[insn->detail->groups_count] = ARM64_GRP_JUMP;
insn->detail->groups_count++;
}
+#endif
}
}
}
@@ -3467,6 +17011,7 @@
const char *AArch64_insn_name(csh handle, unsigned int id)
{
+#ifndef CAPSTONE_DIET
if (id >= ARM64_INS_MAX)
return NULL;
@@ -3482,6 +17027,9 @@
// not found
return NULL;
+#else
+ return NULL;
+#endif
}
// map instruction name to public instruction ID
@@ -3495,4 +17043,5 @@
i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name);
return (i != -1)? i : ARM64_REG_INVALID;
+ return 0;
}
diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
index 0f2fde1..99bc5e4 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
@@ -5689,6 +5689,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0,
/* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0,
@@ -6132,13 +6133,16 @@
/* 3019 */ 'v', 'c', 'l', 'z', 0,
/* 3024 */ 'v', 'r', 'i', 'n', 't', 'z', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 4095)-1);
+#endif
// Fragment 0 encoded into 5 bits for 29 unique commands.
@@ -8185,6 +8189,7 @@
{
// assert(RegNo && RegNo < 289 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
@@ -8406,6 +8411,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index fc78578..9490714 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -12,6 +12,7 @@
#define GET_INSTRINFO_ENUM
#include "ARMGenInstrInfo.inc"
+#ifndef CAPSTONE_DIET
static name_map reg_name_maps[] = {
{ ARM_REG_INVALID, NULL },
{ ARM_REG_APSR, "apsr"},
@@ -125,2181 +126,13007 @@
{ ARM_REG_S30, "s30"},
{ ARM_REG_S31, "s31"},
};
+#endif
const char *ARM_reg_name(csh handle, unsigned int reg)
{
+#ifndef CAPSTONE_DIET
if (reg >= ARM_REG_MAX)
return NULL;
return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
}
static insn_map insns[] = {
- { 0, 0, { 0 }, { 0 }, { 0 }, 0, 0 }, // dummy item
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
- { ARM_ADCri, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADCrr, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADCrsi, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADCrsr, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADDri, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADDrr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADDrsi, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADDrsr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ADR, ARM_INS_ADR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_AESD, ARM_INS_AESD, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_AESE, ARM_INS_AESE, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_AESIMC, ARM_INS_AESIMC, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_AESMC, ARM_INS_AESMC, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_ANDri, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ANDrr, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ANDrsi, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ANDrsr, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BFC, ARM_INS_BFC, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_BFI, ARM_INS_BFI, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_BICri, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BICrr, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BICrsi, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BICrsr, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BKPT, ARM_INS_BKPT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BL, ARM_INS_BL, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BLX, ARM_INS_BLX, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_BLX_pred, ARM_INS_BLX, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_BLXi, ARM_INS_BLX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_BL_pred, ARM_INS_BL, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BX, ARM_INS_BX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 1, 1 },
- { ARM_BXJ, ARM_INS_BXJ, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_BX_RET, ARM_INS_BX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 0 },
- { ARM_BX_pred, ARM_INS_BX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 1, 1 },
- { ARM_Bcc, ARM_INS_B, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 1, 0 },
- { ARM_CDP, ARM_INS_CDP, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_CDP2, ARM_INS_CDP2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_CLREX, ARM_INS_CLREX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_CLZ, ARM_INS_CLZ, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_CMNri, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMNzrr, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMNzrsi, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMNzrsr, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMPri, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMPrr, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMPrsi, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CMPrsr, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CPS1p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CPS2p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CPS3p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_CRC32B, ARM_INS_CRC32B, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_CRC32CB, ARM_INS_CRC32CB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_CRC32CH, ARM_INS_CRC32CH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_CRC32CW, ARM_INS_CRC32CW, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_CRC32H, ARM_INS_CRC32H, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_CRC32W, ARM_INS_CRC32W, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_DBG, ARM_INS_DBG, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_DMB, ARM_INS_DMB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_DSB, ARM_INS_DSB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_EORri, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_EORrr, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_EORrsi, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_EORrsr, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_FCONSTD, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_FCONSTS, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 },
- { ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FLDMXIA, ARM_INS_FLDMIAX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FMSTAT, ARM_INS_VMRS, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FSTMXIA, ARM_INS_FSTMIAX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_HINT, ARM_INS_HINT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_HLT, ARM_INS_HLT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_ISB, ARM_INS_ISB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_LDA, ARM_INS_LDA, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAB, ARM_INS_LDAB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAEX, ARM_INS_LDAEX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAEXB, ARM_INS_LDAEXB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAEXD, ARM_INS_LDAEXD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAEXH, ARM_INS_LDAEXH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDAH, ARM_INS_LDAH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_LDC2L_OFFSET, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2L_OPTION, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2L_POST, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2L_PRE, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2_OFFSET, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2_OPTION, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2_POST, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDC2_PRE, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_LDCL_OFFSET, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDCL_OPTION, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDCL_POST, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDCL_PRE, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDC_OFFSET, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDC_OPTION, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDC_POST, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDC_PRE, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMDA, ARM_INS_LDMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMDA_UPD, ARM_INS_LDMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMDB, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMDB_UPD, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMIA, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMIA_UPD, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMIB, ARM_INS_LDMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDMIB_UPD, ARM_INS_LDMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRBT_POST_REG, ARM_INS_LDRBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRB_POST_IMM, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRB_POST_REG, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRB_PRE_IMM, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRB_PRE_REG, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRBi12, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRBrs, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRD, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_LDRD_PAIR, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_LDRD_POST, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRD_PRE, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDREX, ARM_INS_LDREX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDREXB, ARM_INS_LDREXB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDREXD, ARM_INS_LDREXD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDREXH, ARM_INS_LDREXH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRH, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRHTi, ARM_INS_LDRHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRHTr, ARM_INS_LDRHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRH_POST, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRH_PRE, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSB, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSBTi, ARM_INS_LDRSBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSBTr, ARM_INS_LDRSBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSB_POST, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSB_PRE, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSH, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSHTi, ARM_INS_LDRSHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSHTr, ARM_INS_LDRSHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSH_POST, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRSH_PRE, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRT_POST_IMM, ARM_INS_LDRT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRT_POST_REG, ARM_INS_LDRT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDR_POST_IMM, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDR_POST_REG, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDR_PRE_IMM, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDR_PRE_REG, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRcp, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRi12, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_LDRrs, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MCR, ARM_INS_MCR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MCR2, ARM_INS_MCR2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_MCRR, ARM_INS_MCRR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MCRR2, ARM_INS_MCRR2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_MLA, ARM_INS_MLA, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_MLS, ARM_INS_MLS, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_MOVPCLR, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MOVTi16, ARM_INS_MOVT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_MOVi, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MOVi16, ARM_INS_MOVW, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_MOVr, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MOVr_TC, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MOVsi, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MOVsr, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MRC, ARM_INS_MRC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MRC2, ARM_INS_MRC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_MRRC, ARM_INS_MRRC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MRRC2, ARM_INS_MRRC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_MRS, ARM_INS_MRS, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MRSsys, ARM_INS_MRS, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MSR, ARM_INS_MSR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MSRi, ARM_INS_MSR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MUL, ARM_INS_MUL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_MVNi, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MVNr, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MVNsi, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_MVNsr, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ORRri, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ORRrr, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ORRrsi, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_ORRrsr, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_PKHBT, ARM_INS_PKHBT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_PKHTB, ARM_INS_PKHTB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_PLDWi12, ARM_INS_PLDW, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 },
- { ARM_PLDWrs, ARM_INS_PLDW, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 },
- { ARM_PLDi12, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_PLDrs, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_PLIi12, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_PLIrs, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_QADD, ARM_INS_QADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QADD16, ARM_INS_QADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QADD8, ARM_INS_QADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QASX, ARM_INS_QASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QDADD, ARM_INS_QDADD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QDSUB, ARM_INS_QDSUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QSAX, ARM_INS_QSAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QSUB, ARM_INS_QSUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QSUB16, ARM_INS_QSUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_QSUB8, ARM_INS_QSUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RBIT, ARM_INS_RBIT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_REV, ARM_INS_REV, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_REV16, ARM_INS_REV16, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_REVSH, ARM_INS_REVSH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_RFEDA, ARM_INS_RFEDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEDA_UPD, ARM_INS_RFEDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEDB, ARM_INS_RFEDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEDB_UPD, ARM_INS_RFEDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEIA, ARM_INS_RFEIA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEIA_UPD, ARM_INS_RFEIA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEIB, ARM_INS_RFEIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RFEIB_UPD, ARM_INS_RFEIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSBri, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSBrr, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSBrsi, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSBrsr, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSCri, ARM_INS_RSC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSCrr, ARM_INS_RSC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSCrsi, ARM_INS_RSC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_RSCrsr, ARM_INS_RSC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SADD16, ARM_INS_SADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SADD8, ARM_INS_SADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SASX, ARM_INS_SASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SBCri, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SBCrr, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SBCrsi, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SBCrsr, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SBFX, ARM_INS_SBFX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_SDIV, ARM_INS_SDIV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SEL, ARM_INS_SEL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SETEND, ARM_INS_SETEND, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHA1C, ARM_INS_SHA1C, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA1H, ARM_INS_SHA1H, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA1M, ARM_INS_SHA1M, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA1P, ARM_INS_SHA1P, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA1SU0, ARM_INS_SHA1SU0, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA1SU1, ARM_INS_SHA1SU1, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA256H, ARM_INS_SHA256H, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA256H2, ARM_INS_SHA256H2, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA256SU0, ARM_INS_SHA256SU0, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHA256SU1, ARM_INS_SHA256SU1, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_SHADD16, ARM_INS_SHADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHADD8, ARM_INS_SHADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHASX, ARM_INS_SHASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHSAX, ARM_INS_SHSAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHSUB16, ARM_INS_SHSUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SHSUB8, ARM_INS_SHSUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SMC, ARM_INS_SMC, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 },
- { ARM_SMLABB, ARM_INS_SMLABB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLABT, ARM_INS_SMLABT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLAD, ARM_INS_SMLAD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLADX, ARM_INS_SMLADX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLAL, ARM_INS_SMLAL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLALBB, ARM_INS_SMLALBB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMLALBT, ARM_INS_SMLALBT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMLALD, ARM_INS_SMLALD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLALDX, ARM_INS_SMLALDX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLALTB, ARM_INS_SMLALTB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMLALTT, ARM_INS_SMLALTT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMLATB, ARM_INS_SMLATB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLATT, ARM_INS_SMLATT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLAWB, ARM_INS_SMLAWB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLAWT, ARM_INS_SMLAWT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMLSD, ARM_INS_SMLSD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLSDX, ARM_INS_SMLSDX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLSLD, ARM_INS_SMLSLD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMLSLDX, ARM_INS_SMLSLDX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMMLA, ARM_INS_SMMLA, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMMLAR, ARM_INS_SMMLAR, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMMLS, ARM_INS_SMMLS, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_SMMLSR, ARM_INS_SMMLSR, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMMUL, ARM_INS_SMMUL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMMULR, ARM_INS_SMMULR, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMUAD, ARM_INS_SMUAD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMUADX, ARM_INS_SMUADX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMULBB, ARM_INS_SMULBB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMULBT, ARM_INS_SMULBT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMULL, ARM_INS_SMULL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMULTB, ARM_INS_SMULTB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMULTT, ARM_INS_SMULTT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMULWB, ARM_INS_SMULWB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMULWT, ARM_INS_SMULWT, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_SMUSD, ARM_INS_SMUSD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SMUSDX, ARM_INS_SMUSDX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SRSDA, ARM_INS_SRSDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSDA_UPD, ARM_INS_SRSDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSDB, ARM_INS_SRSDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSDB_UPD, ARM_INS_SRSDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSIA, ARM_INS_SRSIA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSIA_UPD, ARM_INS_SRSIA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSIB, ARM_INS_SRSIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SRSIB_UPD, ARM_INS_SRSIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SSAT, ARM_INS_SSAT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SSAT16, ARM_INS_SSAT16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SSAX, ARM_INS_SSAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SSUB16, ARM_INS_SSUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SSUB8, ARM_INS_SSUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STC2L_OFFSET, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2L_OPTION, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2L_POST, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2L_PRE, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2_OFFSET, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2_OPTION, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2_POST, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STC2_PRE, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_STCL_OFFSET, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STCL_OPTION, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STCL_POST, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STCL_PRE, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STC_OFFSET, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STC_OPTION, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STC_POST, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STC_PRE, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STL, ARM_INS_STL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLB, ARM_INS_STLB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLEX, ARM_INS_STLEX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLEXB, ARM_INS_STLEXB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLEXD, ARM_INS_STLEXD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLEXH, ARM_INS_STLEXH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STLH, ARM_INS_STLH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_STMDA, ARM_INS_STMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMDA_UPD, ARM_INS_STMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMDB, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMDB_UPD, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMIA, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMIA_UPD, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMIB, ARM_INS_STMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STMIB_UPD, ARM_INS_STMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRBT_POST_IMM, ARM_INS_STRBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRBT_POST_REG, ARM_INS_STRBT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRB_POST_IMM, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRB_POST_REG, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRB_PRE_IMM, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRB_PRE_REG, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRBi12, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRBrs, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRD, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_STRD_PAIR, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 },
- { ARM_STRD_POST, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRD_PRE, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STREX, ARM_INS_STREX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STREXB, ARM_INS_STREXB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STREXD, ARM_INS_STREXD, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STREXH, ARM_INS_STREXH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRH, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRHTi, ARM_INS_STRHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRHTr, ARM_INS_STRHT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRH_POST, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRH_PRE, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRT_POST_IMM, ARM_INS_STRT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRT_POST_REG, ARM_INS_STRT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STR_POST_IMM, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STR_POST_REG, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STR_PRE_IMM, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STR_PRE_REG, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRi12, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_STRrs, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SUBri, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SUBrr, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SUBrsi, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SUBrsr, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SVC, ARM_INS_SVC, { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_SWP, ARM_INS_SWP, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_SWPB, ARM_INS_SWPB, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_SXTAB, ARM_INS_SXTAB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SXTAB16, ARM_INS_SXTAB16, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SXTAH, ARM_INS_SXTAH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SXTB, ARM_INS_SXTB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SXTB16, ARM_INS_SXTB16, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_SXTH, ARM_INS_SXTH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_TEQri, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TEQrr, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TEQrsi, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TEQrsr, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TRAP, ARM_INS_TRAP, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TRAPNaCl, ARM_INS_TRAP, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TSTri, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TSTrr, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TSTrsi, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_TSTrsr, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UADD16, ARM_INS_UADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UADD8, ARM_INS_UADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UASX, ARM_INS_UASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UBFX, ARM_INS_UBFX, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 },
- { ARM_UDIV, ARM_INS_UDIV, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHADD16, ARM_INS_UHADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHADD8, ARM_INS_UHADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHASX, ARM_INS_UHASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHSAX, ARM_INS_UHSAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHSUB16, ARM_INS_UHSUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UHSUB8, ARM_INS_UHSUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UMAAL, ARM_INS_UMAAL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UMLAL, ARM_INS_UMLAL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UMULL, ARM_INS_UMULL, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UQADD16, ARM_INS_UQADD16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UQADD8, ARM_INS_UQADD8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UQASX, ARM_INS_UQASX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UQSAX, ARM_INS_UQSAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UQSUB16, ARM_INS_UQSUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UQSUB8, ARM_INS_UQSUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_USAD8, ARM_INS_USAD8, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_USADA8, ARM_INS_USADA8, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_USAT, ARM_INS_USAT, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_USAT16, ARM_INS_USAT16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_USAX, ARM_INS_USAX, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_USUB16, ARM_INS_USUB16, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_USUB8, ARM_INS_USUB8, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_UXTAB, ARM_INS_UXTAB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UXTAB16, ARM_INS_UXTAB16, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UXTAH, ARM_INS_UXTAH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UXTB, ARM_INS_UXTB, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UXTB16, ARM_INS_UXTB16, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_UXTH, ARM_INS_UXTH, { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_VABALsv2i64, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABALsv4i32, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABALsv8i16, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABALuv2i64, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABALuv4i32, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABALuv8i16, ARM_INS_VABAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv16i8, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv2i32, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv4i16, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv4i32, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv8i16, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAsv8i8, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv16i8, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv2i32, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv4i16, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv4i32, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv8i16, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABAuv8i8, ARM_INS_VABA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLsv2i64, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLsv4i32, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLsv8i16, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLuv2i64, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLuv4i32, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDLuv8i16, ARM_INS_VABDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDfd, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDfq, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv16i8, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv2i32, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv4i16, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv4i32, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv8i16, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDsv8i8, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv16i8, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv2i32, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv4i16, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv4i32, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv8i16, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABDuv8i8, ARM_INS_VABD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSD, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VABSS, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VABSfd, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSfq, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv16i8, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv2i32, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv4i16, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv4i32, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv8i16, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VABSv8i8, ARM_INS_VABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VACGEd, ARM_INS_VACGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VACGEq, ARM_INS_VACGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VACGTd, ARM_INS_VACGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VACGTq, ARM_INS_VACGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDD, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VADDHNv2i32, ARM_INS_VADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDHNv4i16, ARM_INS_VADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDHNv8i8, ARM_INS_VADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLsv2i64, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLsv4i32, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLsv8i16, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLuv2i64, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLuv4i32, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDLuv8i16, ARM_INS_VADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDS, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VADDWsv2i64, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDWsv4i32, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDWsv8i16, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDWuv2i64, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDWuv4i32, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDWuv8i16, ARM_INS_VADDW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDfd, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDfq, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv16i8, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv1i64, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv2i32, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv2i64, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv4i16, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv4i32, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv8i16, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VADDv8i8, ARM_INS_VADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VANDd, ARM_INS_VAND, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VANDq, ARM_INS_VAND, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICd, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICiv2i32, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICiv4i16, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICiv4i32, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICiv8i16, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBICq, ARM_INS_VBIC, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBIFd, ARM_INS_VBIF, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBIFq, ARM_INS_VBIF, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBITd, ARM_INS_VBIT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBITq, ARM_INS_VBIT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBSLd, ARM_INS_VBSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VBSLq, ARM_INS_VBSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQfd, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQfq, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv16i8, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv2i32, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv4i16, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv4i32, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv8i16, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCEQv8i8, ARM_INS_VCEQ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEfd, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEfq, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv16i8, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv2i32, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv4i16, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv4i32, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv8i16, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEsv8i8, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv16i8, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv2i32, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv4i16, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv4i32, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv8i16, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGEuv8i8, ARM_INS_VCGE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTfd, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTfq, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv16i8, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv2i32, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv4i16, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv4i32, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv8i16, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTsv8i8, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv16i8, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv2i32, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv4i16, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv4i32, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv8i16, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCGTuv8i8, ARM_INS_VCGT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv16i8, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv2i32, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv4i16, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv4i32, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv8i16, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLSv8i8, ARM_INS_VCLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv16i8, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv2i32, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv4i16, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv4i32, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv8i16, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCLZv8i8, ARM_INS_VCLZ, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCMPD, ARM_INS_VCMP, { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCMPED, ARM_INS_VCMPE, { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCMPES, ARM_INS_VCMPE, { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCMPS, ARM_INS_VCMP, { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCNTd, ARM_INS_VCNT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCNTq, ARM_INS_VCNT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTANSD, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTANSQ, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTANUD, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTANUQ, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTASD, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTASS, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTAUD, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTAUS, ARM_INS_VCVTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTBDH, ARM_INS_VCVTB, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTBHD, ARM_INS_VCVTB, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTBHS, ARM_INS_VCVTB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCVTBSH, ARM_INS_VCVTB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCVTDS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCVTMNSD, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTMNSQ, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTMNUD, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTMNUQ, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTMSD, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTMSS, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTMUD, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTMUS, ARM_INS_VCVTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTNNSD, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTNNSQ, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTNNUD, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTNNUQ, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTNSD, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTNSS, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTNUD, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTNUS, ARM_INS_VCVTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTPNSD, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTPNSQ, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTPNUD, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTPNUQ, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTPSD, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTPSS, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTPUD, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTPUS, ARM_INS_VCVTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VCVTSD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTTDH, ARM_INS_VCVTT, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTTHD, ARM_INS_VCVTT, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VCVTTHS, ARM_INS_VCVTT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCVTTSH, ARM_INS_VCVTT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VCVTf2h, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2sd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2sq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2ud, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2uq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2xsd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2xsq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2xud, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTf2xuq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTh2f, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTs2fd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTs2fq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTu2fd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTu2fq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTxs2fd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTxs2fq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTxu2fd, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VCVTxu2fq, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDIVD, ARM_INS_VDIV, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VDIVS, ARM_INS_VDIV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VDUP16d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUP16q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUP32d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUP32q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUP8d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUP8q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN16d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN16q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN32d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN32q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN8d, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VDUPLN8q, ARM_INS_VDUP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEORd, ARM_INS_VEOR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEORq, ARM_INS_VEOR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTd16, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTd32, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTd8, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTq16, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTq32, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTq64, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VEXTq8, ARM_INS_VEXT, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VFMAD, ARM_INS_VFMA, { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VFMAS, ARM_INS_VFMA, { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFMAfd, ARM_INS_VFMA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFMAfq, ARM_INS_VFMA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFMSD, ARM_INS_VFMS, { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VFMSS, ARM_INS_VFMS, { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFMSfd, ARM_INS_VFMS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFMSfq, ARM_INS_VFMS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFNMAD, ARM_INS_VFNMA, { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VFNMAS, ARM_INS_VFNMA, { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VFNMSD, ARM_INS_VFNMS, { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VFNMSS, ARM_INS_VFNMS, { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 },
- { ARM_VGETLNi32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VGETLNs16, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VGETLNs8, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VGETLNu16, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VGETLNu8, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv16i8, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv2i32, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv4i16, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv4i32, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv8i16, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDsv8i8, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv16i8, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv2i32, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv4i16, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv4i32, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv8i16, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHADDuv8i8, ARM_INS_VHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv16i8, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv2i32, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv4i16, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv4i32, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv8i16, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBsv8i8, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv16i8, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv2i32, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv4i16, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv4i32, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv8i16, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VHSUBuv8i8, ARM_INS_VHSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd16, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd32, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd8, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq16, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq32, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq8, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd16, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd16_UPD, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd32, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd32_UPD, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd8, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1LNd8_UPD, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16Q, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16Qwb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16T, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16Twb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d16wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32Q, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32Qwb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32T, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32Twb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d32wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64Q, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64Qwb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64T, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64Twb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d64wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8Q, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8Qwb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8T, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8Twb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1d8wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q16, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q16wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q16wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q32, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q32wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q32wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q64, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q64wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q64wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q8, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q8wb_fixed, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD1q8wb_register, ARM_INS_VLD1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16x2, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32x2, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8x2, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd16_UPD, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd32_UPD, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd8, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNd8_UPD, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNq16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNq16_UPD, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNq32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2LNq32_UPD, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b16wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b16wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b32wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b32wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b8, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b8wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2b8wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d16wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d16wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d32wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d32wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d8, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d8wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2d8wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q16, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q16wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q16wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q32, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q32wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q32wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q8, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q8wb_fixed, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD2q8wb_register, ARM_INS_VLD2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd8, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq8, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd8, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNd8_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNq16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNq16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNq32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3LNq32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d8, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3d8_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q16, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q16_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q32, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q32_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q8, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD3q8_UPD, ARM_INS_VLD3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd8, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq8, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd8, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNd8_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNq16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNq16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNq32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4LNq32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d8, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4d8_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q16, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q16_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q32, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q32_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q8, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLD4q8_UPD, ARM_INS_VLD4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDMDIA, ARM_INS_VLDMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDMSIA, ARM_INS_VLDMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDRD, ARM_INS_VLDR, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VLDRS, ARM_INS_VLDR, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMAXNMD, ARM_INS_VMAXNM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VMAXNMND, ARM_INS_VMAXNM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXNMNQ, ARM_INS_VMAXNM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXNMS, ARM_INS_VMAXNM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VMAXfd, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXfq, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv16i8, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv2i32, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv4i16, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv4i32, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv8i16, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXsv8i8, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv16i8, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv2i32, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv4i16, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv4i32, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv8i16, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMAXuv8i8, ARM_INS_VMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINNMD, ARM_INS_VMINNM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VMINNMND, ARM_INS_VMINNM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINNMNQ, ARM_INS_VMINNM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINNMS, ARM_INS_VMINNM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VMINfd, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINfq, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv16i8, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv2i32, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv4i16, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv4i32, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv8i16, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINsv8i8, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv16i8, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv2i32, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv4i16, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv4i32, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv8i16, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMINuv8i8, ARM_INS_VMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAD, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLALslsv2i32, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALslsv4i16, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALsluv2i32, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALsluv4i16, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALsv2i64, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALsv4i32, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALsv8i16, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALuv2i64, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALuv4i32, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLALuv8i16, ARM_INS_VMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAS, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLAfd, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLAfq, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLAslfd, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLAslfq, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLAslv2i32, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAslv4i16, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAslv4i32, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAslv8i16, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv16i8, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv2i32, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv4i16, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv4i32, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv8i16, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLAv8i8, ARM_INS_VMLA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSD, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSLslsv2i32, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLslsv4i16, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLsluv2i32, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLsluv4i16, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLsv2i64, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLsv4i32, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLsv8i16, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLuv2i64, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLuv4i32, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSLuv8i16, ARM_INS_VMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSS, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSfd, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSfq, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSslfd, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSslfq, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VMLSslv2i32, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSslv4i16, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSslv4i32, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSslv8i16, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv16i8, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv2i32, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv4i16, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv4i32, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv8i16, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMLSv8i8, ARM_INS_VMLS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVD, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VMOVDRR, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVLsv2i64, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVLsv4i32, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVLsv8i16, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVLuv2i64, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVLuv4i32, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVLuv8i16, ARM_INS_VMOVL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVNv2i32, ARM_INS_VMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVNv4i16, ARM_INS_VMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVNv8i8, ARM_INS_VMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVRRD, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVRRS, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVRS, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVS, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVSR, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVSRR, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMOVv16i8, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv1i64, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv2f32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv2i32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv2i64, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv4f32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv4i16, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv4i32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv8i16, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMOVv8i8, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMRS, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_FPEXC, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_FPINST, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_FPINST2, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_FPSID, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_MVFR0, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_MVFR1, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMRS_MVFR2, ARM_INS_VMRS, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VMSR, ARM_INS_VMSR, { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMSR_FPEXC, ARM_INS_VMSR, { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMSR_FPINST, ARM_INS_VMSR, { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMSR_FPINST2, ARM_INS_VMSR, { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMSR_FPSID, ARM_INS_VMSR, { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMULD, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VMULLp64, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 },
- { ARM_VMULLp8, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLslsv2i32, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLslsv4i16, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLsluv2i32, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLsluv4i16, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLsv2i64, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLsv4i32, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLsv8i16, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLuv2i64, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLuv4i32, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULLuv8i16, ARM_INS_VMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULS, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VMULfd, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULfq, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULpd, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULpq, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslfd, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslfq, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslv2i32, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslv4i16, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslv4i32, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULslv8i16, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv16i8, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv2i32, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv4i16, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv4i32, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv8i16, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMULv8i8, ARM_INS_VMUL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNd, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNq, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNv2i32, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNv4i16, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNv4i32, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VMVNv8i16, ARM_INS_VMVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGD, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VNEGS, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VNEGf32q, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGfd, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs16d, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs16q, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs32d, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs32q, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs8d, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNEGs8q, ARM_INS_VNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VNMLAD, ARM_INS_VNMLA, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VNMLAS, ARM_INS_VNMLA, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VNMLSD, ARM_INS_VNMLS, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VNMLSS, ARM_INS_VNMLS, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 },
- { ARM_VNMULD, ARM_INS_VNMUL, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VNMULS, ARM_INS_VNMUL, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VORNd, ARM_INS_VORN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORNq, ARM_INS_VORN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRd, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRiv2i32, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRiv4i16, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRiv4i32, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRiv8i16, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VORRq, ARM_INS_VORR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv16i8, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv2i32, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv4i16, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv4i32, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv8i16, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALsv8i8, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv16i8, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv2i32, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv4i16, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv4i32, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv8i16, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADALuv8i8, ARM_INS_VPADAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv16i8, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv2i32, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv4i16, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv4i32, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv8i16, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLsv8i8, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv16i8, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv2i32, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv4i16, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv4i32, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv8i16, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDLuv8i8, ARM_INS_VPADDL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDf, ARM_INS_VPADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDi16, ARM_INS_VPADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDi32, ARM_INS_VPADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPADDi8, ARM_INS_VPADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXf, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXs16, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXs32, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXs8, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXu16, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXu32, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMAXu8, ARM_INS_VPMAX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINf, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINs16, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINs32, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINs8, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINu16, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINu32, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VPMINu8, ARM_INS_VPMIN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv16i8, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv2i32, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv4i16, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv4i32, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv8i16, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQABSv8i8, ARM_INS_VQABS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv16i8, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv1i64, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv2i32, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv2i64, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv4i16, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv4i32, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv8i16, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDsv8i8, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv16i8, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv1i64, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv2i32, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv2i64, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv4i16, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv4i32, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv8i16, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQADDuv8i8, ARM_INS_VQADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHv2i32, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHv4i16, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHv4i32, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULHv8i16, ARM_INS_VQDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULLv2i64, ARM_INS_VQDMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQDMULLv4i32, ARM_INS_VQDMULL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv16i8, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv2i32, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv4i16, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv4i32, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv8i16, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQNEGv8i8, ARM_INS_VQNEG, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv16i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv1i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv2i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv2i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv4i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv4i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv8i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsiv8i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv16i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv1i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv2i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv2i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv4i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv4i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv8i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLsv8i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv16i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv1i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv2i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv2i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv4i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv4i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv8i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuiv8i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv16i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv1i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv2i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv2i64, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv4i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv4i32, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv8i16, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHLuv8i8, ARM_INS_VQSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv16i8, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv1i64, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv2i32, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv2i64, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv4i16, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv4i32, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv8i16, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBsv8i8, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv16i8, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv1i64, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv2i32, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv2i64, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv4i16, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv4i32, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv8i16, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VQSUBuv8i8, ARM_INS_VQSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRADDHNv2i32, ARM_INS_VRADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRADDHNv4i16, ARM_INS_VRADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRADDHNv8i8, ARM_INS_VRADDHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPEd, ARM_INS_VRECPE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPEfd, ARM_INS_VRECPE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPEfq, ARM_INS_VRECPE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPEq, ARM_INS_VRECPE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPSfd, ARM_INS_VRECPS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRECPSfq, ARM_INS_VRECPS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV16d8, ARM_INS_VREV16, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV16q8, ARM_INS_VREV16, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV32d16, ARM_INS_VREV32, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV32d8, ARM_INS_VREV32, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV32q16, ARM_INS_VREV32, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV32q8, ARM_INS_VREV32, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64d16, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64d32, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64d8, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64q16, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64q32, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VREV64q8, ARM_INS_VREV64, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv16i8, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv2i32, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv4i16, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv4i32, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv8i16, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDsv8i8, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv16i8, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv2i32, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv4i16, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv4i32, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv8i16, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRHADDuv8i8, ARM_INS_VRHADD, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTAD, ARM_INS_VRINTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTAND, ARM_INS_VRINTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTANQ, ARM_INS_VRINTA, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTAS, ARM_INS_VRINTA, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTMD, ARM_INS_VRINTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTMND, ARM_INS_VRINTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTMNQ, ARM_INS_VRINTM, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTMS, ARM_INS_VRINTM, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTND, ARM_INS_VRINTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTNND, ARM_INS_VRINTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTNNQ, ARM_INS_VRINTN, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTNS, ARM_INS_VRINTN, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTPD, ARM_INS_VRINTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTPND, ARM_INS_VRINTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTPNQ, ARM_INS_VRINTP, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTPS, ARM_INS_VRINTP, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTRD, ARM_INS_VRINTR, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTRS, ARM_INS_VRINTR, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTXD, ARM_INS_VRINTX, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTXND, ARM_INS_VRINTX, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTXNQ, ARM_INS_VRINTX, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTXS, ARM_INS_VRINTX, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRINTZD, ARM_INS_VRINTZ, { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VRINTZND, ARM_INS_VRINTZ, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTZNQ, ARM_INS_VRINTZ, { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRINTZS, ARM_INS_VRINTZ, { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VRSHLsv16i8, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv1i64, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv2i32, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv2i64, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv4i16, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv4i32, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv8i16, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLsv8i8, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv16i8, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv1i64, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv2i32, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv2i64, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv4i16, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv4i32, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv8i16, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHLuv8i8, ARM_INS_VRSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRNv2i32, ARM_INS_VRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRNv4i16, ARM_INS_VRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRNv8i8, ARM_INS_VRSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv16i8, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv1i64, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv2i32, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv2i64, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv4i16, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv4i32, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv8i16, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRsv8i8, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv16i8, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv1i64, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv2i32, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv2i64, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv4i16, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv4i32, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv8i16, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSHRuv8i8, ARM_INS_VRSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTEd, ARM_INS_VRSQRTE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTEfd, ARM_INS_VRSQRTE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTEfq, ARM_INS_VRSQRTE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTEq, ARM_INS_VRSQRTE, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTSfd, ARM_INS_VRSQRTS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSQRTSfq, ARM_INS_VRSQRTS, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv16i8, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv1i64, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv2i32, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv2i64, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv4i16, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv4i32, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv8i16, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAsv8i8, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv16i8, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv1i64, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv2i32, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv2i64, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv4i16, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv4i32, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv8i16, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSRAuv8i8, ARM_INS_VRSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSELEQD, ARM_INS_VSELEQ, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSELEQS, ARM_INS_VSELEQ, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VSELGED, ARM_INS_VSELGE, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSELGES, ARM_INS_VSELGE, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VSELGTD, ARM_INS_VSELGT, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSELGTS, ARM_INS_VSELGT, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VSELVSD, ARM_INS_VSELVS, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSELVSS, ARM_INS_VSELVS, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 },
- { ARM_VSETLNi16, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSETLNi32, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSETLNi8, ARM_INS_VMOV, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLi16, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLi32, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLi8, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLsv2i64, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLsv4i32, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLsv8i16, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLuv2i64, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLuv4i32, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLLuv8i16, ARM_INS_VSHLL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv16i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv1i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv2i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv2i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv4i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv4i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv8i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLiv8i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv16i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv1i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv2i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv2i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv4i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv4i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv8i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLsv8i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv16i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv1i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv2i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv2i64, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv4i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv4i32, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv8i16, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHLuv8i8, ARM_INS_VSHL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRNv2i32, ARM_INS_VSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRNv4i16, ARM_INS_VSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRNv8i8, ARM_INS_VSHRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv16i8, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv1i64, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv2i32, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv2i64, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv4i16, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv4i32, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv8i16, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRsv8i8, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv16i8, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv1i64, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv2i32, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv2i64, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv4i16, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv4i32, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv8i16, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHRuv8i8, ARM_INS_VSHR, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSHTOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSHTOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSITOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSITOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSLIv16i8, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv1i64, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv2i32, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv2i64, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv4i16, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv4i32, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv8i16, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLIv8i8, ARM_INS_VSLI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSLTOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSLTOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSQRTD, ARM_INS_VSQRT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSQRTS, ARM_INS_VSQRT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSRAsv16i8, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv1i64, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv2i32, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv2i64, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv4i16, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv4i32, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv8i16, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAsv8i8, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv16i8, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv1i64, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv2i32, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv2i64, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv4i16, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv4i32, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv8i16, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRAuv8i8, ARM_INS_VSRA, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv16i8, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv1i64, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv2i32, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv2i64, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv4i16, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv4i32, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv8i16, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSRIv8i8, ARM_INS_VSRI, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd16, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd16_UPD, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd32, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd32_UPD, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd8, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1LNd8_UPD, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16Q, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16Qwb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16Qwb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16T, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16Twb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16Twb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d16wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32Q, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32Qwb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32Qwb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32T, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32Twb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32Twb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d32wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64Q, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64Qwb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64Qwb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64T, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64Twb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64Twb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d64wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8Q, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8Qwb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8Qwb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8T, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8Twb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8Twb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1d8wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q16, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q16wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q16wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q32, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q32wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q32wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q64, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q64wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q64wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q8, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q8wb_fixed, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST1q8wb_register, ARM_INS_VST1, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd16, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd16_UPD, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd32, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd32_UPD, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd8, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNd8_UPD, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNq16, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNq16_UPD, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNq32, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2LNq32_UPD, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b16, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b16wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b16wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b32, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b32wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b32wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b8, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b8wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2b8wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d16, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d16wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d16wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d32, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d32wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d32wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d8, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d8wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2d8wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q16, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q16wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q16wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q32, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q32wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q32wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q8, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q8wb_fixed, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST2q8wb_register, ARM_INS_VST2, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd16, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd16_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd32, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd32_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd8, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNd8_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNq16, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNq16_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNq32, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3LNq32_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d16, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d16_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d32, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d32_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d8, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3d8_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q16, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q16_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q32, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q32_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q8, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST3q8_UPD, ARM_INS_VST3, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd16, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd16_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd32, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd32_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd8, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNd8_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNq16, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNq16_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNq32, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4LNq32_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d16, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d16_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d32, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d32_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d8, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4d8_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q16, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q16_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q32, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q32_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q8, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VST4q8_UPD, ARM_INS_VST4, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTMDIA, ARM_INS_VSTMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTMSIA, ARM_INS_VSTMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTRD, ARM_INS_VSTR, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSTRS, ARM_INS_VSTR, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSUBD, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VSUBHNv2i32, ARM_INS_VSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBHNv4i16, ARM_INS_VSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBHNv8i8, ARM_INS_VSUBHN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLsv2i64, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLsv4i32, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLsv8i16, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLuv2i64, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLuv4i32, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBLuv8i16, ARM_INS_VSUBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBS, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VSUBWsv2i64, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBWsv4i32, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBWsv8i16, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBWuv2i64, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBWuv4i32, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBWuv8i16, ARM_INS_VSUBW, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBfd, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBfq, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv16i8, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv1i64, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv2i32, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv2i64, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv4i16, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv4i32, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv8i16, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSUBv8i8, ARM_INS_VSUB, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSWPd, ARM_INS_VSWP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VSWPq, ARM_INS_VSWP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBL1, ARM_INS_VTBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBL2, ARM_INS_VTBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBL3, ARM_INS_VTBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBL4, ARM_INS_VTBL, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBX1, ARM_INS_VTBX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBX2, ARM_INS_VTBX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBX3, ARM_INS_VTBX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTBX4, ARM_INS_VTBX, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTOSHD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOSHS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOSIRD, ARM_INS_VCVTR, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOSIRS, ARM_INS_VCVTR, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOSIZD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOSIZS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOSLD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOSLS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOUHD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOUHS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOUIRD, ARM_INS_VCVTR, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOUIRS, ARM_INS_VCVTR, { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOUIZD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOUIZS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTOULD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VTOULS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VTRNd16, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTRNd32, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTRNd8, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTRNq16, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTRNq32, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTRNq8, ARM_INS_VTRN, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv16i8, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv2i32, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv4i16, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv4i32, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv8i16, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VTSTv8i8, ARM_INS_VTST, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VUHTOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VUHTOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VUITOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VUITOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VULTOD, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 },
- { ARM_VULTOS, ARM_INS_VCVT, { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 },
- { ARM_VUZPd16, ARM_INS_VUZP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VUZPd8, ARM_INS_VUZP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VUZPq16, ARM_INS_VUZP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VUZPq32, ARM_INS_VUZP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VUZPq8, ARM_INS_VUZP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VZIPd16, ARM_INS_VZIP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VZIPd8, ARM_INS_VZIP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VZIPq16, ARM_INS_VZIP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VZIPq32, ARM_INS_VZIP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_VZIPq8, ARM_INS_VZIP, { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 },
- { ARM_sysLDMDA, ARM_INS_LDMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMDA_UPD, ARM_INS_LDMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMDB, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMDB_UPD, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMIA, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMIA_UPD, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMIB, ARM_INS_LDMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysLDMIB_UPD, ARM_INS_LDMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMDA, ARM_INS_STMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMDA_UPD, ARM_INS_STMDA, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMDB, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMDB_UPD, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMIA, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMIA_UPD, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMIB, ARM_INS_STMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_sysSTMIB_UPD, ARM_INS_STMIB, { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 },
- { ARM_t2ADCri, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADCrr, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADCrs, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADDri, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADDri12, ARM_INS_ADDW, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADDrr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADDrs, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ADR, ARM_INS_ADR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ANDri, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ANDrr, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ANDrs, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ASRri, ARM_INS_ASR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ASRrr, ARM_INS_ASR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2B, ARM_INS_B, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 },
- { ARM_t2BFC, ARM_INS_BFC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2BFI, ARM_INS_BFI, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2BICri, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2BICrr, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2BICrs, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2BXJ, ARM_INS_BXJ, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2Bcc, ARM_INS_B, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 },
- { ARM_t2CDP, ARM_INS_CDP, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2CDP2, ARM_INS_CDP2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2CLREX, ARM_INS_CLREX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_t2CLZ, ARM_INS_CLZ, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMNri, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMNzrr, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMNzrs, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMPri, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMPrr, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CMPrs, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CPS1p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CPS2p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CPS3p, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2CRC32B, ARM_INS_CRC32B, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2CRC32CB, ARM_INS_CRC32CB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2CRC32CH, ARM_INS_CRC32CH, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2CRC32CW, ARM_INS_CRC32CW, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2CRC32H, ARM_INS_CRC32H, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2CRC32W, ARM_INS_CRC32W, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 },
- { ARM_t2DBG, ARM_INS_DBG, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2DCPS1, ARM_INS_DCPS1, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2DCPS2, ARM_INS_DCPS2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2DCPS3, ARM_INS_DCPS3, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2DMB, ARM_INS_DMB, { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_t2DSB, ARM_INS_DSB, { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_t2EORri, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2EORrr, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2EORrs, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2HINT, ARM_INS_HINT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ISB, ARM_INS_ISB, { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0 },
- { ARM_t2IT, ARM_INS_IT, { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDA, ARM_INS_LDA, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAB, ARM_INS_LDAB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAEX, ARM_INS_LDAEX, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAEXB, ARM_INS_LDAEXB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAEXD, ARM_INS_LDAEXD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAEXH, ARM_INS_LDAEXH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDAH, ARM_INS_LDAH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2L_POST, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2L_PRE, ARM_INS_LDC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2_OFFSET, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2_OPTION, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2_POST, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDC2_PRE, ARM_INS_LDC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2LDCL_OFFSET, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDCL_OPTION, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDCL_POST, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDCL_PRE, ARM_INS_LDCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDC_OFFSET, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDC_OPTION, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDC_POST, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDC_PRE, ARM_INS_LDC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDMDB, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDMDB_UPD, ARM_INS_LDMDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDMIA, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDMIA_UPD, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRBT, ARM_INS_LDRBT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRB_POST, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRB_PRE, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRBi12, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRBi8, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRBpci, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRBs, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRD_POST, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRD_PRE, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRDi8, ARM_INS_LDRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDREX, ARM_INS_LDREX, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDREXB, ARM_INS_LDREXB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDREXD, ARM_INS_LDREXD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDREXH, ARM_INS_LDREXH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRHT, ARM_INS_LDRHT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRH_POST, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRH_PRE, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRHi12, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRHi8, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRHpci, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRHs, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSBT, ARM_INS_LDRSBT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSB_POST, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSB_PRE, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSBi12, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSBi8, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSBpci, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSBs, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSHT, ARM_INS_LDRSHT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSH_POST, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSH_PRE, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSHi12, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSHi8, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSHpci, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRSHs, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRT, ARM_INS_LDRT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDR_POST, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDR_PRE, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRi12, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRi8, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRpci, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LDRs, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LSLri, ARM_INS_LSL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LSLrr, ARM_INS_LSL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LSRri, ARM_INS_LSR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2LSRrr, ARM_INS_LSR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MCR, ARM_INS_MCR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MCR2, ARM_INS_MCR2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2MCRR, ARM_INS_MCRR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MCRR2, ARM_INS_MCRR2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2MLA, ARM_INS_MLA, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2MLS, ARM_INS_MLS, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2MOVTi16, ARM_INS_MOVT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MOVi, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MOVi16, ARM_INS_MOVW, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MOVr, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MRC, ARM_INS_MRC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MRC2, ARM_INS_MRC2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2MRRC, ARM_INS_MRRC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MRRC2, ARM_INS_MRRC2, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2MRS_AR, ARM_INS_MRS, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 },
- { ARM_t2MRS_M, ARM_INS_MRS, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 },
- { ARM_t2MRSsys_AR, ARM_INS_MRS, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 },
- { ARM_t2MSR_AR, ARM_INS_MSR, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 },
- { ARM_t2MSR_M, ARM_INS_MSR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 },
- { ARM_t2MUL, ARM_INS_MUL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MVNi, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MVNr, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2MVNs, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORNri, ARM_INS_ORN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORNrr, ARM_INS_ORN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORNrs, ARM_INS_ORN, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORRri, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORRrr, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2ORRrs, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PKHBT, ARM_INS_PKHBT, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PKHTB, ARM_INS_PKHTB, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PLDWi12, ARM_INS_PLDW, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 },
- { ARM_t2PLDWi8, ARM_INS_PLDW, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 },
- { ARM_t2PLDWs, ARM_INS_PLDW, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 },
- { ARM_t2PLDi12, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PLDi8, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PLDpci, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PLDs, ARM_INS_PLD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2PLIi12, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_t2PLIi8, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_t2PLIpci, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_t2PLIs, ARM_INS_PLI, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 },
- { ARM_t2QADD, ARM_INS_QADD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QADD16, ARM_INS_QADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QADD8, ARM_INS_QADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QASX, ARM_INS_QASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QDADD, ARM_INS_QDADD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QDSUB, ARM_INS_QDSUB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QSAX, ARM_INS_QSAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QSUB, ARM_INS_QSUB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QSUB16, ARM_INS_QSUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2QSUB8, ARM_INS_QSUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2RBIT, ARM_INS_RBIT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2REV, ARM_INS_REV, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2REV16, ARM_INS_REV16, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2REVSH, ARM_INS_REVSH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RFEDB, ARM_INS_RFEDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RFEDBW, ARM_INS_RFEDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RFEIA, ARM_INS_RFEIA, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RFEIAW, ARM_INS_RFEIA, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RORri, ARM_INS_ROR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RORrr, ARM_INS_ROR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RRX, ARM_INS_RRX, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RSBri, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RSBrr, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2RSBrs, ARM_INS_RSB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SADD16, ARM_INS_SADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SADD8, ARM_INS_SADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SASX, ARM_INS_SASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SBCri, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SBCrr, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SBCrs, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SBFX, ARM_INS_SBFX, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SDIV, ARM_INS_SDIV, { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SEL, ARM_INS_SEL, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHADD16, ARM_INS_SHADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHADD8, ARM_INS_SHADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHASX, ARM_INS_SHASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHSAX, ARM_INS_SHSAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHSUB16, ARM_INS_SHSUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SHSUB8, ARM_INS_SHSUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMC, ARM_INS_SMC, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 },
- { ARM_t2SMLABB, ARM_INS_SMLABB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLABT, ARM_INS_SMLABT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLAD, ARM_INS_SMLAD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLADX, ARM_INS_SMLADX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLAL, ARM_INS_SMLAL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SMLALBB, ARM_INS_SMLALBB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLALBT, ARM_INS_SMLALBT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLALD, ARM_INS_SMLALD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLALDX, ARM_INS_SMLALDX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLALTB, ARM_INS_SMLALTB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLALTT, ARM_INS_SMLALTT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLATB, ARM_INS_SMLATB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLATT, ARM_INS_SMLATT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLAWB, ARM_INS_SMLAWB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLAWT, ARM_INS_SMLAWT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMLSD, ARM_INS_SMLSD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLSDX, ARM_INS_SMLSDX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLSLD, ARM_INS_SMLSLD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMLSLDX, ARM_INS_SMLSLDX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMMLA, ARM_INS_SMMLA, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMMLAR, ARM_INS_SMMLAR, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMMLS, ARM_INS_SMMLS, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 },
- { ARM_t2SMMLSR, ARM_INS_SMMLSR, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMMUL, ARM_INS_SMMUL, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMMULR, ARM_INS_SMMULR, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMUAD, ARM_INS_SMUAD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMUADX, ARM_INS_SMUADX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULBB, ARM_INS_SMULBB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULBT, ARM_INS_SMULBT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULL, ARM_INS_SMULL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SMULTB, ARM_INS_SMULTB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULTT, ARM_INS_SMULTT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULWB, ARM_INS_SMULWB, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMULWT, ARM_INS_SMULWT, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMUSD, ARM_INS_SMUSD, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SMUSDX, ARM_INS_SMUSDX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SRSDB, ARM_INS_SRSDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SRSDB_UPD, ARM_INS_SRSDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SRSIA, ARM_INS_SRSIA, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SRSIA_UPD, ARM_INS_SRSIA, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SSAT, ARM_INS_SSAT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SSAT16, ARM_INS_SSAT16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SSAX, ARM_INS_SSAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SSUB16, ARM_INS_SSUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2SSUB8, ARM_INS_SSUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2STC2L_OFFSET, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2L_OPTION, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2L_POST, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2L_PRE, ARM_INS_STC2L, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2_OFFSET, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2_OPTION, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2_POST, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STC2_PRE, ARM_INS_STC2, { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 },
- { ARM_t2STCL_OFFSET, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STCL_OPTION, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STCL_POST, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STCL_PRE, ARM_INS_STCL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STC_OFFSET, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STC_OPTION, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STC_POST, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STC_PRE, ARM_INS_STC, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STL, ARM_INS_STL, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLB, ARM_INS_STLB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLEX, ARM_INS_STLEX, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLEXB, ARM_INS_STLEXB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLEXD, ARM_INS_STLEXD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLEXH, ARM_INS_STLEXH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STLH, ARM_INS_STLH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_t2STMDB, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STMDB_UPD, ARM_INS_STMDB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STMIA, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STMIA_UPD, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRBT, ARM_INS_STRBT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRB_POST, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRB_PRE, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRBi12, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRBi8, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRBs, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRD_POST, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRD_PRE, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRDi8, ARM_INS_STRD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STREX, ARM_INS_STREX, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STREXB, ARM_INS_STREXB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STREXD, ARM_INS_STREXD, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STREXH, ARM_INS_STREXH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRHT, ARM_INS_STRHT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRH_POST, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRH_PRE, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRHi12, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRHi8, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRHs, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRT, ARM_INS_STRT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STR_POST, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STR_PRE, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRi12, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRi8, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2STRs, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SUBS_PC_LR, ARM_INS_SUBS, { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SUBri, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SUBri12, ARM_INS_SUBW, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SUBrr, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SUBrs, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SXTAB, ARM_INS_SXTAB, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SXTAB16, ARM_INS_SXTAB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SXTAH, ARM_INS_SXTAH, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SXTB, ARM_INS_SXTB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2SXTB16, ARM_INS_SXTB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 },
- { ARM_t2SXTH, ARM_INS_SXTH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TBB, ARM_INS_TBB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 1 },
- { ARM_t2TBH, ARM_INS_TBH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 1 },
- { ARM_t2TEQri, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TEQrr, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TEQrs, ARM_INS_TEQ, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TSTri, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TSTrr, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2TSTrs, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UADD16, ARM_INS_UADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UADD8, ARM_INS_UADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UASX, ARM_INS_UASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UBFX, ARM_INS_UBFX, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UDIV, ARM_INS_UDIV, { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UHADD16, ARM_INS_UHADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UHADD8, ARM_INS_UHADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UHASX, ARM_INS_UHASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UHSAX, ARM_INS_UHSAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UHSUB16, ARM_INS_UHSUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UHSUB8, ARM_INS_UHSUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UMAAL, ARM_INS_UMAAL, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UMLAL, ARM_INS_UMLAL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UMULL, ARM_INS_UMULL, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UQADD16, ARM_INS_UQADD16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UQADD8, ARM_INS_UQADD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UQASX, ARM_INS_UQASX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UQSAX, ARM_INS_UQSAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UQSUB16, ARM_INS_UQSUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UQSUB8, ARM_INS_UQSUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USAD8, ARM_INS_USAD8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USADA8, ARM_INS_USADA8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USAT, ARM_INS_USAT, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2USAT16, ARM_INS_USAT16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USAX, ARM_INS_USAX, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USUB16, ARM_INS_USUB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2USUB8, ARM_INS_USUB8, { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 },
- { ARM_t2UXTAB, ARM_INS_UXTAB, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UXTAB16, ARM_INS_UXTAB16, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UXTAH, ARM_INS_UXTAH, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UXTB, ARM_INS_UXTB, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UXTB16, ARM_INS_UXTB16, { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_t2UXTH, ARM_INS_UXTH, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 },
- { ARM_tADC, ARM_INS_ADC, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDhirr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDi3, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDi8, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDrSP, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDrSPi, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDrr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDspi, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADDspr, ARM_INS_ADD, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tADR, ARM_INS_ADR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tAND, ARM_INS_AND, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tASRri, ARM_INS_ASR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tASRrr, ARM_INS_ASR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tB, ARM_INS_B, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 },
- { ARM_tBIC, ARM_INS_BIC, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tBKPT, ARM_INS_BKPT, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tBL, ARM_INS_BL, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 },
- { ARM_tBLXi, ARM_INS_BLX, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_tBLXr, ARM_INS_BLX, { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 0 },
- { ARM_tBX, ARM_INS_BX, { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 1, 1 },
- { ARM_tBcc, ARM_INS_B, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 },
- { ARM_tCBNZ, ARM_INS_CBNZ, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 },
- { ARM_tCBZ, ARM_INS_CBZ, { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 },
- { ARM_tCMNz, ARM_INS_CMN, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tCMPhir, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tCMPi8, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tCMPr, ARM_INS_CMP, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tCPS, ARM_INS_CPS, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tEOR, ARM_INS_EOR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tHINT, ARM_INS_HINT, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 },
- { ARM_tHLT, ARM_INS_HLT, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 },
- { ARM_tLDMIA, ARM_INS_LDM, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRBi, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRBr, ARM_INS_LDRB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRHi, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRHr, ARM_INS_LDRH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRSB, ARM_INS_LDRSB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRSH, ARM_INS_LDRSH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRi, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRpci, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRr, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLDRspi, ARM_INS_LDR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLSLri, ARM_INS_LSL, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLSLrr, ARM_INS_LSL, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLSRri, ARM_INS_LSR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tLSRrr, ARM_INS_LSR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tMOVSr, ARM_INS_MOVS, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tMOVi8, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tMOVr, ARM_INS_MOV, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tMUL, ARM_INS_MUL, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tMVN, ARM_INS_MVN, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tORR, ARM_INS_ORR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tPOP, ARM_INS_POP, { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tPUSH, ARM_INS_PUSH, { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tREV, ARM_INS_REV, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tREV16, ARM_INS_REV16, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tREVSH, ARM_INS_REVSH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tROR, ARM_INS_ROR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSBC, ARM_INS_SBC, { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSETEND, ARM_INS_SETEND, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTMIA_UPD, ARM_INS_STM, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRBi, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRBr, ARM_INS_STRB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRHi, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRHr, ARM_INS_STRH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRi, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRr, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSTRspi, ARM_INS_STR, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSUBi3, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSUBi8, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSUBrr, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSUBspi, ARM_INS_SUB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSVC, ARM_INS_SVC, { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tSXTB, ARM_INS_SXTB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tSXTH, ARM_INS_SXTH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tTRAP, ARM_INS_TRAP, { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 },
- { ARM_tTST, ARM_INS_TST, { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 },
- { ARM_tUXTB, ARM_INS_UXTB, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
- { ARM_tUXTH, ARM_INS_UXTH, { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 },
+ {
+ ARM_ADCri, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADCrr, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADCrsi, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADCrsr, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADDri, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADDrr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADDrsi, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADDrsr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ADR, ARM_INS_ADR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_AESD, ARM_INS_AESD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_AESE, ARM_INS_AESE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_AESIMC, ARM_INS_AESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_AESMC, ARM_INS_AESMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ANDri, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ANDrr, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ANDrsi, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ANDrsr, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BFC, ARM_INS_BFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BFI, ARM_INS_BFI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BICri, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BICrr, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BICrsi, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BICrsr, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BKPT, ARM_INS_BKPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BL, ARM_INS_BL,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BLX, ARM_INS_BLX,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BLX_pred, ARM_INS_BLX,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BLXi, ARM_INS_BLX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BL_pred, ARM_INS_BL,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BX, ARM_INS_BX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 1, 1
+#endif
+ },
+ {
+ ARM_BXJ, ARM_INS_BXJ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BX_RET, ARM_INS_BX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_BX_pred, ARM_INS_BX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 1, 1
+#endif
+ },
+ {
+ ARM_Bcc, ARM_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_CDP, ARM_INS_CDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CDP2, ARM_INS_CDP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CLREX, ARM_INS_CLREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CLZ, ARM_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMNri, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMNzrr, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMNzrsi, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMNzrsr, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMPri, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMPrr, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMPrsi, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CMPrsr, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CPS1p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CPS2p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CPS3p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32B, ARM_INS_CRC32B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32CB, ARM_INS_CRC32CB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32CH, ARM_INS_CRC32CH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32CW, ARM_INS_CRC32CW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32H, ARM_INS_CRC32H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_CRC32W, ARM_INS_CRC32W,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_DBG, ARM_INS_DBG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_DMB, ARM_INS_DMB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_DSB, ARM_INS_DSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_EORri, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_EORrr, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_EORrsi, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_EORrsr, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FCONSTD, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FCONSTS, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FLDMXIA, ARM_INS_FLDMIAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FMSTAT, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FSTMXIA, ARM_INS_FSTMIAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_HINT, ARM_INS_HINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_HLT, ARM_INS_HLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ISB, ARM_INS_ISB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDA, ARM_INS_LDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAB, ARM_INS_LDAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAEX, ARM_INS_LDAEX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAEXB, ARM_INS_LDAEXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAEXD, ARM_INS_LDAEXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAEXH, ARM_INS_LDAEXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDAH, ARM_INS_LDAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2L_OFFSET, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2L_OPTION, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2L_POST, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2L_PRE, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2_OFFSET, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2_OPTION, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2_POST, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC2_PRE, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDCL_OFFSET, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDCL_OPTION, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDCL_POST, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDCL_PRE, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC_OFFSET, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC_OPTION, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC_POST, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDC_PRE, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMDA, ARM_INS_LDMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMDA_UPD, ARM_INS_LDMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMDB, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMDB_UPD, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMIA, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMIA_UPD, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMIB, ARM_INS_LDMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDMIB_UPD, ARM_INS_LDMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRBT_POST_IMM, ARM_INS_LDRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRBT_POST_REG, ARM_INS_LDRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRB_POST_IMM, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRB_POST_REG, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRB_PRE_IMM, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRB_PRE_REG, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRBi12, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRBrs, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRD, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRD_PAIR, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRD_POST, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRD_PRE, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDREX, ARM_INS_LDREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDREXB, ARM_INS_LDREXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDREXD, ARM_INS_LDREXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDREXH, ARM_INS_LDREXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRH, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRHTi, ARM_INS_LDRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRHTr, ARM_INS_LDRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRH_POST, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRH_PRE, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSB, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSBTi, ARM_INS_LDRSBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSBTr, ARM_INS_LDRSBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSB_POST, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSB_PRE, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSH, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSHTi, ARM_INS_LDRSHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSHTr, ARM_INS_LDRSHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSH_POST, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRSH_PRE, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRT_POST_IMM, ARM_INS_LDRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRT_POST_REG, ARM_INS_LDRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDR_POST_IMM, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDR_POST_REG, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDR_PRE_IMM, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDR_PRE_REG, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRcp, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRi12, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_LDRrs, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MCR, ARM_INS_MCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MCR2, ARM_INS_MCR2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MCRR, ARM_INS_MCRR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MCRR2, ARM_INS_MCRR2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MLA, ARM_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MLS, ARM_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVPCLR, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVTi16, ARM_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVi, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVi16, ARM_INS_MOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVr, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVr_TC, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVsi, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MOVsr, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRC, ARM_INS_MRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRC2, ARM_INS_MRC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRRC, ARM_INS_MRRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRRC2, ARM_INS_MRRC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRS, ARM_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MRSsys, ARM_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MSR, ARM_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MSRi, ARM_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MUL, ARM_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MVNi, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MVNr, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MVNsi, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_MVNsr, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ORRri, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ORRrr, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ORRrsi, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_ORRrsr, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PKHBT, ARM_INS_PKHBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PKHTB, ARM_INS_PKHTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLDWi12, ARM_INS_PLDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLDWrs, ARM_INS_PLDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLDi12, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLDrs, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLIi12, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_PLIrs, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QADD, ARM_INS_QADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QADD16, ARM_INS_QADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QADD8, ARM_INS_QADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QASX, ARM_INS_QASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QDADD, ARM_INS_QDADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QDSUB, ARM_INS_QDSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QSAX, ARM_INS_QSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QSUB, ARM_INS_QSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QSUB16, ARM_INS_QSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_QSUB8, ARM_INS_QSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RBIT, ARM_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_REV, ARM_INS_REV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_REV16, ARM_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_REVSH, ARM_INS_REVSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEDA, ARM_INS_RFEDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEDA_UPD, ARM_INS_RFEDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEDB, ARM_INS_RFEDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEDB_UPD, ARM_INS_RFEDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEIA, ARM_INS_RFEIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEIA_UPD, ARM_INS_RFEIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEIB, ARM_INS_RFEIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RFEIB_UPD, ARM_INS_RFEIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSBri, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSBrr, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSBrsi, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSBrsr, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSCri, ARM_INS_RSC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSCrr, ARM_INS_RSC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSCrsi, ARM_INS_RSC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_RSCrsr, ARM_INS_RSC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SADD16, ARM_INS_SADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SADD8, ARM_INS_SADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SASX, ARM_INS_SASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SBCri, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SBCrr, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SBCrsi, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SBCrsr, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SBFX, ARM_INS_SBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SDIV, ARM_INS_SDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SEL, ARM_INS_SEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SETEND, ARM_INS_SETEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1C, ARM_INS_SHA1C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1H, ARM_INS_SHA1H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1M, ARM_INS_SHA1M,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1P, ARM_INS_SHA1P,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1SU0, ARM_INS_SHA1SU0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA1SU1, ARM_INS_SHA1SU1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA256H, ARM_INS_SHA256H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA256H2, ARM_INS_SHA256H2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA256SU0, ARM_INS_SHA256SU0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHA256SU1, ARM_INS_SHA256SU1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHADD16, ARM_INS_SHADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHADD8, ARM_INS_SHADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHASX, ARM_INS_SHASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHSAX, ARM_INS_SHSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHSUB16, ARM_INS_SHSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SHSUB8, ARM_INS_SHSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMC, ARM_INS_SMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLABB, ARM_INS_SMLABB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLABT, ARM_INS_SMLABT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLAD, ARM_INS_SMLAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLADX, ARM_INS_SMLADX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLAL, ARM_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALBB, ARM_INS_SMLALBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALBT, ARM_INS_SMLALBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALD, ARM_INS_SMLALD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALDX, ARM_INS_SMLALDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALTB, ARM_INS_SMLALTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLALTT, ARM_INS_SMLALTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLATB, ARM_INS_SMLATB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLATT, ARM_INS_SMLATT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLAWB, ARM_INS_SMLAWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLAWT, ARM_INS_SMLAWT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLSD, ARM_INS_SMLSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLSDX, ARM_INS_SMLSDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLSLD, ARM_INS_SMLSLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMLSLDX, ARM_INS_SMLSLDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMLA, ARM_INS_SMMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMLAR, ARM_INS_SMMLAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMLS, ARM_INS_SMMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMLSR, ARM_INS_SMMLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMUL, ARM_INS_SMMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMMULR, ARM_INS_SMMULR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMUAD, ARM_INS_SMUAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMUADX, ARM_INS_SMUADX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULBB, ARM_INS_SMULBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULBT, ARM_INS_SMULBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULL, ARM_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULTB, ARM_INS_SMULTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULTT, ARM_INS_SMULTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULWB, ARM_INS_SMULWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMULWT, ARM_INS_SMULWT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMUSD, ARM_INS_SMUSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SMUSDX, ARM_INS_SMUSDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSDA, ARM_INS_SRSDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSDA_UPD, ARM_INS_SRSDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSDB, ARM_INS_SRSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSDB_UPD, ARM_INS_SRSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSIA, ARM_INS_SRSIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSIA_UPD, ARM_INS_SRSIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSIB, ARM_INS_SRSIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SRSIB_UPD, ARM_INS_SRSIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SSAT, ARM_INS_SSAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SSAT16, ARM_INS_SSAT16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SSAX, ARM_INS_SSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SSUB16, ARM_INS_SSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SSUB8, ARM_INS_SSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2L_OFFSET, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2L_OPTION, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2L_POST, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2L_PRE, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2_OFFSET, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2_OPTION, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2_POST, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC2_PRE, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STCL_OFFSET, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STCL_OPTION, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STCL_POST, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STCL_PRE, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC_OFFSET, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC_OPTION, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC_POST, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STC_PRE, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STL, ARM_INS_STL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLB, ARM_INS_STLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLEX, ARM_INS_STLEX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLEXB, ARM_INS_STLEXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLEXD, ARM_INS_STLEXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLEXH, ARM_INS_STLEXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STLH, ARM_INS_STLH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMDA, ARM_INS_STMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMDA_UPD, ARM_INS_STMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMDB, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMDB_UPD, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMIA, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMIA_UPD, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMIB, ARM_INS_STMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STMIB_UPD, ARM_INS_STMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRBT_POST_IMM, ARM_INS_STRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRBT_POST_REG, ARM_INS_STRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRB_POST_IMM, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRB_POST_REG, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRB_PRE_IMM, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRB_PRE_REG, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRBi12, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRBrs, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRD, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRD_PAIR, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRD_POST, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRD_PRE, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STREX, ARM_INS_STREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STREXB, ARM_INS_STREXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STREXD, ARM_INS_STREXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STREXH, ARM_INS_STREXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRH, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRHTi, ARM_INS_STRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRHTr, ARM_INS_STRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRH_POST, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRH_PRE, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRT_POST_IMM, ARM_INS_STRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRT_POST_REG, ARM_INS_STRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STR_POST_IMM, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STR_POST_REG, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STR_PRE_IMM, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STR_PRE_REG, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRi12, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_STRrs, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SUBri, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SUBrr, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SUBrsi, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SUBrsr, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SVC, ARM_INS_SVC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SWP, ARM_INS_SWP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SWPB, ARM_INS_SWPB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTAB, ARM_INS_SXTAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTAB16, ARM_INS_SXTAB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTAH, ARM_INS_SXTAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTB, ARM_INS_SXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTB16, ARM_INS_SXTB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_SXTH, ARM_INS_SXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TEQri, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TEQrr, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TEQrsi, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TEQrsr, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TRAP, ARM_INS_TRAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TRAPNaCl, ARM_INS_TRAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TSTri, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TSTrr, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TSTrsi, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_TSTrsr, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UADD16, ARM_INS_UADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UADD8, ARM_INS_UADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UASX, ARM_INS_UASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UBFX, ARM_INS_UBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UDIV, ARM_INS_UDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHADD16, ARM_INS_UHADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHADD8, ARM_INS_UHADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHASX, ARM_INS_UHASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHSAX, ARM_INS_UHSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHSUB16, ARM_INS_UHSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UHSUB8, ARM_INS_UHSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UMAAL, ARM_INS_UMAAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UMLAL, ARM_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UMULL, ARM_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQADD16, ARM_INS_UQADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQADD8, ARM_INS_UQADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQASX, ARM_INS_UQASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQSAX, ARM_INS_UQSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQSUB16, ARM_INS_UQSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UQSUB8, ARM_INS_UQSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USAD8, ARM_INS_USAD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USADA8, ARM_INS_USADA8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USAT, ARM_INS_USAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USAT16, ARM_INS_USAT16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USAX, ARM_INS_USAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USUB16, ARM_INS_USUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_USUB8, ARM_INS_USUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTAB, ARM_INS_UXTAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTAB16, ARM_INS_UXTAB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTAH, ARM_INS_UXTAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTB, ARM_INS_UXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTB16, ARM_INS_UXTB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_UXTH, ARM_INS_UXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALsv2i64, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALsv4i32, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALsv8i16, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALuv2i64, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALuv4i32, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABALuv8i16, ARM_INS_VABAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv16i8, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv2i32, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv4i16, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv4i32, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv8i16, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAsv8i8, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv16i8, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv2i32, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv4i16, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv4i32, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv8i16, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABAuv8i8, ARM_INS_VABA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLsv2i64, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLsv4i32, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLsv8i16, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLuv2i64, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLuv4i32, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDLuv8i16, ARM_INS_VABDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDfd, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDfq, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv16i8, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv2i32, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv4i16, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv4i32, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv8i16, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDsv8i8, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv16i8, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv2i32, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv4i16, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv4i32, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv8i16, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABDuv8i8, ARM_INS_VABD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSD, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSS, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSfd, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSfq, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv16i8, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv2i32, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv4i16, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv4i32, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv8i16, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VABSv8i8, ARM_INS_VABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VACGEd, ARM_INS_VACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VACGEq, ARM_INS_VACGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VACGTd, ARM_INS_VACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VACGTq, ARM_INS_VACGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDD, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDHNv2i32, ARM_INS_VADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDHNv4i16, ARM_INS_VADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDHNv8i8, ARM_INS_VADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLsv2i64, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLsv4i32, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLsv8i16, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLuv2i64, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLuv4i32, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDLuv8i16, ARM_INS_VADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDS, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWsv2i64, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWsv4i32, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWsv8i16, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWuv2i64, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWuv4i32, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDWuv8i16, ARM_INS_VADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDfd, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDfq, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv16i8, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv1i64, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv2i32, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv2i64, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv4i16, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv4i32, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv8i16, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VADDv8i8, ARM_INS_VADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VANDd, ARM_INS_VAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VANDq, ARM_INS_VAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICd, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICiv2i32, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICiv4i16, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICiv4i32, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICiv8i16, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBICq, ARM_INS_VBIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBIFd, ARM_INS_VBIF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBIFq, ARM_INS_VBIF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBITd, ARM_INS_VBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBITq, ARM_INS_VBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBSLd, ARM_INS_VBSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VBSLq, ARM_INS_VBSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQfd, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQfq, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv16i8, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv2i32, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv4i16, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv4i32, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv8i16, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCEQv8i8, ARM_INS_VCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEfd, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEfq, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv16i8, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv2i32, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv4i16, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv4i32, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv8i16, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEsv8i8, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv16i8, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv2i32, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv4i16, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv4i32, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv8i16, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGEuv8i8, ARM_INS_VCGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTfd, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTfq, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv16i8, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv2i32, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv4i16, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv4i32, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv8i16, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTsv8i8, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv16i8, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv2i32, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv4i16, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv4i32, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv8i16, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCGTuv8i8, ARM_INS_VCGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv16i8, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv2i32, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv4i16, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv4i32, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv8i16, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLSv8i8, ARM_INS_VCLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv16i8, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv2i32, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv4i16, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv4i32, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv8i16, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCLZv8i8, ARM_INS_VCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCMPD, ARM_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCMPED, ARM_INS_VCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCMPES, ARM_INS_VCMPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCMPS, ARM_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCNTd, ARM_INS_VCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCNTq, ARM_INS_VCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTANSD, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTANSQ, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTANUD, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTANUQ, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTASD, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTASS, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTAUD, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTAUS, ARM_INS_VCVTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTBDH, ARM_INS_VCVTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTBHD, ARM_INS_VCVTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTBHS, ARM_INS_VCVTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTBSH, ARM_INS_VCVTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTDS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMNSD, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMNSQ, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMNUD, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMNUQ, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMSD, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMSS, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMUD, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTMUS, ARM_INS_VCVTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNNSD, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNNSQ, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNNUD, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNNUQ, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNSD, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNSS, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNUD, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTNUS, ARM_INS_VCVTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPNSD, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPNSQ, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPNUD, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPNUQ, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPSD, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPSS, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPUD, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTPUS, ARM_INS_VCVTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTSD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTTDH, ARM_INS_VCVTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTTHD, ARM_INS_VCVTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTTHS, ARM_INS_VCVTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTTSH, ARM_INS_VCVTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2h, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2sd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2sq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2ud, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2uq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2xsd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2xsq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2xud, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTf2xuq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTh2f, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTs2fd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTs2fq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTu2fd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTu2fq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTxs2fd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTxs2fq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTxu2fd, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VCVTxu2fq, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDIVD, ARM_INS_VDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDIVS, ARM_INS_VDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP16d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP16q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP32d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP32q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP8d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUP8q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN16d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN16q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN32d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN32q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN8d, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VDUPLN8q, ARM_INS_VDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEORd, ARM_INS_VEOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEORq, ARM_INS_VEOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTd16, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTd32, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTd8, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTq16, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTq32, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTq64, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VEXTq8, ARM_INS_VEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMAD, ARM_INS_VFMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMAS, ARM_INS_VFMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMAfd, ARM_INS_VFMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMAfq, ARM_INS_VFMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMSD, ARM_INS_VFMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMSS, ARM_INS_VFMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMSfd, ARM_INS_VFMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFMSfq, ARM_INS_VFMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFNMAD, ARM_INS_VFNMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFNMAS, ARM_INS_VFNMA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFNMSD, ARM_INS_VFNMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VFNMSS, ARM_INS_VFNMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VGETLNi32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VGETLNs16, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VGETLNs8, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VGETLNu16, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VGETLNu8, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv16i8, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv2i32, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv4i16, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv4i32, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv8i16, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDsv8i8, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv16i8, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv2i32, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv4i16, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv4i32, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv8i16, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHADDuv8i8, ARM_INS_VHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv16i8, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv2i32, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv4i16, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv4i32, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv8i16, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBsv8i8, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv16i8, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv2i32, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv4i16, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv4i32, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv8i16, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VHSUBuv8i8, ARM_INS_VHSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd16, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd16wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd32, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd32wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd8, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPd8wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq16, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq16wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq32, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq32wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq8, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1DUPq8wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd16, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd16_UPD, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd32, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd32_UPD, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd8, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1LNd8_UPD, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16Q, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16Qwb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16T, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16Twb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16Twb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d16wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32Q, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32Qwb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32T, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32Twb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32Twb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d32wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64Q, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64Qwb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64T, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64Twb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64Twb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d64wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8Q, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8Qwb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8T, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8Twb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8Twb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1d8wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q16, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q16wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q16wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q32, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q32wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q32wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q64, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q64wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q64wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q8, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q8wb_fixed, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD1q8wb_register, ARM_INS_VLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16x2, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32x2, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8x2, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd16_UPD, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd32_UPD, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd8, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNd8_UPD, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNq16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNq16_UPD, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNq32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2LNq32_UPD, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b16wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b16wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b32wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b32wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b8, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b8wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2b8wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d16wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d16wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d32wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d32wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d8, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d8wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2d8wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q16, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q16wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q16wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q32, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q32wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q32wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q8, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q8wb_fixed, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD2q8wb_register, ARM_INS_VLD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd8, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPd8_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq8, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3DUPq8_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd8, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNd8_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNq16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNq16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNq32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3LNq32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d8, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3d8_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q16, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q16_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q32, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q32_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q8, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD3q8_UPD, ARM_INS_VLD3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd8, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPd8_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq8, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4DUPq8_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd8, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNd8_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNq16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNq16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNq32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4LNq32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d8, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4d8_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q16, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q16_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q32, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q32_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q8, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLD4q8_UPD, ARM_INS_VLD4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMDDB_UPD, ARM_INS_VLDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMDIA, ARM_INS_VLDMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMDIA_UPD, ARM_INS_VLDMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMSDB_UPD, ARM_INS_VLDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMSIA, ARM_INS_VLDMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDMSIA_UPD, ARM_INS_VLDMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDRD, ARM_INS_VLDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VLDRS, ARM_INS_VLDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXNMD, ARM_INS_VMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXNMND, ARM_INS_VMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXNMNQ, ARM_INS_VMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXNMS, ARM_INS_VMAXNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXfd, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXfq, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv16i8, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv2i32, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv4i16, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv4i32, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv8i16, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXsv8i8, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv16i8, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv2i32, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv4i16, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv4i32, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv8i16, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMAXuv8i8, ARM_INS_VMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINNMD, ARM_INS_VMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINNMND, ARM_INS_VMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINNMNQ, ARM_INS_VMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINNMS, ARM_INS_VMINNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINfd, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINfq, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv16i8, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv2i32, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv4i16, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv4i32, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv8i16, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINsv8i8, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv16i8, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv2i32, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv4i16, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv4i32, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv8i16, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMINuv8i8, ARM_INS_VMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAD, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALslsv2i32, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALslsv4i16, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALsluv2i32, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALsluv4i16, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALsv2i64, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALsv4i32, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALsv8i16, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALuv2i64, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALuv4i32, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLALuv8i16, ARM_INS_VMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAS, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAfd, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAfq, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslfd, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslfq, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslv2i32, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslv4i16, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslv4i32, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAslv8i16, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv16i8, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv2i32, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv4i16, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv4i32, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv8i16, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLAv8i8, ARM_INS_VMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSD, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLslsv2i32, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLslsv4i16, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLsluv2i32, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLsluv4i16, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLsv2i64, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLsv4i32, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLsv8i16, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLuv2i64, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLuv4i32, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSLuv8i16, ARM_INS_VMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSS, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSfd, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSfq, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslfd, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslfq, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslv2i32, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslv4i16, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslv4i32, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSslv8i16, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv16i8, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv2i32, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv4i16, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv4i32, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv8i16, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMLSv8i8, ARM_INS_VMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVD, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVDRR, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLsv2i64, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLsv4i32, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLsv8i16, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLuv2i64, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLuv4i32, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVLuv8i16, ARM_INS_VMOVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVNv2i32, ARM_INS_VMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVNv4i16, ARM_INS_VMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVNv8i8, ARM_INS_VMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVRRD, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVRRS, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVRS, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVS, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVSR, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVSRR, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv16i8, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv1i64, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv2f32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv2i32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv2i64, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv4f32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv4i16, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv4i32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv8i16, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMOVv8i8, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_FPEXC, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_FPINST, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_FPINST2, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_FPSID, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_MVFR0, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_MVFR1, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMRS_MVFR2, ARM_INS_VMRS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMSR, ARM_INS_VMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMSR_FPEXC, ARM_INS_VMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMSR_FPINST, ARM_INS_VMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMSR_FPINST2, ARM_INS_VMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMSR_FPSID, ARM_INS_VMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULD, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLp64, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLp8, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLslsv2i32, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLslsv4i16, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLsluv2i32, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLsluv4i16, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLsv2i64, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLsv4i32, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLsv8i16, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLuv2i64, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLuv4i32, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULLuv8i16, ARM_INS_VMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULS, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULfd, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULfq, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULpd, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULpq, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslfd, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslfq, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslv2i32, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslv4i16, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslv4i32, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULslv8i16, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv16i8, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv2i32, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv4i16, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv4i32, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv8i16, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMULv8i8, ARM_INS_VMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNd, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNq, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNv2i32, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNv4i16, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNv4i32, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VMVNv8i16, ARM_INS_VMVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGD, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGS, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGf32q, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGfd, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs16d, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs16q, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs32d, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs32q, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs8d, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNEGs8q, ARM_INS_VNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMLAD, ARM_INS_VNMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMLAS, ARM_INS_VNMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMLSD, ARM_INS_VNMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMLSS, ARM_INS_VNMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMULD, ARM_INS_VNMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VNMULS, ARM_INS_VNMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORNd, ARM_INS_VORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORNq, ARM_INS_VORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRd, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRiv2i32, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRiv4i16, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRiv4i32, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRiv8i16, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VORRq, ARM_INS_VORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv16i8, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv2i32, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv4i16, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv4i32, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv8i16, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALsv8i8, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv16i8, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv2i32, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv4i16, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv4i32, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv8i16, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADALuv8i8, ARM_INS_VPADAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv16i8, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv2i32, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv4i16, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv4i32, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv8i16, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLsv8i8, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv16i8, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv2i32, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv4i16, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv4i32, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv8i16, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDLuv8i8, ARM_INS_VPADDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDf, ARM_INS_VPADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDi16, ARM_INS_VPADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDi32, ARM_INS_VPADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPADDi8, ARM_INS_VPADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXf, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXs16, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXs32, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXs8, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXu16, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXu32, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMAXu8, ARM_INS_VPMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINf, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINs16, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINs32, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINs8, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINu16, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINu32, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VPMINu8, ARM_INS_VPMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv16i8, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv2i32, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv4i16, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv4i32, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv8i16, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQABSv8i8, ARM_INS_VQABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv16i8, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv1i64, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv2i32, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv2i64, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv4i16, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv4i32, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv8i16, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDsv8i8, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv16i8, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv1i64, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv2i32, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv2i64, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv4i16, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv4i32, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv8i16, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQADDuv8i8, ARM_INS_VQADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLALv2i64, ARM_INS_VQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLALv4i32, ARM_INS_VQDMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHslv2i32, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHslv4i16, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHslv4i32, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHslv8i16, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHv2i32, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHv4i16, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHv4i32, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULHv8i16, ARM_INS_VQDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULLslv2i32, ARM_INS_VQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULLslv4i16, ARM_INS_VQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULLv2i64, ARM_INS_VQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQDMULLv4i32, ARM_INS_VQDMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsv2i32, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsv4i16, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNsv8i8, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNuv2i32, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNuv4i16, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQMOVNuv8i8, ARM_INS_VQMOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv16i8, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv2i32, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv4i16, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv4i32, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv8i16, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQNEGv8i8, ARM_INS_VQNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv16i8, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv1i64, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv2i32, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv2i64, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv4i16, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv4i32, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv8i16, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLsv8i8, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv16i8, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv1i64, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv2i32, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv2i64, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv4i16, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv4i32, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv8i16, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHLuv8i8, ARM_INS_VQRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv16i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv1i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv2i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv2i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv4i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv4i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv8i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsiv8i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv16i8, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv1i64, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv2i32, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv2i64, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv4i16, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv4i32, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv8i16, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsuv8i8, ARM_INS_VQSHLU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv16i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv1i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv2i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv2i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv4i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv4i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv8i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLsv8i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv16i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv1i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv2i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv2i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv4i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv4i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv8i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuiv8i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv16i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv1i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv2i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv2i64, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv4i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv4i32, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv8i16, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHLuv8i8, ARM_INS_VQSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNsv2i32, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNsv4i16, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNsv8i8, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNuv2i32, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNuv4i16, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRNuv8i8, ARM_INS_VQSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv16i8, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv1i64, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv2i32, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv2i64, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv4i16, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv4i32, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv8i16, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBsv8i8, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv16i8, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv1i64, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv2i32, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv2i64, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv4i16, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv4i32, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv8i16, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VQSUBuv8i8, ARM_INS_VQSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRADDHNv2i32, ARM_INS_VRADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRADDHNv4i16, ARM_INS_VRADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRADDHNv8i8, ARM_INS_VRADDHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPEd, ARM_INS_VRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPEfd, ARM_INS_VRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPEfq, ARM_INS_VRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPEq, ARM_INS_VRECPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPSfd, ARM_INS_VRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRECPSfq, ARM_INS_VRECPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV16d8, ARM_INS_VREV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV16q8, ARM_INS_VREV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV32d16, ARM_INS_VREV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV32d8, ARM_INS_VREV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV32q16, ARM_INS_VREV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV32q8, ARM_INS_VREV32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64d16, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64d32, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64d8, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64q16, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64q32, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VREV64q8, ARM_INS_VREV64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv16i8, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv2i32, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv4i16, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv4i32, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv8i16, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDsv8i8, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv16i8, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv2i32, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv4i16, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv4i32, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv8i16, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRHADDuv8i8, ARM_INS_VRHADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTAD, ARM_INS_VRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTAND, ARM_INS_VRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTANQ, ARM_INS_VRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTAS, ARM_INS_VRINTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTMD, ARM_INS_VRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTMND, ARM_INS_VRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTMNQ, ARM_INS_VRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTMS, ARM_INS_VRINTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTND, ARM_INS_VRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTNND, ARM_INS_VRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTNNQ, ARM_INS_VRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTNS, ARM_INS_VRINTN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTPD, ARM_INS_VRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTPND, ARM_INS_VRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTPNQ, ARM_INS_VRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTPS, ARM_INS_VRINTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTRD, ARM_INS_VRINTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTRS, ARM_INS_VRINTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTXD, ARM_INS_VRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTXND, ARM_INS_VRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTXNQ, ARM_INS_VRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTXS, ARM_INS_VRINTX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTZD, ARM_INS_VRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTZND, ARM_INS_VRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTZNQ, ARM_INS_VRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRINTZS, ARM_INS_VRINTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv16i8, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv1i64, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv2i32, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv2i64, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv4i16, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv4i32, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv8i16, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLsv8i8, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv16i8, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv1i64, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv2i32, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv2i64, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv4i16, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv4i32, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv8i16, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHLuv8i8, ARM_INS_VRSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRNv2i32, ARM_INS_VRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRNv4i16, ARM_INS_VRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRNv8i8, ARM_INS_VRSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv16i8, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv1i64, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv2i32, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv2i64, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv4i16, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv4i32, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv8i16, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRsv8i8, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv16i8, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv1i64, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv2i32, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv2i64, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv4i16, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv4i32, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv8i16, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSHRuv8i8, ARM_INS_VRSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTEd, ARM_INS_VRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTEfd, ARM_INS_VRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTEfq, ARM_INS_VRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTEq, ARM_INS_VRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTSfd, ARM_INS_VRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSQRTSfq, ARM_INS_VRSQRTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv16i8, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv1i64, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv2i32, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv2i64, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv4i16, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv4i32, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv8i16, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAsv8i8, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv16i8, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv1i64, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv2i32, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv2i64, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv4i16, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv4i32, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv8i16, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSRAuv8i8, ARM_INS_VRSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELEQD, ARM_INS_VSELEQ,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELEQS, ARM_INS_VSELEQ,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELGED, ARM_INS_VSELGE,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELGES, ARM_INS_VSELGE,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELGTD, ARM_INS_VSELGT,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELGTS, ARM_INS_VSELGT,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELVSD, ARM_INS_VSELVS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSELVSS, ARM_INS_VSELVS,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSETLNi16, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSETLNi32, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSETLNi8, ARM_INS_VMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLi16, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLi32, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLi8, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLsv2i64, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLsv4i32, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLsv8i16, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLuv2i64, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLuv4i32, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLLuv8i16, ARM_INS_VSHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv16i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv1i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv2i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv2i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv4i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv4i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv8i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLiv8i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv16i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv1i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv2i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv2i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv4i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv4i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv8i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLsv8i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv16i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv1i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv2i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv2i64, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv4i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv4i32, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv8i16, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHLuv8i8, ARM_INS_VSHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRNv2i32, ARM_INS_VSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRNv4i16, ARM_INS_VSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRNv8i8, ARM_INS_VSHRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv16i8, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv1i64, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv2i32, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv2i64, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv4i16, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv4i32, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv8i16, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRsv8i8, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv16i8, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv1i64, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv2i32, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv2i64, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv4i16, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv4i32, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv8i16, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHRuv8i8, ARM_INS_VSHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHTOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSHTOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSITOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSITOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv16i8, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv1i64, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv2i32, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv2i64, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv4i16, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv4i32, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv8i16, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLIv8i8, ARM_INS_VSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLTOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSLTOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSQRTD, ARM_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSQRTS, ARM_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv16i8, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv1i64, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv2i32, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv2i64, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv4i16, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv4i32, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv8i16, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAsv8i8, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv16i8, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv1i64, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv2i32, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv2i64, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv4i16, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv4i32, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv8i16, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRAuv8i8, ARM_INS_VSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv16i8, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv1i64, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv2i32, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv2i64, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv4i16, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv4i32, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv8i16, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSRIv8i8, ARM_INS_VSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd16, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd16_UPD, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd32, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd32_UPD, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd8, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1LNd8_UPD, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16Q, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16Qwb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16Qwb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16T, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16Twb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16Twb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d16wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32Q, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32Qwb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32Qwb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32T, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32Twb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32Twb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d32wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64Q, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64Qwb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64Qwb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64T, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64Twb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64Twb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d64wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8Q, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8Qwb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8Qwb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8T, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8Twb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8Twb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1d8wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q16, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q16wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q16wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q32, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q32wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q32wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q64, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q64wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q64wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q8, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q8wb_fixed, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST1q8wb_register, ARM_INS_VST1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd16, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd16_UPD, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd32, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd32_UPD, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd8, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNd8_UPD, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNq16, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNq16_UPD, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNq32, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2LNq32_UPD, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b16, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b16wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b16wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b32, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b32wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b32wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b8, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b8wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2b8wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d16, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d16wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d16wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d32, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d32wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d32wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d8, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d8wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2d8wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q16, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q16wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q16wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q32, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q32wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q32wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q8, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q8wb_fixed, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST2q8wb_register, ARM_INS_VST2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd16, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd16_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd32, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd32_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd8, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNd8_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNq16, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNq16_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNq32, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3LNq32_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d16, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d16_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d32, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d32_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d8, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3d8_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q16, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q16_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q32, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q32_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q8, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST3q8_UPD, ARM_INS_VST3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd16, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd16_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd32, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd32_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd8, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNd8_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNq16, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNq16_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNq32, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4LNq32_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d16, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d16_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d32, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d32_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d8, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4d8_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q16, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q16_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q32, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q32_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q8, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VST4q8_UPD, ARM_INS_VST4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMDDB_UPD, ARM_INS_VSTMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMDIA, ARM_INS_VSTMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMDIA_UPD, ARM_INS_VSTMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMSDB_UPD, ARM_INS_VSTMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMSIA, ARM_INS_VSTMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTMSIA_UPD, ARM_INS_VSTMIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTRD, ARM_INS_VSTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSTRS, ARM_INS_VSTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBD, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBHNv2i32, ARM_INS_VSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBHNv4i16, ARM_INS_VSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBHNv8i8, ARM_INS_VSUBHN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLsv2i64, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLsv4i32, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLsv8i16, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLuv2i64, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLuv4i32, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBLuv8i16, ARM_INS_VSUBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBS, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWsv2i64, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWsv4i32, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWsv8i16, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWuv2i64, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWuv4i32, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBWuv8i16, ARM_INS_VSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBfd, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBfq, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv16i8, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv1i64, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv2i32, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv2i64, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv4i16, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv4i32, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv8i16, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSUBv8i8, ARM_INS_VSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSWPd, ARM_INS_VSWP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VSWPq, ARM_INS_VSWP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBL1, ARM_INS_VTBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBL2, ARM_INS_VTBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBL3, ARM_INS_VTBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBL4, ARM_INS_VTBL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBX1, ARM_INS_VTBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBX2, ARM_INS_VTBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBX3, ARM_INS_VTBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTBX4, ARM_INS_VTBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSHD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSHS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSIRD, ARM_INS_VCVTR,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSIRS, ARM_INS_VCVTR,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSIZD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSIZS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSLD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOSLS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUHD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUHS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUIRD, ARM_INS_VCVTR,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUIRS, ARM_INS_VCVTR,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUIZD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOUIZS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOULD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTOULS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNd16, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNd32, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNd8, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNq16, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNq32, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTRNq8, ARM_INS_VTRN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv16i8, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv2i32, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv4i16, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv4i32, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv8i16, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VTSTv8i8, ARM_INS_VTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUHTOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUHTOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUITOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUITOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VULTOD, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VULTOS, ARM_INS_VCVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUZPd16, ARM_INS_VUZP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUZPd8, ARM_INS_VUZP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUZPq16, ARM_INS_VUZP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUZPq32, ARM_INS_VUZP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VUZPq8, ARM_INS_VUZP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VZIPd16, ARM_INS_VZIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VZIPd8, ARM_INS_VZIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VZIPq16, ARM_INS_VZIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VZIPq32, ARM_INS_VZIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_VZIPq8, ARM_INS_VZIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMDA, ARM_INS_LDMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMDA_UPD, ARM_INS_LDMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMDB, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMDB_UPD, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMIA, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMIA_UPD, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMIB, ARM_INS_LDMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysLDMIB_UPD, ARM_INS_LDMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMDA, ARM_INS_STMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMDA_UPD, ARM_INS_STMDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMDB, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMDB_UPD, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMIA, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMIA_UPD, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMIB, ARM_INS_STMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_sysSTMIB_UPD, ARM_INS_STMIB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADCri, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADCrr, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADCrs, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADDri, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADDri12, ARM_INS_ADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADDrr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADDrs, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ADR, ARM_INS_ADR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ANDri, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ANDrr, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ANDrs, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ASRri, ARM_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ASRrr, ARM_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2B, ARM_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_t2BFC, ARM_INS_BFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2BFI, ARM_INS_BFI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2BICri, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2BICrr, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2BICrs, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2BXJ, ARM_INS_BXJ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2Bcc, ARM_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_t2CDP, ARM_INS_CDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CDP2, ARM_INS_CDP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CLREX, ARM_INS_CLREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CLZ, ARM_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMNri, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMNzrr, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMNzrs, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMPri, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMPrr, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CMPrs, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CPS1p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CPS2p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CPS3p, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32B, ARM_INS_CRC32B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32CB, ARM_INS_CRC32CB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32CH, ARM_INS_CRC32CH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32CW, ARM_INS_CRC32CW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32H, ARM_INS_CRC32H,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2CRC32W, ARM_INS_CRC32W,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DBG, ARM_INS_DBG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DCPS1, ARM_INS_DCPS1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DCPS2, ARM_INS_DCPS2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DCPS3, ARM_INS_DCPS3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DMB, ARM_INS_DMB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2DSB, ARM_INS_DSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2EORri, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2EORrr, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2EORrs, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2HINT, ARM_INS_HINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ISB, ARM_INS_ISB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2IT, ARM_INS_IT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDA, ARM_INS_LDA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAB, ARM_INS_LDAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAEX, ARM_INS_LDAEX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAEXB, ARM_INS_LDAEXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAEXD, ARM_INS_LDAEXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAEXH, ARM_INS_LDAEXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDAH, ARM_INS_LDAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2L_OPTION, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2L_POST, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2L_PRE, ARM_INS_LDC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2_OFFSET, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2_OPTION, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2_POST, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC2_PRE, ARM_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDCL_OFFSET, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDCL_OPTION, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDCL_POST, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDCL_PRE, ARM_INS_LDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC_OFFSET, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC_OPTION, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC_POST, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDC_PRE, ARM_INS_LDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDMDB, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDMDB_UPD, ARM_INS_LDMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDMIA, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDMIA_UPD, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRBT, ARM_INS_LDRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRB_POST, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRB_PRE, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRBi12, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRBi8, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRBpci, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRBs, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRD_POST, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRD_PRE, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRDi8, ARM_INS_LDRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDREX, ARM_INS_LDREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDREXB, ARM_INS_LDREXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDREXD, ARM_INS_LDREXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDREXH, ARM_INS_LDREXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRHT, ARM_INS_LDRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRH_POST, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRH_PRE, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRHi12, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRHi8, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRHpci, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRHs, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSBT, ARM_INS_LDRSBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSB_POST, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSB_PRE, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSBi12, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSBi8, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSBpci, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSBs, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSHT, ARM_INS_LDRSHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSH_POST, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSH_PRE, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSHi12, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSHi8, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSHpci, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRSHs, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRT, ARM_INS_LDRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDR_POST, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDR_PRE, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRi12, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRi8, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRpci, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LDRs, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LSLri, ARM_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LSLrr, ARM_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LSRri, ARM_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2LSRrr, ARM_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MCR, ARM_INS_MCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MCR2, ARM_INS_MCR2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MCRR, ARM_INS_MCRR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MCRR2, ARM_INS_MCRR2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MLA, ARM_INS_MLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MLS, ARM_INS_MLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MOVTi16, ARM_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MOVi, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MOVi16, ARM_INS_MOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MOVr, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRC, ARM_INS_MRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRC2, ARM_INS_MRC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRRC, ARM_INS_MRRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRRC2, ARM_INS_MRRC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRS_AR, ARM_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRS_M, ARM_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MRSsys_AR, ARM_INS_MRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MSR_AR, ARM_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MSR_M, ARM_INS_MSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MUL, ARM_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MVNi, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MVNr, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2MVNs, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORNri, ARM_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORNrr, ARM_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORNrs, ARM_INS_ORN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORRri, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORRrr, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2ORRrs, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PKHBT, ARM_INS_PKHBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PKHTB, ARM_INS_PKHTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDWi12, ARM_INS_PLDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDWi8, ARM_INS_PLDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDWs, ARM_INS_PLDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDi12, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDi8, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDpci, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLDs, ARM_INS_PLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLIi12, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLIi8, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLIpci, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2PLIs, ARM_INS_PLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QADD, ARM_INS_QADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QADD16, ARM_INS_QADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QADD8, ARM_INS_QADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QASX, ARM_INS_QASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QDADD, ARM_INS_QDADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QDSUB, ARM_INS_QDSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QSAX, ARM_INS_QSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QSUB, ARM_INS_QSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QSUB16, ARM_INS_QSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2QSUB8, ARM_INS_QSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RBIT, ARM_INS_RBIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2REV, ARM_INS_REV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2REV16, ARM_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2REVSH, ARM_INS_REVSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RFEDB, ARM_INS_RFEDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RFEDBW, ARM_INS_RFEDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RFEIA, ARM_INS_RFEIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RFEIAW, ARM_INS_RFEIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RORri, ARM_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RORrr, ARM_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RRX, ARM_INS_RRX,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RSBri, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RSBrr, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2RSBrs, ARM_INS_RSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SADD16, ARM_INS_SADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SADD8, ARM_INS_SADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SASX, ARM_INS_SASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SBCri, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SBCrr, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SBCrs, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SBFX, ARM_INS_SBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SDIV, ARM_INS_SDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SEL, ARM_INS_SEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHADD16, ARM_INS_SHADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHADD8, ARM_INS_SHADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHASX, ARM_INS_SHASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHSAX, ARM_INS_SHSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHSUB16, ARM_INS_SHSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SHSUB8, ARM_INS_SHSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMC, ARM_INS_SMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLABB, ARM_INS_SMLABB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLABT, ARM_INS_SMLABT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLAD, ARM_INS_SMLAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLADX, ARM_INS_SMLADX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLAL, ARM_INS_SMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALBB, ARM_INS_SMLALBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALBT, ARM_INS_SMLALBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALD, ARM_INS_SMLALD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALDX, ARM_INS_SMLALDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALTB, ARM_INS_SMLALTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLALTT, ARM_INS_SMLALTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLATB, ARM_INS_SMLATB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLATT, ARM_INS_SMLATT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLAWB, ARM_INS_SMLAWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLAWT, ARM_INS_SMLAWT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLSD, ARM_INS_SMLSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLSDX, ARM_INS_SMLSDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLSLD, ARM_INS_SMLSLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMLSLDX, ARM_INS_SMLSLDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMLA, ARM_INS_SMMLA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMLAR, ARM_INS_SMMLAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMLS, ARM_INS_SMMLS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMLSR, ARM_INS_SMMLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMUL, ARM_INS_SMMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMMULR, ARM_INS_SMMULR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMUAD, ARM_INS_SMUAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMUADX, ARM_INS_SMUADX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULBB, ARM_INS_SMULBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULBT, ARM_INS_SMULBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULL, ARM_INS_SMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULTB, ARM_INS_SMULTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULTT, ARM_INS_SMULTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULWB, ARM_INS_SMULWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMULWT, ARM_INS_SMULWT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMUSD, ARM_INS_SMUSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SMUSDX, ARM_INS_SMUSDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SRSDB, ARM_INS_SRSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SRSDB_UPD, ARM_INS_SRSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SRSIA, ARM_INS_SRSIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SRSIA_UPD, ARM_INS_SRSIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SSAT, ARM_INS_SSAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SSAT16, ARM_INS_SSAT16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SSAX, ARM_INS_SSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SSUB16, ARM_INS_SSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SSUB8, ARM_INS_SSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2L_OFFSET, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2L_OPTION, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2L_POST, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2L_PRE, ARM_INS_STC2L,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2_OFFSET, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2_OPTION, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2_POST, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC2_PRE, ARM_INS_STC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STCL_OFFSET, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STCL_OPTION, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STCL_POST, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STCL_PRE, ARM_INS_STCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC_OFFSET, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC_OPTION, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC_POST, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STC_PRE, ARM_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STL, ARM_INS_STL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLB, ARM_INS_STLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLEX, ARM_INS_STLEX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLEXB, ARM_INS_STLEXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLEXD, ARM_INS_STLEXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLEXH, ARM_INS_STLEXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STLH, ARM_INS_STLH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STMDB, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STMDB_UPD, ARM_INS_STMDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STMIA, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STMIA_UPD, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRBT, ARM_INS_STRBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRB_POST, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRB_PRE, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRBi12, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRBi8, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRBs, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRD_POST, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRD_PRE, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRDi8, ARM_INS_STRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STREX, ARM_INS_STREX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STREXB, ARM_INS_STREXB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STREXD, ARM_INS_STREXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STREXH, ARM_INS_STREXH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRHT, ARM_INS_STRHT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRH_POST, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRH_PRE, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRHi12, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRHi8, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRHs, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRT, ARM_INS_STRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STR_POST, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STR_PRE, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRi12, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRi8, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2STRs, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SUBS_PC_LR, ARM_INS_SUBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SUBri, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SUBri12, ARM_INS_SUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SUBrr, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SUBrs, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTAB, ARM_INS_SXTAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTAB16, ARM_INS_SXTAB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTAH, ARM_INS_SXTAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTB, ARM_INS_SXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTB16, ARM_INS_SXTB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2SXTH, ARM_INS_SXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TBB, ARM_INS_TBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 1
+#endif
+ },
+ {
+ ARM_t2TBH, ARM_INS_TBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 1
+#endif
+ },
+ {
+ ARM_t2TEQri, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TEQrr, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TEQrs, ARM_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TSTri, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TSTrr, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2TSTrs, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UADD16, ARM_INS_UADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UADD8, ARM_INS_UADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UASX, ARM_INS_UASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UBFX, ARM_INS_UBFX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UDIV, ARM_INS_UDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHADD16, ARM_INS_UHADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHADD8, ARM_INS_UHADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHASX, ARM_INS_UHASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHSAX, ARM_INS_UHSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHSUB16, ARM_INS_UHSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UHSUB8, ARM_INS_UHSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UMAAL, ARM_INS_UMAAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UMLAL, ARM_INS_UMLAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UMULL, ARM_INS_UMULL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQADD16, ARM_INS_UQADD16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQADD8, ARM_INS_UQADD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQASX, ARM_INS_UQASX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQSAX, ARM_INS_UQSAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQSUB16, ARM_INS_UQSUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UQSUB8, ARM_INS_UQSUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USAD8, ARM_INS_USAD8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USADA8, ARM_INS_USADA8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USAT, ARM_INS_USAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USAT16, ARM_INS_USAT16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USAX, ARM_INS_USAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USUB16, ARM_INS_USUB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2USUB8, ARM_INS_USUB8,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTAB, ARM_INS_UXTAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTAB16, ARM_INS_UXTAB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTAH, ARM_INS_UXTAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTB, ARM_INS_UXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTB16, ARM_INS_UXTB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_t2UXTH, ARM_INS_UXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADC, ARM_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDhirr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDi3, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDi8, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDrSP, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDrSPi, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDrr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDspi, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADDspr, ARM_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tADR, ARM_INS_ADR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tAND, ARM_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tASRri, ARM_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tASRrr, ARM_INS_ASR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tB, ARM_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_tBIC, ARM_INS_BIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tBKPT, ARM_INS_BKPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tBL, ARM_INS_BL,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tBLXi, ARM_INS_BLX,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tBLXr, ARM_INS_BLX,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tBX, ARM_INS_BX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 1, 1
+#endif
+ },
+ {
+ ARM_tBcc, ARM_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_tCBNZ, ARM_INS_CBNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_tCBZ, ARM_INS_CBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
+#endif
+ },
+ {
+ ARM_tCMNz, ARM_INS_CMN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tCMPhir, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tCMPi8, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tCMPr, ARM_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tCPS, ARM_INS_CPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tEOR, ARM_INS_EOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tHINT, ARM_INS_HINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tHLT, ARM_INS_HLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDMIA, ARM_INS_LDM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRBi, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRBr, ARM_INS_LDRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRHi, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRHr, ARM_INS_LDRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRSB, ARM_INS_LDRSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRSH, ARM_INS_LDRSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRi, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRpci, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRr, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLDRspi, ARM_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLSLri, ARM_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLSLrr, ARM_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLSRri, ARM_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tLSRrr, ARM_INS_LSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tMOVSr, ARM_INS_MOVS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tMOVi8, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tMOVr, ARM_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tMUL, ARM_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tMVN, ARM_INS_MVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tORR, ARM_INS_ORR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tPOP, ARM_INS_POP,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tPUSH, ARM_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tREV, ARM_INS_REV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tREV16, ARM_INS_REV16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tREVSH, ARM_INS_REVSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tROR, ARM_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSBC, ARM_INS_SBC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSETEND, ARM_INS_SETEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTMIA_UPD, ARM_INS_STM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRBi, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRBr, ARM_INS_STRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRHi, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRHr, ARM_INS_STRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRi, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRr, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSTRspi, ARM_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSUBi3, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSUBi8, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSUBrr, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSUBspi, ARM_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSVC, ARM_INS_SVC,
+#ifndef CAPSTONE_DIET
+ { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSXTB, ARM_INS_SXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tSXTH, ARM_INS_SXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tTRAP, ARM_INS_TRAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tTST, ARM_INS_TST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tUXTB, ARM_INS_UXTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
+ {
+ ARM_tUXTH, ARM_INS_UXTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0
+#endif
+ },
};
void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
@@ -2309,6 +13136,7 @@
insn->id = insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
cs_struct handle;
handle.detail = h->detail;
@@ -2328,10 +13156,12 @@
insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP;
insn->detail->groups_count++;
}
+#endif
}
}
}
+#ifndef CAPSTONE_DIET
static name_map insn_name_maps[] = {
{ ARM_INS_INVALID, NULL },
@@ -2757,28 +13587,23 @@
{ ARM_INS_POP, "pop" },
{ ARM_INS_PUSH, "push" },
};
+#endif
const char *ARM_insn_name(csh handle, unsigned int id)
{
+#ifndef CAPSTONE_DIET
if (id >= ARM_INS_MAX)
return NULL;
return insn_name_maps[id].name;
-}
-
-arm_reg ARM_map_insn(const char *name)
-{
- int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
-
- if (i != -1)
- return i;
-
- // nothing match
- return (i != -1)? i : ARM_REG_INVALID;
+#else
+ return NULL;
+#endif
}
bool ARM_rel_branch(cs_struct *h, unsigned int id)
{
+#ifndef CAPSTONE_DIET
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0)
return (insns[i].branch && !insns[i].indirect_branch);
@@ -2786,4 +13611,8 @@
printf("ALERT: rel_branch() got incorrect id!\n");
return false;
}
+#else
+ printf("ALERT: rel_branch() got incorrect id!\n");
+ return false;
+#endif
}
diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h
index 1f2ed72..f3b99e2 100644
--- a/arch/ARM/ARMMapping.h
+++ b/arch/ARM/ARMMapping.h
@@ -16,9 +16,6 @@
const char *ARM_insn_name(csh handle, unsigned int id);
-// map instruction name to instruction ID
-arm_reg ARM_map_insn(const char *name);
-
// check if this insn is relative branch
bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
diff --git a/arch/Mips/MipsGenAsmWriter.inc b/arch/Mips/MipsGenAsmWriter.inc
index 73c2efd..9309b35 100644
--- a/arch/Mips/MipsGenAsmWriter.inc
+++ b/arch/Mips/MipsGenAsmWriter.inc
@@ -2989,6 +2989,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0,
/* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0,
@@ -3882,13 +3883,16 @@
/* 7918 */ 'd', 'e', 'r', 'e', 't', 0,
/* 7924 */ 'w', 'a', 'i', 't', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 8191)-1);
+#endif
// Fragment 0 encoded into 3 bits for 5 unique commands.
@@ -4235,6 +4239,7 @@
{
// assert(RegNo && RegNo < 317 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'f', '1', '0', 0,
/* 4 */ 'w', '1', '0', 0,
@@ -4391,6 +4396,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index db38806..baec86c 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -12,6 +12,7 @@
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
+#ifndef CAPSTONE_DIET
static name_map reg_name_maps[] = {
{ MIPS_REG_INVALID, NULL },
@@ -172,1299 +173,7700 @@
{ MIPS_REG_W30, "w30"},
{ MIPS_REG_W31, "w31"},
};
+#endif
const char *Mips_reg_name(csh handle, unsigned int reg)
{
+#ifndef CAPSTONE_DIET
if (reg >= MIPS_REG_MAX)
return NULL;
return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
}
static insn_map insns[] = {
- { 0, 0, { 0 }, { 0 }, { 0 }, 0, 0 }, // dummy item
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
- { Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADD, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ADDQH_PH, MIPS_INS_ADDQH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDQH_W, MIPS_INS_ADDQH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDQ_PH, MIPS_INS_ADDQ, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDSC, MIPS_INS_ADDSC, { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDS_A_B, MIPS_INS_ADDS_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_A_D, MIPS_INS_ADDS_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_A_H, MIPS_INS_ADDS_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_A_W, MIPS_INS_ADDS_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_S_B, MIPS_INS_ADDS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_S_D, MIPS_INS_ADDS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_S_H, MIPS_INS_ADDS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_S_W, MIPS_INS_ADDS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_U_B, MIPS_INS_ADDS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_U_D, MIPS_INS_ADDS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_U_H, MIPS_INS_ADDS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDS_U_W, MIPS_INS_ADDS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDUH_QB, MIPS_INS_ADDUH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDU_PH, MIPS_INS_ADDU, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDU_QB, MIPS_INS_ADDU, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDU_S_PH, MIPS_INS_ADDU_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ADDU_S_QB, MIPS_INS_ADDU_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADDVI_B, MIPS_INS_ADDVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDVI_D, MIPS_INS_ADDVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDVI_H, MIPS_INS_ADDVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDVI_W, MIPS_INS_ADDVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDV_B, MIPS_INS_ADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDV_D, MIPS_INS_ADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDV_H, MIPS_INS_ADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDV_W, MIPS_INS_ADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADDWC, MIPS_INS_ADDWC, { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_ADD_A_B, MIPS_INS_ADD_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADD_A_D, MIPS_INS_ADD_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADD_A_H, MIPS_INS_ADD_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADD_A_W, MIPS_INS_ADD_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ADD_MM, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ADDi, MIPS_INS_ADDI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ADDi_MM, MIPS_INS_ADDI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ADDiu, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ADDiu_MM, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ADDu, MIPS_INS_ADDU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ADDu_MM, MIPS_INS_ADDU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_AND, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_AND64, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ANDI_B, MIPS_INS_ANDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AND_MM, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_AND_V, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ANDi, MIPS_INS_ANDI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ANDi64, MIPS_INS_ANDI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ANDi_MM, MIPS_INS_ANDI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_APPEND, MIPS_INS_APPEND, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_ASUB_S_B, MIPS_INS_ASUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_S_D, MIPS_INS_ASUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_S_H, MIPS_INS_ASUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_S_W, MIPS_INS_ASUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_U_B, MIPS_INS_ASUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_U_D, MIPS_INS_ASUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_U_H, MIPS_INS_ASUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ASUB_U_W, MIPS_INS_ASUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_S_B, MIPS_INS_AVER_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_S_D, MIPS_INS_AVER_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_S_H, MIPS_INS_AVER_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_S_W, MIPS_INS_AVER_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_U_B, MIPS_INS_AVER_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_U_D, MIPS_INS_AVER_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_U_H, MIPS_INS_AVER_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVER_U_W, MIPS_INS_AVER_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_S_B, MIPS_INS_AVE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_S_D, MIPS_INS_AVE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_S_H, MIPS_INS_AVE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_S_W, MIPS_INS_AVE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_U_B, MIPS_INS_AVE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_U_D, MIPS_INS_AVE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_U_H, MIPS_INS_AVE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AVE_U_W, MIPS_INS_AVE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_AddiuRxImmX16, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AddiuSpImmX16, MIPS_INS_ADDIU, { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AdduRxRyRz16, MIPS_INS_ADDU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_AndRxRxRy16, MIPS_INS_AND, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_BALIGN, MIPS_INS_BALIGN, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_BC1F, MIPS_INS_BC1F, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BC1F_MM, MIPS_INS_BC1F, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BC1T, MIPS_INS_BC1T, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BC1T_MM, MIPS_INS_BC1T, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BCLRI_B, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLRI_D, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLRI_H, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLRI_W, MIPS_INS_BCLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLR_B, MIPS_INS_BCLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLR_D, MIPS_INS_BCLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLR_H, MIPS_INS_BCLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BCLR_W, MIPS_INS_BCLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BEQ, MIPS_INS_BEQ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BEQ64, MIPS_INS_BEQ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BEQ_MM, MIPS_INS_BEQ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BGEZ, MIPS_INS_BGEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BGEZ64, MIPS_INS_BGEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BGEZAL, MIPS_INS_BGEZAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_BGEZAL_MM, MIPS_INS_BGEZAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_BGEZ_MM, MIPS_INS_BGEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BGTZ, MIPS_INS_BGTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BGTZ64, MIPS_INS_BGTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BGTZ_MM, MIPS_INS_BGTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BINSLI_B, MIPS_INS_BINSLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSLI_D, MIPS_INS_BINSLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSLI_H, MIPS_INS_BINSLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSLI_W, MIPS_INS_BINSLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSL_B, MIPS_INS_BINSL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSL_D, MIPS_INS_BINSL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSL_H, MIPS_INS_BINSL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSL_W, MIPS_INS_BINSL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSRI_B, MIPS_INS_BINSRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSRI_D, MIPS_INS_BINSRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSRI_H, MIPS_INS_BINSRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSRI_W, MIPS_INS_BINSRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSR_B, MIPS_INS_BINSR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSR_D, MIPS_INS_BINSR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSR_H, MIPS_INS_BINSR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BINSR_W, MIPS_INS_BINSR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BITREV, MIPS_INS_BITREV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_BLEZ, MIPS_INS_BLEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BLEZ64, MIPS_INS_BLEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BLEZ_MM, MIPS_INS_BLEZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BLTZ, MIPS_INS_BLTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BLTZ64, MIPS_INS_BLTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BLTZAL, MIPS_INS_BLTZAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_BLTZAL_MM, MIPS_INS_BLTZAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_BLTZ_MM, MIPS_INS_BLTZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BMNZI_B, MIPS_INS_BMNZI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BMNZ_V, MIPS_INS_BMNZ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BMZI_B, MIPS_INS_BMZI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BMZ_V, MIPS_INS_BMZ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNE, MIPS_INS_BNE, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BNE64, MIPS_INS_BNE, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_BNEGI_B, MIPS_INS_BNEGI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEGI_D, MIPS_INS_BNEGI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEGI_H, MIPS_INS_BNEGI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEGI_W, MIPS_INS_BNEGI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEG_B, MIPS_INS_BNEG, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEG_D, MIPS_INS_BNEG, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEG_H, MIPS_INS_BNEG, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNEG_W, MIPS_INS_BNEG, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BNE_MM, MIPS_INS_BNE, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 },
- { Mips_BNZ_B, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BNZ_D, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BNZ_H, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BNZ_V, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BNZ_W, MIPS_INS_BNZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BPOSGE32, MIPS_INS_BPOSGE32, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0 },
- { Mips_BREAK, MIPS_INS_BREAK, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_BREAK_MM, MIPS_INS_BREAK, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_BSELI_B, MIPS_INS_BSELI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSEL_V, MIPS_INS_BSEL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSETI_B, MIPS_INS_BSETI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSETI_D, MIPS_INS_BSETI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSETI_H, MIPS_INS_BSETI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSETI_W, MIPS_INS_BSETI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSET_B, MIPS_INS_BSET, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSET_D, MIPS_INS_BSET, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSET_H, MIPS_INS_BSET, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BSET_W, MIPS_INS_BSET, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_BZ_B, MIPS_INS_BZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BZ_D, MIPS_INS_BZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BZ_H, MIPS_INS_BZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BZ_V, MIPS_INS_BZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BZ_W, MIPS_INS_BZ, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 },
- { Mips_BeqzRxImmX16, MIPS_INS_BEQZ, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 },
- { Mips_BimmX16, MIPS_INS_B, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 },
- { Mips_BnezRxImmX16, MIPS_INS_BNEZ, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 },
- { Mips_Break16, MIPS_INS_BREAK, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_BteqzX16, MIPS_INS_BTEQZ, { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 },
- { Mips_BtnezX16, MIPS_INS_BTNEZ, { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 },
- { Mips_CEIL_L_D64, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CEIL_L_S, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CEIL_W_D32, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CEIL_W_D64, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CEIL_W_MM, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CEIL_W_S, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CEIL_W_S_MM, MIPS_INS_CEIL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CEQI_B, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQI_D, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQI_H, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQI_W, MIPS_INS_CEQI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQ_B, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQ_D, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQ_H, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CEQ_W, MIPS_INS_CEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CFC1, MIPS_INS_CFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CFC1_MM, MIPS_INS_CFC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CFCMSA, MIPS_INS_CFCMSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_S_B, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_S_D, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_S_H, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_S_W, MIPS_INS_CLEI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_U_B, MIPS_INS_CLEI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_U_D, MIPS_INS_CLEI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_U_H, MIPS_INS_CLEI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLEI_U_W, MIPS_INS_CLEI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_S_B, MIPS_INS_CLE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_S_D, MIPS_INS_CLE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_S_H, MIPS_INS_CLE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_S_W, MIPS_INS_CLE_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_U_B, MIPS_INS_CLE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_U_D, MIPS_INS_CLE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_U_H, MIPS_INS_CLE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLE_U_W, MIPS_INS_CLE_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLO, MIPS_INS_CLO, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CLO_MM, MIPS_INS_CLO, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CLTI_S_B, MIPS_INS_CLTI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_S_D, MIPS_INS_CLTI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_S_H, MIPS_INS_CLTI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_S_W, MIPS_INS_CLTI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_U_B, MIPS_INS_CLTI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_U_D, MIPS_INS_CLTI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_U_H, MIPS_INS_CLTI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLTI_U_W, MIPS_INS_CLTI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_S_B, MIPS_INS_CLT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_S_D, MIPS_INS_CLT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_S_H, MIPS_INS_CLT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_S_W, MIPS_INS_CLT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_U_B, MIPS_INS_CLT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_U_D, MIPS_INS_CLT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_U_H, MIPS_INS_CLT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLT_U_W, MIPS_INS_CLT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CLZ, MIPS_INS_CLZ, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CLZ_MM, MIPS_INS_CLZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMPU_EQ_QB, MIPS_INS_CMPU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMPU_LE_QB, MIPS_INS_CMPU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMPU_LT_QB, MIPS_INS_CMPU, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMP_EQ_PH, MIPS_INS_CMP, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMP_LE_PH, MIPS_INS_CMP, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_CMP_LT_PH, MIPS_INS_CMP, { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_COPY_S_B, MIPS_INS_COPY_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_COPY_S_D, MIPS_INS_COPY_S, { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_COPY_S_H, MIPS_INS_COPY_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_COPY_S_W, MIPS_INS_COPY_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_COPY_U_B, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_COPY_U_D, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_COPY_U_H, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_COPY_U_W, MIPS_INS_COPY_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CTC1, MIPS_INS_CTC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CTC1_MM, MIPS_INS_CTC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CTCMSA, MIPS_INS_CTCMSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_CVT_D32_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_D32_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_D32_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_D64_L, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_D64_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_D64_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_D_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_L_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_L_D64_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_L_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_L_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_S_D32, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_S_D32_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_S_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_S_L, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_S_W, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_S_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_W_D32, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_W_D64, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_W_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_CVT_W_S, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CVT_W_S_MM, MIPS_INS_CVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_C_EQ_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_EQ_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_EQ_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_F_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_F_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_F_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LE_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LE_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LE_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LT_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LT_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_LT_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGE_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGE_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGE_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGLE_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGLE_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGLE_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGL_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGL_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGL_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGT_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGT_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_NGT_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLE_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLE_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLE_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLT_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLT_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_OLT_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SEQ_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SEQ_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SEQ_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SF_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SF_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_SF_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UEQ_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UEQ_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UEQ_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULE_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULE_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULE_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULT_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULT_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_ULT_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UN_D32, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UN_D64, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_C_UN_S, MIPS_INS_C, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_CmpRxRy16, MIPS_INS_CMP, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_CmpiRxImmX16, MIPS_INS_CMPI, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_DADD, MIPS_INS_DADD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DADDi, MIPS_INS_DADDI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DADDiu, MIPS_INS_DADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DADDu, MIPS_INS_DADDU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DCLO, MIPS_INS_DCLO, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DCLZ, MIPS_INS_DCLZ, { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DERET, MIPS_INS_DERET, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DERET_MM, MIPS_INS_DERET, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_DEXT, MIPS_INS_DEXT, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DEXTM, MIPS_INS_DEXTM, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DEXTU, MIPS_INS_DEXTU, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DI, MIPS_INS_DI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DINS, MIPS_INS_DINS, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DINSM, MIPS_INS_DINSM, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DINSU, MIPS_INS_DINSU, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DIV_S_B, MIPS_INS_DIV_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_S_D, MIPS_INS_DIV_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_S_H, MIPS_INS_DIV_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_S_W, MIPS_INS_DIV_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_U_B, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_U_D, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_U_H, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DIV_U_W, MIPS_INS_DIV_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DI_MM, MIPS_INS_DI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_DLSA, MIPS_INS_DLSA, { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_DMFC0, MIPS_INS_DMFC0, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_DMFC1, MIPS_INS_DMFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DMFC2, MIPS_INS_DMFC2, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_DMTC0, MIPS_INS_DMTC0, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_DMTC1, MIPS_INS_DMTC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DMTC2, MIPS_INS_DMTC2, { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_DMULT, MIPS_INS_DMULT, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DMULTu, MIPS_INS_DMULTU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DOTP_S_D, MIPS_INS_DOTP_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DOTP_S_H, MIPS_INS_DOTP_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DOTP_S_W, MIPS_INS_DOTP_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DOTP_U_D, MIPS_INS_DOTP_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DOTP_U_H, MIPS_INS_DOTP_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DOTP_U_W, MIPS_INS_DOTP_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_S_D, MIPS_INS_DPADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_S_H, MIPS_INS_DPADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_S_W, MIPS_INS_DPADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_U_D, MIPS_INS_DPADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_U_H, MIPS_INS_DPADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPADD_U_W, MIPS_INS_DPADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPAU_H_QBL, MIPS_INS_DPAU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPAU_H_QBR, MIPS_INS_DPAU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPAX_W_PH, MIPS_INS_DPAX, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPA_W_PH, MIPS_INS_DPA, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_DPSU_H_QBL, MIPS_INS_DPSU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPSU_H_QBR, MIPS_INS_DPSU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_DPSX_W_PH, MIPS_INS_DPSX, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DPS_W_PH, MIPS_INS_DPS, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_DROTR, MIPS_INS_DROTR, { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DROTR32, MIPS_INS_DROTR32, { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DROTRV, MIPS_INS_DROTRV, { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSBH, MIPS_INS_DSBH, { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSDIV, MIPS_INS_DDIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSHD, MIPS_INS_DSHD, { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSLL, MIPS_INS_DSLL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSLL32, MIPS_INS_DSLL32, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSLL64_32, MIPS_INS_DSLL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSLLV, MIPS_INS_DSLLV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRA, MIPS_INS_DSRA, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRA32, MIPS_INS_DSRA32, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRAV, MIPS_INS_DSRAV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRL, MIPS_INS_DSRL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRL32, MIPS_INS_DSRL32, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSRLV, MIPS_INS_DSRLV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DSUBu, MIPS_INS_DSUBU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DUDIV, MIPS_INS_DDIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_DivRxRy16, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_DivuRxRy16, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_EI, MIPS_INS_EI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_EI_MM, MIPS_INS_EI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ERET, MIPS_INS_ERET, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ERET_MM, MIPS_INS_ERET, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_EXT, MIPS_INS_EXT, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_EXTP, MIPS_INS_EXTP, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTPDP, MIPS_INS_EXTPDP, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTPDPV, MIPS_INS_EXTPDPV, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTPV, MIPS_INS_EXTPV, { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTRV_W, MIPS_INS_EXTRV, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTR_R_W, MIPS_INS_EXTR_R, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTR_S_H, MIPS_INS_EXTR_S, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXTR_W, MIPS_INS_EXTR, { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_EXT_MM, MIPS_INS_EXT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FABS_D32, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FABS_D64, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FABS_MM, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FABS_S, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FABS_S_MM, MIPS_INS_ABS, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FADD_D, MIPS_INS_FADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FADD_D32, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FADD_D64, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FADD_MM, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FADD_S, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FADD_S_MM, MIPS_INS_ADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FADD_W, MIPS_INS_FADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCAF_D, MIPS_INS_FCAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCAF_W, MIPS_INS_FCAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCEQ_D, MIPS_INS_FCEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCEQ_W, MIPS_INS_FCEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLASS_D, MIPS_INS_FCLASS, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLASS_W, MIPS_INS_FCLASS, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLE_D, MIPS_INS_FCLE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLE_W, MIPS_INS_FCLE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLT_D, MIPS_INS_FCLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCLT_W, MIPS_INS_FCLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCMP_D32, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FCMP_D32_MM, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FCMP_D64, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FCMP_S32, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FCMP_S32_MM, MIPS_INS_C, { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FCNE_D, MIPS_INS_FCNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCNE_W, MIPS_INS_FCNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCOR_D, MIPS_INS_FCOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCOR_W, MIPS_INS_FCOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUEQ_D, MIPS_INS_FCUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUEQ_W, MIPS_INS_FCUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCULE_D, MIPS_INS_FCULE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCULE_W, MIPS_INS_FCULE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCULT_D, MIPS_INS_FCULT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCULT_W, MIPS_INS_FCULT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUNE_D, MIPS_INS_FCUNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUNE_W, MIPS_INS_FCUNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUN_D, MIPS_INS_FCUN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FCUN_W, MIPS_INS_FCUN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FDIV_D, MIPS_INS_FDIV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FDIV_D32, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FDIV_D64, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FDIV_MM, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FDIV_S, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FDIV_S_MM, MIPS_INS_DIV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FDIV_W, MIPS_INS_FDIV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXDO_H, MIPS_INS_FEXDO, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXDO_W, MIPS_INS_FEXDO, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXP2_D, MIPS_INS_FEXP2, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXP2_W, MIPS_INS_FEXP2, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXUPL_D, MIPS_INS_FEXUPL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXUPL_W, MIPS_INS_FEXUPL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXUPR_D, MIPS_INS_FEXUPR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FEXUPR_W, MIPS_INS_FEXUPR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFINT_S_D, MIPS_INS_FFINT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFINT_S_W, MIPS_INS_FFINT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFINT_U_D, MIPS_INS_FFINT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFINT_U_W, MIPS_INS_FFINT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFQL_D, MIPS_INS_FFQL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFQL_W, MIPS_INS_FFQL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFQR_D, MIPS_INS_FFQR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FFQR_W, MIPS_INS_FFQR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FILL_B, MIPS_INS_FILL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FILL_D, MIPS_INS_FILL, { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_FILL_H, MIPS_INS_FILL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FILL_W, MIPS_INS_FILL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FLOG2_D, MIPS_INS_FLOG2, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FLOG2_W, MIPS_INS_FLOG2, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FLOOR_L_D64, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FLOOR_L_S, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FLOOR_W_D32, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FLOOR_W_D64, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FLOOR_W_MM, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FLOOR_W_S, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FMADD_D, MIPS_INS_FMADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMADD_W, MIPS_INS_FMADD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMAX_A_D, MIPS_INS_FMAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMAX_A_W, MIPS_INS_FMAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMAX_D, MIPS_INS_FMAX, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMAX_W, MIPS_INS_FMAX, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMIN_A_D, MIPS_INS_FMIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMIN_A_W, MIPS_INS_FMIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMIN_D, MIPS_INS_FMIN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMIN_W, MIPS_INS_FMIN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMOV_D32, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMOV_D32_MM, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FMOV_D64, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMOV_S, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMOV_S_MM, MIPS_INS_MOV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FMSUB_D, MIPS_INS_FMSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMSUB_W, MIPS_INS_FMSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMUL_D, MIPS_INS_FMUL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FMUL_D32, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMUL_D64, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMUL_MM, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FMUL_S, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FMUL_S_MM, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FMUL_W, MIPS_INS_FMUL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FNEG_D32, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FNEG_D64, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FNEG_MM, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FNEG_S, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FNEG_S_MM, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FRCP_D, MIPS_INS_FRCP, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FRCP_W, MIPS_INS_FRCP, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FRINT_D, MIPS_INS_FRINT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FRINT_W, MIPS_INS_FRINT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FRSQRT_D, MIPS_INS_FRSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FRSQRT_W, MIPS_INS_FRSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSAF_D, MIPS_INS_FSAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSAF_W, MIPS_INS_FSAF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSEQ_D, MIPS_INS_FSEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSEQ_W, MIPS_INS_FSEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSLE_D, MIPS_INS_FSLE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSLE_W, MIPS_INS_FSLE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSLT_D, MIPS_INS_FSLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSLT_W, MIPS_INS_FSLT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSNE_D, MIPS_INS_FSNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSNE_W, MIPS_INS_FSNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSOR_D, MIPS_INS_FSOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSOR_W, MIPS_INS_FSOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSQRT_D, MIPS_INS_FSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSQRT_D32, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSQRT_D64, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSQRT_MM, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FSQRT_S, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSQRT_S_MM, MIPS_INS_SQRT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FSQRT_W, MIPS_INS_FSQRT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUB_D, MIPS_INS_FSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUB_D32, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSUB_D64, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSUB_MM, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FSUB_S, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_FSUB_S_MM, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_FSUB_W, MIPS_INS_FSUB, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUEQ_D, MIPS_INS_FSUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUEQ_W, MIPS_INS_FSUEQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSULE_D, MIPS_INS_FSULE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSULE_W, MIPS_INS_FSULE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSULT_D, MIPS_INS_FSULT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSULT_W, MIPS_INS_FSULT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUNE_D, MIPS_INS_FSUNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUNE_W, MIPS_INS_FSUNE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUN_D, MIPS_INS_FSUN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FSUN_W, MIPS_INS_FSUN, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTINT_S_D, MIPS_INS_FTINT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTINT_S_W, MIPS_INS_FTINT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTINT_U_D, MIPS_INS_FTINT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTINT_U_W, MIPS_INS_FTINT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTQ_H, MIPS_INS_FTQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTQ_W, MIPS_INS_FTQ, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_S_D, MIPS_INS_HADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_S_H, MIPS_INS_HADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_S_W, MIPS_INS_HADD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_U_D, MIPS_INS_HADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_U_H, MIPS_INS_HADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HADD_U_W, MIPS_INS_HADD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_S_D, MIPS_INS_HSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_S_H, MIPS_INS_HSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_S_W, MIPS_INS_HSUB_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_U_D, MIPS_INS_HSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_U_H, MIPS_INS_HSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_HSUB_U_W, MIPS_INS_HSUB_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVEV_B, MIPS_INS_ILVEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVEV_D, MIPS_INS_ILVEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVEV_H, MIPS_INS_ILVEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVEV_W, MIPS_INS_ILVEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVL_B, MIPS_INS_ILVL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVL_D, MIPS_INS_ILVL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVL_H, MIPS_INS_ILVL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVL_W, MIPS_INS_ILVL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVOD_B, MIPS_INS_ILVOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVOD_D, MIPS_INS_ILVOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVOD_H, MIPS_INS_ILVOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVOD_W, MIPS_INS_ILVOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVR_B, MIPS_INS_ILVR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVR_D, MIPS_INS_ILVR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVR_H, MIPS_INS_ILVR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ILVR_W, MIPS_INS_ILVR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INS, MIPS_INS_INS, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_INSERT_B, MIPS_INS_INSERT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSERT_D, MIPS_INS_INSERT, { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 },
- { Mips_INSERT_H, MIPS_INS_INSERT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSERT_W, MIPS_INS_INSERT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSV, MIPS_INS_INSV, { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_INSVE_B, MIPS_INS_INSVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSVE_D, MIPS_INS_INSVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSVE_H, MIPS_INS_INSVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INSVE_W, MIPS_INS_INSVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_INS_MM, MIPS_INS_INS, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_J, MIPS_INS_J, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 },
- { Mips_JAL, MIPS_INS_JAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_JALR, MIPS_INS_JALR, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_JALR64, MIPS_INS_JALR, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_JALR_MM, MIPS_INS_JALR, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_JAL_MM, MIPS_INS_JAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_JR, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 },
- { Mips_JR64, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 },
- { Mips_JR_MM, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 },
- { Mips_J_MM, MIPS_INS_J, { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_Jal16, MIPS_INS_JAL, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_JrRa16, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
- { Mips_JrcRa16, MIPS_INS_JRC, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
- { Mips_JrcRx16, MIPS_INS_JRC, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 },
- { Mips_JumpLinkReg16, MIPS_INS_JALRC, { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LB, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LB64, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LBUX, MIPS_INS_LBUX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_LB_MM, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LBu, MIPS_INS_LBU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LBu64, MIPS_INS_LBU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LBu_MM, MIPS_INS_LBU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LD, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDC1, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDC164, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDC1_MM, MIPS_INS_LDC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LDC2, MIPS_INS_LDC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDI_B, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LDI_D, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LDI_H, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LDI_W, MIPS_INS_LDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LDL, MIPS_INS_LDL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDR, MIPS_INS_LDR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LDXC1, MIPS_INS_LDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_LDXC164, MIPS_INS_LDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LD_B, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LD_D, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LD_H, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LD_W, MIPS_INS_LD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LEA_ADDiu, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LEA_ADDiu64, MIPS_INS_DADDIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LH, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LH64, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LHX, MIPS_INS_LHX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_LH_MM, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LHu, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LHu64, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LHu_MM, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LL, MIPS_INS_LL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_LLD, MIPS_INS_LLD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LL_MM, MIPS_INS_LL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LSA, MIPS_INS_LSA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_LUXC1, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_LUXC164, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LUXC1_MM, MIPS_INS_LUXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LUi, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LUi64, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LUi_MM, MIPS_INS_LUI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LW, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LW64, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LWC1, MIPS_INS_LWC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LWC1_MM, MIPS_INS_LWC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LWC2, MIPS_INS_LWC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LWL, MIPS_INS_LWL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_LWL64, MIPS_INS_LWL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LWL_MM, MIPS_INS_LWL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LWR, MIPS_INS_LWR, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_LWR64, MIPS_INS_LWR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LWR_MM, MIPS_INS_LWR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LWU_MM, MIPS_INS_LWU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LWX, MIPS_INS_LWX, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_LWXC1, MIPS_INS_LWXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_LWXC1_MM, MIPS_INS_LWXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LW_MM, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_LWu, MIPS_INS_LWU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_LbRxRyOffMemX16, MIPS_INS_LB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LhRxRyOffMemX16, MIPS_INS_LH, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LiRxImmX16, MIPS_INS_LI, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LwRxPcTcpX16, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LwRxRyOffMemX16, MIPS_INS_LW, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_LwRxSpImmX16, MIPS_INS_LW, { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_MADD, MIPS_INS_MADD, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADDU, MIPS_INS_MADDU, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MADDU_DSP, MIPS_INS_MADDU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MADDU_MM, MIPS_INS_MADDU, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MADDV_B, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADDV_D, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADDV_H, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADDV_W, MIPS_INS_MADDV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADD_D32, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MADD_D32_MM, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MADD_D64, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MADD_DSP, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MADD_MM, MIPS_INS_MADD, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MADD_Q_H, MIPS_INS_MADD_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADD_Q_W, MIPS_INS_MADD_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MADD_S, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MADD_S_MM, MIPS_INS_MADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MAXI_S_B, MIPS_INS_MAXI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_S_D, MIPS_INS_MAXI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_S_H, MIPS_INS_MAXI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_S_W, MIPS_INS_MAXI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_U_B, MIPS_INS_MAXI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_U_D, MIPS_INS_MAXI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_U_H, MIPS_INS_MAXI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAXI_U_W, MIPS_INS_MAXI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_A_B, MIPS_INS_MAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_A_D, MIPS_INS_MAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_A_H, MIPS_INS_MAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_A_W, MIPS_INS_MAX_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_S_B, MIPS_INS_MAX_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_S_D, MIPS_INS_MAX_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_S_H, MIPS_INS_MAX_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_S_W, MIPS_INS_MAX_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_U_B, MIPS_INS_MAX_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_U_D, MIPS_INS_MAX_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_U_H, MIPS_INS_MAX_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MAX_U_W, MIPS_INS_MAX_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MFC0, MIPS_INS_MFC0, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFC1, MIPS_INS_MFC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFC1_MM, MIPS_INS_MFC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MFC2, MIPS_INS_MFC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFHC1, MIPS_INS_MFHC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFHC1_MM, MIPS_INS_MFHC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MFHI, MIPS_INS_MFHI, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFHI64, MIPS_INS_MFHI, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFHI_DSP, MIPS_INS_MFHI, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MFHI_MM, MIPS_INS_MFHI, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MFLO, MIPS_INS_MFLO, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFLO64, MIPS_INS_MFLO, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MFLO_DSP, MIPS_INS_MFLO, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MFLO_MM, MIPS_INS_MFLO, { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MINI_S_B, MIPS_INS_MINI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_S_D, MIPS_INS_MINI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_S_H, MIPS_INS_MINI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_S_W, MIPS_INS_MINI_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_U_B, MIPS_INS_MINI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_U_D, MIPS_INS_MINI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_U_H, MIPS_INS_MINI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MINI_U_W, MIPS_INS_MINI_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_A_B, MIPS_INS_MIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_A_D, MIPS_INS_MIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_A_H, MIPS_INS_MIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_A_W, MIPS_INS_MIN_A, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_S_B, MIPS_INS_MIN_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_S_D, MIPS_INS_MIN_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_S_H, MIPS_INS_MIN_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_S_W, MIPS_INS_MIN_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_U_B, MIPS_INS_MIN_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_U_D, MIPS_INS_MIN_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_U_H, MIPS_INS_MIN_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MIN_U_W, MIPS_INS_MIN_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MODSUB, MIPS_INS_MODSUB, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MOD_S_B, MIPS_INS_MOD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_S_D, MIPS_INS_MOD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_S_H, MIPS_INS_MOD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_S_W, MIPS_INS_MOD_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_U_B, MIPS_INS_MOD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_U_D, MIPS_INS_MOD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_U_H, MIPS_INS_MOD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOD_U_W, MIPS_INS_MOD_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOVE_V, MIPS_INS_MOVE, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MOVF_D32, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVF_D32_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVF_D64, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVF_I, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVF_I64, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVF_I_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVF_S, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVF_S_MM, MIPS_INS_MOVF, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVN_I64_D64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I64_I, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I64_I64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I64_S, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_D32, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVN_I_D64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_I, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_I64, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVN_I_S, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVN_I_S_MM, MIPS_INS_MOVN, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVT_D32, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVT_D32_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVT_D64, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVT_I, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVT_I64, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVT_I_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVT_S, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVT_S_MM, MIPS_INS_MOVT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I64_I, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I64_S, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_D32, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVZ_I_D64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_I, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_I64, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MOVZ_I_S, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MSUB, MIPS_INS_MSUB, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUBU, MIPS_INS_MSUBU, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MSUBU_DSP, MIPS_INS_MSUBU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MSUBU_MM, MIPS_INS_MSUBU, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MSUBV_B, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUBV_D, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUBV_H, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUBV_W, MIPS_INS_MSUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUB_D32, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MSUB_D32_MM, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MSUB_D64, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MSUB_DSP, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MSUB_MM, MIPS_INS_MSUB, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MSUB_S, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MSUB_S_MM, MIPS_INS_MSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MTC0, MIPS_INS_MTC0, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTC1, MIPS_INS_MTC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTC1_MM, MIPS_INS_MTC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MTC2, MIPS_INS_MTC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTHC1, MIPS_INS_MTHC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTHC1_MM, MIPS_INS_MTHC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MTHI, MIPS_INS_MTHI, { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTHI64, MIPS_INS_MTHI, { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTHI_DSP, MIPS_INS_MTHI, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MTHI_MM, MIPS_INS_MTHI, { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MTHLIP, MIPS_INS_MTHLIP, { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MTLO, MIPS_INS_MTLO, { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTLO64, MIPS_INS_MTLO, { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MTLO_DSP, MIPS_INS_MTLO, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MTLO_MM, MIPS_INS_MTLO, { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MUL, MIPS_INS_MUL, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_MULQ_S_PH, MIPS_INS_MULQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_MULQ_S_W, MIPS_INS_MULQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_MULR_Q_H, MIPS_INS_MULR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MULR_Q_W, MIPS_INS_MULR_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULSA_W_PH, MIPS_INS_MULSA, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_MULT, MIPS_INS_MULT, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MULTU_DSP, MIPS_INS_MULTU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULT_DSP, MIPS_INS_MULT, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_MULT_MM, MIPS_INS_MULT, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MULTu, MIPS_INS_MULTU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_MULTu_MM, MIPS_INS_MULTU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MULV_B, MIPS_INS_MULV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MULV_D, MIPS_INS_MULV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MULV_H, MIPS_INS_MULV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MULV_W, MIPS_INS_MULV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MUL_MM, MIPS_INS_MUL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_MUL_PH, MIPS_INS_MUL, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_MUL_Q_H, MIPS_INS_MUL_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MUL_Q_W, MIPS_INS_MUL_Q, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_MUL_S_PH, MIPS_INS_MUL_S, { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_Mfhi16, MIPS_INS_MFHI, { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_Mflo16, MIPS_INS_MFLO, { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_Move32R16, MIPS_INS_MOVE, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_MoveR3216, MIPS_INS_MOVE, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_NLOC_B, MIPS_INS_NLOC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLOC_D, MIPS_INS_NLOC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLOC_H, MIPS_INS_NLOC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLOC_W, MIPS_INS_NLOC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLZC_B, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLZC_D, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLZC_H, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NLZC_W, MIPS_INS_NLZC, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NMADD_D32, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMADD_D32_MM, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_NMADD_D64, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMADD_S, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMADD_S_MM, MIPS_INS_NMADD, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_NMSUB_D32, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_NMSUB_D64, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMSUB_S, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NMSUB_S_MM, MIPS_INS_NMSUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_NOR, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NOR64, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_NORI_B, MIPS_INS_NORI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NOR_MM, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_NOR_V, MIPS_INS_NOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_NegRxRy16, MIPS_INS_NEG, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_NotRxRy16, MIPS_INS_NOT, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_OR, MIPS_INS_OR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_OR64, MIPS_INS_OR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ORI_B, MIPS_INS_ORI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_OR_MM, MIPS_INS_OR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_OR_V, MIPS_INS_OR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ORi, MIPS_INS_ORI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ORi64, MIPS_INS_ORI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ORi_MM, MIPS_INS_ORI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_OrRxRxRy16, MIPS_INS_OR, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_PACKRL_PH, MIPS_INS_PACKRL, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PCKEV_B, MIPS_INS_PCKEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKEV_D, MIPS_INS_PCKEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKEV_H, MIPS_INS_PCKEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKEV_W, MIPS_INS_PCKEV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKOD_B, MIPS_INS_PCKOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKOD_D, MIPS_INS_PCKOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKOD_H, MIPS_INS_PCKOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCKOD_W, MIPS_INS_PCKOD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCNT_B, MIPS_INS_PCNT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCNT_D, MIPS_INS_PCNT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCNT_H, MIPS_INS_PCNT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PCNT_W, MIPS_INS_PCNT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_PICK_PH, MIPS_INS_PICK, { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PICK_QB, MIPS_INS_PICK, { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_PRECR_QB_PH, MIPS_INS_PRECR, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_PREPEND, MIPS_INS_PREPEND, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_RADDU_W_QB, MIPS_INS_RADDU, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_RDDSP, MIPS_INS_RDDSP, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_RDHWR, MIPS_INS_RDHWR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_RDHWR64, MIPS_INS_RDHWR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_REPLV_PH, MIPS_INS_REPLV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_REPLV_QB, MIPS_INS_REPLV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_REPL_PH, MIPS_INS_REPL, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_REPL_QB, MIPS_INS_REPL, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_RET, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_RET_MM, MIPS_INS_JR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ROTR, MIPS_INS_ROTR, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROTRV, MIPS_INS_ROTRV, { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROTRV_MM, MIPS_INS_ROTRV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ROTR_MM, MIPS_INS_ROTR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ROUND_L_D64, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROUND_L_S, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROUND_W_D32, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROUND_W_D64, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROUND_W_MM, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_ROUND_W_S, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_ROUND_W_S_MM, MIPS_INS_ROUND, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SAT_S_B, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_S_D, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_S_H, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_S_W, MIPS_INS_SAT_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_U_B, MIPS_INS_SAT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_U_D, MIPS_INS_SAT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_U_H, MIPS_INS_SAT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SAT_U_W, MIPS_INS_SAT_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SB, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SB64, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SB_MM, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SC, MIPS_INS_SC, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_SCD, MIPS_INS_SCD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SC_MM, MIPS_INS_SC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SD, MIPS_INS_SD, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDC1, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDC164, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDC1_MM, MIPS_INS_SDC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SDC2, MIPS_INS_SDC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDIV, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDIV_MM, MIPS_INS_DIV, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SDL, MIPS_INS_SDL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDR, MIPS_INS_SDR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SDXC1, MIPS_INS_SDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_SDXC164, MIPS_INS_SDXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SEB, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SEB64, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SEB_MM, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SEH, MIPS_INS_SEH, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SEH64, MIPS_INS_SEH, { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SEH_MM, MIPS_INS_SEH, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SH, MIPS_INS_SH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SH64, MIPS_INS_SH, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SHF_B, MIPS_INS_SHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SHF_H, MIPS_INS_SHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SHF_W, MIPS_INS_SHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SHILO, MIPS_INS_SHILO, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHILOV, MIPS_INS_SHILOV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLLV_PH, MIPS_INS_SHLLV, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLLV_QB, MIPS_INS_SHLLV, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLL_PH, MIPS_INS_SHLL, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLL_QB, MIPS_INS_SHLL, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLL_S_PH, MIPS_INS_SHLL_S, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHLL_S_W, MIPS_INS_SHLL_S, { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRAV_PH, MIPS_INS_SHRAV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRAV_QB, MIPS_INS_SHRAV, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRA_PH, MIPS_INS_SHRA, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRA_QB, MIPS_INS_SHRA, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRA_R_PH, MIPS_INS_SHRA_R, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRA_R_QB, MIPS_INS_SHRA_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRA_R_W, MIPS_INS_SHRA_R, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRLV_PH, MIPS_INS_SHRLV, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRLV_QB, MIPS_INS_SHRLV, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SHRL_PH, MIPS_INS_SHRL, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SHRL_QB, MIPS_INS_SHRL, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SH_MM, MIPS_INS_SH, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLDI_B, MIPS_INS_SLDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLDI_D, MIPS_INS_SLDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLDI_H, MIPS_INS_SLDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLDI_W, MIPS_INS_SLDI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLD_B, MIPS_INS_SLD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLD_D, MIPS_INS_SLD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLD_H, MIPS_INS_SLD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLD_W, MIPS_INS_SLD, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLL, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLL64_32, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLL64_64, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLLI_B, MIPS_INS_SLLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLLI_D, MIPS_INS_SLLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLLI_H, MIPS_INS_SLLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLLI_W, MIPS_INS_SLLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLLV, MIPS_INS_SLLV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLLV_MM, MIPS_INS_SLLV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLL_B, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLL_D, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLL_H, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLL_MM, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLL_W, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SLT, MIPS_INS_SLT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLT64, MIPS_INS_SLT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLT_MM, MIPS_INS_SLT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLTi, MIPS_INS_SLTI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTi64, MIPS_INS_SLTI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTi_MM, MIPS_INS_SLTI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLTiu, MIPS_INS_SLTIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTiu64, MIPS_INS_SLTIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTiu_MM, MIPS_INS_SLTIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SLTu, MIPS_INS_SLTU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTu64, MIPS_INS_SLTU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SLTu_MM, MIPS_INS_SLTU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SPLATI_B, MIPS_INS_SPLATI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLATI_D, MIPS_INS_SPLATI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLATI_H, MIPS_INS_SPLATI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLATI_W, MIPS_INS_SPLATI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLAT_B, MIPS_INS_SPLAT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLAT_D, MIPS_INS_SPLAT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLAT_H, MIPS_INS_SPLAT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SPLAT_W, MIPS_INS_SPLAT, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRA, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SRAI_B, MIPS_INS_SRAI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAI_D, MIPS_INS_SRAI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAI_H, MIPS_INS_SRAI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAI_W, MIPS_INS_SRAI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRARI_B, MIPS_INS_SRARI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRARI_D, MIPS_INS_SRARI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRARI_H, MIPS_INS_SRARI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRARI_W, MIPS_INS_SRARI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAR_B, MIPS_INS_SRAR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAR_D, MIPS_INS_SRAR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAR_H, MIPS_INS_SRAR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAR_W, MIPS_INS_SRAR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRAV, MIPS_INS_SRAV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SRAV_MM, MIPS_INS_SRAV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SRA_B, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRA_D, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRA_H, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRA_MM, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SRA_W, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRL, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SRLI_B, MIPS_INS_SRLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLI_D, MIPS_INS_SRLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLI_H, MIPS_INS_SRLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLI_W, MIPS_INS_SRLI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLRI_B, MIPS_INS_SRLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLRI_D, MIPS_INS_SRLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLRI_H, MIPS_INS_SRLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLRI_W, MIPS_INS_SRLRI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLR_B, MIPS_INS_SRLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLR_D, MIPS_INS_SRLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLR_H, MIPS_INS_SRLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLR_W, MIPS_INS_SRLR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRLV, MIPS_INS_SRLV, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SRLV_MM, MIPS_INS_SRLV, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SRL_B, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRL_D, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRL_H, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SRL_MM, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SRL_W, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ST_B, MIPS_INS_ST, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ST_D, MIPS_INS_ST, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ST_H, MIPS_INS_ST, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_ST_W, MIPS_INS_ST, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUB, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SUBQH_PH, MIPS_INS_SUBQH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBQH_W, MIPS_INS_SUBQH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBQ_PH, MIPS_INS_SUBQ, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_S_B, MIPS_INS_SUBS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_S_D, MIPS_INS_SUBS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_S_H, MIPS_INS_SUBS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_S_W, MIPS_INS_SUBS_S, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_U_B, MIPS_INS_SUBS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_U_D, MIPS_INS_SUBS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_U_H, MIPS_INS_SUBS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBS_U_W, MIPS_INS_SUBS_U, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBUH_QB, MIPS_INS_SUBUH, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBU_PH, MIPS_INS_SUBU, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBU_QB, MIPS_INS_SUBU, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SUBU_S_PH, MIPS_INS_SUBU_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 },
- { Mips_SUBU_S_QB, MIPS_INS_SUBU_S, { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_SUBVI_B, MIPS_INS_SUBVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBVI_D, MIPS_INS_SUBVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBVI_H, MIPS_INS_SUBVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBVI_W, MIPS_INS_SUBVI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBV_B, MIPS_INS_SUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBV_D, MIPS_INS_SUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBV_H, MIPS_INS_SUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUBV_W, MIPS_INS_SUBV, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_SUB_MM, MIPS_INS_SUB, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SUBu, MIPS_INS_SUBU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SUBu_MM, MIPS_INS_SUBU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SUXC1, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_SUXC164, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SUXC1_MM, MIPS_INS_SUXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SW, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SW64, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SWC1, MIPS_INS_SWC1, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SWC1_MM, MIPS_INS_SWC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SWC2, MIPS_INS_SWC2, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SWL, MIPS_INS_SWL, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_SWL64, MIPS_INS_SWL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SWL_MM, MIPS_INS_SWL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SWR, MIPS_INS_SWR, { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 },
- { Mips_SWR64, MIPS_INS_SWR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SWR_MM, MIPS_INS_SWR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SWXC1, MIPS_INS_SWXC1, { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0 },
- { Mips_SWXC1_MM, MIPS_INS_SWXC1, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SW_MM, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SYNC, MIPS_INS_SYNC, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SYNC_MM, MIPS_INS_SYNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SYSCALL, MIPS_INS_SYSCALL, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_SYSCALL_MM, MIPS_INS_SYSCALL, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_SbRxRyOffMemX16, MIPS_INS_SB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SebRx16, MIPS_INS_SEB, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SehRx16, MIPS_INS_SEH, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_ShRxRyOffMemX16, MIPS_INS_SH, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SllX16, MIPS_INS_SLL, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SllvRxRy16, MIPS_INS_SLLV, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SltRxRy16, MIPS_INS_SLT, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SltiRxImmX16, MIPS_INS_SLTI, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SltiuRxImmX16, MIPS_INS_SLTIU, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SltuRxRy16, MIPS_INS_SLTU, { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SraX16, MIPS_INS_SRA, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SravRxRy16, MIPS_INS_SRAV, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SrlX16, MIPS_INS_SRL, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SrlvRxRy16, MIPS_INS_SRLV, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SubuRxRyRz16, MIPS_INS_SUBU, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SwRxRyOffMemX16, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_SwRxSpImmX16, MIPS_INS_SW, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
- { Mips_TEQ, MIPS_INS_TEQ, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TEQI, MIPS_INS_TEQI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TEQI_MM, MIPS_INS_TEQI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TEQ_MM, MIPS_INS_TEQ, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TGE, MIPS_INS_TGE, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TGEI, MIPS_INS_TGEI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TGEIU, MIPS_INS_TGEIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TGEIU_MM, MIPS_INS_TGEIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TGEI_MM, MIPS_INS_TGEI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TGEU, MIPS_INS_TGEU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TGEU_MM, MIPS_INS_TGEU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TGE_MM, MIPS_INS_TGE, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TLT, MIPS_INS_TLT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TLTI, MIPS_INS_TLTI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TLTIU_MM, MIPS_INS_TLTIU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TLTI_MM, MIPS_INS_TLTI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TLTU, MIPS_INS_TLTU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TLTU_MM, MIPS_INS_TLTU, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TLT_MM, MIPS_INS_TLT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TNE, MIPS_INS_TNE, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TNEI, MIPS_INS_TNEI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TNEI_MM, MIPS_INS_TNEI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TNE_MM, MIPS_INS_TNE, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TRUNC_L_D64, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TRUNC_L_S, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TRUNC_W_D32, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TRUNC_W_D64, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TRUNC_W_MM, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TRUNC_W_S, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_TTLTIU, MIPS_INS_TLTIU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_UDIV, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_UDIV_MM, MIPS_INS_DIVU, { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_VSHF_B, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_VSHF_D, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_VSHF_H, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_VSHF_W, MIPS_INS_VSHF, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_WAIT, MIPS_INS_WAIT, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_WAIT_MM, MIPS_INS_WAIT, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_WRDSP, MIPS_INS_WRDSP, { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 },
- { Mips_WSBH, MIPS_INS_WSBH, { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_WSBH_MM, MIPS_INS_WSBH, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_XOR, MIPS_INS_XOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_XOR64, MIPS_INS_XOR, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_XORI_B, MIPS_INS_XORI, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_XOR_MM, MIPS_INS_XOR, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_XOR_V, MIPS_INS_XOR, { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 },
- { Mips_XORi, MIPS_INS_XORI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_XORi64, MIPS_INS_XORI, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
- { Mips_XORi_MM, MIPS_INS_XORI, { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 },
- { Mips_XorRxRxRy16, MIPS_INS_XOR, { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 },
+ {
+ Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ABSQ_S_W, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQH_PH, MIPS_INS_ADDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQH_R_W, MIPS_INS_ADDQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQH_W, MIPS_INS_ADDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQ_PH, MIPS_INS_ADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDQ_S_W, MIPS_INS_ADDQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDSC, MIPS_INS_ADDSC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_A_B, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_A_D, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_A_H, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_A_W, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_S_B, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_S_D, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_S_H, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_S_W, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_U_B, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_U_D, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_U_H, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDS_U_W, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDUH_QB, MIPS_INS_ADDUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDU_PH, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDU_QB, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDU_S_PH, MIPS_INS_ADDU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDU_S_QB, MIPS_INS_ADDU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDVI_B, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDVI_D, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDVI_H, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDVI_W, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDV_B, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDV_D, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDV_H, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDV_W, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDWC, MIPS_INS_ADDWC,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD_A_B, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD_A_D, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD_A_H, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD_A_W, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADD_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDi, MIPS_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDi_MM, MIPS_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDiu, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDiu_MM, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDu, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ADDu_MM, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AND, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AND64, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ANDI_B, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AND_MM, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AND_V, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ANDi, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ANDi64, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ANDi_MM, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_APPEND, MIPS_INS_APPEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_S_B, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_S_D, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_S_H, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_S_W, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_U_B, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_U_D, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_U_H, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ASUB_U_W, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_S_B, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_S_D, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_S_H, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_S_W, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_U_B, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_U_D, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_U_H, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVER_U_W, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_S_B, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_S_D, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_S_H, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_S_W, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_U_B, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_U_D, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_U_H, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AVE_U_W, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AddiuRxImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AddiuSpImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AdduRxRyRz16, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_AndRxRxRy16, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BALIGN, MIPS_INS_BALIGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BC1F, MIPS_INS_BC1F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BC1F_MM, MIPS_INS_BC1F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BC1T, MIPS_INS_BC1T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BC1T_MM, MIPS_INS_BC1T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BCLRI_B, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLRI_D, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLRI_H, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLRI_W, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLR_B, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLR_D, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLR_H, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BCLR_W, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BEQ, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BEQ64, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BEQ_MM, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGEZ, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGEZ64, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGEZAL, MIPS_INS_BGEZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BGEZ_MM, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGTZ, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGTZ64, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BGTZ_MM, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BINSLI_B, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSLI_D, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSLI_H, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSLI_W, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSL_B, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSL_D, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSL_H, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSL_W, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSRI_B, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSRI_D, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSRI_H, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSRI_W, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSR_B, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSR_D, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSR_H, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BINSR_W, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BITREV, MIPS_INS_BITREV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BLEZ, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BLEZ64, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BLEZ_MM, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BLTZ, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BLTZ64, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BLTZAL, MIPS_INS_BLTZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BLTZ_MM, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BMNZI_B, MIPS_INS_BMNZI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BMNZ_V, MIPS_INS_BMNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BMZI_B, MIPS_INS_BMZI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BMZ_V, MIPS_INS_BMZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNE, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNE64, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNEGI_B, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEGI_D, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEGI_H, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEGI_W, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEG_B, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEG_D, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEG_H, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNEG_W, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BNE_MM, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNZ_B, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNZ_D, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNZ_H, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNZ_V, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BNZ_W, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BPOSGE32, MIPS_INS_BPOSGE32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BREAK, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BREAK_MM, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSELI_B, MIPS_INS_BSELI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSEL_V, MIPS_INS_BSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSETI_B, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSETI_D, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSETI_H, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSETI_W, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSET_B, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSET_D, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSET_H, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BSET_W, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BZ_B, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BZ_D, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BZ_H, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BZ_V, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BZ_W, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BimmX16, MIPS_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BnezRxImmX16, MIPS_INS_BNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_Break16, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_BteqzX16, MIPS_INS_BTEQZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_BtnezX16, MIPS_INS_BTNEZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_CEIL_L_D64, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_L_S, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_W_D32, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_W_D64, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_W_MM, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_W_S, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEIL_W_S_MM, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQI_B, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQI_D, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQI_H, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQI_W, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQ_B, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQ_D, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQ_H, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CEQ_W, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CFC1, MIPS_INS_CFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CFC1_MM, MIPS_INS_CFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CFCMSA, MIPS_INS_CFCMSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_S_B, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_S_D, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_S_H, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_S_W, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_U_B, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_U_D, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_U_H, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLEI_U_W, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_S_B, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_S_D, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_S_H, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_S_W, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_U_B, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_U_D, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_U_H, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLE_U_W, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLO, MIPS_INS_CLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLO_MM, MIPS_INS_CLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_S_B, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_S_D, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_S_H, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_S_W, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_U_B, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_U_D, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_U_H, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLTI_U_W, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_S_B, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_S_D, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_S_H, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_S_W, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_U_B, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_U_D, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_U_H, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLT_U_W, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLZ, MIPS_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CLZ_MM, MIPS_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGU_LE_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPGU_LT_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPU_EQ_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPU_LE_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMPU_LT_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMP_EQ_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMP_LE_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CMP_LT_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_S_B, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_S_D, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_S_H, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_S_W, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_U_B, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_U_D, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_U_H, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_COPY_U_W, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CTC1, MIPS_INS_CTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CTC1_MM, MIPS_INS_CTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CTCMSA, MIPS_INS_CTCMSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D32_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D32_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D32_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D64_L, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D64_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D64_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_D_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_L_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_L_D64_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_L_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_L_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_D32, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_D32_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_L, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_S_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_W_D32, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_W_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_W_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CVT_W_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_EQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_EQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_EQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_F_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_F_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_F_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_LT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGLE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGLE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGLE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGL_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGL_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGL_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_NGT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_OLT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SEQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SEQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SEQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SF_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SF_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_SF_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UEQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UEQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UEQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_ULT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UN_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UN_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_C_UN_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CmpRxRy16, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_CmpiRxImmX16, MIPS_INS_CMPI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DADD, MIPS_INS_DADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DADDi, MIPS_INS_DADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DADDiu, MIPS_INS_DADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DADDu, MIPS_INS_DADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DCLO, MIPS_INS_DCLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DCLZ, MIPS_INS_DCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BITCOUNT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DERET, MIPS_INS_DERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DERET_MM, MIPS_INS_DERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DEXT, MIPS_INS_DEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DEXTM, MIPS_INS_DEXTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DEXTU, MIPS_INS_DEXTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DI, MIPS_INS_DI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DINS, MIPS_INS_DINS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DINSM, MIPS_INS_DINSM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DINSU, MIPS_INS_DINSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_S_B, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_S_D, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_S_H, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_S_W, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_U_B, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_U_D, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_U_H, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DIV_U_W, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DI_MM, MIPS_INS_DI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DLSA, MIPS_INS_DLSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMFC0, MIPS_INS_DMFC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMFC1, MIPS_INS_DMFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMFC2, MIPS_INS_DMFC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMTC0, MIPS_INS_DMTC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMTC1, MIPS_INS_DMTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMTC2, MIPS_INS_DMTC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMULT, MIPS_INS_DMULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DMULTu, MIPS_INS_DMULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_S_D, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_S_H, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_S_W, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_U_D, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_U_H, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DOTP_U_W, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_S_D, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_S_H, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_S_W, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_U_D, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_U_H, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPADD_U_W, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAU_H_QBL, MIPS_INS_DPAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAU_H_QBR, MIPS_INS_DPAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPAX_W_PH, MIPS_INS_DPAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPA_W_PH, MIPS_INS_DPA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_S_D, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_S_H, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_S_W, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_U_D, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_U_H, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSUB_U_W, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSU_H_QBL, MIPS_INS_DPSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSU_H_QBR, MIPS_INS_DPSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPSX_W_PH, MIPS_INS_DPSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DPS_W_PH, MIPS_INS_DPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DROTR, MIPS_INS_DROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DROTR32, MIPS_INS_DROTR32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DROTRV, MIPS_INS_DROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSBH, MIPS_INS_DSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSDIV, MIPS_INS_DDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSHD, MIPS_INS_DSHD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSLL, MIPS_INS_DSLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSLL32, MIPS_INS_DSLL32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSLL64_32, MIPS_INS_DSLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSLLV, MIPS_INS_DSLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRA, MIPS_INS_DSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRA32, MIPS_INS_DSRA32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRAV, MIPS_INS_DSRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRL, MIPS_INS_DSRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRL32, MIPS_INS_DSRL32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSRLV, MIPS_INS_DSRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DSUBu, MIPS_INS_DSUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DUDIV, MIPS_INS_DDIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DivRxRy16, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_DivuRxRy16, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EI, MIPS_INS_EI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EI_MM, MIPS_INS_EI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ERET, MIPS_INS_ERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ERET_MM, MIPS_INS_ERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXT, MIPS_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTP, MIPS_INS_EXTP,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTPDP, MIPS_INS_EXTPDP,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTPDPV, MIPS_INS_EXTPDPV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTPV, MIPS_INS_EXTPV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTRV_R_W, MIPS_INS_EXTRV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTRV_S_H, MIPS_INS_EXTRV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTRV_W, MIPS_INS_EXTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTR_RS_W, MIPS_INS_EXTR_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTR_R_W, MIPS_INS_EXTR_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTR_S_H, MIPS_INS_EXTR_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXTR_W, MIPS_INS_EXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_EXT_MM, MIPS_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FABS_D32, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FABS_D64, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FABS_MM, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FABS_S, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FABS_S_MM, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_D, MIPS_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_D32, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_D64, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_S, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_S_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FADD_W, MIPS_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCAF_D, MIPS_INS_FCAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCAF_W, MIPS_INS_FCAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCEQ_D, MIPS_INS_FCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCEQ_W, MIPS_INS_FCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLASS_D, MIPS_INS_FCLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLASS_W, MIPS_INS_FCLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLE_D, MIPS_INS_FCLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLE_W, MIPS_INS_FCLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLT_D, MIPS_INS_FCLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCLT_W, MIPS_INS_FCLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCMP_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCMP_D32_MM, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCMP_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCMP_S32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCMP_S32_MM, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCNE_D, MIPS_INS_FCNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCNE_W, MIPS_INS_FCNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCOR_D, MIPS_INS_FCOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCOR_W, MIPS_INS_FCOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUEQ_D, MIPS_INS_FCUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUEQ_W, MIPS_INS_FCUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCULE_D, MIPS_INS_FCULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCULE_W, MIPS_INS_FCULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCULT_D, MIPS_INS_FCULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCULT_W, MIPS_INS_FCULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUNE_D, MIPS_INS_FCUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUNE_W, MIPS_INS_FCUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUN_D, MIPS_INS_FCUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FCUN_W, MIPS_INS_FCUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_D, MIPS_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_D32, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_D64, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_S, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_S_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FDIV_W, MIPS_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXDO_H, MIPS_INS_FEXDO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXDO_W, MIPS_INS_FEXDO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXP2_D, MIPS_INS_FEXP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXP2_W, MIPS_INS_FEXP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXUPL_D, MIPS_INS_FEXUPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXUPL_W, MIPS_INS_FEXUPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXUPR_D, MIPS_INS_FEXUPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FEXUPR_W, MIPS_INS_FEXUPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFINT_S_D, MIPS_INS_FFINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFINT_S_W, MIPS_INS_FFINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFINT_U_D, MIPS_INS_FFINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFINT_U_W, MIPS_INS_FFINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFQL_D, MIPS_INS_FFQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFQL_W, MIPS_INS_FFQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFQR_D, MIPS_INS_FFQR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FFQR_W, MIPS_INS_FFQR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FILL_B, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FILL_D, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FILL_H, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FILL_W, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOG2_D, MIPS_INS_FLOG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOG2_W, MIPS_INS_FLOG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_L_D64, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_L_S, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_W_D32, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_W_D64, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_W_MM, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_W_S, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMADD_D, MIPS_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMADD_W, MIPS_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMAX_A_D, MIPS_INS_FMAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMAX_A_W, MIPS_INS_FMAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMAX_D, MIPS_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMAX_W, MIPS_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMIN_A_D, MIPS_INS_FMIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMIN_A_W, MIPS_INS_FMIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMIN_D, MIPS_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMIN_W, MIPS_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMOV_D32, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMOV_D32_MM, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMOV_D64, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMOV_S, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMOV_S_MM, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMSUB_D, MIPS_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMSUB_W, MIPS_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_D, MIPS_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_D32, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_D64, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_S, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_S_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FMUL_W, MIPS_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FNEG_D32, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FNEG_D64, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FNEG_MM, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FNEG_S, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FNEG_S_MM, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRCP_D, MIPS_INS_FRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRCP_W, MIPS_INS_FRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRINT_D, MIPS_INS_FRINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRINT_W, MIPS_INS_FRINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRSQRT_D, MIPS_INS_FRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FRSQRT_W, MIPS_INS_FRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSAF_D, MIPS_INS_FSAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSAF_W, MIPS_INS_FSAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSEQ_D, MIPS_INS_FSEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSEQ_W, MIPS_INS_FSEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSLE_D, MIPS_INS_FSLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSLE_W, MIPS_INS_FSLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSLT_D, MIPS_INS_FSLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSLT_W, MIPS_INS_FSLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSNE_D, MIPS_INS_FSNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSNE_W, MIPS_INS_FSNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSOR_D, MIPS_INS_FSOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSOR_W, MIPS_INS_FSOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_D, MIPS_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_D32, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_D64, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_MM, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_S, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_S_MM, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSQRT_W, MIPS_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_D, MIPS_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_D32, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_D64, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_S, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_S_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUB_W, MIPS_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUEQ_D, MIPS_INS_FSUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUEQ_W, MIPS_INS_FSUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSULE_D, MIPS_INS_FSULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSULE_W, MIPS_INS_FSULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSULT_D, MIPS_INS_FSULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSULT_W, MIPS_INS_FSULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUNE_D, MIPS_INS_FSUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUNE_W, MIPS_INS_FSUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUN_D, MIPS_INS_FSUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FSUN_W, MIPS_INS_FSUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTINT_S_D, MIPS_INS_FTINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTINT_S_W, MIPS_INS_FTINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTINT_U_D, MIPS_INS_FTINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTINT_U_W, MIPS_INS_FTINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTQ_H, MIPS_INS_FTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTQ_W, MIPS_INS_FTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_S_D, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_S_H, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_S_W, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_U_D, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_U_H, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HADD_U_W, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_S_D, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_S_H, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_S_W, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_U_D, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_U_H, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_HSUB_U_W, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVEV_B, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVEV_D, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVEV_H, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVEV_W, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVL_B, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVL_D, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVL_H, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVL_W, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVOD_B, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVOD_D, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVOD_H, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVOD_W, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVR_B, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVR_D, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVR_H, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ILVR_W, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INS, MIPS_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSERT_B, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSERT_D, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSERT_H, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSERT_W, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSV, MIPS_INS_INSV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSVE_B, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSVE_D, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSVE_H, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INSVE_W, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_INS_MM, MIPS_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_J, MIPS_INS_J,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+ },
+ {
+ Mips_JAL, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JALR, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JALR64, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JALR_MM, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JAL_MM, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JR, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_JR64, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_JR_MM, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_J_MM, MIPS_INS_J,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_Jal16, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_JrRa16, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_JrcRa16, MIPS_INS_JRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_JrcRx16, MIPS_INS_JRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+ },
+ {
+ Mips_JumpLinkReg16, MIPS_INS_JALRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LB, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LB64, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LBUX, MIPS_INS_LBUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LB_MM, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LBu, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LBu64, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LBu_MM, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LD, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDC1, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDC164, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDC1_MM, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDC2, MIPS_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDI_B, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDI_D, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDI_H, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDI_W, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDL, MIPS_INS_LDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDR, MIPS_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDXC1, MIPS_INS_LDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LDXC164, MIPS_INS_LDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LD_B, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LD_D, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LD_H, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LD_W, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LEA_ADDiu, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LEA_ADDiu64, MIPS_INS_DADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LH, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LH64, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LHX, MIPS_INS_LHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LH_MM, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LHu, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LHu64, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LHu_MM, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LL, MIPS_INS_LL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LLD, MIPS_INS_LLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LL_MM, MIPS_INS_LL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LSA, MIPS_INS_LSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUXC1, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUXC164, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUXC1_MM, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUi, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUi64, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LUi_MM, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LW, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LW64, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWC1, MIPS_INS_LWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWC1_MM, MIPS_INS_LWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWC2, MIPS_INS_LWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWL, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWL64, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWL_MM, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWR, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWR64, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWR_MM, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWU_MM, MIPS_INS_LWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWX, MIPS_INS_LWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWXC1, MIPS_INS_LWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWXC1_MM, MIPS_INS_LWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LW_MM, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LWu, MIPS_INS_LWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LbRxRyOffMemX16, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LbuRxRyOffMemX16, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LhRxRyOffMemX16, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LhuRxRyOffMemX16, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LiRxImmX16, MIPS_INS_LI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LwRxPcTcpX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LwRxRyOffMemX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_LwRxSpImmX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDR_Q_H, MIPS_INS_MADDR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDR_Q_W, MIPS_INS_MADDR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDU, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDU_DSP, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDU_MM, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDV_B, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDV_D, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDV_H, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADDV_W, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_D32, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_D32_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_D64, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_DSP, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_Q_H, MIPS_INS_MADD_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_Q_W, MIPS_INS_MADD_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_S, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MADD_S_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_S_B, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_S_D, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_S_H, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_S_W, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_U_B, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_U_D, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_U_H, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAXI_U_W, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_A_B, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_A_D, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_A_H, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_A_W, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_S_B, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_S_D, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_S_H, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_S_W, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_U_B, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_U_D, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_U_H, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MAX_U_W, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFC0, MIPS_INS_MFC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFC1, MIPS_INS_MFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFC1_MM, MIPS_INS_MFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFC2, MIPS_INS_MFC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHC1, MIPS_INS_MFHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHC1_MM, MIPS_INS_MFHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHI, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHI64, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHI_DSP, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFHI_MM, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFLO, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFLO64, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFLO_DSP, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MFLO_MM, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_S_B, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_S_D, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_S_H, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_S_W, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_U_B, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_U_D, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_U_H, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MINI_U_W, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_A_B, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_A_D, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_A_H, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_A_W, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_S_B, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_S_D, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_S_H, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_S_W, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_U_B, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_U_D, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_U_H, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MIN_U_W, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MODSUB, MIPS_INS_MODSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_S_B, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_S_D, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_S_H, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_S_W, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_U_B, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_U_D, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_U_H, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOD_U_W, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVE_V, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_D32, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_D32_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_D64, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_I, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_I64, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_I_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_S, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVF_S_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I64_D64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I64_I, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I64_I64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I64_S, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_D32, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_D32_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_D64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_I, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_I64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_S, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVN_I_S_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_D32, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_D32_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_D64, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_I, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_I64, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_I_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_S, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVT_S_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I64_D64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I64_I, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I64_I64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I64_S, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_D32, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_D64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_I, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_I64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_S, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBU, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBU_DSP, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBU_MM, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBV_B, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBV_D, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBV_H, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUBV_W, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_D32, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_D32_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_D64, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_DSP, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_Q_H, MIPS_INS_MSUB_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_Q_W, MIPS_INS_MSUB_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_S, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MSUB_S_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTC0, MIPS_INS_MTC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTC1, MIPS_INS_MTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTC1_MM, MIPS_INS_MTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTC2, MIPS_INS_MTC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHC1, MIPS_INS_MTHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHC1_MM, MIPS_INS_MTHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHI, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHI64, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHI_DSP, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHI_MM, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTHLIP, MIPS_INS_MTHLIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTLO, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTLO64, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTLO_DSP, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MTLO_MM, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULQ_RS_W, MIPS_INS_MULQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULQ_S_PH, MIPS_INS_MULQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULQ_S_W, MIPS_INS_MULQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULR_Q_H, MIPS_INS_MULR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULR_Q_W, MIPS_INS_MULR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULSA_W_PH, MIPS_INS_MULSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULT, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULTU_DSP, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULT_DSP, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULT_MM, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULTu, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULTu_MM, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULV_B, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULV_D, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULV_H, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MULV_W, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL_PH, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL_Q_H, MIPS_INS_MUL_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL_Q_W, MIPS_INS_MUL_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MUL_S_PH, MIPS_INS_MUL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_Mfhi16, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_Mflo16, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_Move32R16, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_MoveR3216, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLOC_B, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLOC_D, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLOC_H, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLOC_W, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLZC_B, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLZC_D, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLZC_H, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NLZC_W, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMADD_D32, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMADD_D32_MM, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMADD_D64, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMADD_S, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMADD_S_MM, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMSUB_D32, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMSUB_D32_MM, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMSUB_D64, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMSUB_S, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_NONANSFPMATH, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NMSUB_S_MM, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NOR, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NOR64, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NORI_B, MIPS_INS_NORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NOR_MM, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NOR_V, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NegRxRy16, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_NotRxRy16, MIPS_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_OR, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_OR64, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ORI_B, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_OR_MM, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_OR_V, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ORi, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ORi64, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ORi_MM, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_OrRxRxRy16, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PACKRL_PH, MIPS_INS_PACKRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKEV_B, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKEV_D, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKEV_H, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKEV_W, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKOD_B, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKOD_D, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKOD_H, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCKOD_W, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCNT_B, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCNT_D, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCNT_H, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PCNT_W, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PICK_PH, MIPS_INS_PICK,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PICK_QB, MIPS_INS_PICK,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECR_QB_PH, MIPS_INS_PRECR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_PREPEND, MIPS_INS_PREPEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RADDU_W_QB, MIPS_INS_RADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RDDSP, MIPS_INS_RDDSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RDHWR, MIPS_INS_RDHWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RDHWR64, MIPS_INS_RDHWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_REPLV_PH, MIPS_INS_REPLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_REPLV_QB, MIPS_INS_REPLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_REPL_PH, MIPS_INS_REPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_REPL_QB, MIPS_INS_REPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RET, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_RET_MM, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROTR, MIPS_INS_ROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROTRV, MIPS_INS_ROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS32R2, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROTRV_MM, MIPS_INS_ROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROTR_MM, MIPS_INS_ROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_L_D64, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_L_S, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_W_D32, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_W_D64, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_W_MM, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_W_S, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ROUND_W_S_MM, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_S_B, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_S_D, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_S_H, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_S_W, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_U_B, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_U_D, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_U_H, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SAT_U_W, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SB, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SB64, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SB_MM, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SC, MIPS_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SCD, MIPS_INS_SCD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SC_MM, MIPS_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SD, MIPS_INS_SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDC1, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDC164, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDC1_MM, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDC2, MIPS_INS_SDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDIV, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDIV_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDL, MIPS_INS_SDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDR, MIPS_INS_SDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDXC1, MIPS_INS_SDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SDXC164, MIPS_INS_SDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEB, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEB64, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEB_MM, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEH, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEH64, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SEINREG, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SEH_MM, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SH, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SH64, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHF_B, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHF_H, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHF_W, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHILO, MIPS_INS_SHILO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHILOV, MIPS_INS_SHILOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLLV_PH, MIPS_INS_SHLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLLV_QB, MIPS_INS_SHLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLLV_S_W, MIPS_INS_SHLLV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLL_PH, MIPS_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLL_QB, MIPS_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLL_S_PH, MIPS_INS_SHLL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHLL_S_W, MIPS_INS_SHLL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRAV_PH, MIPS_INS_SHRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRAV_QB, MIPS_INS_SHRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRAV_R_W, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRA_PH, MIPS_INS_SHRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRA_QB, MIPS_INS_SHRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRA_R_PH, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRA_R_QB, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRA_R_W, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRLV_PH, MIPS_INS_SHRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRLV_QB, MIPS_INS_SHRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRL_PH, MIPS_INS_SHRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SHRL_QB, MIPS_INS_SHRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SH_MM, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLDI_B, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLDI_D, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLDI_H, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLDI_W, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLD_B, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLD_D, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLD_H, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLD_W, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL64_32, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL64_64, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLI_B, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLI_D, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLI_H, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLI_W, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLV, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLLV_MM, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL_B, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL_D, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL_H, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL_MM, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLL_W, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLT, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLT64, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLT_MM, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTi, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTi64, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTi_MM, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTiu, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTiu64, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTiu_MM, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTu, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTu64, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SLTu_MM, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLATI_B, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLATI_D, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLATI_H, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLATI_W, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLAT_B, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLAT_D, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLAT_H, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SPLAT_W, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAI_B, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAI_D, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAI_H, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAI_W, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRARI_B, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRARI_D, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRARI_H, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRARI_W, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAR_B, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAR_D, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAR_H, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAR_W, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAV, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRAV_MM, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA_B, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA_D, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA_H, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA_MM, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRA_W, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLI_B, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLI_D, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLI_H, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLI_W, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLRI_B, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLRI_D, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLRI_H, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLRI_W, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLR_B, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLR_D, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLR_H, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLR_W, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLV, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRLV_MM, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL_B, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL_D, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL_H, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL_MM, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SRL_W, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ST_B, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ST_D, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ST_H, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ST_W, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUB, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQH_PH, MIPS_INS_SUBQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQH_R_W, MIPS_INS_SUBQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQH_W, MIPS_INS_SUBQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQ_PH, MIPS_INS_SUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBQ_S_W, MIPS_INS_SUBQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_S_B, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_S_D, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_S_H, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_S_W, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_U_B, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_U_D, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_U_H, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBS_U_W, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBUH_QB, MIPS_INS_SUBUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBU_PH, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBU_QB, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBU_S_PH, MIPS_INS_SUBU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBU_S_QB, MIPS_INS_SUBU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBVI_B, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBVI_D, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBVI_H, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBVI_W, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBV_B, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBV_D, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBV_H, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBV_W, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUB_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBu, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBu_MM, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUXC1, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUXC164, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUXC1_MM, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SW, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SW64, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWC1, MIPS_INS_SWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWC1_MM, MIPS_INS_SWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWC2, MIPS_INS_SWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWL, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWL64, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWL_MM, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWR, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWR64, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWR_MM, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWXC1, MIPS_INS_SWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FPIDX, MIPS_GRP_STDENC, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SWXC1_MM, MIPS_INS_SWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SW_MM, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SYNC, MIPS_INS_SYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SYNC_MM, MIPS_INS_SYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SYSCALL, MIPS_INS_SYSCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SYSCALL_MM, MIPS_INS_SYSCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SbRxRyOffMemX16, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SebRx16, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SehRx16, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_ShRxRyOffMemX16, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SllX16, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SllvRxRy16, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SltRxRy16, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SltiRxImmX16, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SltiuRxImmX16, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SltuRxRy16, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SraX16, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SravRxRy16, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SrlX16, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SrlvRxRy16, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SubuRxRyRz16, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SwRxRyOffMemX16, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SwRxSpImmX16, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TEQ, MIPS_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TEQI, MIPS_INS_TEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TEQI_MM, MIPS_INS_TEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TEQ_MM, MIPS_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGE, MIPS_INS_TGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEI, MIPS_INS_TGEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEIU, MIPS_INS_TGEIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEIU_MM, MIPS_INS_TGEIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEI_MM, MIPS_INS_TGEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEU, MIPS_INS_TGEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGEU_MM, MIPS_INS_TGEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TGE_MM, MIPS_INS_TGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLT, MIPS_INS_TLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLTI, MIPS_INS_TLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLTIU_MM, MIPS_INS_TLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLTI_MM, MIPS_INS_TLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLTU, MIPS_INS_TLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLTU_MM, MIPS_INS_TLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TLT_MM, MIPS_INS_TLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TNE, MIPS_INS_TNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TNEI, MIPS_INS_TNEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TNEI_MM, MIPS_INS_TNEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TNE_MM, MIPS_INS_TNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_L_D64, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_L_S, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_W_D32, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTFP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_W_D64, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_FP64BIT, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_W_MM, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_W_S, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_TTLTIU, MIPS_INS_TLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_UDIV, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_UDIV_MM, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_VSHF_B, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_VSHF_D, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_VSHF_H, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_VSHF_W, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_WAIT, MIPS_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_WAIT_MM, MIPS_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_WRDSP, MIPS_INS_WRDSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_WSBH, MIPS_INS_WSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_SWAP, MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_WSBH_MM, MIPS_INS_WSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XOR, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XOR64, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XORI_B, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XOR_MM, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XOR_V, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XORi, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XORi64, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XORi_MM, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_XorRxRxRy16, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+ },
};
static insn_map alias_insns[] = {
- { (unsigned short)-2, MIPS_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { Mips_SUBu, MIPS_INS_NEGU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
+ {
+ (unsigned short)-2, MIPS_INS_NOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ Mips_SUBu, MIPS_INS_NEGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+ },
};
// given internal insn id, return public instruction info
@@ -1478,6 +7880,7 @@
insn->id = alias_insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(alias_insns[i].regs_use);
@@ -1493,8 +7896,9 @@
insn->detail->groups_count++;
}
- return;
+#endif
}
+ return;
}
}
@@ -1503,6 +7907,7 @@
insn->id = insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
@@ -1517,6 +7922,7 @@
insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP;
insn->detail->groups_count++;
}
+#endif
}
}
}
@@ -1991,6 +8397,7 @@
const char *Mips_insn_name(csh handle, unsigned int id)
{
+#ifndef CAPSTONE_DIET
if (id >= MIPS_INS_MAX)
return NULL;
@@ -2002,6 +8409,9 @@
}
return insn_name_maps[id].name;
+#else
+ return NULL;
+#endif
}
mips_reg Mips_map_insn(const char *name)
diff --git a/arch/PowerPC/PPCGenAsmWriter.inc b/arch/PowerPC/PPCGenAsmWriter.inc
index 01d23dd..5c89cf2 100644
--- a/arch/PowerPC/PPCGenAsmWriter.inc
+++ b/arch/PowerPC/PPCGenAsmWriter.inc
@@ -1794,6 +1794,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0,
/* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0,
@@ -2454,13 +2455,16 @@
/* 5695 */ 'b', 'd', 'n', 'z', 'l', 'r', 0,
/* 5702 */ 'b', 'c', 't', 'r', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 8191)-1);
+#endif
// Fragment 0 encoded into 4 bits for 13 unique commands.
@@ -2868,6 +2872,7 @@
{
//assert(RegNo && RegNo < 182 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static const char AsmStrs[] = {
/* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0,
/* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
@@ -2997,6 +3002,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index 180c280..47a873b 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -12,6 +12,7 @@
#define GET_INSTRINFO_ENUM
#include "PPCGenInstrInfo.inc"
+#ifndef CAPSTONE_DIET
static name_map reg_name_maps[] = {
{ PPC_REG_INVALID, NULL },
@@ -154,767 +155,4523 @@
{ PPC_REG_LR8, "lr8" },
{ PPC_REG_CR1EQ, "cr1eq" },
};
+#endif
const char *PPC_reg_name(csh handle, unsigned int reg)
{
+#ifndef CAPSTONE_DIET
if (reg >= PPC_REG_MAX)
return NULL;
return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
}
static insn_map insns[] = {
- { 0, 0, { 0 }, { 0 }, { 0 }, 0, 0 }, // dummy item
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
- { PPC_ADD4, PPC_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADD4TLS, PPC_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADD4o, PPC_INS_ADD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADD8, PPC_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADD8TLS, PPC_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADD8TLS_, PPC_INS_ADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADD8o, PPC_INS_ADD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDC, PPC_INS_ADDC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDC8, PPC_INS_ADDC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDC8o, PPC_INS_ADDC, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDCo, PPC_INS_ADDC, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDE, PPC_INS_ADDE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDE8, PPC_INS_ADDE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDE8o, PPC_INS_ADDE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDEo, PPC_INS_ADDE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDI, PPC_INS_ADDI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADDI8, PPC_INS_ADDI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADDIC, PPC_INS_ADDIC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDIC8, PPC_INS_ADDIC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDICo, PPC_INS_ADDIC, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDIS, PPC_INS_ADDIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADDIS8, PPC_INS_ADDIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ADDME, PPC_INS_ADDME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDME8, PPC_INS_ADDME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDME8o, PPC_INS_ADDME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDMEo, PPC_INS_ADDME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDZE, PPC_INS_ADDZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDZE8, PPC_INS_ADDZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_ADDZE8o, PPC_INS_ADDZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ADDZEo, PPC_INS_ADDZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_AND, PPC_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_AND8, PPC_INS_AND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_AND8o, PPC_INS_AND, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDC, PPC_INS_ANDC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ANDC8, PPC_INS_ANDC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ANDC8o, PPC_INS_ANDC, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDCo, PPC_INS_ANDC, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDISo, PPC_INS_ANDIS, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDISo8, PPC_INS_ANDIS, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDIo, PPC_INS_ANDI, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDIo8, PPC_INS_ANDI, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ANDo, PPC_INS_AND, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_B, PPC_INS_B, { 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_BA, PPC_INS_BA, { 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_BCC, PPC_INS_B, { 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_BCCA, PPC_INS_B, { 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_BCCL, PPC_INS_B, { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BCCLA, PPC_INS_B, { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BCCTR, PPC_INS_B, { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 },
- { PPC_BCCTR8, PPC_INS_B, { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 },
- { PPC_BCCTRL, PPC_INS_B, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BCCTRL8, PPC_INS_B, { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 },
- { PPC_BCLR, PPC_INS_B, { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_BCLRL, PPC_INS_B, { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BCLalways, PPC_INS_BCL, { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BCTR, PPC_INS_BCTR, { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 },
- { PPC_BCTR8, PPC_INS_BCTR, { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 },
- { PPC_BCTRL, PPC_INS_BCTRL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { PPC_GRP_MODE32, 0 }, 0, 0 },
- { PPC_BCTRL8, PPC_INS_BCTRL, { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0 },
- { PPC_BDNZ, PPC_INS_BDNZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZ8, PPC_INS_BDNZ, { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZA, PPC_INS_BDNZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZAm, PPC_INS_BDNZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZAp, PPC_INS_BDNZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZL, PPC_INS_BDNZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLA, PPC_INS_BDNZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLAm, PPC_INS_BDNZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLAp, PPC_INS_BDNZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLR, PPC_INS_BDNZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZLR8, PPC_INS_BDNZLR, { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZLRL, PPC_INS_BDNZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLRLm, PPC_INS_BDNZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLRLp, PPC_INS_BDNZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLRm, PPC_INS_BDNZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZLRp, PPC_INS_BDNZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZLm, PPC_INS_BDNZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZLp, PPC_INS_BDNZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDNZm, PPC_INS_BDNZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDNZp, PPC_INS_BDNZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZ, PPC_INS_BDZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZ8, PPC_INS_BDZ, { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 },
- { PPC_BDZA, PPC_INS_BDZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZAm, PPC_INS_BDZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZAp, PPC_INS_BDZA, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZL, PPC_INS_BDZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLA, PPC_INS_BDZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLAm, PPC_INS_BDZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLAp, PPC_INS_BDZLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLR, PPC_INS_BDZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZLR8, PPC_INS_BDZLR, { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 },
- { PPC_BDZLRL, PPC_INS_BDZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLRLm, PPC_INS_BDZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLRLp, PPC_INS_BDZLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLRm, PPC_INS_BDZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZLRp, PPC_INS_BDZLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZLm, PPC_INS_BDZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZLp, PPC_INS_BDZL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_BDZm, PPC_INS_BDZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BDZp, PPC_INS_BDZ, { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 },
- { PPC_BL, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BL8, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BL8_NOP, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BL8_NOP_TLS, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BL8_TLS, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BL8_TLS_, PPC_INS_BL, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BLA, PPC_INS_BLA, { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_BLA8, PPC_INS_BLA, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BLA8_NOP, PPC_INS_BLA, { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_BLR, PPC_INS_BLR, { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_BLRL, PPC_INS_BLRL, { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_CMPD, PPC_INS_CMPD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPDI, PPC_INS_CMPDI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPLD, PPC_INS_CMPLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPLDI, PPC_INS_CMPLDI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPLW, PPC_INS_CMPLW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPLWI, PPC_INS_CMPLWI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPW, PPC_INS_CMPW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CMPWI, PPC_INS_CMPWI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CNTLZD, PPC_INS_CNTLZD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CNTLZDo, PPC_INS_CNTLZD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_CNTLZW, PPC_INS_CNTLZW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CNTLZWo, PPC_INS_CNTLZW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_CR6SET, PPC_INS_CREQV, { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 },
- { PPC_CR6UNSET, PPC_INS_CRXOR, { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 },
- { PPC_CRAND, PPC_INS_CRAND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRANDC, PPC_INS_CRANDC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CREQV, PPC_INS_CREQV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRNAND, PPC_INS_CRNAND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRNOR, PPC_INS_CRNOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CROR, PPC_INS_CROR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRORC, PPC_INS_CRORC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRSET, PPC_INS_CREQV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRUNSET, PPC_INS_CRXOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_CRXOR, PPC_INS_CRXOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBA, PPC_INS_DCBA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBF, PPC_INS_DCBF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBI, PPC_INS_DCBI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBST, PPC_INS_DCBST, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBT, PPC_INS_DCBT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBTST, PPC_INS_DCBTST, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBZ, PPC_INS_DCBZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DCBZL, PPC_INS_DCBZL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DIVD, PPC_INS_DIVD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DIVDU, PPC_INS_DIVDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DIVDUo, PPC_INS_DIVDU, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_DIVDo, PPC_INS_DIVD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_DIVW, PPC_INS_DIVW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DIVWU, PPC_INS_DIVWU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_DIVWUo, PPC_INS_DIVWU, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_DIVWo, PPC_INS_DIVW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_DSS, PPC_INS_DSS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSSALL, PPC_INS_DSSALL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DST, PPC_INS_DST, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DST64, PPC_INS_DST, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTST, PPC_INS_DSTST, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTST64, PPC_INS_DSTST, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTSTT, PPC_INS_DSTSTT, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTSTT64, PPC_INS_DSTSTT, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTT, PPC_INS_DSTT, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_DSTT64, PPC_INS_DSTT, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_EIEIO, PPC_INS_EIEIO, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EQV, PPC_INS_EQV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EQV8, PPC_INS_EQV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EQV8o, PPC_INS_EQV, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EQVo, PPC_INS_EQV, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSB, PPC_INS_EXTSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSB8, PPC_INS_EXTSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSB8_32_64, PPC_INS_EXTSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSB8o, PPC_INS_EXTSB, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSBo, PPC_INS_EXTSB, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSH, PPC_INS_EXTSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSH8, PPC_INS_EXTSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSH8_32_64, PPC_INS_EXTSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSH8o, PPC_INS_EXTSH, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSHo, PPC_INS_EXTSH, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSW, PPC_INS_EXTSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSW_32_64, PPC_INS_EXTSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_EXTSW_32_64o, PPC_INS_EXTSW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_EXTSWo, PPC_INS_EXTSW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_FABSD, PPC_INS_FABS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FABSDo, PPC_INS_FABS, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FABSS, PPC_INS_FABS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FABSSo, PPC_INS_FABS, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FADD, PPC_INS_FADD, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FADDS, PPC_INS_FADDS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FADDSo, PPC_INS_FADDS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FADDo, PPC_INS_FADD, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCFID, PPC_INS_FCFID, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDS, PPC_INS_FCFIDS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDSo, PPC_INS_FCFIDS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDU, PPC_INS_FCFIDU, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDUS, PPC_INS_FCFIDUS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDUSo, PPC_INS_FCFIDUS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDUo, PPC_INS_FCFIDU, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCFIDo, PPC_INS_FCFID, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCMPUD, PPC_INS_FCMPU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCMPUS, PPC_INS_FCMPU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCPSGND, PPC_INS_FCPSGN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCPSGNDo, PPC_INS_FCPSGN, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCPSGNS, PPC_INS_FCPSGN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCPSGNSo, PPC_INS_FCPSGN, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTID, PPC_INS_FCTID, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIDUZ, PPC_INS_FCTIDUZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIDUZo, PPC_INS_FCTIDUZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTIDZ, PPC_INS_FCTIDZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIDZo, PPC_INS_FCTIDZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTIDo, PPC_INS_FCTID, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTIW, PPC_INS_FCTIW, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIWUZ, PPC_INS_FCTIWUZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIWUZo, PPC_INS_FCTIWUZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTIWZ, PPC_INS_FCTIWZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FCTIWZo, PPC_INS_FCTIWZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FCTIWo, PPC_INS_FCTIW, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FDIV, PPC_INS_FDIV, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FDIVS, PPC_INS_FDIVS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FDIVSo, PPC_INS_FDIVS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FDIVo, PPC_INS_FDIV, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMADD, PPC_INS_FMADD, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMADDS, PPC_INS_FMADDS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMADDSo, PPC_INS_FMADDS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMADDo, PPC_INS_FMADD, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMR, PPC_INS_FMR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMRo, PPC_INS_FMR, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMSUB, PPC_INS_FMSUB, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMSUBS, PPC_INS_FMSUBS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMSUBSo, PPC_INS_FMSUBS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMSUBo, PPC_INS_FMSUB, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMUL, PPC_INS_FMUL, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMULS, PPC_INS_FMULS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FMULSo, PPC_INS_FMULS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FMULo, PPC_INS_FMUL, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNABSD, PPC_INS_FNABS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNABSDo, PPC_INS_FNABS, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNABSS, PPC_INS_FNABS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNABSSo, PPC_INS_FNABS, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNEGD, PPC_INS_FNEG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNEGDo, PPC_INS_FNEG, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNEGS, PPC_INS_FNEG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNEGSo, PPC_INS_FNEG, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNMADD, PPC_INS_FNMADD, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNMADDS, PPC_INS_FNMADDS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNMADDSo, PPC_INS_FNMADDS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNMADDo, PPC_INS_FNMADD, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNMSUB, PPC_INS_FNMSUB, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNMSUBS, PPC_INS_FNMSUBS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FNMSUBSo, PPC_INS_FNMSUBS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FNMSUBo, PPC_INS_FNMSUB, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRE, PPC_INS_FRE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRES, PPC_INS_FRES, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRESo, PPC_INS_FRES, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FREo, PPC_INS_FRE, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIMD, PPC_INS_FRIM, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIMDo, PPC_INS_FRIM, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIMS, PPC_INS_FRIM, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIMSo, PPC_INS_FRIM, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIND, PPC_INS_FRIN, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRINDo, PPC_INS_FRIN, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRINS, PPC_INS_FRIN, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRINSo, PPC_INS_FRIN, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIPD, PPC_INS_FRIP, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIPDo, PPC_INS_FRIP, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIPS, PPC_INS_FRIP, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIPSo, PPC_INS_FRIP, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIZD, PPC_INS_FRIZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIZDo, PPC_INS_FRIZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRIZS, PPC_INS_FRIZ, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRIZSo, PPC_INS_FRIZ, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRSP, PPC_INS_FRSP, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRSPo, PPC_INS_FRSP, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRSQRTE, PPC_INS_FRSQRTE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRSQRTES, PPC_INS_FRSQRTES, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FRSQRTESo, PPC_INS_FRSQRTES, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FRSQRTEo, PPC_INS_FRSQRTE, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSELD, PPC_INS_FSEL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSELDo, PPC_INS_FSEL, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSELS, PPC_INS_FSEL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSELSo, PPC_INS_FSEL, { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSQRT, PPC_INS_FSQRT, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSQRTS, PPC_INS_FSQRTS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSQRTSo, PPC_INS_FSQRTS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSQRTo, PPC_INS_FSQRT, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSUB, PPC_INS_FSUB, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSUBS, PPC_INS_FSUBS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_FSUBSo, PPC_INS_FSUBS, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_FSUBo, PPC_INS_FSUB, { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 },
- { PPC_ICBI, PPC_INS_ICBI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ISEL, PPC_INS_ISEL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ISEL8, PPC_INS_ISEL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ISYNC, PPC_INS_ISYNC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LA, PPC_INS_LA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZ, PPC_INS_LBZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZ8, PPC_INS_LBZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZU, PPC_INS_LBZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZU8, PPC_INS_LBZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZUX, PPC_INS_LBZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZUX8, PPC_INS_LBZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZX, PPC_INS_LBZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LBZX8, PPC_INS_LBZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LD, PPC_INS_LD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDARX, PPC_INS_LDARX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDBRX, PPC_INS_LDBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDU, PPC_INS_LDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDUX, PPC_INS_LDUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDX, PPC_INS_LDX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDinto_toc, PPC_INS_LD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LDtoc_restore, PPC_INS_LD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFD, PPC_INS_LFD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFDU, PPC_INS_LFDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFDUX, PPC_INS_LFDUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFDX, PPC_INS_LFDX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFIWAX, PPC_INS_LFIWAX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFIWZX, PPC_INS_LFIWZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFS, PPC_INS_LFS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFSU, PPC_INS_LFSU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFSUX, PPC_INS_LFSUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LFSX, PPC_INS_LFSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHA, PPC_INS_LHA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHA8, PPC_INS_LHA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAU, PPC_INS_LHAU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAU8, PPC_INS_LHAU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAUX, PPC_INS_LHAUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAUX8, PPC_INS_LHAUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAX, PPC_INS_LHAX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHAX8, PPC_INS_LHAX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHBRX, PPC_INS_LHBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZ, PPC_INS_LHZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZ8, PPC_INS_LHZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZU, PPC_INS_LHZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZU8, PPC_INS_LHZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZUX, PPC_INS_LHZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZUX8, PPC_INS_LHZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZX, PPC_INS_LHZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LHZX8, PPC_INS_LHZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LI, PPC_INS_LI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LI8, PPC_INS_LI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LIS, PPC_INS_LIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LIS8, PPC_INS_LIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LMW, PPC_INS_LMW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LVEBX, PPC_INS_LVEBX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVEHX, PPC_INS_LVEHX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVEWX, PPC_INS_LVEWX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVSL, PPC_INS_LVSL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVSR, PPC_INS_LVSR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVX, PPC_INS_LVX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LVXL, PPC_INS_LVXL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_LWA, PPC_INS_LWA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWARX, PPC_INS_LWARX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWAUX, PPC_INS_LWAUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWAX, PPC_INS_LWAX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWAX_32, PPC_INS_LWAX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWA_32, PPC_INS_LWA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWBRX, PPC_INS_LWBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZ, PPC_INS_LWZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZ8, PPC_INS_LWZ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZU, PPC_INS_LWZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZU8, PPC_INS_LWZU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZUX, PPC_INS_LWZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZUX8, PPC_INS_LWZUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZX, PPC_INS_LWZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_LWZX8, PPC_INS_LWZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MCRF, PPC_INS_MCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFCR, PPC_INS_MFCR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFCR8, PPC_INS_MFCR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFCTR, PPC_INS_MFCTR, { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFCTR8, PPC_INS_MFCTR, { PPC_REG_CTR8, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFFS, PPC_INS_MFFS, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFLR, PPC_INS_MFLR, { PPC_REG_LR, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFLR8, PPC_INS_MFLR, { PPC_REG_LR8, 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFMSR, PPC_INS_MFMSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFOCRF, PPC_INS_MFOCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFOCRF8, PPC_INS_MFOCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFSPR, PPC_INS_MFSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFTB, PPC_INS_MFTB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFTB8, PPC_INS_MFSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFVRSAVE, PPC_INS_MFSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFVRSAVEv, PPC_INS_MFSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MFVSCR, PPC_INS_MFVSCR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_MSYNC, PPC_INS_MSYNC, { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 },
- { PPC_MTCRF, PPC_INS_MTCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTCRF8, PPC_INS_MTCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTCTR, PPC_INS_MTCTR, { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_MTCTR8, PPC_INS_MTCTR, { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 },
- { PPC_MTCTR8loop, PPC_INS_MTCTR, { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 },
- { PPC_MTCTRloop, PPC_INS_MTCTR, { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_MTFSB0, PPC_INS_MTFSB0, { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 },
- { PPC_MTFSB1, PPC_INS_MTFSB1, { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 },
- { PPC_MTFSF, PPC_INS_MTFSF, { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 },
- { PPC_MTLR, PPC_INS_MTLR, { 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 },
- { PPC_MTLR8, PPC_INS_MTLR, { 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 },
- { PPC_MTMSR, PPC_INS_MTMSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTMSRD, PPC_INS_MTMSRD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTOCRF, PPC_INS_MTOCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTOCRF8, PPC_INS_MTOCRF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTSPR, PPC_INS_MTSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTVRSAVE, PPC_INS_MTSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTVRSAVEv, PPC_INS_MTSPR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MTVSCR, PPC_INS_MTVSCR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_MULHD, PPC_INS_MULHD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULHDU, PPC_INS_MULHDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULHDUo, PPC_INS_MULHDU, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_MULHDo, PPC_INS_MULHD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_MULHW, PPC_INS_MULHW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULHWU, PPC_INS_MULHWU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULHWUo, PPC_INS_MULHWU, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_MULHWo, PPC_INS_MULHW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_MULLD, PPC_INS_MULLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULLDo, PPC_INS_MULLD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_MULLI, PPC_INS_MULLI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULLI8, PPC_INS_MULLI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULLW, PPC_INS_MULLW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_MULLWo, PPC_INS_MULLW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NAND, PPC_INS_NAND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NAND8, PPC_INS_NAND, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NAND8o, PPC_INS_NAND, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NANDo, PPC_INS_NAND, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NEG, PPC_INS_NEG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NEG8, PPC_INS_NEG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NEG8o, PPC_INS_NEG, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NEGo, PPC_INS_NEG, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NOP, PPC_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NOP_GT_PWR6, PPC_INS_ORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NOP_GT_PWR7, PPC_INS_ORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NOR, PPC_INS_NOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NOR8, PPC_INS_NOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_NOR8o, PPC_INS_NOR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_NORo, PPC_INS_NOR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_OR, PPC_INS_OR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_OR8, PPC_INS_OR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_OR8o, PPC_INS_OR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ORC, PPC_INS_ORC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORC8, PPC_INS_ORC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORC8o, PPC_INS_ORC, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ORCo, PPC_INS_ORC, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_ORI, PPC_INS_ORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORI8, PPC_INS_ORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORIS, PPC_INS_ORIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORIS8, PPC_INS_ORIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_ORo, PPC_INS_OR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_POPCNTD, PPC_INS_POPCNTD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_POPCNTW, PPC_INS_POPCNTW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDCL, PPC_INS_RLDCL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDCLo, PPC_INS_RLDCL, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLDCR, PPC_INS_RLDCR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDCRo, PPC_INS_RLDCR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLDIC, PPC_INS_RLDIC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDICL, PPC_INS_RLDICL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDICL_32_64, PPC_INS_RLDICL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDICLo, PPC_INS_RLDICL, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLDICR, PPC_INS_RLDICR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDICRo, PPC_INS_RLDICR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLDICo, PPC_INS_RLDIC, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLDIMI, PPC_INS_RLDIMI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLDIMIo, PPC_INS_RLDIMI, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLWIMI, PPC_INS_RLWIMI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLWIMIo, PPC_INS_RLWIMI, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLWINM, PPC_INS_RLWINM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLWINM8, PPC_INS_RLWINM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLWINM8o, PPC_INS_RLWINM, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLWINMo, PPC_INS_RLWINM, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_RLWNM, PPC_INS_RLWNM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_RLWNMo, PPC_INS_RLWNM, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SC, PPC_INS_SC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLBIA, PPC_INS_SLBIA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLBIE, PPC_INS_SLBIE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLBMFEE, PPC_INS_SLBMFEE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLBMTE, PPC_INS_SLBMTE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLD, PPC_INS_SLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLDo, PPC_INS_SLD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SLW, PPC_INS_SLW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SLWo, PPC_INS_SLW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRAD, PPC_INS_SRAD, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SRADI, PPC_INS_SRADI, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SRADIo, PPC_INS_SRADI, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRADo, PPC_INS_SRAD, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRAW, PPC_INS_SRAW, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SRAWI, PPC_INS_SRAWI, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SRAWIo, PPC_INS_SRAWI, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRAWo, PPC_INS_SRAW, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRD, PPC_INS_SRD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SRDo, PPC_INS_SRD, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SRW, PPC_INS_SRW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SRWo, PPC_INS_SRW, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_STB, PPC_INS_STB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STB8, PPC_INS_STB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBU, PPC_INS_STBU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBU8, PPC_INS_STBU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBUX, PPC_INS_STBUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBUX8, PPC_INS_STBUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBX, PPC_INS_STBX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STBX8, PPC_INS_STBX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STD, PPC_INS_STD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STDBRX, PPC_INS_STDBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STDCX, PPC_INS_STDCX, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_STDU, PPC_INS_STDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STDUX, PPC_INS_STDUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STDX, PPC_INS_STDX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFD, PPC_INS_STFD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFDU, PPC_INS_STFDU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFDUX, PPC_INS_STFDUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFDX, PPC_INS_STFDX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFIWX, PPC_INS_STFIWX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFS, PPC_INS_STFS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFSU, PPC_INS_STFSU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFSUX, PPC_INS_STFSUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STFSX, PPC_INS_STFSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STH, PPC_INS_STH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STH8, PPC_INS_STH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHBRX, PPC_INS_STHBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHU, PPC_INS_STHU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHU8, PPC_INS_STHU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHUX, PPC_INS_STHUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHUX8, PPC_INS_STHUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHX, PPC_INS_STHX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STHX8, PPC_INS_STHX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STMW, PPC_INS_STMW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STVEBX, PPC_INS_STVEBX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_STVEHX, PPC_INS_STVEHX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_STVEWX, PPC_INS_STVEWX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_STVX, PPC_INS_STVX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_STVXL, PPC_INS_STVXL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_STW, PPC_INS_STW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STW8, PPC_INS_STW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWBRX, PPC_INS_STWBRX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWCX, PPC_INS_STWCX, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_STWU, PPC_INS_STWU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWU8, PPC_INS_STWU, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWUX, PPC_INS_STWUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWUX8, PPC_INS_STWUX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWX, PPC_INS_STWX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_STWX8, PPC_INS_STWX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SUBF, PPC_INS_SUBF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SUBF8, PPC_INS_SUBF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_SUBF8o, PPC_INS_SUBF, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFC, PPC_INS_SUBFC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFC8, PPC_INS_SUBFC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFC8o, PPC_INS_SUBFC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFCo, PPC_INS_SUBFC, { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFE, PPC_INS_SUBFE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFE8, PPC_INS_SUBFE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFE8o, PPC_INS_SUBFE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFEo, PPC_INS_SUBFE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFIC, PPC_INS_SUBFIC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFIC8, PPC_INS_SUBFIC, { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFME, PPC_INS_SUBFME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFME8, PPC_INS_SUBFME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFME8o, PPC_INS_SUBFME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFMEo, PPC_INS_SUBFME, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFZE, PPC_INS_SUBFZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFZE8, PPC_INS_SUBFZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFZE8o, PPC_INS_SUBFZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFZEo, PPC_INS_SUBFZE, { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SUBFo, PPC_INS_SUBF, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_SYNC, PPC_INS_SYNC, { 0 }, { 0 }, { PPC_GRP_NOTBOOKE, 0 }, 0, 0 },
- { PPC_TAILB, PPC_INS_B, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_TAILB8, PPC_INS_B, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_TAILBA, PPC_INS_BA, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_TAILBA8, PPC_INS_BA, { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 },
- { PPC_TAILBCTR, PPC_INS_BCTR, { PPC_REG_CTR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 1 },
- { PPC_TAILBCTR8, PPC_INS_BCTR, { PPC_REG_CTR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 },
- { PPC_TD, PPC_INS_TD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TDI, PPC_INS_TDI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TLBIE, PPC_INS_TLBIE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TLBIEL, PPC_INS_TLBIEL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TLBSYNC, PPC_INS_TLBSYNC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TRAP, PPC_INS_TRAP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TW, PPC_INS_TW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_TWI, PPC_INS_TWI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_VADDCUW, PPC_INS_VADDCUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDFP, PPC_INS_VADDFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDSBS, PPC_INS_VADDSBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDSHS, PPC_INS_VADDSHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDSWS, PPC_INS_VADDSWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUBM, PPC_INS_VADDUBM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUBS, PPC_INS_VADDUBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUHM, PPC_INS_VADDUHM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUHS, PPC_INS_VADDUHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUWM, PPC_INS_VADDUWM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VADDUWS, PPC_INS_VADDUWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAND, PPC_INS_VAND, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VANDC, PPC_INS_VANDC, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGSB, PPC_INS_VAVGSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGSH, PPC_INS_VAVGSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGSW, PPC_INS_VAVGSW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGUB, PPC_INS_VAVGUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGUH, PPC_INS_VAVGUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VAVGUW, PPC_INS_VAVGUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCFSX, PPC_INS_VCFSX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCFSX_0, PPC_INS_VCFSX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCFUX, PPC_INS_VCFUX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCFUX_0, PPC_INS_VCFUX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPBFP, PPC_INS_VCMPBFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPBFPo, PPC_INS_VCMPBFP, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQFP, PPC_INS_VCMPEQFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQFPo, PPC_INS_VCMPEQFP, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUB, PPC_INS_VCMPEQUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUBo, PPC_INS_VCMPEQUB, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUH, PPC_INS_VCMPEQUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUHo, PPC_INS_VCMPEQUH, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUW, PPC_INS_VCMPEQUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPEQUWo, PPC_INS_VCMPEQUW, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGEFP, PPC_INS_VCMPGEFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGEFPo, PPC_INS_VCMPGEFP, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTFP, PPC_INS_VCMPGTFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTFPo, PPC_INS_VCMPGTFP, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSB, PPC_INS_VCMPGTSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSBo, PPC_INS_VCMPGTSB, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSH, PPC_INS_VCMPGTSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSHo, PPC_INS_VCMPGTSH, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSW, PPC_INS_VCMPGTSW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTSWo, PPC_INS_VCMPGTSW, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUB, PPC_INS_VCMPGTUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUBo, PPC_INS_VCMPGTUB, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUH, PPC_INS_VCMPGTUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUHo, PPC_INS_VCMPGTUH, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUW, PPC_INS_VCMPGTUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCMPGTUWo, PPC_INS_VCMPGTUW, { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCTSXS, PPC_INS_VCTSXS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCTSXS_0, PPC_INS_VCTSXS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCTUXS, PPC_INS_VCTUXS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VCTUXS_0, PPC_INS_VCTUXS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VEXPTEFP, PPC_INS_VEXPTEFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VLOGEFP, PPC_INS_VLOGEFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMADDFP, PPC_INS_VMADDFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXFP, PPC_INS_VMAXFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXSB, PPC_INS_VMAXSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXSH, PPC_INS_VMAXSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXSW, PPC_INS_VMAXSW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXUB, PPC_INS_VMAXUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXUH, PPC_INS_VMAXUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMAXUW, PPC_INS_VMAXUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMHADDSHS, PPC_INS_VMHADDSHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMHRADDSHS, PPC_INS_VMHRADDSHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINFP, PPC_INS_VMINFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINSB, PPC_INS_VMINSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINSH, PPC_INS_VMINSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINSW, PPC_INS_VMINSW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINUB, PPC_INS_VMINUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINUH, PPC_INS_VMINUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMINUW, PPC_INS_VMINUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMLADDUHM, PPC_INS_VMLADDUHM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGHB, PPC_INS_VMRGHB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGHH, PPC_INS_VMRGHH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGHW, PPC_INS_VMRGHW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGLB, PPC_INS_VMRGLB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGLH, PPC_INS_VMRGLH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMRGLW, PPC_INS_VMRGLW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMMBM, PPC_INS_VMSUMMBM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMSHM, PPC_INS_VMSUMSHM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMSHS, PPC_INS_VMSUMSHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMUBM, PPC_INS_VMSUMUBM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMUHM, PPC_INS_VMSUMUHM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMSUMUHS, PPC_INS_VMSUMUHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULESB, PPC_INS_VMULESB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULESH, PPC_INS_VMULESH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULEUB, PPC_INS_VMULEUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULEUH, PPC_INS_VMULEUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULOSB, PPC_INS_VMULOSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULOSH, PPC_INS_VMULOSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULOUB, PPC_INS_VMULOUB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VMULOUH, PPC_INS_VMULOUH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VNMSUBFP, PPC_INS_VNMSUBFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VNOR, PPC_INS_VNOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VOR, PPC_INS_VOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPERM, PPC_INS_VPERM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKPX, PPC_INS_VPKPX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKSHSS, PPC_INS_VPKSHSS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKSHUS, PPC_INS_VPKSHUS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKSWSS, PPC_INS_VPKSWSS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKSWUS, PPC_INS_VPKSWUS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKUHUM, PPC_INS_VPKUHUM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKUHUS, PPC_INS_VPKUHUS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKUWUM, PPC_INS_VPKUWUM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VPKUWUS, PPC_INS_VPKUWUS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VREFP, PPC_INS_VREFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRFIM, PPC_INS_VRFIM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRFIN, PPC_INS_VRFIN, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRFIP, PPC_INS_VRFIP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRFIZ, PPC_INS_VRFIZ, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRLB, PPC_INS_VRLB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRLH, PPC_INS_VRLH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRLW, PPC_INS_VRLW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VRSQRTEFP, PPC_INS_VRSQRTEFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSEL, PPC_INS_VSEL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSL, PPC_INS_VSL, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSLB, PPC_INS_VSLB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSLDOI, PPC_INS_VSLDOI, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSLH, PPC_INS_VSLH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSLO, PPC_INS_VSLO, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSLW, PPC_INS_VSLW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTB, PPC_INS_VSPLTB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTH, PPC_INS_VSPLTH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTISB, PPC_INS_VSPLTISB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTISH, PPC_INS_VSPLTISH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTISW, PPC_INS_VSPLTISW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSPLTW, PPC_INS_VSPLTW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSR, PPC_INS_VSR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRAB, PPC_INS_VSRAB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRAH, PPC_INS_VSRAH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRAW, PPC_INS_VSRAW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRB, PPC_INS_VSRB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRH, PPC_INS_VSRH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRO, PPC_INS_VSRO, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSRW, PPC_INS_VSRW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBCUW, PPC_INS_VSUBCUW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBFP, PPC_INS_VSUBFP, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBSBS, PPC_INS_VSUBSBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBSHS, PPC_INS_VSUBSHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBSWS, PPC_INS_VSUBSWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUBM, PPC_INS_VSUBUBM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUBS, PPC_INS_VSUBUBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUHM, PPC_INS_VSUBUHM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUHS, PPC_INS_VSUBUHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUWM, PPC_INS_VSUBUWM, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUBUWS, PPC_INS_VSUBUWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUM2SWS, PPC_INS_VSUM2SWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUM4SBS, PPC_INS_VSUM4SBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUM4SHS, PPC_INS_VSUM4SHS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUM4UBS, PPC_INS_VSUM4UBS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VSUMSWS, PPC_INS_VSUMSWS, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKHPX, PPC_INS_VUPKHPX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKHSB, PPC_INS_VUPKHSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKHSH, PPC_INS_VUPKHSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKLPX, PPC_INS_VUPKLPX, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKLSB, PPC_INS_VUPKLSB, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VUPKLSH, PPC_INS_VUPKLSH, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_VXOR, PPC_INS_VXOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SET0, PPC_INS_VXOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SET0B, PPC_INS_VXOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SET0H, PPC_INS_VXOR, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SETALLONES, PPC_INS_VSPLTISW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SETALLONESB, PPC_INS_VSPLTISW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_V_SETALLONESH, PPC_INS_VSPLTISW, { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 },
- { PPC_WAIT, PPC_INS_WAIT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XOR, PPC_INS_XOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XOR8, PPC_INS_XOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XOR8o, PPC_INS_XOR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_XORI, PPC_INS_XORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XORI8, PPC_INS_XORI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XORIS, PPC_INS_XORIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XORIS8, PPC_INS_XORIS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { PPC_XORo, PPC_INS_XOR, { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 },
- { PPC_gBC, PPC_INS_BC, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCA, PPC_INS_BCA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCCTR, PPC_INS_BCCTR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCCTRL, PPC_INS_BCCTRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCL, PPC_INS_BCL, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCLA, PPC_INS_BCLA, { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCLR, PPC_INS_BCLR, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
- { PPC_gBCLRL, PPC_INS_BCLRL, { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0 },
+ {
+ PPC_ADD4, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD4TLS, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD4o, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD8, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD8TLS, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD8TLS_, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADD8o, PPC_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDC, PPC_INS_ADDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDC8, PPC_INS_ADDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDC8o, PPC_INS_ADDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDCo, PPC_INS_ADDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDE, PPC_INS_ADDE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDE8, PPC_INS_ADDE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDE8o, PPC_INS_ADDE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDEo, PPC_INS_ADDE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDI, PPC_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDI8, PPC_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDIC, PPC_INS_ADDIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDIC8, PPC_INS_ADDIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDICo, PPC_INS_ADDIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDIS, PPC_INS_ADDIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDIS8, PPC_INS_ADDIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDME, PPC_INS_ADDME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDME8, PPC_INS_ADDME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDME8o, PPC_INS_ADDME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDMEo, PPC_INS_ADDME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDZE, PPC_INS_ADDZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDZE8, PPC_INS_ADDZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDZE8o, PPC_INS_ADDZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ADDZEo, PPC_INS_ADDZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_AND, PPC_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_AND8, PPC_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_AND8o, PPC_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDC, PPC_INS_ANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDC8, PPC_INS_ANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDC8o, PPC_INS_ANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDCo, PPC_INS_ANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDISo, PPC_INS_ANDIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDISo8, PPC_INS_ANDIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDIo, PPC_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDIo8, PPC_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ANDo, PPC_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_B, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BA, PPC_INS_BA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BCC, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BCCA, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BCCL, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCCLA, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCCTR, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_BCCTR8, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_BCCTRL, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCCTRL8, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCLR, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BCLRL, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCLalways, PPC_INS_BCL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCTR, PPC_INS_BCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_BCTR8, PPC_INS_BCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_BCTRL, PPC_INS_BCTRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { PPC_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BCTRL8, PPC_INS_BCTRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZ, PPC_INS_BDNZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZ8, PPC_INS_BDNZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZA, PPC_INS_BDNZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZAm, PPC_INS_BDNZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZAp, PPC_INS_BDNZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZL, PPC_INS_BDNZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLA, PPC_INS_BDNZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLAm, PPC_INS_BDNZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLAp, PPC_INS_BDNZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLR, PPC_INS_BDNZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZLR8, PPC_INS_BDNZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZLRL, PPC_INS_BDNZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLRLm, PPC_INS_BDNZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLRLp, PPC_INS_BDNZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLRm, PPC_INS_BDNZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZLRp, PPC_INS_BDNZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZLm, PPC_INS_BDNZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZLp, PPC_INS_BDNZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDNZm, PPC_INS_BDNZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDNZp, PPC_INS_BDNZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZ, PPC_INS_BDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZ8, PPC_INS_BDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZA, PPC_INS_BDZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZAm, PPC_INS_BDZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZAp, PPC_INS_BDZA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZL, PPC_INS_BDZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLA, PPC_INS_BDZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLAm, PPC_INS_BDZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLAp, PPC_INS_BDZLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLR, PPC_INS_BDZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZLR8, PPC_INS_BDZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZLRL, PPC_INS_BDZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLRLm, PPC_INS_BDZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLRLp, PPC_INS_BDZLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLRm, PPC_INS_BDZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZLRp, PPC_INS_BDZLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZLm, PPC_INS_BDZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZLp, PPC_INS_BDZL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BDZm, PPC_INS_BDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BDZp, PPC_INS_BDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_BL, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BL8, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BL8_NOP, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BL8_NOP_TLS, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BL8_TLS, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BL8_TLS_, PPC_INS_BL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BLA, PPC_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BLA8, PPC_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BLA8_NOP, PPC_INS_BLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BLR, PPC_INS_BLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_BLRL, PPC_INS_BLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPD, PPC_INS_CMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPDI, PPC_INS_CMPDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPLD, PPC_INS_CMPLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPLDI, PPC_INS_CMPLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPLW, PPC_INS_CMPLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPLWI, PPC_INS_CMPLWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPW, PPC_INS_CMPW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CMPWI, PPC_INS_CMPWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CNTLZD, PPC_INS_CNTLZD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CNTLZDo, PPC_INS_CNTLZD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CNTLZW, PPC_INS_CNTLZW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CNTLZWo, PPC_INS_CNTLZW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CR6SET, PPC_INS_CREQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CR6UNSET, PPC_INS_CRXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRAND, PPC_INS_CRAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRANDC, PPC_INS_CRANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CREQV, PPC_INS_CREQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRNAND, PPC_INS_CRNAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRNOR, PPC_INS_CRNOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CROR, PPC_INS_CROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRORC, PPC_INS_CRORC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRSET, PPC_INS_CREQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRUNSET, PPC_INS_CRXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_CRXOR, PPC_INS_CRXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBA, PPC_INS_DCBA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBF, PPC_INS_DCBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBI, PPC_INS_DCBI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBST, PPC_INS_DCBST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBT, PPC_INS_DCBT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBTST, PPC_INS_DCBTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBZ, PPC_INS_DCBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DCBZL, PPC_INS_DCBZL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVD, PPC_INS_DIVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVDU, PPC_INS_DIVDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVDUo, PPC_INS_DIVDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVDo, PPC_INS_DIVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVW, PPC_INS_DIVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVWU, PPC_INS_DIVWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVWUo, PPC_INS_DIVWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DIVWo, PPC_INS_DIVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSS, PPC_INS_DSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSSALL, PPC_INS_DSSALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DST, PPC_INS_DST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DST64, PPC_INS_DST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTST, PPC_INS_DSTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTST64, PPC_INS_DSTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTSTT, PPC_INS_DSTSTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTSTT64, PPC_INS_DSTSTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTT, PPC_INS_DSTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_DSTT64, PPC_INS_DSTT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EIEIO, PPC_INS_EIEIO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EQV, PPC_INS_EQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EQV8, PPC_INS_EQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EQV8o, PPC_INS_EQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EQVo, PPC_INS_EQV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSB, PPC_INS_EXTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSB8, PPC_INS_EXTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSB8_32_64, PPC_INS_EXTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSB8o, PPC_INS_EXTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSBo, PPC_INS_EXTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSH, PPC_INS_EXTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSH8, PPC_INS_EXTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSH8_32_64, PPC_INS_EXTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSH8o, PPC_INS_EXTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSHo, PPC_INS_EXTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSW, PPC_INS_EXTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSW_32_64, PPC_INS_EXTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSW_32_64o, PPC_INS_EXTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_EXTSWo, PPC_INS_EXTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FABSD, PPC_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FABSDo, PPC_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FABSS, PPC_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FABSSo, PPC_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FADD, PPC_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FADDS, PPC_INS_FADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FADDSo, PPC_INS_FADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FADDo, PPC_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFID, PPC_INS_FCFID,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDS, PPC_INS_FCFIDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDSo, PPC_INS_FCFIDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDU, PPC_INS_FCFIDU,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDUS, PPC_INS_FCFIDUS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDUSo, PPC_INS_FCFIDUS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDUo, PPC_INS_FCFIDU,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCFIDo, PPC_INS_FCFID,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCMPUD, PPC_INS_FCMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCMPUS, PPC_INS_FCMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCPSGND, PPC_INS_FCPSGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCPSGNDo, PPC_INS_FCPSGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCPSGNS, PPC_INS_FCPSGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCPSGNSo, PPC_INS_FCPSGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTID, PPC_INS_FCTID,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIDUZ, PPC_INS_FCTIDUZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIDUZo, PPC_INS_FCTIDUZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIDZ, PPC_INS_FCTIDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIDZo, PPC_INS_FCTIDZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIDo, PPC_INS_FCTID,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIW, PPC_INS_FCTIW,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIWUZ, PPC_INS_FCTIWUZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIWUZo, PPC_INS_FCTIWUZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIWZ, PPC_INS_FCTIWZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIWZo, PPC_INS_FCTIWZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FCTIWo, PPC_INS_FCTIW,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FDIV, PPC_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FDIVS, PPC_INS_FDIVS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FDIVSo, PPC_INS_FDIVS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FDIVo, PPC_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMADD, PPC_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMADDS, PPC_INS_FMADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMADDSo, PPC_INS_FMADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMADDo, PPC_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMR, PPC_INS_FMR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMRo, PPC_INS_FMR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMSUB, PPC_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMSUBS, PPC_INS_FMSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMSUBSo, PPC_INS_FMSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMSUBo, PPC_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMUL, PPC_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMULS, PPC_INS_FMULS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMULSo, PPC_INS_FMULS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FMULo, PPC_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNABSD, PPC_INS_FNABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNABSDo, PPC_INS_FNABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNABSS, PPC_INS_FNABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNABSSo, PPC_INS_FNABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNEGD, PPC_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNEGDo, PPC_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNEGS, PPC_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNEGSo, PPC_INS_FNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMADD, PPC_INS_FNMADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMADDS, PPC_INS_FNMADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMADDSo, PPC_INS_FNMADDS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMADDo, PPC_INS_FNMADD,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMSUB, PPC_INS_FNMSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMSUBS, PPC_INS_FNMSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMSUBSo, PPC_INS_FNMSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FNMSUBo, PPC_INS_FNMSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRE, PPC_INS_FRE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRES, PPC_INS_FRES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRESo, PPC_INS_FRES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FREo, PPC_INS_FRE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIMD, PPC_INS_FRIM,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIMDo, PPC_INS_FRIM,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIMS, PPC_INS_FRIM,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIMSo, PPC_INS_FRIM,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIND, PPC_INS_FRIN,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRINDo, PPC_INS_FRIN,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRINS, PPC_INS_FRIN,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRINSo, PPC_INS_FRIN,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIPD, PPC_INS_FRIP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIPDo, PPC_INS_FRIP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIPS, PPC_INS_FRIP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIPSo, PPC_INS_FRIP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIZD, PPC_INS_FRIZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIZDo, PPC_INS_FRIZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIZS, PPC_INS_FRIZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRIZSo, PPC_INS_FRIZ,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSP, PPC_INS_FRSP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSPo, PPC_INS_FRSP,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSQRTE, PPC_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSQRTES, PPC_INS_FRSQRTES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSQRTESo, PPC_INS_FRSQRTES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FRSQRTEo, PPC_INS_FRSQRTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSELD, PPC_INS_FSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSELDo, PPC_INS_FSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSELS, PPC_INS_FSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSELSo, PPC_INS_FSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSQRT, PPC_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSQRTS, PPC_INS_FSQRTS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSQRTSo, PPC_INS_FSQRTS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSQRTo, PPC_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSUB, PPC_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSUBS, PPC_INS_FSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSUBSo, PPC_INS_FSUBS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_FSUBo, PPC_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ICBI, PPC_INS_ICBI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ISEL, PPC_INS_ISEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ISEL8, PPC_INS_ISEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ISYNC, PPC_INS_ISYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LA, PPC_INS_LA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZ, PPC_INS_LBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZ8, PPC_INS_LBZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZU, PPC_INS_LBZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZU8, PPC_INS_LBZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZUX, PPC_INS_LBZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZUX8, PPC_INS_LBZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZX, PPC_INS_LBZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LBZX8, PPC_INS_LBZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LD, PPC_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDARX, PPC_INS_LDARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDBRX, PPC_INS_LDBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDU, PPC_INS_LDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDUX, PPC_INS_LDUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDX, PPC_INS_LDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDinto_toc, PPC_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LDtoc_restore, PPC_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFD, PPC_INS_LFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFDU, PPC_INS_LFDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFDUX, PPC_INS_LFDUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFDX, PPC_INS_LFDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFIWAX, PPC_INS_LFIWAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFIWZX, PPC_INS_LFIWZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFS, PPC_INS_LFS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFSU, PPC_INS_LFSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFSUX, PPC_INS_LFSUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LFSX, PPC_INS_LFSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHA, PPC_INS_LHA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHA8, PPC_INS_LHA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAU, PPC_INS_LHAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAU8, PPC_INS_LHAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAUX, PPC_INS_LHAUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAUX8, PPC_INS_LHAUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAX, PPC_INS_LHAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHAX8, PPC_INS_LHAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHBRX, PPC_INS_LHBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZ, PPC_INS_LHZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZ8, PPC_INS_LHZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZU, PPC_INS_LHZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZU8, PPC_INS_LHZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZUX, PPC_INS_LHZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZUX8, PPC_INS_LHZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZX, PPC_INS_LHZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LHZX8, PPC_INS_LHZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LI, PPC_INS_LI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LI8, PPC_INS_LI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LIS, PPC_INS_LIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LIS8, PPC_INS_LIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LMW, PPC_INS_LMW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVEBX, PPC_INS_LVEBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVEHX, PPC_INS_LVEHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVEWX, PPC_INS_LVEWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVSL, PPC_INS_LVSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVSR, PPC_INS_LVSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVX, PPC_INS_LVX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LVXL, PPC_INS_LVXL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWA, PPC_INS_LWA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWARX, PPC_INS_LWARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWAUX, PPC_INS_LWAUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWAX, PPC_INS_LWAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWAX_32, PPC_INS_LWAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWA_32, PPC_INS_LWA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWBRX, PPC_INS_LWBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZ, PPC_INS_LWZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZ8, PPC_INS_LWZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZU, PPC_INS_LWZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZU8, PPC_INS_LWZU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZUX, PPC_INS_LWZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZUX8, PPC_INS_LWZUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZX, PPC_INS_LWZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_LWZX8, PPC_INS_LWZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MCRF, PPC_INS_MCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFCR, PPC_INS_MFCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFCR8, PPC_INS_MFCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFCTR, PPC_INS_MFCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFCTR8, PPC_INS_MFCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFFS, PPC_INS_MFFS,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFLR, PPC_INS_MFLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFLR8, PPC_INS_MFLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_LR8, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFMSR, PPC_INS_MFMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFOCRF, PPC_INS_MFOCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFOCRF8, PPC_INS_MFOCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFSPR, PPC_INS_MFSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFTB, PPC_INS_MFTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFTB8, PPC_INS_MFSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFVRSAVE, PPC_INS_MFSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFVRSAVEv, PPC_INS_MFSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MFVSCR, PPC_INS_MFVSCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MSYNC, PPC_INS_MSYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCRF, PPC_INS_MTCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCRF8, PPC_INS_MTCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCTR, PPC_INS_MTCTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCTR8, PPC_INS_MTCTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCTR8loop, PPC_INS_MTCTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTCTRloop, PPC_INS_MTCTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTFSB0, PPC_INS_MTFSB0,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTFSB1, PPC_INS_MTFSB1,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTFSF, PPC_INS_MTFSF,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTLR, PPC_INS_MTLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTLR8, PPC_INS_MTLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTMSR, PPC_INS_MTMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTMSRD, PPC_INS_MTMSRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTOCRF, PPC_INS_MTOCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTOCRF8, PPC_INS_MTOCRF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTSPR, PPC_INS_MTSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTVRSAVE, PPC_INS_MTSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTVRSAVEv, PPC_INS_MTSPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MTVSCR, PPC_INS_MTVSCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHD, PPC_INS_MULHD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHDU, PPC_INS_MULHDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHDUo, PPC_INS_MULHDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHDo, PPC_INS_MULHD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHW, PPC_INS_MULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHWU, PPC_INS_MULHWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHWUo, PPC_INS_MULHWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULHWo, PPC_INS_MULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLD, PPC_INS_MULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLDo, PPC_INS_MULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLI, PPC_INS_MULLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLI8, PPC_INS_MULLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLW, PPC_INS_MULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_MULLWo, PPC_INS_MULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NAND, PPC_INS_NAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NAND8, PPC_INS_NAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NAND8o, PPC_INS_NAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NANDo, PPC_INS_NAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NEG, PPC_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NEG8, PPC_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NEG8o, PPC_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NEGo, PPC_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOP, PPC_INS_NOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOP_GT_PWR6, PPC_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOP_GT_PWR7, PPC_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOR, PPC_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOR8, PPC_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NOR8o, PPC_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_NORo, PPC_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_OR, PPC_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_OR8, PPC_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_OR8o, PPC_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORC, PPC_INS_ORC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORC8, PPC_INS_ORC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORC8o, PPC_INS_ORC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORCo, PPC_INS_ORC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORI, PPC_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORI8, PPC_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORIS, PPC_INS_ORIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORIS8, PPC_INS_ORIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_ORo, PPC_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_POPCNTD, PPC_INS_POPCNTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_POPCNTW, PPC_INS_POPCNTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDCL, PPC_INS_RLDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDCLo, PPC_INS_RLDCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDCR, PPC_INS_RLDCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDCRo, PPC_INS_RLDCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDIC, PPC_INS_RLDIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICL, PPC_INS_RLDICL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICL_32_64, PPC_INS_RLDICL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICLo, PPC_INS_RLDICL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICR, PPC_INS_RLDICR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICRo, PPC_INS_RLDICR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDICo, PPC_INS_RLDIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDIMI, PPC_INS_RLDIMI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLDIMIo, PPC_INS_RLDIMI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWIMI, PPC_INS_RLWIMI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWIMIo, PPC_INS_RLWIMI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWINM, PPC_INS_RLWINM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWINM8, PPC_INS_RLWINM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWINM8o, PPC_INS_RLWINM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWINMo, PPC_INS_RLWINM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWNM, PPC_INS_RLWNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_RLWNMo, PPC_INS_RLWNM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SC, PPC_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLBIA, PPC_INS_SLBIA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLBIE, PPC_INS_SLBIE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLBMFEE, PPC_INS_SLBMFEE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLBMTE, PPC_INS_SLBMTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLD, PPC_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLDo, PPC_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLW, PPC_INS_SLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SLWo, PPC_INS_SLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRAD, PPC_INS_SRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRADI, PPC_INS_SRADI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRADIo, PPC_INS_SRADI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRADo, PPC_INS_SRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRAW, PPC_INS_SRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRAWI, PPC_INS_SRAWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRAWIo, PPC_INS_SRAWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRAWo, PPC_INS_SRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRD, PPC_INS_SRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRDo, PPC_INS_SRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRW, PPC_INS_SRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SRWo, PPC_INS_SRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STB, PPC_INS_STB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STB8, PPC_INS_STB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBU, PPC_INS_STBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBU8, PPC_INS_STBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBUX, PPC_INS_STBUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBUX8, PPC_INS_STBUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBX, PPC_INS_STBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STBX8, PPC_INS_STBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STD, PPC_INS_STD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STDBRX, PPC_INS_STDBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STDCX, PPC_INS_STDCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STDU, PPC_INS_STDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STDUX, PPC_INS_STDUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STDX, PPC_INS_STDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFD, PPC_INS_STFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFDU, PPC_INS_STFDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFDUX, PPC_INS_STFDUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFDX, PPC_INS_STFDX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFIWX, PPC_INS_STFIWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFS, PPC_INS_STFS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFSU, PPC_INS_STFSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFSUX, PPC_INS_STFSUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STFSX, PPC_INS_STFSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STH, PPC_INS_STH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STH8, PPC_INS_STH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHBRX, PPC_INS_STHBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHU, PPC_INS_STHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHU8, PPC_INS_STHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHUX, PPC_INS_STHUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHUX8, PPC_INS_STHUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHX, PPC_INS_STHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STHX8, PPC_INS_STHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STMW, PPC_INS_STMW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STVEBX, PPC_INS_STVEBX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STVEHX, PPC_INS_STVEHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STVEWX, PPC_INS_STVEWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STVX, PPC_INS_STVX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STVXL, PPC_INS_STVXL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STW, PPC_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STW8, PPC_INS_STW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWBRX, PPC_INS_STWBRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWCX, PPC_INS_STWCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWU, PPC_INS_STWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWU8, PPC_INS_STWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWUX, PPC_INS_STWUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWUX8, PPC_INS_STWUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWX, PPC_INS_STWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_STWX8, PPC_INS_STWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBF, PPC_INS_SUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBF8, PPC_INS_SUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBF8o, PPC_INS_SUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFC, PPC_INS_SUBFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFC8, PPC_INS_SUBFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFC8o, PPC_INS_SUBFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFCo, PPC_INS_SUBFC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFE, PPC_INS_SUBFE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFE8, PPC_INS_SUBFE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFE8o, PPC_INS_SUBFE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFEo, PPC_INS_SUBFE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFIC, PPC_INS_SUBFIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFIC8, PPC_INS_SUBFIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFME, PPC_INS_SUBFME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFME8, PPC_INS_SUBFME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFME8o, PPC_INS_SUBFME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFMEo, PPC_INS_SUBFME,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFZE, PPC_INS_SUBFZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFZE8, PPC_INS_SUBFZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFZE8o, PPC_INS_SUBFZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFZEo, PPC_INS_SUBFZE,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SUBFo, PPC_INS_SUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_SYNC, PPC_INS_SYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_NOTBOOKE, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TAILB, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_TAILB8, PPC_INS_B,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_TAILBA, PPC_INS_BA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_TAILBA8, PPC_INS_BA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ PPC_TAILBCTR, PPC_INS_BCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_TAILBCTR8, PPC_INS_BCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1
+#endif
+ },
+ {
+ PPC_TD, PPC_INS_TD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TDI, PPC_INS_TDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TLBIE, PPC_INS_TLBIE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TLBIEL, PPC_INS_TLBIEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TLBSYNC, PPC_INS_TLBSYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TRAP, PPC_INS_TRAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TW, PPC_INS_TW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_TWI, PPC_INS_TWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDCUW, PPC_INS_VADDCUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDFP, PPC_INS_VADDFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDSBS, PPC_INS_VADDSBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDSHS, PPC_INS_VADDSHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDSWS, PPC_INS_VADDSWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUBM, PPC_INS_VADDUBM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUBS, PPC_INS_VADDUBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUHM, PPC_INS_VADDUHM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUHS, PPC_INS_VADDUHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUWM, PPC_INS_VADDUWM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VADDUWS, PPC_INS_VADDUWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAND, PPC_INS_VAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VANDC, PPC_INS_VANDC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGSB, PPC_INS_VAVGSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGSH, PPC_INS_VAVGSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGSW, PPC_INS_VAVGSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGUB, PPC_INS_VAVGUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGUH, PPC_INS_VAVGUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VAVGUW, PPC_INS_VAVGUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCFSX, PPC_INS_VCFSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCFSX_0, PPC_INS_VCFSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCFUX, PPC_INS_VCFUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCFUX_0, PPC_INS_VCFUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPBFP, PPC_INS_VCMPBFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPBFPo, PPC_INS_VCMPBFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQFP, PPC_INS_VCMPEQFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQFPo, PPC_INS_VCMPEQFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUB, PPC_INS_VCMPEQUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUBo, PPC_INS_VCMPEQUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUH, PPC_INS_VCMPEQUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUHo, PPC_INS_VCMPEQUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUW, PPC_INS_VCMPEQUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPEQUWo, PPC_INS_VCMPEQUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGEFP, PPC_INS_VCMPGEFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGEFPo, PPC_INS_VCMPGEFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTFP, PPC_INS_VCMPGTFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTFPo, PPC_INS_VCMPGTFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSB, PPC_INS_VCMPGTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSBo, PPC_INS_VCMPGTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSH, PPC_INS_VCMPGTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSHo, PPC_INS_VCMPGTSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSW, PPC_INS_VCMPGTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTSWo, PPC_INS_VCMPGTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUB, PPC_INS_VCMPGTUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUBo, PPC_INS_VCMPGTUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUH, PPC_INS_VCMPGTUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUHo, PPC_INS_VCMPGTUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUW, PPC_INS_VCMPGTUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCMPGTUWo, PPC_INS_VCMPGTUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCTSXS, PPC_INS_VCTSXS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCTSXS_0, PPC_INS_VCTSXS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCTUXS, PPC_INS_VCTUXS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VCTUXS_0, PPC_INS_VCTUXS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VEXPTEFP, PPC_INS_VEXPTEFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VLOGEFP, PPC_INS_VLOGEFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMADDFP, PPC_INS_VMADDFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXFP, PPC_INS_VMAXFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXSB, PPC_INS_VMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXSH, PPC_INS_VMAXSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXSW, PPC_INS_VMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXUB, PPC_INS_VMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXUH, PPC_INS_VMAXUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMAXUW, PPC_INS_VMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMHADDSHS, PPC_INS_VMHADDSHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMHRADDSHS, PPC_INS_VMHRADDSHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINFP, PPC_INS_VMINFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINSB, PPC_INS_VMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINSH, PPC_INS_VMINSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINSW, PPC_INS_VMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINUB, PPC_INS_VMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINUH, PPC_INS_VMINUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMINUW, PPC_INS_VMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMLADDUHM, PPC_INS_VMLADDUHM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGHB, PPC_INS_VMRGHB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGHH, PPC_INS_VMRGHH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGHW, PPC_INS_VMRGHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGLB, PPC_INS_VMRGLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGLH, PPC_INS_VMRGLH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMRGLW, PPC_INS_VMRGLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMMBM, PPC_INS_VMSUMMBM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMSHM, PPC_INS_VMSUMSHM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMSHS, PPC_INS_VMSUMSHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMUBM, PPC_INS_VMSUMUBM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMUHM, PPC_INS_VMSUMUHM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMSUMUHS, PPC_INS_VMSUMUHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULESB, PPC_INS_VMULESB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULESH, PPC_INS_VMULESH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULEUB, PPC_INS_VMULEUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULEUH, PPC_INS_VMULEUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULOSB, PPC_INS_VMULOSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULOSH, PPC_INS_VMULOSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULOUB, PPC_INS_VMULOUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VMULOUH, PPC_INS_VMULOUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VNMSUBFP, PPC_INS_VNMSUBFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VNOR, PPC_INS_VNOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VOR, PPC_INS_VOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPERM, PPC_INS_VPERM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKPX, PPC_INS_VPKPX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKSHSS, PPC_INS_VPKSHSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKSHUS, PPC_INS_VPKSHUS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKSWSS, PPC_INS_VPKSWSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKSWUS, PPC_INS_VPKSWUS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKUHUM, PPC_INS_VPKUHUM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKUHUS, PPC_INS_VPKUHUS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKUWUM, PPC_INS_VPKUWUM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VPKUWUS, PPC_INS_VPKUWUS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VREFP, PPC_INS_VREFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRFIM, PPC_INS_VRFIM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRFIN, PPC_INS_VRFIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRFIP, PPC_INS_VRFIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRFIZ, PPC_INS_VRFIZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRLB, PPC_INS_VRLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRLH, PPC_INS_VRLH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRLW, PPC_INS_VRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VRSQRTEFP, PPC_INS_VRSQRTEFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSEL, PPC_INS_VSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSL, PPC_INS_VSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSLB, PPC_INS_VSLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSLDOI, PPC_INS_VSLDOI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSLH, PPC_INS_VSLH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSLO, PPC_INS_VSLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSLW, PPC_INS_VSLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTB, PPC_INS_VSPLTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTH, PPC_INS_VSPLTH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTISB, PPC_INS_VSPLTISB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTISH, PPC_INS_VSPLTISH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTISW, PPC_INS_VSPLTISW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSPLTW, PPC_INS_VSPLTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSR, PPC_INS_VSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRAB, PPC_INS_VSRAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRAH, PPC_INS_VSRAH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRAW, PPC_INS_VSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRB, PPC_INS_VSRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRH, PPC_INS_VSRH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRO, PPC_INS_VSRO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSRW, PPC_INS_VSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBCUW, PPC_INS_VSUBCUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBFP, PPC_INS_VSUBFP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBSBS, PPC_INS_VSUBSBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBSHS, PPC_INS_VSUBSHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBSWS, PPC_INS_VSUBSWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUBM, PPC_INS_VSUBUBM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUBS, PPC_INS_VSUBUBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUHM, PPC_INS_VSUBUHM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUHS, PPC_INS_VSUBUHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUWM, PPC_INS_VSUBUWM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUBUWS, PPC_INS_VSUBUWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUM2SWS, PPC_INS_VSUM2SWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUM4SBS, PPC_INS_VSUM4SBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUM4SHS, PPC_INS_VSUM4SHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUM4UBS, PPC_INS_VSUM4UBS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VSUMSWS, PPC_INS_VSUMSWS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKHPX, PPC_INS_VUPKHPX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKHSB, PPC_INS_VUPKHSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKHSH, PPC_INS_VUPKHSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKLPX, PPC_INS_VUPKLPX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKLSB, PPC_INS_VUPKLSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VUPKLSH, PPC_INS_VUPKLSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_VXOR, PPC_INS_VXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SET0, PPC_INS_VXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SET0B, PPC_INS_VXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SET0H, PPC_INS_VXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SETALLONES, PPC_INS_VSPLTISW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SETALLONESB, PPC_INS_VSPLTISW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_V_SETALLONESH, PPC_INS_VSPLTISW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_WAIT, PPC_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XOR, PPC_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XOR8, PPC_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XOR8o, PPC_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XORI, PPC_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XORI8, PPC_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XORIS, PPC_INS_XORIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XORIS8, PPC_INS_XORIS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_XORo, PPC_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBC, PPC_INS_BC,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCA, PPC_INS_BCA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCCTR, PPC_INS_BCCTR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCCTRL, PPC_INS_BCCTRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCL, PPC_INS_BCL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCLA, PPC_INS_BCLA,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCLR, PPC_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ PPC_gBCLRL, PPC_INS_BCLRL,
+#ifndef CAPSTONE_DIET
+ { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 0, 0
+#endif
+ },
};
// given internal insn id, return public instruction info
@@ -927,6 +4684,7 @@
insn->id = insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
cs_struct handle;
handle.detail = h->detail;
@@ -946,10 +4704,12 @@
}
insn->detail->ppc.update_cr0 = cs_reg_write((csh)&handle, insn, PPC_REG_CR0);
+#endif
}
}
}
+#ifndef CAPSTONE_DIET
static name_map insn_name_maps[] = {
{ PPC_INS_INVALID, NULL },
@@ -1394,9 +5154,11 @@
static name_map alias_insn_names[] = {
{ 0, NULL }
};
+#endif
const char *PPC_insn_name(csh handle, unsigned int id)
{
+#ifndef CAPSTONE_DIET
if (id >= PPC_INS_MAX)
return NULL;
@@ -1408,22 +5170,9 @@
}
return insn_name_maps[id].name;
-}
-
-ppc_reg PPC_map_insn(const char *name)
-{
- // handle special alias first
- int i;
-
- for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
- if (!strcasecmp(alias_insn_names[i].name, name))
- return alias_insn_names[i].id;
- }
-
- // NOTE: skip first NULL name in insn_name_maps
- i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
-
- return (i != -1)? i : PPC_REG_INVALID;
+#else
+ return NULL;
+#endif
}
// map internal raw register to 'public' register
diff --git a/arch/PowerPC/PPCMapping.h b/arch/PowerPC/PPCMapping.h
index b6975a0..01ab8ec 100644
--- a/arch/PowerPC/PPCMapping.h
+++ b/arch/PowerPC/PPCMapping.h
@@ -15,9 +15,6 @@
const char *PPC_insn_name(csh handle, unsigned int id);
-// map instruction name to instruction ID
-ppc_reg PPC_map_insn(const char *name);
-
// map internal raw register to 'public' register
ppc_reg PPC_map_register(unsigned int r);
diff --git a/arch/X86/X86GenAsmWriter.inc b/arch/X86/X86GenAsmWriter.inc
index 401c305..744bfce 100644
--- a/arch/X86/X86GenAsmWriter.inc
+++ b/arch/X86/X86GenAsmWriter.inc
@@ -10781,6 +10781,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 32, 9, 0,
/* 12 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 32, 9, 0,
@@ -12340,13 +12341,16 @@
/* 15407 */ 'f', 'n', 'c', 'l', 'e', 'x', 0,
/* 15414 */ 'f', 'l', 'd', 'z', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 16383)-1);
+#endif
// Fragment 0 encoded into 7 bits for 78 unique commands.
@@ -13428,6 +13432,7 @@
{
// assert(RegNo && RegNo < 233 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
@@ -13662,6 +13667,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/X86/X86GenAsmWriter1.inc b/arch/X86/X86GenAsmWriter1.inc
index b3d40e0..f022dd4 100644
--- a/arch/X86/X86GenAsmWriter1.inc
+++ b/arch/X86/X86GenAsmWriter1.inc
@@ -10781,6 +10781,7 @@
0U
};
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 32, 9, 0,
/* 12 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 32, 9, 0,
@@ -12051,13 +12052,16 @@
/* 12905 */ 'f', 'n', 'c', 'l', 'e', 'x', 0,
/* 12912 */ 'f', 'l', 'd', 'z', 0,
};
+#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
// assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 16383)-1);
+#endif
// Fragment 0 encoded into 6 bits for 45 unique commands.
@@ -12939,6 +12943,7 @@
{
// assert(RegNo && RegNo < 233 && "Invalid register number!");
+#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 's', 't', '(', '0', ')', 0,
/* 6 */ 's', 't', '(', '1', ')', 0,
@@ -13173,6 +13178,9 @@
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
}
#ifdef PRINT_ALIAS_INSTR
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 923fe3b..0feeb7e 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -63,6 +63,7 @@
return segment_map[r];
}
+#ifndef CAPSTONE_DIET
static name_map reg_name_maps[] = {
{ X86_REG_INVALID, NULL },
@@ -299,9 +300,11 @@
{ X86_REG_R14W, "r14w" },
{ X86_REG_R15W, "r15w" },
};
+#endif
const char *X86_reg_name(csh handle, unsigned int reg)
{
+#ifndef CAPSTONE_DIET
cs_struct *ud = (cs_struct *)handle;
if (reg >= X86_REG_MAX)
@@ -315,10 +318,15 @@
}
return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
}
+// map register string to register ID
x86_reg x86_map_regname(const char *reg)
{
+#ifndef CAPSTONE_DIET
int i = name2id(®_name_maps[1], ARR_SIZE(reg_name_maps) - 1, reg);
if (i != -1)
@@ -326,8 +334,12 @@
// nothing match
return (i != -1)? i : X86_REG_INVALID;
+#else
+ return 0;
+#endif
}
+#ifndef CAPSTONE_DIET
static name_map insn_name_maps[] = {
{ X86_INS_INVALID, NULL },
@@ -1590,5054 +1602,30146 @@
{ X86_INS_XSTORE, "xstore" },
{ X86_INS_XTEST, "xtest" },
};
+#endif
const char *X86_insn_name(csh handle, unsigned int id)
{
+#ifndef CAPSTONE_DIET
if (id >= X86_INS_MAX)
return NULL;
return insn_name_maps[id].name;
-}
-
-// return insn id, given insn mnemonic
-x86_reg X86_map_insn(const char *name)
-{
- int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
-
- if (i == -1) {
- // xstorerng is a special case
- if (!strcmp(name, "xstorerng"))
- i = X86_INS_XSTORE;
- }
-
- return (i != -1)? i : X86_REG_INVALID;
+#else
+ return NULL;
+#endif
}
#define GET_INSTRINFO_ENUM
#include "X86GenInstrInfo.inc"
static insn_map insns[] = {
- { 0, 0, { 0 }, { 0 }, { 0 }, 0, 0 }, // dummy item
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
- { X86_AAA, X86_INS_AAA, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_AAD8i8, X86_INS_AAD, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_AAM8i8, X86_INS_AAM, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_AAS, X86_INS_AAS, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_ABS_F, X86_INS_FABS, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ADC16i16, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16mi, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16mi8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16mr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16ri, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16ri8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16rm, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16rr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC16rr_REV, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32i32, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32mi, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32mi8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32mr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32ri, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32ri8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32rm, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32rr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC32rr_REV, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64i32, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64mi32, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64mi8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64mr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64ri32, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64ri8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64rm, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64rr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC64rr_REV, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8i8, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8mi, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8mr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8ri, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8rm, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8rr, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADC8rr_REV, X86_INS_ADC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADCX32rm, X86_INS_ADCX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADCX32rr, X86_INS_ADCX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADCX64rm, X86_INS_ADCX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADCX64rr, X86_INS_ADCX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADD16i16, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16ri, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16ri8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16rm, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16rr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD16rr_REV, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32i32, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32ri, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32ri8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32rm, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32rr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD32rr_REV, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64i32, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64mi32, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64ri32, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64ri8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64rm, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64rr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD64rr_REV, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8i8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8ri, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8rm, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8rr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADD8rr_REV, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ADDPDrm, X86_INS_ADDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDPDrr, X86_INS_ADDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDPSrm, X86_INS_ADDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDPSrr, X86_INS_ADDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDSDrm, X86_INS_ADDSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDSDrm_Int, X86_INS_ADDSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDSDrr, X86_INS_ADDSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDSDrr_Int, X86_INS_ADDSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ADDSSrm, X86_INS_ADDSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDSSrm_Int, X86_INS_ADDSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDSSrr, X86_INS_ADDSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDSSrr_Int, X86_INS_ADDSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ADDSUBPDrm, X86_INS_ADDSUBPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_ADDSUBPDrr, X86_INS_ADDSUBPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_ADDSUBPSrm, X86_INS_ADDSUBPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_ADDSUBPSrr, X86_INS_ADDSUBPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_ADD_F32m, X86_INS_FADD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ADD_F64m, X86_INS_FADD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ADD_FI16m, X86_INS_FIADD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ADD_FI32m, X86_INS_FIADD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ADD_FPrST0, X86_INS_FADDP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ADD_FST0r, X86_INS_FADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ADD_FrST0, X86_INS_FADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ADOX32rm, X86_INS_ADOX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADOX32rr, X86_INS_ADOX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADOX64rm, X86_INS_ADOX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_ADOX64rr, X86_INS_ADOX, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 },
- { X86_AESDECLASTrm, X86_INS_AESDECLAST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESDECLASTrr, X86_INS_AESDECLAST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESDECrm, X86_INS_AESDEC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESDECrr, X86_INS_AESDEC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESENCLASTrm, X86_INS_AESENCLAST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESENCLASTrr, X86_INS_AESENCLAST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESENCrm, X86_INS_AESENC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESENCrr, X86_INS_AESENC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESIMCrm, X86_INS_AESIMC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESIMCrr, X86_INS_AESIMC, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST, { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 },
- { X86_AND16i16, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16ri, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16ri8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16rm, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16rr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND16rr_REV, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32i32, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32ri, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32ri8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32rm, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32rr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND32rr_REV, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64i32, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64mi32, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64ri32, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64ri8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64rm, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64rr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND64rr_REV, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8i8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8ri, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8rm, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8rr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_AND8rr_REV, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ANDN32rm, X86_INS_ANDN, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_ANDN32rr, X86_INS_ANDN, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_ANDN64rm, X86_INS_ANDN, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_ANDN64rr, X86_INS_ANDN, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_ANDNPDrm, X86_INS_ANDNPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ANDNPDrr, X86_INS_ANDNPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ANDNPSrm, X86_INS_ANDNPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ANDNPSrr, X86_INS_ANDNPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ANDPDrm, X86_INS_ANDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ANDPDrr, X86_INS_ANDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ANDPSrm, X86_INS_ANDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ANDPSrr, X86_INS_ANDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ARPL16mr, X86_INS_ARPL, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_ARPL16rr, X86_INS_ARPL, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_BEXTR32rm, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BEXTR32rr, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BEXTR64rm, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BEXTR64rr, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BEXTRI32mi, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BEXTRI32ri, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BEXTRI64mi, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BEXTRI64ri, X86_INS_BEXTR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCFILL32rm, X86_INS_BLCFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCFILL32rr, X86_INS_BLCFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCFILL64rm, X86_INS_BLCFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCFILL64rr, X86_INS_BLCFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCI32rm, X86_INS_BLCI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCI32rr, X86_INS_BLCI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCI64rm, X86_INS_BLCI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCI64rr, X86_INS_BLCI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCIC32rm, X86_INS_BLCIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCIC32rr, X86_INS_BLCIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCIC64rm, X86_INS_BLCIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCIC64rr, X86_INS_BLCIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCMSK32rm, X86_INS_BLCMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCMSK32rr, X86_INS_BLCMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCMSK64rm, X86_INS_BLCMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCMSK64rr, X86_INS_BLCMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCS32rm, X86_INS_BLCS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCS32rr, X86_INS_BLCS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCS64rm, X86_INS_BLCS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLCS64rr, X86_INS_BLCS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLENDPDrmi, X86_INS_BLENDPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDPDrri, X86_INS_BLENDPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDPSrmi, X86_INS_BLENDPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDPSrri, X86_INS_BLENDPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDVPDrm0, X86_INS_BLENDVPD, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDVPDrr0, X86_INS_BLENDVPD, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDVPSrm0, X86_INS_BLENDVPS, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLENDVPSrr0, X86_INS_BLENDVPS, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_BLSFILL32rm, X86_INS_BLSFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSFILL32rr, X86_INS_BLSFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSFILL64rm, X86_INS_BLSFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSFILL64rr, X86_INS_BLSFILL, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSI32rm, X86_INS_BLSI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSI32rr, X86_INS_BLSI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSI64rm, X86_INS_BLSI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSI64rr, X86_INS_BLSI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSIC32rm, X86_INS_BLSIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSIC32rr, X86_INS_BLSIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSIC64rm, X86_INS_BLSIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSIC64rr, X86_INS_BLSIC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_BLSMSK32rm, X86_INS_BLSMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSMSK32rr, X86_INS_BLSMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSMSK64rm, X86_INS_BLSMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSMSK64rr, X86_INS_BLSMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSR32rm, X86_INS_BLSR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSR32rr, X86_INS_BLSR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSR64rm, X86_INS_BLSR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BLSR64rr, X86_INS_BLSR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_BOUNDS16rm, X86_INS_BOUND, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_BOUNDS32rm, X86_INS_BOUND, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_BSF16rm, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSF16rr, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSF32rm, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSF32rr, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSF64rm, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSF64rr, X86_INS_BSF, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR16rm, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR16rr, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR32rm, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR32rr, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR64rm, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSR64rr, X86_INS_BSR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BSWAP32r, X86_INS_BSWAP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_BSWAP64r, X86_INS_BSWAP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_BT16mi8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT16mr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT16ri8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT16rr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT32mi8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT32mr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT32ri8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT32rr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT64mi8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT64mr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT64ri8, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BT64rr, X86_INS_BT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC16mi8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC16mr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC16ri8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC16rr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC32mi8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC32mr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC32ri8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC32rr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC64mi8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC64mr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC64ri8, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTC64rr, X86_INS_BTC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR16mi8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR16mr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR16ri8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR16rr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR32mi8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR32mr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR32ri8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR32rr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR64mi8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR64mr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR64ri8, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTR64rr, X86_INS_BTR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS16mi8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS16mr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS16ri8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS16rr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS32mi8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS32mr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS32ri8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS32rr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS64mi8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS64mr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS64ri8, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BTS64rr, X86_INS_BTS, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_BZHI32rm, X86_INS_BZHI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_BZHI32rr, X86_INS_BZHI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_BZHI64rm, X86_INS_BZHI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_BZHI64rr, X86_INS_BZHI, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_CALL16m, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CALL16r, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CALL32m, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CALL32r, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CALL64m, X86_INS_CALL, { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_CALL64pcrel32, X86_INS_CALL, { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_CALL64r, X86_INS_CALL, { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_CALLpcrel16, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CALLpcrel32, X86_INS_CALL, { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CBW, X86_INS_CBW, { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_CDQ, X86_INS_CDQ, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 },
- { X86_CDQE, X86_INS_CDQE, { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0 },
- { X86_CHS_F, X86_INS_FCHS, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_CLAC, X86_INS_CLAC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CLC, X86_INS_CLC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CLD, X86_INS_CLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CLFLUSH, X86_INS_CLFLUSH, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CLGI, X86_INS_CLGI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CLI, X86_INS_CLI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CLTS, X86_INS_CLTS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMC, X86_INS_CMC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMOVA16rm, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVA16rr, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVA32rm, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVA32rr, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVA64rm, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVA64rr, X86_INS_CMOVA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE16rm, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE16rr, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE32rm, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE32rr, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE64rm, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVAE64rr, X86_INS_CMOVAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB16rm, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB16rr, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB32rm, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB32rr, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB64rm, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB64rr, X86_INS_CMOVB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE16rm, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE16rr, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE32rm, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE32rr, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE64rm, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE64rr, X86_INS_CMOVBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVBE_F, X86_INS_FCMOVBE, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVB_F, X86_INS_FCMOVB, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE16rm, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE16rr, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE32rm, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE32rr, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE64rm, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE64rr, X86_INS_CMOVE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVE_F, X86_INS_FCMOVE, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG16rm, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG16rr, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG32rm, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG32rr, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG64rm, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVG64rr, X86_INS_CMOVG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE16rm, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE16rr, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE32rm, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE32rr, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE64rm, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVGE64rr, X86_INS_CMOVGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL16rm, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL16rr, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL32rm, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL32rr, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL64rm, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVL64rr, X86_INS_CMOVL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE16rm, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE16rr, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE32rm, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE32rr, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE64rm, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVLE64rr, X86_INS_CMOVLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNBE_F, X86_INS_FCMOVNBE, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNB_F, X86_INS_FCMOVNB, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE16rm, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE16rr, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE32rm, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE32rr, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE64rm, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE64rr, X86_INS_CMOVNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNE_F, X86_INS_FCMOVNE, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO16rm, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO16rr, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO32rm, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO32rr, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO64rm, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNO64rr, X86_INS_CMOVNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP16rm, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP16rr, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP32rm, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP32rr, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP64rm, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP64rr, X86_INS_CMOVNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNP_F, X86_INS_FCMOVNU, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS16rm, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS16rr, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS32rm, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS32rr, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS64rm, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVNS64rr, X86_INS_CMOVNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO16rm, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO16rr, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO32rm, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO32rr, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO64rm, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVO64rr, X86_INS_CMOVO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP16rm, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP16rr, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP32rm, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP32rr, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP64rm, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP64rr, X86_INS_CMOVP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVP_F, X86_INS_FCMOVU, { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS16rm, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS16rr, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS32rm, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS32rr, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS64rm, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMOVS64rr, X86_INS_CMOVS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 },
- { X86_CMP16i16, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16mi, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16mi8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16mr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16ri, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16ri8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16rm, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16rr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP16rr_REV, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32i32, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32mi, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32mi8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32mr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32ri, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32ri8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32rm, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32rr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP32rr_REV, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64i32, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64mi32, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64mi8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64mr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64ri32, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64ri8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64rm, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64rr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP64rr_REV, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8i8, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8mi, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8mr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8ri, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8rm, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8rr, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMP8rr_REV, X86_INS_CMP, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMPPDrmi, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPPDrmi_alt, X86_INS_CMPPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPPDrri, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPPDrri_alt, X86_INS_CMPPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPPSrmi, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPPSrmi_alt, X86_INS_CMPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPPSrri, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPPSrri_alt, X86_INS_CMPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPS16, X86_INS_CMPSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPS32, X86_INS_CMPSD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPS64, X86_INS_CMPSQ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPS8, X86_INS_CMPSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPSDrm, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPSDrm_alt, X86_INS_CMPSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPSDrr, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPSDrr_alt, X86_INS_CMPSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CMPSSrm, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPSSrm_alt, X86_INS_CMPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPSSrr, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPSSrr_alt, X86_INS_CMPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CMPXCHG16B, X86_INS_CMPXCHG16B, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG16rm, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG16rr, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG32rm, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG32rr, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG64rm, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG64rr, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG8B, X86_INS_CMPXCHG8B, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG8rm, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CMPXCHG8rr, X86_INS_CMPXCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_COMISDrm, X86_INS_COMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_COMISDrr, X86_INS_COMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_COMISSrm, X86_INS_COMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_COMISSrr, X86_INS_COMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_COMP_FST0r, X86_INS_FCOMP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_COM_FIPr, X86_INS_FCOMPI, { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_COM_FIr, X86_INS_FCOMI, { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_COM_FST0r, X86_INS_FCOM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_COS_F, X86_INS_FCOS, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_CPUID32, X86_INS_CPUID, { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_CPUID64, X86_INS_CPUID, { X86_REG_RAX, X86_REG_RCX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_CQO, X86_INS_CQO, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 },
- { X86_CRC32r32m16, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r32m32, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r32m8, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r32r16, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r32r32, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r32r8, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r64m64, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r64m8, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r64r64, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CRC32r64r8, X86_INS_CRC32, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_CS_PREFIX, X86_INS_CS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPD2DQrm, X86_INS_CVTPD2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPD2DQrr, X86_INS_CVTPD2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPD2PSrm, X86_INS_CVTPD2PS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPD2PSrr, X86_INS_CVTPD2PS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPS2DQrm, X86_INS_CVTPS2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPS2DQrr, X86_INS_CVTPS2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPS2PDrm, X86_INS_CVTPS2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTPS2PDrr, X86_INS_CVTPS2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SI64rm, X86_INS_CVTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SI64rr, X86_INS_CVTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SIrm, X86_INS_CVTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SIrr, X86_INS_CVTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SSrm, X86_INS_CVTSD2SS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSD2SSrr, X86_INS_CVTSD2SS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSI2SD64rm, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSI2SD64rr, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSI2SDrm, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSI2SDrr, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSI2SS64rm, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSI2SS64rr, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSI2SSrm, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSI2SSrr, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSS2SDrm, X86_INS_CVTSS2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSS2SDrr, X86_INS_CVTSS2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTSS2SI64rm, X86_INS_CVTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSS2SI64rr, X86_INS_CVTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSS2SIrm, X86_INS_CVTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTSS2SIrr, X86_INS_CVTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_CWD, X86_INS_CWD, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0 },
- { X86_CWDE, X86_INS_CWDE, { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 },
- { X86_DAA, X86_INS_DAA, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DAS, X86_INS_DAS, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DATA16_PREFIX, X86_INS_DATA16, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DEC16m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC16r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC32_16r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC32_32r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC32m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC32r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_DEC64_16m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_DEC64_16r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_DEC64_32m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_DEC64_32r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_DEC64m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DEC64r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DEC8m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DEC8r, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV16m, X86_INS_DIV, { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV16r, X86_INS_DIV, { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV32m, X86_INS_DIV, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV32r, X86_INS_DIV, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV64m, X86_INS_DIV, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV64r, X86_INS_DIV, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV8m, X86_INS_DIV, { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIV8r, X86_INS_DIV, { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_DIVPDrm, X86_INS_DIVPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVPDrr, X86_INS_DIVPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVPSrm, X86_INS_DIVPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIVPSrr, X86_INS_DIVPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIVR_F32m, X86_INS_FDIVR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIVR_F64m, X86_INS_FDIVR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIVR_FI16m, X86_INS_FIDIVR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIVR_FI32m, X86_INS_FIDIVR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIVR_FPrST0, X86_INS_FDIVRP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DIVR_FST0r, X86_INS_FDIVR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DIVR_FrST0, X86_INS_FDIVR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DIVSDrm, X86_INS_DIVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVSDrm_Int, X86_INS_DIVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVSDrr, X86_INS_DIVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVSDrr_Int, X86_INS_DIVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_DIVSSrm, X86_INS_DIVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIVSSrm_Int, X86_INS_DIVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIVSSrr, X86_INS_DIVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIVSSrr_Int, X86_INS_DIVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_DIV_F32m, X86_INS_FDIV, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIV_F64m, X86_INS_FDIV, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIV_FI16m, X86_INS_FIDIV, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIV_FI32m, X86_INS_FIDIV, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_DIV_FPrST0, X86_INS_FDIVP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DIV_FST0r, X86_INS_FDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DIV_FrST0, X86_INS_FDIV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_DPPDrmi, X86_INS_DPPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_DPPDrri, X86_INS_DPPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_DPPSrmi, X86_INS_DPPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_DPPSrri, X86_INS_DPPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_DS_PREFIX, X86_INS_DS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ENTER, X86_INS_ENTER, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ES_PREFIX, X86_INS_ES, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_EXTRACTPSmr, X86_INS_EXTRACTPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_EXTRACTPSrr, X86_INS_EXTRACTPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_EXTRQ, X86_INS_EXTRQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_EXTRQI, X86_INS_EXTRQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_F2XM1, X86_INS_F2XM1, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARCALL16i, X86_INS_LCALL, { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARCALL16m, X86_INS_LCALL, { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARCALL32i, X86_INS_LCALL, { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARCALL32m, X86_INS_LCALL, { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARCALL64, X86_INS_LCALL, { X86_REG_RSP, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FARJMP16i, X86_INS_LJMP, { 0 }, { 0 }, { 0 }, 1, 1 },
- { X86_FARJMP16m, X86_INS_LJMP, { 0 }, { 0 }, { 0 }, 1, 1 },
- { X86_FARJMP32i, X86_INS_LJMP, { 0 }, { 0 }, { 0 }, 1, 1 },
- { X86_FARJMP32m, X86_INS_LJMP, { 0 }, { 0 }, { 0 }, 1, 1 },
- { X86_FARJMP64, X86_INS_LJMP, { 0 }, { 0 }, { 0 }, 1, 1 },
- { X86_FBLDm, X86_INS_FBLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FBSTPm, X86_INS_FBSTP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FCOM32m, X86_INS_FCOM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FCOM64m, X86_INS_FCOM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FCOMP32m, X86_INS_FCOMP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FCOMP64m, X86_INS_FCOMP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FCOMPP, X86_INS_FCOMPP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FDECSTP, X86_INS_FDECSTP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FEMMS, X86_INS_FEMMS, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_FFREE, X86_INS_FFREE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FICOM16m, X86_INS_FICOM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FICOM32m, X86_INS_FICOM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FICOMP16m, X86_INS_FICOMP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FICOMP32m, X86_INS_FICOMP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FINCSTP, X86_INS_FINCSTP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDCW16m, X86_INS_FLDCW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDENVm, X86_INS_FLDENV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDL2E, X86_INS_FLDL2E, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDL2T, X86_INS_FLDL2T, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDLG2, X86_INS_FLDLG2, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDLN2, X86_INS_FLDLN2, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FLDPI, X86_INS_FLDPI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FNCLEX, X86_INS_FNCLEX, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_FNINIT, X86_INS_FNINIT, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_FNOP, X86_INS_FNOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FNSTCW16m, X86_INS_FNSTCW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FNSTSW16r, X86_INS_FNSTSW, { X86_REG_FPSW, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_FNSTSWm, X86_INS_FNSTSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FPATAN, X86_INS_FPATAN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FPREM, X86_INS_FPREM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FPREM1, X86_INS_FPREM1, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FPTAN, X86_INS_FPTAN, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FRNDINT, X86_INS_FRNDINT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FRSTORm, X86_INS_FRSTOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FSAVEm, X86_INS_FNSAVE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FSCALE, X86_INS_FSCALE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FSETPM, X86_INS_FSETPM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FSINCOS, X86_INS_FSINCOS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FSTENVm, X86_INS_FNSTENV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FS_PREFIX, X86_INS_FS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FXAM, X86_INS_FXAM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FXRSTOR, X86_INS_FXRSTOR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FXRSTOR64, X86_INS_FXRSTOR64, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_FXSAVE, X86_INS_FXSAVE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FXSAVE64, X86_INS_FXSAVE64, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_FXTRACT, X86_INS_FXTRACT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FYL2X, X86_INS_FYL2X, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FYL2XP1, X86_INS_FYL2XP1, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_FsANDNPDrm, X86_INS_ANDNPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsANDNPDrr, X86_INS_ANDNPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsANDNPSrm, X86_INS_ANDNPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsANDNPSrr, X86_INS_ANDNPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsANDPDrm, X86_INS_ANDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsANDPDrr, X86_INS_ANDPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsANDPSrm, X86_INS_ANDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsANDPSrr, X86_INS_ANDPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsMOVAPDrm, X86_INS_MOVAPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsMOVAPSrm, X86_INS_MOVAPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsORPDrm, X86_INS_ORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsORPDrr, X86_INS_ORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsORPSrm, X86_INS_ORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsORPSrr, X86_INS_ORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsVMOVAPDrm, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_FsVMOVAPSrm, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_FsXORPDrm, X86_INS_XORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsXORPDrr, X86_INS_XORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_FsXORPSrm, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_FsXORPSrr, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_GETSEC, X86_INS_GETSEC, { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_GS_PREFIX, X86_INS_GS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_HADDPDrm, X86_INS_HADDPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HADDPDrr, X86_INS_HADDPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HADDPSrm, X86_INS_HADDPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HADDPSrr, X86_INS_HADDPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HLT, X86_INS_HLT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_HSUBPDrm, X86_INS_HSUBPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HSUBPDrr, X86_INS_HSUBPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HSUBPSrm, X86_INS_HSUBPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_HSUBPSrr, X86_INS_HSUBPS, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_IDIV16m, X86_INS_IDIV, { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV16r, X86_INS_IDIV, { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV32m, X86_INS_IDIV, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV32r, X86_INS_IDIV, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV64m, X86_INS_IDIV, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV64r, X86_INS_IDIV, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV8m, X86_INS_IDIV, { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IDIV8r, X86_INS_IDIV, { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ILD_F16m, X86_INS_FILD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ILD_F32m, X86_INS_FILD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ILD_F64m, X86_INS_FILD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16m, X86_INS_IMUL, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16r, X86_INS_IMUL, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rm, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rmi, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rmi8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rr, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rri, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL16rri8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32m, X86_INS_IMUL, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32r, X86_INS_IMUL, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rm, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rmi, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rmi8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rr, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rri, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL32rri8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64m, X86_INS_IMUL, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64r, X86_INS_IMUL, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rm, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rmi32, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rmi8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rr, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rri32, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL64rri8, X86_INS_IMUL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_IMUL8m, X86_INS_IMUL, { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_IMUL8r, X86_INS_IMUL, { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_IN16, X86_INS_INSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_IN16ri, X86_INS_IN, { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_IN16rr, X86_INS_IN, { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_IN32, X86_INS_INSD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_IN32ri, X86_INS_IN, { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 },
- { X86_IN32rr, X86_INS_IN, { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 },
- { X86_IN8, X86_INS_INSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_IN8ri, X86_INS_IN, { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 },
- { X86_IN8rr, X86_INS_IN, { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 },
- { X86_INC16m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC16r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC32_16r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC32_32r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC32m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC32r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INC64_16m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INC64_16r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INC64_32m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INC64_32r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INC64m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_INC64r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_INC8m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_INC8r, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_INSERTPSrm, X86_INS_INSERTPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_INSERTPSrr, X86_INS_INSERTPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_INSERTQ, X86_INS_INSERTQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_INSERTQI, X86_INS_INSERTQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_INT, X86_INS_INT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_INT1, X86_INS_INT1, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_INT3, X86_INS_INT3, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_INTO, X86_INS_INTO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_INVD, X86_INS_INVD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_INVEPT32, X86_INS_INVEPT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INVEPT64, X86_INS_INVEPT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INVLPG, X86_INS_INVLPG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_INVLPGA32, X86_INS_INVLPGA, { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INVLPGA64, X86_INS_INVLPGA, { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INVPCID32, X86_INS_INVPCID, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INVPCID64, X86_INS_INVPCID, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_INVVPID32, X86_INS_INVVPID, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_INVVPID64, X86_INS_INVVPID, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_IRET16, X86_INS_IRET, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_IRET32, X86_INS_IRETD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_IRET64, X86_INS_IRETQ, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_ISTT_FP16m, X86_INS_FISTTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ISTT_FP32m, X86_INS_FISTTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ISTT_FP64m, X86_INS_FISTTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IST_F16m, X86_INS_FIST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IST_F32m, X86_INS_FIST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IST_FP16m, X86_INS_FISTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IST_FP32m, X86_INS_FISTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_IST_FP64m, X86_INS_FISTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_Int_CMPSDrm, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CMPSDrr, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CMPSSrm, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CMPSSrr, X86_INS_CMP, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_COMISDrm, X86_INS_COMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_COMISDrr, X86_INS_COMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_COMISSrm, X86_INS_COMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_COMISSrr, X86_INS_COMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTSD2SSrm, X86_INS_CVTSD2SS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSD2SSrr, X86_INS_CVTSD2SS, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSI2SD64rm, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSI2SD64rr, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSI2SDrm, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSI2SDrr, X86_INS_CVTSI2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSI2SS64rm, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTSI2SS64rr, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTSI2SSrm, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTSI2SSrr, X86_INS_CVTSI2SS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTSS2SDrm, X86_INS_CVTSS2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTSS2SDrr, X86_INS_CVTSS2SD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTTSD2SI64rm, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTTSD2SI64rr, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTTSD2SIrm, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTTSD2SIrr, X86_INS_CVTTSD2SI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_CVTTSS2SI64rm, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTTSS2SI64rr, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTTSS2SIrm, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_CVTTSS2SIrr, X86_INS_CVTTSS2SI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_UCOMISDrm, X86_INS_UCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_UCOMISDrr, X86_INS_UCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_Int_UCOMISSrm, X86_INS_UCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_UCOMISSrr, X86_INS_UCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_Int_VCMPSDrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCMPSDrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCMPSSrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCMPSSrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCOMISDZrm, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCOMISDZrr, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCOMISDrm, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCOMISDrr, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCOMISSZrm, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCOMISSZrr, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCOMISSrm, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCOMISSrr, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSD2SSrm, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSD2SSrr, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SD64Zrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SD64Zrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SD64rm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SD64rr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SDZrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SDZrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SDrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SDrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SS64Zrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SS64Zrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SS64rm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SS64rr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SSZrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SSZrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SSrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSI2SSrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSS2SDrm, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTSS2SDrr, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SD64Zrm, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SD64Zrr, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SS64Zrm, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SS64Zrr, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VUCOMISDZrm, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VUCOMISDZrr, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VUCOMISDrm, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VUCOMISDrr, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VUCOMISSZrm, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VUCOMISSZrr, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_Int_VUCOMISSrm, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_Int_VUCOMISSrr, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_JAE_1, X86_INS_JAE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JAE_2, X86_INS_JAE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JAE_4, X86_INS_JAE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JA_1, X86_INS_JA, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JA_2, X86_INS_JA, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JA_4, X86_INS_JA, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JBE_1, X86_INS_JBE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JBE_2, X86_INS_JBE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JBE_4, X86_INS_JBE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JB_1, X86_INS_JB, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JB_2, X86_INS_JB, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JB_4, X86_INS_JB, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JCXZ, X86_INS_JCXZ, { X86_REG_CX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 0 },
- { X86_JECXZ_32, X86_INS_JECXZ, { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 0 },
- { X86_JECXZ_64, X86_INS_JECXZ, { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 0 },
- { X86_JE_1, X86_INS_JE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JE_2, X86_INS_JE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JE_4, X86_INS_JE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JGE_1, X86_INS_JGE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JGE_2, X86_INS_JGE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JGE_4, X86_INS_JGE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JG_1, X86_INS_JG, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JG_2, X86_INS_JG, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JG_4, X86_INS_JG, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JLE_1, X86_INS_JLE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JLE_2, X86_INS_JLE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JLE_4, X86_INS_JLE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JL_1, X86_INS_JL, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JL_2, X86_INS_JL, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JL_4, X86_INS_JL, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JMP16m, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 },
- { X86_JMP16r, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 },
- { X86_JMP32m, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 },
- { X86_JMP32r, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 },
- { X86_JMP64m, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 },
- { X86_JMP64r, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 },
- { X86_JMP_1, X86_INS_JMP, { 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JMP_2, X86_INS_JMP, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JMP_4, X86_INS_JMP, { 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNE_1, X86_INS_JNE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNE_2, X86_INS_JNE, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JNE_4, X86_INS_JNE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNO_1, X86_INS_JNO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNO_2, X86_INS_JNO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JNO_4, X86_INS_JNO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNP_1, X86_INS_JNP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNP_2, X86_INS_JNP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JNP_4, X86_INS_JNP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNS_1, X86_INS_JNS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JNS_2, X86_INS_JNS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JNS_4, X86_INS_JNS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JO_1, X86_INS_JO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JO_2, X86_INS_JO, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JO_4, X86_INS_JO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JP_1, X86_INS_JP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JP_2, X86_INS_JP, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JP_4, X86_INS_JP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JRCXZ, X86_INS_JRCXZ, { X86_REG_RCX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 0 },
- { X86_JS_1, X86_INS_JS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_JS_2, X86_INS_JS, { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0 },
- { X86_JS_4, X86_INS_JS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 },
- { X86_KANDNWrr, X86_INS_KANDNW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KANDWrr, X86_INS_KANDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KMOVWkk, X86_INS_KMOVW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KMOVWkm, X86_INS_KMOVW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KMOVWkr, X86_INS_KMOVW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KMOVWmk, X86_INS_KMOVW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KMOVWrk, X86_INS_KMOVW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KNOTWrr, X86_INS_KNOTW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KORTESTWrr, X86_INS_KORTESTW, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KORWrr, X86_INS_KORW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KSHIFTLWri, X86_INS_KSHIFTLW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KSHIFTRWri, X86_INS_KSHIFTRW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KUNPCKBWrr, X86_INS_KUNPCKBW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KXNORWrr, X86_INS_KXNORW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_KXORWrr, X86_INS_KXORW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_LAHF, X86_INS_LAHF, { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0 },
- { X86_LAR16rm, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LAR16rr, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LAR32rm, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LAR32rr, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LAR64rm, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LAR64rr, X86_INS_LAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG16, X86_INS_CMPXCHG, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG16B, X86_INS_CMPXCHG16B, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG32, X86_INS_CMPXCHG, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG64, X86_INS_CMPXCHG, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG8, X86_INS_CMPXCHG, { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LCMPXCHG8B, X86_INS_CMPXCHG8B, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LDDQUrm, X86_INS_LDDQU, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_LDMXCSR, X86_INS_LDMXCSR, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_LDS16rm, X86_INS_LDS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LDS32rm, X86_INS_LDS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LD_F0, X86_INS_FLDZ, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LD_F1, X86_INS_FLD1, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LD_F32m, X86_INS_FLD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LD_F64m, X86_INS_FLD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LD_F80m, X86_INS_FLD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LD_Frr, X86_INS_FLD, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_LEA16r, X86_INS_LEA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LEA32r, X86_INS_LEA, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LEA64_32r, X86_INS_LEA, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LEA64r, X86_INS_LEA, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LEAVE, X86_INS_LEAVE, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LEAVE64, X86_INS_LEAVE, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LES16rm, X86_INS_LES, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LES32rm, X86_INS_LES, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LFENCE, X86_INS_LFENCE, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_LFS16rm, X86_INS_LFS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LFS32rm, X86_INS_LFS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LFS64rm, X86_INS_LFS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LGDT16m, X86_INS_LGDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LGDT32m, X86_INS_LGDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LGDT64m, X86_INS_LGDT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LGS16rm, X86_INS_LGS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LGS32rm, X86_INS_LGS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LGS64rm, X86_INS_LGS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LIDT16m, X86_INS_LIDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LIDT32m, X86_INS_LIDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_LIDT64m, X86_INS_LIDT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LLDT16m, X86_INS_LLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LLDT16r, X86_INS_LLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LMSW16m, X86_INS_LMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LMSW16r, X86_INS_LMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD16mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD16mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD16mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD32mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD32mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD32mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD64mi32, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD64mi8, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD64mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD8mi, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_ADD8mr, X86_INS_ADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND16mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND16mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND16mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND32mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND32mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND32mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND64mi32, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND64mi8, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND64mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND8mi, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_AND8mr, X86_INS_AND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_DEC16m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_DEC32m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_DEC64m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_DEC8m, X86_INS_DEC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_INC16m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_INC32m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_INC64m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_INC8m, X86_INS_INC, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR16mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR16mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR16mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR32mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR32mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR32mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR64mi32, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR64mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR64mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR8mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_OR8mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_PREFIX, X86_INS_LOCK, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB16mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB16mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB16mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB32mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB32mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB32mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB64mi32, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB64mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB64mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB8mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_SUB8mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR16mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR16mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR16mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR32mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR32mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR32mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR64mi32, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR64mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR64mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR8mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LOCK_XOR8mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LODSB, X86_INS_LODSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LODSL, X86_INS_LODSD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LODSQ, X86_INS_LODSQ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LODSW, X86_INS_LODSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LOOP, X86_INS_LOOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LOOPE, X86_INS_LOOPE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LOOPNE, X86_INS_LOOPNE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LRETIL, X86_INS_RETF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LRETIQ, X86_INS_RETFQ, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LRETIW, X86_INS_RETF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LRETL, X86_INS_RETF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LRETQ, X86_INS_RETFQ, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_LRETW, X86_INS_RETF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL16rm, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL16rr, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL32rm, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL32rr, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL64rm, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSL64rr, X86_INS_LSL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSS16rm, X86_INS_LSS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSS32rm, X86_INS_LSS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LSS64rm, X86_INS_LSS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LTRm, X86_INS_LTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LTRr, X86_INS_LTR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_LXADD16, X86_INS_XADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LXADD32, X86_INS_XADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LXADD64, X86_INS_XADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LXADD8, X86_INS_XADD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT16rm, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT16rr, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT32rm, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT32rr, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT64rm, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_LZCNT64rr, X86_INS_LZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MASKMOVDQU, X86_INS_MASKMOVDQU, { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MASKMOVDQU64, X86_INS_MASKMOVDQU, { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MAXCPDrm, X86_INS_MAXPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXCPDrr, X86_INS_MAXPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXCPSrm, X86_INS_MAXPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXCPSrr, X86_INS_MAXPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXCSDrm, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXCSDrr, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXCSSrm, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXCSSrr, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXPDrm, X86_INS_MAXPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXPDrr, X86_INS_MAXPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXPSrm, X86_INS_MAXPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXPSrr, X86_INS_MAXPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXSDrm, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXSDrm_Int, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXSDrr, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXSDrr_Int, X86_INS_MAXSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MAXSSrm, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXSSrm_Int, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXSSrr, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MAXSSrr_Int, X86_INS_MAXSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MFENCE, X86_INS_MFENCE, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINCPDrm, X86_INS_MINPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINCPDrr, X86_INS_MINPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINCPSrm, X86_INS_MINPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINCPSrr, X86_INS_MINPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINCSDrm, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINCSDrr, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINCSSrm, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINCSSrr, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINPDrm, X86_INS_MINPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINPDrr, X86_INS_MINPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINPSrm, X86_INS_MINPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINPSrr, X86_INS_MINPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINSDrm, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINSDrm_Int, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINSDrr, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINSDrr_Int, X86_INS_MINSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MINSSrm, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINSSrm_Int, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINSSrr, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MINSSrr_Int, X86_INS_MINSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MMX_EMMS, X86_INS_EMMS, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ, { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ, { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MMX_MOVD64from64rr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVD64grr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVD64mr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVD64rm, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVD64rr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVD64to64rr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_MOVNTQmr, X86_INS_MOVNTQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MMX_MOVQ64mr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVQ64rm, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_MOVQ64rr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PABSBrm64, X86_INS_PABSB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PABSBrr64, X86_INS_PABSB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PABSDrm64, X86_INS_PABSD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PABSDrr64, X86_INS_PABSD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PABSWrm64, X86_INS_PABSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PABSWrr64, X86_INS_PABSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDBirm, X86_INS_PADDB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDBirr, X86_INS_PADDB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDDirm, X86_INS_PADDD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDDirr, X86_INS_PADDD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDQirm, X86_INS_PADDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDQirr, X86_INS_PADDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDSBirm, X86_INS_PADDSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDSBirr, X86_INS_PADDSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDSWirm, X86_INS_PADDSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDSWirr, X86_INS_PADDSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDUSBirm, X86_INS_PADDUSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDUSBirr, X86_INS_PADDUSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDUSWirm, X86_INS_PADDUSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDUSWirr, X86_INS_PADDUSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDWirm, X86_INS_PADDW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PADDWirr, X86_INS_PADDW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PALIGNR64irm, X86_INS_PALIGNR, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PALIGNR64irr, X86_INS_PALIGNR, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PANDNirm, X86_INS_PANDN, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PANDNirr, X86_INS_PANDN, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PANDirm, X86_INS_PAND, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PANDirr, X86_INS_PAND, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PAVGBirm, X86_INS_PAVGB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PAVGBirr, X86_INS_PAVGB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PAVGWirm, X86_INS_PAVGW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PAVGWirr, X86_INS_PAVGW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PEXTRWirri, X86_INS_PEXTRW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PHADDSWrm64, X86_INS_PHADDSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHADDSWrr64, X86_INS_PHADDSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHADDWrm64, X86_INS_PHADDW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHADDWrr64, X86_INS_PHADDW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHADDrm64, X86_INS_PHADDD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHADDrr64, X86_INS_PHADDD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBDrm64, X86_INS_PHSUBD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBDrr64, X86_INS_PHSUBD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBSWrm64, X86_INS_PHSUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBSWrr64, X86_INS_PHSUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBWrm64, X86_INS_PHSUBW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PHSUBWrr64, X86_INS_PHSUBW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PINSRWirmi, X86_INS_PINSRW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PINSRWirri, X86_INS_PINSRW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMADDUBSWrm64, X86_INS_PMADDUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PMADDUBSWrr64, X86_INS_PMADDUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PMADDWDirm, X86_INS_PMADDWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMADDWDirr, X86_INS_PMADDWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMAXSWirm, X86_INS_PMAXSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMAXSWirr, X86_INS_PMAXSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMAXUBirm, X86_INS_PMAXUB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMAXUBirr, X86_INS_PMAXUB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMINSWirm, X86_INS_PMINSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMINSWirr, X86_INS_PMINSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMINUBirm, X86_INS_PMINUB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMINUBirr, X86_INS_PMINUB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULHRSWrm64, X86_INS_PMULHRSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PMULHRSWrr64, X86_INS_PMULHRSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PMULHUWirm, X86_INS_PMULHUW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULHUWirr, X86_INS_PMULHUW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULHWirm, X86_INS_PMULHW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULHWirr, X86_INS_PMULHW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULLWirm, X86_INS_PMULLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULLWirr, X86_INS_PMULLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULUDQirm, X86_INS_PMULUDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PMULUDQirr, X86_INS_PMULUDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PORirm, X86_INS_POR, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PORirr, X86_INS_POR, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSADBWirm, X86_INS_PSADBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSADBWirr, X86_INS_PSADBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSHUFBrm64, X86_INS_PSHUFB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSHUFBrr64, X86_INS_PSHUFB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSHUFWmi, X86_INS_PSHUFW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSHUFWri, X86_INS_PSHUFW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSIGNBrm64, X86_INS_PSIGNB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSIGNBrr64, X86_INS_PSIGNB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSIGNDrm64, X86_INS_PSIGND, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSIGNDrr64, X86_INS_PSIGND, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSIGNWrm64, X86_INS_PSIGNW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSIGNWrr64, X86_INS_PSIGNW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_MMX_PSLLDri, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLDrm, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLDrr, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLQri, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLQrm, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLQrr, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLWri, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLWrm, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSLLWrr, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRADri, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRADrm, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRADrr, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRAWri, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRAWrm, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRAWrr, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLDri, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLDrm, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLDrr, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLQri, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLQrm, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLQrr, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLWri, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLWrm, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSRLWrr, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBBirm, X86_INS_PSUBB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBBirr, X86_INS_PSUBB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBDirm, X86_INS_PSUBD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBDirr, X86_INS_PSUBD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBQirm, X86_INS_PSUBQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBQirr, X86_INS_PSUBQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBSBirm, X86_INS_PSUBSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBSBirr, X86_INS_PSUBSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBSWirm, X86_INS_PSUBSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBSWirr, X86_INS_PSUBSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBWirm, X86_INS_PSUBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PSUBWirr, X86_INS_PSUBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PXORirm, X86_INS_PXOR, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MMX_PXORirr, X86_INS_PXOR, { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 },
- { X86_MONITORrrr, X86_INS_MONITOR, { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MONTMUL, X86_INS_MONTMUL, { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0 },
- { X86_MOV16ao16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV16ao16_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV16mi, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16mr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16ms, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16o16a, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV16o16a_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV16ri, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16rm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16rr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16rr_REV, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16rs, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16sm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV16sr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32ao32, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV32ao32_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV32cr, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MOV32dr, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MOV32mi, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32mr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32ms, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32o32a, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV32o32a_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV32rc, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MOV32rd, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_MOV32ri, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32rm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32rr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32rr_REV, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32rs, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32sm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV32sr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64ao16, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64ao32, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64ao64, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64ao8, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64cr, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64dr, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64mi32, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64mr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64ms, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64o16a, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64o32a, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64o64a, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64o8a, X86_INS_MOVABS, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64rc, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64rd, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_MOV64ri, X86_INS_MOVABS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64ri32, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64rm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64rr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64rr_REV, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64rs, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64sm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64sr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV64toPQIrr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOV64toSDrm, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOV64toSDrr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOV8ao8, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV8ao8_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV8mi, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV8mr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV8o8a, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0 },
- { X86_MOV8o8a_16, X86_INS_MOV, { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0 },
- { X86_MOV8ri, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV8rm, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV8rr, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOV8rr_REV, X86_INS_MOV, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVAPDmr, X86_INS_MOVAPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVAPDrm, X86_INS_MOVAPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVAPDrr, X86_INS_MOVAPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVAPDrr_REV, X86_INS_MOVAPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVAPSmr, X86_INS_MOVAPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVAPSrm, X86_INS_MOVAPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVAPSrr, X86_INS_MOVAPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVAPSrr_REV, X86_INS_MOVAPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVBE16mr, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVBE16rm, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVBE32mr, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVBE32rm, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVBE64mr, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVBE64rm, X86_INS_MOVBE, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVDDUPrm, X86_INS_MOVDDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVDDUPrr, X86_INS_MOVDDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVDI2PDIrm, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDI2PDIrr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDI2SSrm, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDI2SSrr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQAmr, X86_INS_MOVDQA, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQArm, X86_INS_MOVDQA, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQArr, X86_INS_MOVDQA, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQArr_REV, X86_INS_MOVDQA, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQUmr, X86_INS_MOVDQU, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQUrm, X86_INS_MOVDQU, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQUrr, X86_INS_MOVDQU, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVDQUrr_REV, X86_INS_MOVDQU, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVHLPSrr, X86_INS_MOVHLPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVHPDmr, X86_INS_MOVHPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVHPDrm, X86_INS_MOVHPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVHPSmr, X86_INS_MOVHPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVHPSrm, X86_INS_MOVHPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVLHPSrr, X86_INS_MOVLHPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVLPDmr, X86_INS_MOVLPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVLPDrm, X86_INS_MOVLPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVLPSmr, X86_INS_MOVLPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVLPSrm, X86_INS_MOVLPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVMSKPDrr, X86_INS_MOVMSKPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVMSKPSrr, X86_INS_MOVMSKPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVNTDQArm, X86_INS_MOVNTDQA, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_MOVNTDQmr, X86_INS_MOVNTDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVNTI_64mr, X86_INS_MOVNTI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVNTImr, X86_INS_MOVNTI, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVNTPDmr, X86_INS_MOVNTPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVNTPSmr, X86_INS_MOVNTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVNTSD, X86_INS_MOVNTSD, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_MOVNTSS, X86_INS_MOVNTSS, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
- { X86_MOVPDI2DImr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVPDI2DIrr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVPQI2QImr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVPQI2QIrr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVPQIto64rr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVQI2PQIrm, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSB, X86_INS_MOVSB, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 },
- { X86_MOVSDmr, X86_INS_MOVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSDrm, X86_INS_MOVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSDrr, X86_INS_MOVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSDrr_REV, X86_INS_MOVSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSDto64mr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSDto64rr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSHDUPrm, X86_INS_MOVSHDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVSHDUPrr, X86_INS_MOVSHDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVSL, X86_INS_MOVSD, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 },
- { X86_MOVSLDUPrm, X86_INS_MOVSLDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVSLDUPrr, X86_INS_MOVSLDUP, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_MOVSQ, X86_INS_MOVSQ, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 },
- { X86_MOVSS2DImr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSS2DIrr, X86_INS_MOVD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVSSmr, X86_INS_MOVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVSSrm, X86_INS_MOVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVSSrr, X86_INS_MOVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVSSrr_REV, X86_INS_MOVSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVSW, X86_INS_MOVSW, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 },
- { X86_MOVSX16rm8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX16rr8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX32rm16, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX32rm8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX32rr16, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX32rr8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rm16, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rm32, X86_INS_MOVSXD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rm8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rr16, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rr32, X86_INS_MOVSXD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVSX64rr8, X86_INS_MOVSX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVUPDmr, X86_INS_MOVUPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVUPDrm, X86_INS_MOVUPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVUPDrr, X86_INS_MOVUPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVUPDrr_REV, X86_INS_MOVUPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVUPSmr, X86_INS_MOVUPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVUPSrm, X86_INS_MOVUPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVUPSrr, X86_INS_MOVUPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVUPSrr_REV, X86_INS_MOVUPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MOVZPQILo2PQIrm, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVZPQILo2PQIrr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVZQI2PQIrm, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVZQI2PQIrr, X86_INS_MOVQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MOVZX16rm8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX16rr8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32_NOREXrm8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32_NOREXrr8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32rm16, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32rm8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32rr16, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX32rr8, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX64rm16_Q, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX64rm8_Q, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX64rr16_Q, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MOVZX64rr8_Q, X86_INS_MOVZX, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MPSADBWrmi, X86_INS_MPSADBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_MPSADBWrri, X86_INS_MPSADBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_MUL16m, X86_INS_MUL, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL16r, X86_INS_MUL, { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL32m, X86_INS_MUL, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL32r, X86_INS_MUL, { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL64m, X86_INS_MUL, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL64r, X86_INS_MUL, { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_MUL8m, X86_INS_MUL, { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_MUL8r, X86_INS_MUL, { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 },
- { X86_MULPDrm, X86_INS_MULPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULPDrr, X86_INS_MULPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULPSrm, X86_INS_MULPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULPSrr, X86_INS_MULPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULSDrm, X86_INS_MULSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULSDrm_Int, X86_INS_MULSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULSDrr, X86_INS_MULSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULSDrr_Int, X86_INS_MULSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_MULSSrm, X86_INS_MULSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULSSrm_Int, X86_INS_MULSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULSSrr, X86_INS_MULSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULSSrr_Int, X86_INS_MULSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_MULX32rm, X86_INS_MULX, { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_MULX32rr, X86_INS_MULX, { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_MULX64rm, X86_INS_MULX, { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_MULX64rr, X86_INS_MULX, { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_MUL_F32m, X86_INS_FMUL, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_MUL_F64m, X86_INS_FMUL, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_MUL_FI16m, X86_INS_FIMUL, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_MUL_FI32m, X86_INS_FIMUL, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_MUL_FPrST0, X86_INS_FMULP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MUL_FST0r, X86_INS_FMUL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MUL_FrST0, X86_INS_FMUL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_MWAITrr, X86_INS_MWAIT, { X86_REG_ECX, X86_REG_EAX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
- { X86_NEG16m, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG16r, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG32m, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG32r, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG64m, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG64r, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG8m, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NEG8r, X86_INS_NEG, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_NOOP, X86_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOOPL, X86_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOOPW, X86_INS_NOP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT16m, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT16r, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT32m, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT32r, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT64m, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT64r, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT8m, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_NOT8r, X86_INS_NOT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OR16i16, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16ri, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16ri8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16rm, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16rr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR16rr_REV, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32i32, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32mrLocked, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_OR32ri, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32ri8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32rm, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32rr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR32rr_REV, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64i32, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64mi32, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64mi8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64ri32, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64ri8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64rm, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64rr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR64rr_REV, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8i8, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8mi, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8mr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8ri, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8rm, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8rr, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_OR8rr_REV, X86_INS_OR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ORPDrm, X86_INS_ORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ORPDrr, X86_INS_ORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_ORPSrm, X86_INS_ORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_ORPSrr, X86_INS_ORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_OUT16ir, X86_INS_OUT, { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUT16rr, X86_INS_OUT, { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUT32ir, X86_INS_OUT, { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUT32rr, X86_INS_OUT, { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUT8ir, X86_INS_OUT, { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUT8rr, X86_INS_OUT, { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUTSB, X86_INS_OUTSB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUTSL, X86_INS_OUTSD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_OUTSW, X86_INS_OUTSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_PABSBrm128, X86_INS_PABSB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PABSBrr128, X86_INS_PABSB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PABSDrm128, X86_INS_PABSD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PABSDrr128, X86_INS_PABSD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PABSWrm128, X86_INS_PABSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PABSWrr128, X86_INS_PABSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PACKSSDWrm, X86_INS_PACKSSDW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PACKSSDWrr, X86_INS_PACKSSDW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PACKSSWBrm, X86_INS_PACKSSWB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PACKSSWBrr, X86_INS_PACKSSWB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PACKUSDWrm, X86_INS_PACKUSDW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PACKUSDWrr, X86_INS_PACKUSDW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PACKUSWBrm, X86_INS_PACKUSWB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PACKUSWBrr, X86_INS_PACKUSWB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDBrm, X86_INS_PADDB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDBrr, X86_INS_PADDB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDDrm, X86_INS_PADDD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDDrr, X86_INS_PADDD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDQrm, X86_INS_PADDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDQrr, X86_INS_PADDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDSBrm, X86_INS_PADDSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDSBrr, X86_INS_PADDSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDSWrm, X86_INS_PADDSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDSWrr, X86_INS_PADDSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDUSBrm, X86_INS_PADDUSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDUSBrr, X86_INS_PADDUSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDUSWrm, X86_INS_PADDUSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDUSWrr, X86_INS_PADDUSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDWrm, X86_INS_PADDW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PADDWrr, X86_INS_PADDW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PALIGNR128rm, X86_INS_PALIGNR, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PALIGNR128rr, X86_INS_PALIGNR, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PANDNrm, X86_INS_PANDN, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PANDNrr, X86_INS_PANDN, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PANDrm, X86_INS_PAND, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PANDrr, X86_INS_PAND, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PAUSE, X86_INS_PAUSE, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PAVGBrm, X86_INS_PAVGB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PAVGBrr, X86_INS_PAVGB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PAVGUSBrm, X86_INS_PAVGUSB, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PAVGUSBrr, X86_INS_PAVGUSB, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PAVGWrm, X86_INS_PAVGW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PAVGWrr, X86_INS_PAVGW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PBLENDVBrm0, X86_INS_PBLENDVB, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PBLENDVBrr0, X86_INS_PBLENDVB, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PBLENDWrmi, X86_INS_PBLENDW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PBLENDWrri, X86_INS_PBLENDW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PCLMULQDQrm, X86_INS_PCLMULQDQ, { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 },
- { X86_PCLMULQDQrr, X86_INS_PCLMULQDQ, { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 },
- { X86_PCMPEQBrm, X86_INS_PCMPEQB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPEQBrr, X86_INS_PCMPEQB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPEQDrm, X86_INS_PCMPEQD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPEQDrr, X86_INS_PCMPEQD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPEQQrm, X86_INS_PCMPEQQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PCMPEQQrr, X86_INS_PCMPEQQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PCMPEQWrm, X86_INS_PCMPEQW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPEQWrr, X86_INS_PCMPEQW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPESTRIrm, X86_INS_PCMPESTRI, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPESTRIrr, X86_INS_PCMPESTRI, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPESTRM128rm, X86_INS_PCMPESTRM, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPESTRM128rr, X86_INS_PCMPESTRM, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPGTBrm, X86_INS_PCMPGTB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPGTBrr, X86_INS_PCMPGTB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPGTDrm, X86_INS_PCMPGTD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPGTDrr, X86_INS_PCMPGTD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPGTQrm, X86_INS_PCMPGTQ, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPGTQrr, X86_INS_PCMPGTQ, { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPGTWrm, X86_INS_PCMPGTW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPGTWrr, X86_INS_PCMPGTW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PCMPISTRIrm, X86_INS_PCMPISTRI, { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPISTRIrr, X86_INS_PCMPISTRI, { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPISTRM128rm, X86_INS_PCMPISTRM, { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PCMPISTRM128rr, X86_INS_PCMPISTRM, { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 },
- { X86_PDEP32rm, X86_INS_PDEP, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PDEP32rr, X86_INS_PDEP, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PDEP64rm, X86_INS_PDEP, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PDEP64rr, X86_INS_PDEP, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PEXT32rm, X86_INS_PEXT, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PEXT32rr, X86_INS_PEXT, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PEXT64rm, X86_INS_PEXT, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PEXT64rr, X86_INS_PEXT, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_PEXTRBmr, X86_INS_PEXTRB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRBrr, X86_INS_PEXTRB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRDmr, X86_INS_PEXTRD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRDrr, X86_INS_PEXTRD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRQmr, X86_INS_PEXTRQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRQrr, X86_INS_PEXTRQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRWmr, X86_INS_PEXTRW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PEXTRWri, X86_INS_PEXTRW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PEXTRWrr_REV, X86_INS_PEXTRW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PF2IDrm, X86_INS_PF2ID, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PF2IDrr, X86_INS_PF2ID, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PF2IWrm, X86_INS_PF2IW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PF2IWrr, X86_INS_PF2IW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFACCrm, X86_INS_PFACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFACCrr, X86_INS_PFACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFADDrm, X86_INS_PFADD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFADDrr, X86_INS_PFADD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPEQrm, X86_INS_PFCMPEQ, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPEQrr, X86_INS_PFCMPEQ, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPGErm, X86_INS_PFCMPGE, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPGErr, X86_INS_PFCMPGE, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPGTrm, X86_INS_PFCMPGT, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFCMPGTrr, X86_INS_PFCMPGT, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMAXrm, X86_INS_PFMAX, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMAXrr, X86_INS_PFMAX, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMINrm, X86_INS_PFMIN, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMINrr, X86_INS_PFMIN, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMULrm, X86_INS_PFMUL, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFMULrr, X86_INS_PFMUL, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFNACCrm, X86_INS_PFNACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFNACCrr, X86_INS_PFNACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFPNACCrm, X86_INS_PFPNACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFPNACCrr, X86_INS_PFPNACC, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPIT1rm, X86_INS_PFRCPIT1, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPIT1rr, X86_INS_PFRCPIT1, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPIT2rm, X86_INS_PFRCPIT2, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPIT2rr, X86_INS_PFRCPIT2, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPrm, X86_INS_PFRCP, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRCPrr, X86_INS_PFRCP, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRSQIT1rm, X86_INS_PFRSQIT1, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRSQIT1rr, X86_INS_PFRSQIT1, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRSQRTrm, X86_INS_PFRSQRT, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFRSQRTrr, X86_INS_PFRSQRT, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFSUBRrm, X86_INS_PFSUBR, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFSUBRrr, X86_INS_PFSUBR, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFSUBrm, X86_INS_PFSUB, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PFSUBrr, X86_INS_PFSUB, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PHADDDrm, X86_INS_PHADDD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHADDDrr, X86_INS_PHADDD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHADDSWrm128, X86_INS_PHADDSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHADDSWrr128, X86_INS_PHADDSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHADDWrm, X86_INS_PHADDW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHADDWrr, X86_INS_PHADDW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHMINPOSUWrm128, X86_INS_PHMINPOSUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PHMINPOSUWrr128, X86_INS_PHMINPOSUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PHSUBDrm, X86_INS_PHSUBD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHSUBDrr, X86_INS_PHSUBD, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHSUBSWrm128, X86_INS_PHSUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHSUBSWrr128, X86_INS_PHSUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHSUBWrm, X86_INS_PHSUBW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PHSUBWrr, X86_INS_PHSUBW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PI2FDrm, X86_INS_PI2FD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PI2FDrr, X86_INS_PI2FD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PI2FWrm, X86_INS_PI2FW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PI2FWrr, X86_INS_PI2FW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PINSRBrm, X86_INS_PINSRB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRBrr, X86_INS_PINSRB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRDrm, X86_INS_PINSRD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRDrr, X86_INS_PINSRD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRQrm, X86_INS_PINSRQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRQrr, X86_INS_PINSRQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PINSRWrmi, X86_INS_PINSRW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PINSRWrri, X86_INS_PINSRW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMADDUBSWrm128, X86_INS_PMADDUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PMADDUBSWrr128, X86_INS_PMADDUBSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PMADDWDrm, X86_INS_PMADDWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMADDWDrr, X86_INS_PMADDWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMAXSBrm, X86_INS_PMAXSB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXSBrr, X86_INS_PMAXSB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXSDrm, X86_INS_PMAXSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXSDrr, X86_INS_PMAXSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXSWrm, X86_INS_PMAXSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMAXSWrr, X86_INS_PMAXSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMAXUBrm, X86_INS_PMAXUB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMAXUBrr, X86_INS_PMAXUB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMAXUDrm, X86_INS_PMAXUD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXUDrr, X86_INS_PMAXUD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXUWrm, X86_INS_PMAXUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMAXUWrr, X86_INS_PMAXUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINSBrm, X86_INS_PMINSB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINSBrr, X86_INS_PMINSB, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINSDrm, X86_INS_PMINSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINSDrr, X86_INS_PMINSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINSWrm, X86_INS_PMINSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMINSWrr, X86_INS_PMINSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMINUBrm, X86_INS_PMINUB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMINUBrr, X86_INS_PMINUB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMINUDrm, X86_INS_PMINUD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINUDrr, X86_INS_PMINUD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINUWrm, X86_INS_PMINUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMINUWrr, X86_INS_PMINUW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVMSKBrr, X86_INS_PMOVMSKB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMOVSXBDrm, X86_INS_PMOVSXBD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXBDrr, X86_INS_PMOVSXBD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXBQrm, X86_INS_PMOVSXBQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXBQrr, X86_INS_PMOVSXBQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXBWrm, X86_INS_PMOVSXBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXBWrr, X86_INS_PMOVSXBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXDQrm, X86_INS_PMOVSXDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXDQrr, X86_INS_PMOVSXDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXWDrm, X86_INS_PMOVSXWD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXWDrr, X86_INS_PMOVSXWD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXWQrm, X86_INS_PMOVSXWQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVSXWQrr, X86_INS_PMOVSXWQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBDrm, X86_INS_PMOVZXBD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBDrr, X86_INS_PMOVZXBD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBQrm, X86_INS_PMOVZXBQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBQrr, X86_INS_PMOVZXBQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBWrm, X86_INS_PMOVZXBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXBWrr, X86_INS_PMOVZXBW, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXDQrm, X86_INS_PMOVZXDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXDQrr, X86_INS_PMOVZXDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXWDrm, X86_INS_PMOVZXWD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXWDrr, X86_INS_PMOVZXWD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXWQrm, X86_INS_PMOVZXWQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMOVZXWQrr, X86_INS_PMOVZXWQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMULDQrm, X86_INS_PMULDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMULDQrr, X86_INS_PMULDQ, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMULHRSWrm128, X86_INS_PMULHRSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PMULHRSWrr128, X86_INS_PMULHRSW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PMULHRWrm, X86_INS_PMULHRW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PMULHRWrr, X86_INS_PMULHRW, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PMULHUWrm, X86_INS_PMULHUW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULHUWrr, X86_INS_PMULHUW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULHWrm, X86_INS_PMULHW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULHWrr, X86_INS_PMULHW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULLDrm, X86_INS_PMULLD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMULLDrr, X86_INS_PMULLD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PMULLWrm, X86_INS_PMULLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULLWrr, X86_INS_PMULLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULUDQrm, X86_INS_PMULUDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PMULUDQrr, X86_INS_PMULUDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_POP16r, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_POP16rmm, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_POP16rmr, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_POP32r, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POP32rmm, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POP32rmr, X86_INS_POP, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POP64r, X86_INS_POP, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POP64rmm, X86_INS_POP, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POP64rmr, X86_INS_POP, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POPA16, X86_INS_POPAW, { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPA32, X86_INS_POPAL, { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPCNT16rm, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPCNT16rr, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPCNT32rm, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPCNT32rr, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPCNT64rm, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPCNT64rr, X86_INS_POPCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_POPDS16, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPDS32, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPES16, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPES32, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPF16, X86_INS_POPF, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_POPF32, X86_INS_POPFD, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPF64, X86_INS_POPFQ, { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POPFS16, X86_INS_POP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_POPFS32, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPFS64, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POPGS16, X86_INS_POP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_POPGS32, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPGS64, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_POPSS16, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_POPSS32, X86_INS_POP, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PORrm, X86_INS_POR, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PORrr, X86_INS_POR, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PREFETCH, X86_INS_PREFETCH, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PREFETCHNTA, X86_INS_PREFETCHNTA, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_PREFETCHT0, X86_INS_PREFETCHT0, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_PREFETCHT1, X86_INS_PREFETCHT1, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_PREFETCHT2, X86_INS_PREFETCHT2, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_PREFETCHW, X86_INS_PREFETCHW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_PSADBWrm, X86_INS_PSADBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSADBWrr, X86_INS_PSADBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFBrm, X86_INS_PSHUFB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSHUFBrr, X86_INS_PSHUFB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSHUFDmi, X86_INS_PSHUFD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFDri, X86_INS_PSHUFD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFHWmi, X86_INS_PSHUFHW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFHWri, X86_INS_PSHUFHW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFLWmi, X86_INS_PSHUFLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSHUFLWri, X86_INS_PSHUFLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSIGNBrm, X86_INS_PSIGNB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSIGNBrr, X86_INS_PSIGNB, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSIGNDrm, X86_INS_PSIGND, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSIGNDrr, X86_INS_PSIGND, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSIGNWrm, X86_INS_PSIGNW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSIGNWrr, X86_INS_PSIGNW, { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 },
- { X86_PSLLDQri, X86_INS_PSLLDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLDri, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLDrm, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLDrr, X86_INS_PSLLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLQri, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLQrm, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLQrr, X86_INS_PSLLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLWri, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLWrm, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSLLWrr, X86_INS_PSLLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRADri, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRADrm, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRADrr, X86_INS_PSRAD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRAWri, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRAWrm, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRAWrr, X86_INS_PSRAW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLDQri, X86_INS_PSRLDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLDri, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLDrm, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLDrr, X86_INS_PSRLD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLQri, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLQrm, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLQrr, X86_INS_PSRLQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLWri, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLWrm, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSRLWrr, X86_INS_PSRLW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBBrm, X86_INS_PSUBB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBBrr, X86_INS_PSUBB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBDrm, X86_INS_PSUBD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBDrr, X86_INS_PSUBD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBQrm, X86_INS_PSUBQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBQrr, X86_INS_PSUBQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBSBrm, X86_INS_PSUBSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBSBrr, X86_INS_PSUBSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBSWrm, X86_INS_PSUBSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBSWrr, X86_INS_PSUBSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBUSBrm, X86_INS_PSUBUSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBUSBrr, X86_INS_PSUBUSB, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBUSWrm, X86_INS_PSUBUSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBUSWrr, X86_INS_PSUBUSW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBWrm, X86_INS_PSUBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSUBWrr, X86_INS_PSUBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PSWAPDrm, X86_INS_PSWAPD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PSWAPDrr, X86_INS_PSWAPD, { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 },
- { X86_PTESTrm, X86_INS_PTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PTESTrr, X86_INS_PTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PUSH16i8, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSH16r, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_PUSH16rmm, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_PUSH16rmr, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_PUSH32i8, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSH32r, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSH32rmm, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSH32rmr, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSH64i16, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSH64i32, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSH64i8, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSH64r, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSH64rmm, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSH64rmr, X86_INS_PUSH, { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSHA16, X86_INS_PUSHAW, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHA32, X86_INS_PUSHAL, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHCS16, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHCS32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHDS16, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHDS32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHES16, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHES32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHF16, X86_INS_PUSHF, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 },
- { X86_PUSHF32, X86_INS_PUSHFD, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHF64, X86_INS_PUSHFQ, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSHFS16, X86_INS_PUSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_PUSHFS32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHFS64, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSHGS16, X86_INS_PUSH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_PUSHGS32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHGS64, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_PUSHSS16, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHSS32, X86_INS_PUSH, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHi16, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PUSHi32, X86_INS_PUSH, { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_PXORrm, X86_INS_PXOR, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_PXORrr, X86_INS_PXOR, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_RCL16m1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL16mCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL16mi, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL16r1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL16rCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL16ri, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32m1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32mCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32mi, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32r1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32rCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL32ri, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64m1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64mCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64mi, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64r1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64rCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL64ri, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8m1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8mCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8mi, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8r1, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8rCL, X86_INS_RCL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCL8ri, X86_INS_RCL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCPPSm, X86_INS_RCPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPPSm_Int, X86_INS_RCPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPPSr, X86_INS_RCPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPPSr_Int, X86_INS_RCPPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPSSm, X86_INS_RCPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPSSm_Int, X86_INS_RCPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPSSr, X86_INS_RCPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCPSSr_Int, X86_INS_RCPSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RCR16m1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR16mCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR16mi, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR16r1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR16rCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR16ri, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32m1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32mCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32mi, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32r1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32rCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR32ri, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64m1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64mCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64mi, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64r1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64rCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR64ri, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8m1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8mCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8mi, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8r1, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8rCL, X86_INS_RCR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RCR8ri, X86_INS_RCR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDFSBASE, X86_INS_RDFSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RDFSBASE64, X86_INS_RDFSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RDGSBASE, X86_INS_RDGSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RDGSBASE64, X86_INS_RDGSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RDMSR, X86_INS_RDMSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_RDPMC, X86_INS_RDPMC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_RDRAND16r, X86_INS_RDRAND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDRAND32r, X86_INS_RDRAND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDRAND64r, X86_INS_RDRAND, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDSEED16r, X86_INS_RDSEED, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDSEED32r, X86_INS_RDSEED, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDSEED64r, X86_INS_RDSEED, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RDTSC, X86_INS_RDTSC, { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 },
- { X86_RDTSCP, X86_INS_RDTSCP, { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { 0 }, 0, 0 },
- { X86_REPNE_PREFIX, X86_INS_REPNE, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_REG_ECX, 0 }, { 0 }, 0, 0 },
- { X86_REP_MOVSB_32, X86_INS_REP, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_MOVSB_64, X86_INS_REP, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_MOVSD_32, X86_INS_REP, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_MOVSD_64, X86_INS_REP, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_MOVSQ_64, X86_INS_REP, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_MOVSW_32, X86_INS_REP, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_MOVSW_64, X86_INS_REP, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_PREFIX, X86_INS_REP, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_REG_ECX, 0 }, { 0 }, 0, 0 },
- { X86_REP_STOSB_32, X86_INS_REP, { X86_REG_AL, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_STOSB_64, X86_INS_REP, { X86_REG_AL, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_STOSD_32, X86_INS_REP, { X86_REG_EAX, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_STOSD_64, X86_INS_REP, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_STOSQ_64, X86_INS_REP, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_REP_STOSW_32, X86_INS_REP, { X86_REG_AX, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_REP_STOSW_64, X86_INS_REP, { X86_REG_AX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RETIL, X86_INS_RET, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_RETIQ, X86_INS_RET, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RETIW, X86_INS_RET, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_RETL, X86_INS_RET, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_RETQ, X86_INS_RET, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_RETW, X86_INS_RET, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_REX64_PREFIX, X86_INS_REX64, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_ROL16m1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL16mCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL16mi, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL16r1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL16rCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL16ri, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32m1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32mCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32mi, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32r1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32rCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL32ri, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64m1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64mCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64mi, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64r1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64rCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL64ri, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8m1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8mCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8mi, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8r1, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8rCL, X86_INS_ROL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROL8ri, X86_INS_ROL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16m1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16mCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16mi, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16r1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16rCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR16ri, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32m1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32mCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32mi, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32r1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32rCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR32ri, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64m1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64mCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64mi, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64r1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64rCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR64ri, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8m1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8mCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8mi, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8r1, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8rCL, X86_INS_ROR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_ROR8ri, X86_INS_ROR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_RORX32mi, X86_INS_RORX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_RORX32ri, X86_INS_RORX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_RORX64mi, X86_INS_RORX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_RORX64ri, X86_INS_RORX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_ROUNDPDm, X86_INS_ROUNDPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDPDr, X86_INS_ROUNDPD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDPSm, X86_INS_ROUNDPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDPSr, X86_INS_ROUNDPS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSDm, X86_INS_ROUNDSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSDr, X86_INS_ROUNDSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSDr_Int, X86_INS_ROUNDSD, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSSm, X86_INS_ROUNDSS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSSr, X86_INS_ROUNDSS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_ROUNDSSr_Int, X86_INS_ROUNDSS, { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 },
- { X86_RSM, X86_INS_RSM, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_RSQRTPSm, X86_INS_RSQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTPSm_Int, X86_INS_RSQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTPSr, X86_INS_RSQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTPSr_Int, X86_INS_RSQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTSSm, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTSSm_Int, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTSSr, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_RSQRTSSr_Int, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SAHF, X86_INS_SAHF, { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SALC, X86_INS_SALC, { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 },
- { X86_SAR16m1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR16mCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR16mi, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR16r1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR16rCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR16ri, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32m1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32mCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32mi, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32r1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32rCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR32ri, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64m1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64mCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64mi, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64r1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64rCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR64ri, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8m1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8mCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8mi, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8r1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8rCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SAR8ri, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SARX32rm, X86_INS_SARX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SARX32rr, X86_INS_SARX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SARX64rm, X86_INS_SARX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SARX64rr, X86_INS_SARX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SBB16i16, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16mi, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16mi8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16mr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16ri, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16ri8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16rm, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16rr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB16rr_REV, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32i32, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32mi, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32mi8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32mr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32ri, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32ri8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32rm, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32rr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB32rr_REV, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64i32, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64mi32, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64mi8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64mr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64ri32, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64ri8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64rm, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64rr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB64rr_REV, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8i8, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8mi, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8mr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8ri, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8rm, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8rr, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SBB8rr_REV, X86_INS_SBB, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SCAS16, X86_INS_SCASW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SCAS32, X86_INS_SCASD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SCAS64, X86_INS_SCASQ, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SCAS8, X86_INS_SCASB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETAEm, X86_INS_SETAE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETAEr, X86_INS_SETAE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETAm, X86_INS_SETA, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETAr, X86_INS_SETA, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETBEm, X86_INS_SETBE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETBEr, X86_INS_SETBE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETBm, X86_INS_SETB, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETBr, X86_INS_SETB, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETEm, X86_INS_SETE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETEr, X86_INS_SETE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETGEm, X86_INS_SETGE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETGEr, X86_INS_SETGE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETGm, X86_INS_SETG, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETGr, X86_INS_SETG, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETLEm, X86_INS_SETLE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETLEr, X86_INS_SETLE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETLm, X86_INS_SETL, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETLr, X86_INS_SETL, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNEm, X86_INS_SETNE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNEr, X86_INS_SETNE, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNOm, X86_INS_SETNO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNOr, X86_INS_SETNO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNPm, X86_INS_SETNP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNPr, X86_INS_SETNP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNSm, X86_INS_SETNS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETNSr, X86_INS_SETNS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETOm, X86_INS_SETO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETOr, X86_INS_SETO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETPm, X86_INS_SETP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETPr, X86_INS_SETP, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETSm, X86_INS_SETS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SETSr, X86_INS_SETS, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SFENCE, X86_INS_SFENCE, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SGDT16m, X86_INS_SGDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_SGDT32m, X86_INS_SGDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_SGDT64m, X86_INS_SGDT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_SHA1MSG1rm, X86_INS_SHA1MSG1, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1MSG1rr, X86_INS_SHA1MSG1, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1MSG2rm, X86_INS_SHA1MSG2, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1MSG2rr, X86_INS_SHA1MSG2, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1NEXTErm, X86_INS_SHA1NEXTE, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1NEXTErr, X86_INS_SHA1NEXTE, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256MSG1rm, X86_INS_SHA256MSG1, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256MSG1rr, X86_INS_SHA256MSG1, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256MSG2rm, X86_INS_SHA256MSG2, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256MSG2rr, X86_INS_SHA256MSG2, { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2, { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 },
- { X86_SHL16m1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL16mCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL16mi, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL16r1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL16rCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL16ri, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32m1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32mCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32mi, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32r1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32rCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL32ri, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64m1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64mCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64mi, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64r1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64rCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL64ri, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8m1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8mCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8mi, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8r1, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8rCL, X86_INS_SHL, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHL8ri, X86_INS_SHL, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD16mrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD16mri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD16rrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD16rri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD32mrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD32mri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD32rrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD32rri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD64mrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD64mri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD64rrCL, X86_INS_SHLD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLD64rri8, X86_INS_SHLD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHLX32rm, X86_INS_SHLX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHLX32rr, X86_INS_SHLX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHLX64rm, X86_INS_SHLX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHLX64rr, X86_INS_SHLX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHR16m1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR16mCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR16mi, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR16r1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR16rCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR16ri, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32m1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32mCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32mi, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32r1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32rCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR32ri, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64m1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64mCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64mi, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64r1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64rCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR64ri, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8m1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8mCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8mi, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8r1, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8rCL, X86_INS_SHR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHR8ri, X86_INS_SHR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD16mrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD16mri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD16rrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD16rri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD32mrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD32mri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD32rrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD32rri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD64mrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD64mri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD64rrCL, X86_INS_SHRD, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRD64rri8, X86_INS_SHRD, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SHRX32rm, X86_INS_SHRX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHRX32rr, X86_INS_SHRX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHRX64rm, X86_INS_SHRX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHRX64rr, X86_INS_SHRX, { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 },
- { X86_SHUFPDrmi, X86_INS_SHUFPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SHUFPDrri, X86_INS_SHUFPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SHUFPSrmi, X86_INS_SHUFPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SHUFPSrri, X86_INS_SHUFPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SIDT16m, X86_INS_SIDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_SIDT32m, X86_INS_SIDT, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_SIDT64m, X86_INS_SIDT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_SIN_F, X86_INS_FSIN, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SKINIT, X86_INS_SKINIT, { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SLDT16m, X86_INS_SLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SLDT16r, X86_INS_SLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SLDT32r, X86_INS_SLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SLDT64m, X86_INS_SLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SLDT64r, X86_INS_SLDT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SMSW16m, X86_INS_SMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SMSW16r, X86_INS_SMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SMSW32r, X86_INS_SMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SMSW64r, X86_INS_SMSW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SQRTPDm, X86_INS_SQRTPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTPDr, X86_INS_SQRTPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTPSm, X86_INS_SQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRTPSr, X86_INS_SQRTPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRTSDm, X86_INS_SQRTSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTSDm_Int, X86_INS_SQRTSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTSDr, X86_INS_SQRTSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTSDr_Int, X86_INS_SQRTSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SQRTSSm, X86_INS_SQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRTSSm_Int, X86_INS_SQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRTSSr, X86_INS_SQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRTSSr_Int, X86_INS_SQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SQRT_F, X86_INS_FSQRT, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SS_PREFIX, X86_INS_SS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STAC, X86_INS_STAC, { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_STC, X86_INS_STC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STD, X86_INS_STD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STGI, X86_INS_STGI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STI, X86_INS_STI, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STMXCSR, X86_INS_STMXCSR, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_STOSB, X86_INS_STOSB, { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 },
- { X86_STOSL, X86_INS_STOSD, { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 },
- { X86_STOSQ, X86_INS_STOSQ, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_STOSW, X86_INS_STOSW, { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 },
- { X86_STR16r, X86_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STR32r, X86_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STR64r, X86_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_STRm, X86_INS_STR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_ST_F32m, X86_INS_FST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_F64m, X86_INS_FST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_FP32m, X86_INS_FSTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_FP64m, X86_INS_FSTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_FP80m, X86_INS_FSTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_FPrr, X86_INS_FSTP, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_ST_Frr, X86_INS_FST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUB16i16, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16ri, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16ri8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16rm, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16rr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB16rr_REV, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32i32, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32ri, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32ri8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32rm, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32rr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB32rr_REV, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64i32, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64mi32, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64mi8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64ri32, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64ri8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64rm, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64rr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB64rr_REV, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8i8, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8mi, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8mr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8ri, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8rm, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8rr, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUB8rr_REV, X86_INS_SUB, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_SUBPDrm, X86_INS_SUBPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBPDrr, X86_INS_SUBPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBPSrm, X86_INS_SUBPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUBPSrr, X86_INS_SUBPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUBR_F32m, X86_INS_FSUBR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUBR_F64m, X86_INS_FSUBR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUBR_FI16m, X86_INS_FISUBR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUBR_FI32m, X86_INS_FISUBR, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUBR_FPrST0, X86_INS_FSUBRP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SUBR_FST0r, X86_INS_FSUBR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SUBR_FrST0, X86_INS_FSUBR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SUBSDrm, X86_INS_SUBSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBSDrm_Int, X86_INS_SUBSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBSDrr, X86_INS_SUBSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBSDrr_Int, X86_INS_SUBSD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_SUBSSrm, X86_INS_SUBSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUBSSrm_Int, X86_INS_SUBSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUBSSrr, X86_INS_SUBSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUBSSrr_Int, X86_INS_SUBSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_SUB_F32m, X86_INS_FSUB, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUB_F64m, X86_INS_FSUB, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUB_FI16m, X86_INS_FISUB, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUB_FI32m, X86_INS_FISUB, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_SUB_FPrST0, X86_INS_FSUBP, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SUB_FST0r, X86_INS_FSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SUB_FrST0, X86_INS_FSUB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SWAPGS, X86_INS_SWAPGS, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SYSCALL, X86_INS_SYSCALL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SYSENTER, X86_INS_SYSENTER, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SYSEXIT, X86_INS_SYSEXIT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SYSEXIT64, X86_INS_SYSEXIT, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_SYSRET, X86_INS_SYSRET, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_SYSRET64, X86_INS_SYSRET, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_T1MSKC32rm, X86_INS_T1MSKC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_T1MSKC32rr, X86_INS_T1MSKC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_T1MSKC64rm, X86_INS_T1MSKC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_T1MSKC64rr, X86_INS_T1MSKC, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_TEST16i16, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST16mi, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST16ri, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST16rm, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST16rr, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST32i32, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST32mi, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST32ri, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST32rm, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST32rr, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST64i32, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST64mi32, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST64ri32, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST64rm, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST64rr, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST8i8, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST8mi, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST8ri, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST8rm, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TEST8rr, X86_INS_TEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_TRAP, X86_INS_UD2, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_TST_F, X86_INS_FTST, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_TZCNT16rm, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZCNT16rr, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZCNT32rm, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZCNT32rr, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZCNT64rm, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZCNT64rr, X86_INS_TZCNT, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 },
- { X86_TZMSK32rm, X86_INS_TZMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_TZMSK32rr, X86_INS_TZMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_TZMSK64rm, X86_INS_TZMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_TZMSK64rr, X86_INS_TZMSK, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 },
- { X86_UCOMISDrm, X86_INS_UCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UCOMISDrr, X86_INS_UCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UCOMISSrm, X86_INS_UCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_UCOMISSrr, X86_INS_UCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_UCOM_FIPr, X86_INS_FUCOMPI, { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_UCOM_FIr, X86_INS_FUCOMI, { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_UCOM_FPPr, X86_INS_FUCOMPP, { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_UCOM_FPr, X86_INS_FUCOMP, { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_UCOM_Fr, X86_INS_FUCOM, { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_UD2B, X86_INS_UD2B, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_UNPCKHPDrm, X86_INS_UNPCKHPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UNPCKHPDrr, X86_INS_UNPCKHPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UNPCKHPSrm, X86_INS_UNPCKHPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_UNPCKHPSrr, X86_INS_UNPCKHPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_UNPCKLPDrm, X86_INS_UNPCKLPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UNPCKLPDrr, X86_INS_UNPCKLPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_UNPCKLPSrm, X86_INS_UNPCKLPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_UNPCKLPSrr, X86_INS_UNPCKLPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_VADDPDYrm, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPDYrr, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPDZrm, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPDZrmb, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPDZrr, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPDrm, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPDrr, X86_INS_VADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPSYrm, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPSYrr, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPSZrm, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPSZrmb, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPSZrr, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDPSrm, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDPSrr, X86_INS_VADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSDZrm, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDSDZrr, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDSDrm, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSDrm_Int, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSDrr, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSDrr_Int, X86_INS_VADDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSSZrm, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDSSZrr, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VADDSSrm, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSSrm_Int, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSSrr, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSSrr_Int, X86_INS_VADDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPDYrm, X86_INS_VADDSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPDYrr, X86_INS_VADDSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPDrm, X86_INS_VADDSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPDrr, X86_INS_VADDSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPSYrm, X86_INS_VADDSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPSYrr, X86_INS_VADDSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPSrm, X86_INS_VADDSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VADDSUBPSrr, X86_INS_VADDSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VAESDECLASTrm, X86_INS_VAESDECLAST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESDECLASTrr, X86_INS_VAESDECLAST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESDECrm, X86_INS_VAESDEC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESDECrr, X86_INS_VAESDEC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESENCLASTrm, X86_INS_VAESENCLAST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESENCLASTrr, X86_INS_VAESENCLAST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESENCrm, X86_INS_VAESENC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESENCrr, X86_INS_VAESENC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESIMCrm, X86_INS_VAESIMC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESIMCrr, X86_INS_VAESIMC, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 },
- { X86_VALIGNDrmi, X86_INS_VALIGND, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VALIGNDrri, X86_INS_VALIGND, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VALIGNQrmi, X86_INS_VALIGNQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VALIGNQrri, X86_INS_VALIGNQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VANDNPDYrm, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPDYrr, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPDrm, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPDrr, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPSYrm, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPSYrr, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPSrm, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDNPSrr, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPDYrm, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPDYrr, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPDrm, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPDrr, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPSYrm, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPSYrr, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPSrm, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VANDPSrr, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDMPDZrm, X86_INS_VBLENDMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBLENDMPDZrr, X86_INS_VBLENDMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBLENDMPSZrm, X86_INS_VBLENDMPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBLENDMPSZrr, X86_INS_VBLENDMPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBLENDPDYrmi, X86_INS_VBLENDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPDYrri, X86_INS_VBLENDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPDrmi, X86_INS_VBLENDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPDrri, X86_INS_VBLENDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPSYrmi, X86_INS_VBLENDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPSYrri, X86_INS_VBLENDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPSrmi, X86_INS_VBLENDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDPSrri, X86_INS_VBLENDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPDYrm, X86_INS_VBLENDVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPDYrr, X86_INS_VBLENDVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPDrm, X86_INS_VBLENDVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPDrr, X86_INS_VBLENDVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPSYrm, X86_INS_VBLENDVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPSYrr, X86_INS_VBLENDVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPSrm, X86_INS_VBLENDVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBLENDVPSrr, X86_INS_VBLENDVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBROADCASTF128, X86_INS_VBROADCASTF128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBROADCASTI128, X86_INS_VBROADCASTI128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VBROADCASTSDZrm, X86_INS_VBROADCASTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBROADCASTSDZrr, X86_INS_VBROADCASTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VBROADCASTSSZrm, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBROADCASTSSZrr, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VCMPPDYrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDYrmi_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDYrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDYrri_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDZrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPDZrmi_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPDZrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPDZrri_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPDZrrib, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPDrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDrmi_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPDrri_alt, X86_INS_VCMPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSYrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSYrmi_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSYrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSYrri_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSZrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPSZrmi_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPSZrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPSZrri_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPSZrrib, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPPSrmi, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSrmi_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSrri, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPPSrri_alt, X86_INS_VCMPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSDZrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSDZrmi_alt, X86_INS_VCMPSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSDZrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSDZrri_alt, X86_INS_VCMPSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSDrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSDrm_alt, X86_INS_VCMPSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSDrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSDrr_alt, X86_INS_VCMPSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSSZrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSSZrmi_alt, X86_INS_VCMPSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSSZrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSSZrri_alt, X86_INS_VCMPSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCMPSSrm, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSSrm_alt, X86_INS_VCMPSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSSrr, X86_INS_VCMP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCMPSSrr_alt, X86_INS_VCMPSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCOMISDZrm, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCOMISDZrr, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCOMISDrm, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCOMISDrr, X86_INS_VCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCOMISSZrm, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCOMISSZrr, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCOMISSrm, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCOMISSrr, X86_INS_VCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2DQXrm, X86_INS_VCVTPD2DQX, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2PSXrm, X86_INS_VCVTPD2PSX, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH, { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 },
- { X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SI64Zrm, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SI64Zrr, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SI64rm, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2SI64rr, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2SIZrm, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SIZrr, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SIrm, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2SIrr, X86_INS_VCVTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSD2USI64Zrm, X86_INS_VCVTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2USI64Zrr, X86_INS_VCVTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2USIZrm, X86_INS_VCVTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSD2USIZrr, X86_INS_VCVTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI2SD64rm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SD64rr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SS64rm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SS64rr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2SI64Zrm, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SI64Zrr, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SI64rm, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2SI64rr, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2SIZrm, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SIZrr, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2SIrm, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2SIrr, X86_INS_VCVTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTSS2USI64Zrm, X86_INS_VCVTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2USI64Zrr, X86_INS_VCVTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2USIZrm, X86_INS_VCVTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTSS2USIZrr, X86_INS_VCVTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPD2DQXrm, X86_INS_VCVTTPD2DQX, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPDYrm, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPDYrr, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPDZrm, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPDZrmb, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPDZrr, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPDrm, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPDrr, X86_INS_VDIVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPSYrm, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPSYrr, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPSZrm, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPSZrmb, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPSZrr, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVPSrm, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVPSrr, X86_INS_VDIVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSDZrm, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVSDZrr, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVSDrm, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSDrm_Int, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSDrr, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSDrr_Int, X86_INS_VDIVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSSZrm, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVSSZrr, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VDIVSSrm, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSSrm_Int, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSSrr, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDIVSSrr_Int, X86_INS_VDIVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPDrmi, X86_INS_VDPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPDrri, X86_INS_VDPPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPSYrmi, X86_INS_VDPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPSYrri, X86_INS_VDPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPSrmi, X86_INS_VDPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VDPPSrri, X86_INS_VDPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VERRm, X86_INS_VERR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VERRr, X86_INS_VERR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VERWm, X86_INS_VERW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VERWr, X86_INS_VERW, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VEXTRACTF32x4mr, X86_INS_VEXTRACTF32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTF32x4rr, X86_INS_VEXTRACTF32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTF64x4mr, X86_INS_VEXTRACTF64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTF64x4rr, X86_INS_VEXTRACTF64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VEXTRACTI32x4mr, X86_INS_VEXTRACTI32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTI32x4rr, X86_INS_VEXTRACTI32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTI64x4mr, X86_INS_VEXTRACTI64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTI64x4rr, X86_INS_VEXTRACTI64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VEXTRACTPSzmr, X86_INS_VEXTRACTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VEXTRACTPSzrr, X86_INS_VEXTRACTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD132PDZm, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD132PDZmb, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD132PSZm, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD132PSZmb, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PDZm, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PDZmb, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PDZr, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PSZm, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PSZmb, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADD213PSZr, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDPD4mr, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4mrY, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rm, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rmY, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rr, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rrY, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rrY_REV, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPDr132m, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr132mY, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr132r, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr132rY, X86_INS_VFMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr213m, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr213mY, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr213r, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr213rY, X86_INS_VFMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr231m, X86_INS_VFMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr231mY, X86_INS_VFMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr231r, X86_INS_VFMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPDr231rY, X86_INS_VFMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPS4mr, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4mrY, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rm, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rmY, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rr, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rrY, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rrY_REV, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDPSr132m, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr132mY, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr132r, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr132rY, X86_INS_VFMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr213m, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr213mY, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr213r, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr213rY, X86_INS_VFMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr231m, X86_INS_VFMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr231mY, X86_INS_VFMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr231r, X86_INS_VFMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDPSr231rY, X86_INS_VFMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSD4mr, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4rm, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4rr, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSDZm, X86_INS_VFMADD213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSDZr, X86_INS_VFMADD213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSDr132m, X86_INS_VFMADD132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSDr132r, X86_INS_VFMADD132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSDr213m, X86_INS_VFMADD213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSDr213r, X86_INS_VFMADD213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSDr231m, X86_INS_VFMADD231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSDr231r, X86_INS_VFMADD231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSS4mr, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4rm, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4rr, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSSZm, X86_INS_VFMADD213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSSZr, X86_INS_VFMADD213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSSr132m, X86_INS_VFMADD132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSSr132r, X86_INS_VFMADD132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSSr213m, X86_INS_VFMADD213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSSr213r, X86_INS_VFMADD213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSSr231m, X86_INS_VFMADD231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSSr231r, X86_INS_VFMADD231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4mrY, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rmY, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rrY, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rrY_REV, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr132m, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr132mY, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr132r, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr132rY, X86_INS_VFMADDSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr213m, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr213mY, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr213r, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr213rY, X86_INS_VFMADDSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr231m, X86_INS_VFMADDSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr231mY, X86_INS_VFMADDSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr231r, X86_INS_VFMADDSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPDr231rY, X86_INS_VFMADDSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4mrY, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rmY, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rrY, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rrY_REV, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr132m, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr132mY, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr132r, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr132rY, X86_INS_VFMADDSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr213m, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr213mY, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr213r, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr213rY, X86_INS_VFMADDSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr231m, X86_INS_VFMADDSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr231mY, X86_INS_VFMADDSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr231r, X86_INS_VFMADDSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMADDSUBPSr231rY, X86_INS_VFMADDSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4mrY, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rmY, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rrY, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rrY_REV, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr132m, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr132mY, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr132r, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr132rY, X86_INS_VFMSUBADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr213m, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr213mY, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr213r, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr213rY, X86_INS_VFMSUBADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr231m, X86_INS_VFMSUBADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr231mY, X86_INS_VFMSUBADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr231r, X86_INS_VFMSUBADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPDr231rY, X86_INS_VFMSUBADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4mrY, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rmY, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rrY, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rrY_REV, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr132m, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr132mY, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr132r, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr132rY, X86_INS_VFMSUBADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr213m, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr213mY, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr213r, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr213rY, X86_INS_VFMSUBADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr231m, X86_INS_VFMSUBADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr231mY, X86_INS_VFMSUBADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr231r, X86_INS_VFMSUBADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBADDPSr231rY, X86_INS_VFMSUBADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPD4mr, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4mrY, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rm, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rmY, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rr, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rrY, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rrY_REV, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPDr132m, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr132mY, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr132r, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr132rY, X86_INS_VFMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr213m, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr213mY, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr213r, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr213rY, X86_INS_VFMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr231m, X86_INS_VFMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr231mY, X86_INS_VFMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr231r, X86_INS_VFMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPDr231rY, X86_INS_VFMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPS4mr, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4mrY, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rm, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rmY, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rr, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rrY, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rrY_REV, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBPSr132m, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr132mY, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr132r, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr132rY, X86_INS_VFMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr213m, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr213mY, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr213r, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr213rY, X86_INS_VFMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr231m, X86_INS_VFMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr231mY, X86_INS_VFMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr231r, X86_INS_VFMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBPSr231rY, X86_INS_VFMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSD4mr, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4rm, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4rr, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSDZm, X86_INS_VFMSUB213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBSDZr, X86_INS_VFMSUB213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBSDr132m, X86_INS_VFMSUB132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSDr132r, X86_INS_VFMSUB132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSDr213m, X86_INS_VFMSUB213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSDr213r, X86_INS_VFMSUB213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSDr231m, X86_INS_VFMSUB231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSDr231r, X86_INS_VFMSUB231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSS4mr, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4rm, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4rr, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFMSUBSSZm, X86_INS_VFMSUB213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBSSZr, X86_INS_VFMSUB213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFMSUBSSr132m, X86_INS_VFMSUB132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSSr132r, X86_INS_VFMSUB132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSSr213m, X86_INS_VFMSUB213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSSr213r, X86_INS_VFMSUB213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSSr231m, X86_INS_VFMSUB231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFMSUBSSr231r, X86_INS_VFMSUB231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADDPD4mr, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4mrY, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rm, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rmY, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rr, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rrY, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rrY_REV, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPDr132m, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr132mY, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr132r, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr132rY, X86_INS_VFNMADD132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr213m, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr213mY, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr213r, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr213rY, X86_INS_VFNMADD213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr231m, X86_INS_VFNMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr231mY, X86_INS_VFNMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr231r, X86_INS_VFNMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPDr231rY, X86_INS_VFNMADD231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPS4mr, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4mrY, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rm, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rmY, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rr, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rrY, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rrY_REV, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDPSr132m, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr132mY, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr132r, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr132rY, X86_INS_VFNMADD132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr213m, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr213mY, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr213r, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr213rY, X86_INS_VFNMADD213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr231m, X86_INS_VFNMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr231mY, X86_INS_VFNMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr231r, X86_INS_VFNMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDPSr231rY, X86_INS_VFNMADD231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSD4mr, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4rm, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4rr, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSDZm, X86_INS_VFNMADD213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADDSDZr, X86_INS_VFNMADD213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADDSDr132m, X86_INS_VFNMADD132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSDr132r, X86_INS_VFNMADD132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSDr213m, X86_INS_VFNMADD213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSDr213r, X86_INS_VFNMADD213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSDr231m, X86_INS_VFNMADD231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSDr231r, X86_INS_VFNMADD231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSS4mr, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4rm, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4rr, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMADDSSZm, X86_INS_VFNMADD213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADDSSZr, X86_INS_VFNMADD213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMADDSSr132m, X86_INS_VFNMADD132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSSr132r, X86_INS_VFNMADD132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSSr213m, X86_INS_VFNMADD213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSSr213r, X86_INS_VFNMADD213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSSr231m, X86_INS_VFNMADD231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMADDSSr231r, X86_INS_VFNMADD231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4mrY, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rmY, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rrY, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rrY_REV, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPDr132m, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr132mY, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr132r, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr132rY, X86_INS_VFNMSUB132PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr213m, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr213mY, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr213r, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr213rY, X86_INS_VFNMSUB213PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr231m, X86_INS_VFNMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr231mY, X86_INS_VFNMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr231r, X86_INS_VFNMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPDr231rY, X86_INS_VFNMSUB231PD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4mrY, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rmY, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rrY, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rrY_REV, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBPSr132m, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr132mY, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr132r, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr132rY, X86_INS_VFNMSUB132PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr213m, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr213mY, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr213r, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr213rY, X86_INS_VFNMSUB213PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr231m, X86_INS_VFNMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr231mY, X86_INS_VFNMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr231r, X86_INS_VFNMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBPSr231rY, X86_INS_VFNMSUB231PS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSDZm, X86_INS_VFNMSUB213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUBSDZr, X86_INS_VFNMSUB213SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUBSDr132m, X86_INS_VFNMSUB132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSDr132r, X86_INS_VFNMSUB132SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSDr213m, X86_INS_VFNMSUB213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSDr213r, X86_INS_VFNMSUB213SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSDr231m, X86_INS_VFNMSUB231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSDr231r, X86_INS_VFNMSUB231SD, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS, { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 },
- { X86_VFNMSUBSSZm, X86_INS_VFNMSUB213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUBSSZr, X86_INS_VFNMSUB213SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VFNMSUBSSr132m, X86_INS_VFNMSUB132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSSr132r, X86_INS_VFNMSUB132SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSSr213m, X86_INS_VFNMSUB213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSSr213r, X86_INS_VFNMSUB213SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSSr231m, X86_INS_VFNMSUB231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFNMSUBSSr231r, X86_INS_VFNMSUB231SS, { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0 },
- { X86_VFRCZPDrm, X86_INS_VFRCZPD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPDrmY, X86_INS_VFRCZPD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPDrr, X86_INS_VFRCZPD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPDrrY, X86_INS_VFRCZPD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPSrm, X86_INS_VFRCZPS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPSrmY, X86_INS_VFRCZPS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPSrr, X86_INS_VFRCZPS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZPSrrY, X86_INS_VFRCZPS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZSDrm, X86_INS_VFRCZSD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZSDrr, X86_INS_VFRCZSD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZSSrm, X86_INS_VFRCZSS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFRCZSSrr, X86_INS_VFRCZSS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VFsANDNPDrm, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDNPDrr, X86_INS_VANDNPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDNPSrm, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDNPSrr, X86_INS_VANDNPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDPDrm, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDPDrr, X86_INS_VANDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDPSrm, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsANDPSrr, X86_INS_VANDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsORPDrm, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsORPDrr, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsORPSrm, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsORPSrr, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsXORPDrm, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsXORPDrr, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsXORPSrm, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VFsXORPSrr, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VGATHERDPDYrm, X86_INS_VGATHERDPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERDPDZrm, X86_INS_VGATHERDPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VGATHERDPDrm, X86_INS_VGATHERDPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERDPSYrm, X86_INS_VGATHERDPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERDPSZrm, X86_INS_VGATHERDPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VGATHERDPSrm, X86_INS_VGATHERDPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERQPDYrm, X86_INS_VGATHERQPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERQPDZrm, X86_INS_VGATHERQPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VGATHERQPDrm, X86_INS_VGATHERQPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERQPSYrm, X86_INS_VGATHERQPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VGATHERQPSZrm, X86_INS_VGATHERQPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VGATHERQPSrm, X86_INS_VGATHERQPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VHADDPDYrm, X86_INS_VHADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPDYrr, X86_INS_VHADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPDrm, X86_INS_VHADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPDrr, X86_INS_VHADDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPSYrm, X86_INS_VHADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPSYrr, X86_INS_VHADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPSrm, X86_INS_VHADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHADDPSrr, X86_INS_VHADDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPDYrm, X86_INS_VHSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPDYrr, X86_INS_VHSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPDrm, X86_INS_VHSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPDrr, X86_INS_VHSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPSYrm, X86_INS_VHSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPSYrr, X86_INS_VHSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPSrm, X86_INS_VHSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VHSUBPSrr, X86_INS_VHSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VINSERTF128rm, X86_INS_VINSERTF128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VINSERTF128rr, X86_INS_VINSERTF128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VINSERTF32x4rm, X86_INS_VINSERTF32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTF32x4rr, X86_INS_VINSERTF32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTF64x4rm, X86_INS_VINSERTF64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTF64x4rr, X86_INS_VINSERTF64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTI128rm, X86_INS_VINSERTI128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VINSERTI128rr, X86_INS_VINSERTI128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VINSERTI32x4rm, X86_INS_VINSERTI32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTI32x4rr, X86_INS_VINSERTI32X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTI64x4rm, X86_INS_VINSERTI64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTI64x4rr, X86_INS_VINSERTI64X4, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTPSrm, X86_INS_VINSERTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VINSERTPSrr, X86_INS_VINSERTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VINSERTPSzrm, X86_INS_VINSERTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VINSERTPSzrr, X86_INS_VINSERTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VLDDQUYrm, X86_INS_VLDDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VLDDQUrm, X86_INS_VLDDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VLDMXCSR, X86_INS_VLDMXCSR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU, { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU, { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPDYrm, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPDYrr, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPDrm, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPDrr, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPSYrm, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPSYrr, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPSrm, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCPSrr, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCSDrm, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCSDrr, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCSSrm, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXCSSrr, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPDYrm, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPDYrr, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPDZrm, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPDZrmb, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPDZrr, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPDrm, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPDrr, X86_INS_VMAXPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPSYrm, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPSYrr, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPSZrm, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPSZrmb, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPSZrr, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXPSrm, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXPSrr, X86_INS_VMAXPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSDZrm, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXSDZrr, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXSDrm, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSDrm_Int, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSDrr, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSDrr_Int, X86_INS_VMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSSZrm, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXSSZrr, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMAXSSrm, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSSrm_Int, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSSrr, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMAXSSrr_Int, X86_INS_VMAXSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMCALL, X86_INS_VMCALL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMCLEARm, X86_INS_VMCLEAR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMFUNC, X86_INS_VMFUNC, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMINCPDYrm, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPDYrr, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPDrm, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPDrr, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPSYrm, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPSYrr, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPSrm, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCPSrr, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCSDrm, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCSDrr, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCSSrm, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINCSSrr, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPDYrm, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPDYrr, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPDZrm, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPDZrmb, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPDZrr, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPDrm, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPDrr, X86_INS_VMINPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPSYrm, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPSYrr, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPSZrm, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPSZrmb, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPSZrr, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINPSrm, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINPSrr, X86_INS_VMINPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSDZrm, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINSDZrr, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINSDrm, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSDrm_Int, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSDrr, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSDrr_Int, X86_INS_VMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSSZrm, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINSSZrr, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMINSSrm, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSSrm_Int, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSSrr, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMINSSrr_Int, X86_INS_VMINSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMLAUNCH, X86_INS_VMLAUNCH, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMLOAD32, X86_INS_VMLOAD, { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMLOAD64, X86_INS_VMLOAD, { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMMCALL, X86_INS_VMMCALL, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMOV64toPQIZrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOV64toPQIrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOV64toSDZrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOV64toSDrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOV64toSDrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDYmr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDYrm, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDYrr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDZmr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPDZrm, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPDZrmk, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPDZrr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPDZrrk, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPDmr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDrm, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDrr, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPDrr_REV, X86_INS_VMOVAPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSYmr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSYrm, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSYrr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSZmr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPSZrm, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPSZrmk, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPSZrr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPSZrrk, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVAPSmr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSrm, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSrr, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVAPSrr_REV, X86_INS_VMOVAPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDDUPYrm, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDDUPYrr, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDDUPZrm, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDDUPZrr, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDDUPrm, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDDUPrr, X86_INS_VMOVDDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDI2PDIZrm, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDI2PDIZrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDI2PDIrm, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDI2PDIrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDI2SSZrm, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDI2SSZrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDI2SSrm, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDI2SSrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQA32mr, X86_INS_VMOVDQA32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQA32rm, X86_INS_VMOVDQA32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQA32rr, X86_INS_VMOVDQA32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQA64mr, X86_INS_VMOVDQA64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQA64rm, X86_INS_VMOVDQA64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQA64rr, X86_INS_VMOVDQA64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQAYmr, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQAYrm, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQAYrr, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQAmr, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQArm, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQArr, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQArr_REV, X86_INS_VMOVDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQU32mr, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU32rm, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU32rmk, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU32rr, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU32rrk, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU32rrkz, X86_INS_VMOVDQU32, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64mr, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64rm, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64rmk, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64rr, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64rrk, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQU64rrkz, X86_INS_VMOVDQU64, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVDQUYmr, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUYrm, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUYrr, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUmr, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUrm, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUrr, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVDQUrr_REV, X86_INS_VMOVDQU, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVHLPSZrr, X86_INS_VMOVHLPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVHLPSrr, X86_INS_VMOVHLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVHPDmr, X86_INS_VMOVHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVHPDrm, X86_INS_VMOVHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVHPSmr, X86_INS_VMOVHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVHPSrm, X86_INS_VMOVHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVLHPSZrr, X86_INS_VMOVLHPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVLHPSrr, X86_INS_VMOVLHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVLPDmr, X86_INS_VMOVLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVLPDrm, X86_INS_VMOVLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVLPSmr, X86_INS_VMOVLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVLPSrm, X86_INS_VMOVLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VMOVNTDQArm, X86_INS_VMOVNTDQA, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTDQmr, X86_INS_VMOVNTDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTPDYmr, X86_INS_VMOVNTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTPDmr, X86_INS_VMOVNTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTPSYmr, X86_INS_VMOVNTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVNTPSmr, X86_INS_VMOVNTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVPDI2DIZmr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVPDI2DIZrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVPDI2DImr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVPDI2DIrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVPQI2QImr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVPQI2QIrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVPQIto64Zmr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMOVPQIto64Zrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMOVPQIto64rr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVQI2PQIZrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVQI2PQIrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDZmr, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDZrm, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDZrr, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDZrr_REV, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDZrrk, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDmr, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDrm, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDrr, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDrr_REV, X86_INS_VMOVSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDto64Zmr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDto64Zrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSDto64mr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSDto64rr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSS2DIZmr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSS2DIZrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSS2DImr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSS2DIrr, X86_INS_VMOVD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSSZmr, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSSZrm, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSSZrr, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSSZrr_REV, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSSZrrk, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVSSmr, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSSrm, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSSrr, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVSSrr_REV, X86_INS_VMOVSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDYmr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDYrm, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDYrr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDZmr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPDZrm, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPDZrmk, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPDZrr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPDZrrk, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPDmr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDrm, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDrr, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPDrr_REV, X86_INS_VMOVUPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSYmr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSYrm, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSYrr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSZmr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPSZrm, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPSZrmk, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPSZrr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPSZrrk, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVUPSmr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSrm, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSrr, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVUPSrr_REV, X86_INS_VMOVUPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVZPQILo2PQIZrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMOVZPQILo2PQIrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVZQI2PQIrm, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMOVZQI2PQIrr, X86_INS_VMOVQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMPSADBWYrmi, X86_INS_VMPSADBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VMPSADBWYrri, X86_INS_VMPSADBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VMPSADBWrmi, X86_INS_VMPSADBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMPSADBWrri, X86_INS_VMPSADBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMPTRLDm, X86_INS_VMPTRLD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMPTRSTm, X86_INS_VMPTRST, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMREAD32rm, X86_INS_VMREAD, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMREAD32rr, X86_INS_VMREAD, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMREAD64rm, X86_INS_VMREAD, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMREAD64rr, X86_INS_VMREAD, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMRESUME, X86_INS_VMRESUME, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMRUN32, X86_INS_VMRUN, { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMRUN64, X86_INS_VMRUN, { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMSAVE32, X86_INS_VMSAVE, { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMSAVE64, X86_INS_VMSAVE, { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMULPDYrm, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPDYrr, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPDZrm, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPDZrmb, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPDZrr, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPDrm, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPDrr, X86_INS_VMULPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPSYrm, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPSYrr, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPSZrm, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPSZrmb, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPSZrr, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULPSrm, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULPSrr, X86_INS_VMULPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSDZrm, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULSDZrr, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULSDrm, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSDrm_Int, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSDrr, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSDrr_Int, X86_INS_VMULSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSSZrm, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULSSZrr, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VMULSSrm, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSSrm_Int, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSSrr, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMULSSrr_Int, X86_INS_VMULSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VMWRITE32rm, X86_INS_VMWRITE, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMWRITE32rr, X86_INS_VMWRITE, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_VMWRITE64rm, X86_INS_VMWRITE, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMWRITE64rr, X86_INS_VMWRITE, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_VMXOFF, X86_INS_VMXOFF, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VMXON, X86_INS_VMXON, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_VORPDYrm, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPDYrr, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPDrm, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPDrr, X86_INS_VORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPSYrm, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPSYrr, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPSrm, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VORPSrr, X86_INS_VORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSBrm128, X86_INS_VPABSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSBrm256, X86_INS_VPABSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPABSBrr128, X86_INS_VPABSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSBrr256, X86_INS_VPABSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPABSDrm, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPABSDrm128, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSDrm256, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPABSDrr, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPABSDrr128, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSDrr256, X86_INS_VPABSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPABSQrm, X86_INS_VPABSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPABSQrr, X86_INS_VPABSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPABSWrm128, X86_INS_VPABSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSWrm256, X86_INS_VPABSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPABSWrr128, X86_INS_VPABSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPABSWrr256, X86_INS_VPABSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKSSDWYrm, X86_INS_VPACKSSDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKSSDWYrr, X86_INS_VPACKSSDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKSSDWrm, X86_INS_VPACKSSDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKSSDWrr, X86_INS_VPACKSSDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKSSWBYrm, X86_INS_VPACKSSWB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKSSWBYrr, X86_INS_VPACKSSWB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKSSWBrm, X86_INS_VPACKSSWB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKSSWBrr, X86_INS_VPACKSSWB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKUSDWYrm, X86_INS_VPACKUSDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKUSDWYrr, X86_INS_VPACKUSDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKUSDWrm, X86_INS_VPACKUSDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKUSDWrr, X86_INS_VPACKUSDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKUSWBYrm, X86_INS_VPACKUSWB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKUSWBYrr, X86_INS_VPACKUSWB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPACKUSWBrm, X86_INS_VPACKUSWB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPACKUSWBrr, X86_INS_VPACKUSWB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDBYrm, X86_INS_VPADDB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDBYrr, X86_INS_VPADDB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDBrm, X86_INS_VPADDB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDBrr, X86_INS_VPADDB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDDYrm, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDDYrr, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDDZrm, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDDZrmb, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDDZrr, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDDrm, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDDrr, X86_INS_VPADDD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDQYrm, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDQYrr, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDQZrm, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDQZrmb, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDQZrr, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPADDQrm, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDQrr, X86_INS_VPADDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDSBYrm, X86_INS_VPADDSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDSBYrr, X86_INS_VPADDSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDSBrm, X86_INS_VPADDSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDSBrr, X86_INS_VPADDSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDSWYrm, X86_INS_VPADDSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDSWYrr, X86_INS_VPADDSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDSWrm, X86_INS_VPADDSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDSWrr, X86_INS_VPADDSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDUSBYrm, X86_INS_VPADDUSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDUSBYrr, X86_INS_VPADDUSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDUSBrm, X86_INS_VPADDUSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDUSBrr, X86_INS_VPADDUSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDUSWYrm, X86_INS_VPADDUSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDUSWYrr, X86_INS_VPADDUSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDUSWrm, X86_INS_VPADDUSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDUSWrr, X86_INS_VPADDUSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDWYrm, X86_INS_VPADDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDWYrr, X86_INS_VPADDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPADDWrm, X86_INS_VPADDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPADDWrr, X86_INS_VPADDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPALIGNR128rm, X86_INS_VPALIGNR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPALIGNR128rr, X86_INS_VPALIGNR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPALIGNR256rm, X86_INS_VPALIGNR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPALIGNR256rr, X86_INS_VPALIGNR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPANDDZrm, X86_INS_VPANDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDDZrmb, X86_INS_VPANDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDDZrr, X86_INS_VPANDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNDZrm, X86_INS_VPANDND, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNDZrmb, X86_INS_VPANDND, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNDZrr, X86_INS_VPANDND, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNQZrm, X86_INS_VPANDNQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNQZrmb, X86_INS_VPANDNQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNQZrr, X86_INS_VPANDNQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDNYrm, X86_INS_VPANDN, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPANDNYrr, X86_INS_VPANDN, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPANDNrm, X86_INS_VPANDN, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPANDNrr, X86_INS_VPANDN, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPANDQZrm, X86_INS_VPANDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDQZrmb, X86_INS_VPANDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDQZrr, X86_INS_VPANDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPANDYrm, X86_INS_VPAND, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPANDYrr, X86_INS_VPAND, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPANDrm, X86_INS_VPAND, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPANDrr, X86_INS_VPAND, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPAVGBYrm, X86_INS_VPAVGB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPAVGBYrr, X86_INS_VPAVGB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPAVGBrm, X86_INS_VPAVGB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPAVGBrr, X86_INS_VPAVGB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPAVGWYrm, X86_INS_VPAVGW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPAVGWYrr, X86_INS_VPAVGW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPAVGWrm, X86_INS_VPAVGW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPAVGWrr, X86_INS_VPAVGW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPBLENDDYrmi, X86_INS_VPBLENDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDDYrri, X86_INS_VPBLENDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDDrmi, X86_INS_VPBLENDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDDrri, X86_INS_VPBLENDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDMDZrm, X86_INS_VPBLENDMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBLENDMDZrr, X86_INS_VPBLENDMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBLENDVBYrm, X86_INS_VPBLENDVB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDVBYrr, X86_INS_VPBLENDVB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDVBrm, X86_INS_VPBLENDVB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPBLENDVBrr, X86_INS_VPBLENDVB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPBLENDWYrmi, X86_INS_VPBLENDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDWYrri, X86_INS_VPBLENDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBLENDWrmi, X86_INS_VPBLENDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPBLENDWrri, X86_INS_VPBLENDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTDZkrm, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDZkrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDZrm, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDZrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDrZkrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDrZrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTMB2Qrr, X86_INS_VPBROADCASTMB2Q, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTMW2Drr, X86_INS_VPBROADCASTMW2D, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTQZkrm, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQZkrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQZrm, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQZrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQrZkrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQrZrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 },
- { X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ, { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 },
- { X86_VPCMOVmr, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMOVmrY, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMOVrm, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMOVrmY, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMOVrr, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMOVrrY, X86_INS_VPCMOV, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCMPDZrmi, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPDZrmi_alt, X86_INS_VPCMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPDZrri, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPDZrri_alt, X86_INS_VPCMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPEQBYrm, X86_INS_VPCMPEQB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQBYrr, X86_INS_VPCMPEQB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQBrm, X86_INS_VPCMPEQB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQBrr, X86_INS_VPCMPEQB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQDYrm, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQDYrr, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQDZrm, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPEQDZrr, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPEQDrm, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQDrr, X86_INS_VPCMPEQD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPEQQrm, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQQrr, X86_INS_VPCMPEQQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQWYrm, X86_INS_VPCMPEQW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQWYrr, X86_INS_VPCMPEQW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPEQWrm, X86_INS_VPCMPEQW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPEQWrr, X86_INS_VPCMPEQW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPESTRM128rm, X86_INS_VPCMPESTRM, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPESTRM128rr, X86_INS_VPCMPESTRM, { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTBYrm, X86_INS_VPCMPGTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTBYrr, X86_INS_VPCMPGTB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTBrm, X86_INS_VPCMPGTB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTBrr, X86_INS_VPCMPGTB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTDYrm, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTDYrr, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTDZrm, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPGTDZrr, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPGTDrm, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTDrr, X86_INS_VPCMPGTD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPGTQrm, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTQrr, X86_INS_VPCMPGTQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTWYrm, X86_INS_VPCMPGTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTWYrr, X86_INS_VPCMPGTW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPCMPGTWrm, X86_INS_VPCMPGTW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPGTWrr, X86_INS_VPCMPGTW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI, { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI, { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPISTRM128rm, X86_INS_VPCMPISTRM, { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPISTRM128rr, X86_INS_VPCMPISTRM, { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPCMPQZrmi, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPQZrri, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPQZrri_alt, X86_INS_VPCMPQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUDZrmi, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUDZrri, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUQZrmi, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUQZrri, X86_INS_VPCMP, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPCOMBmi, X86_INS_VPCOMB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMBri, X86_INS_VPCOMB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMDmi, X86_INS_VPCOMD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMDri, X86_INS_VPCOMD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMQmi, X86_INS_VPCOMQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMQri, X86_INS_VPCOMQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUBmi, X86_INS_VPCOMUB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUBri, X86_INS_VPCOMUB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUDmi, X86_INS_VPCOMUD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUDri, X86_INS_VPCOMUD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUQmi, X86_INS_VPCOMUQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUQri, X86_INS_VPCOMUQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUWmi, X86_INS_VPCOMUW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMUWri, X86_INS_VPCOMUW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMWmi, X86_INS_VPCOMW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCOMWri, X86_INS_VPCOMW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPCONFLICTDrm, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrmb, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrmbk, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrmbkz, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrmk, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrmkz, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrr, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrrk, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTDrrkz, X86_INS_VPCONFLICTD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrm, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrmb, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrmbk, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrmbkz, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrmk, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrmkz, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrr, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrrk, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPCONFLICTQrrkz, X86_INS_VPCONFLICTQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPERM2F128rm, X86_INS_VPERM2F128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERM2F128rr, X86_INS_VPERM2F128, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERM2I128rm, X86_INS_VPERM2I128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERM2I128rr, X86_INS_VPERM2I128, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMDYrm, X86_INS_VPERMD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMDYrr, X86_INS_VPERMD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMDZrm, X86_INS_VPERMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMDZrr, X86_INS_VPERMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2Drm, X86_INS_VPERMI2D, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2Drr, X86_INS_VPERMI2D, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2PDrm, X86_INS_VPERMI2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2PDrr, X86_INS_VPERMI2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2PSrm, X86_INS_VPERMI2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2PSrr, X86_INS_VPERMI2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2Qrm, X86_INS_VPERMI2Q, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMI2Qrr, X86_INS_VPERMI2Q, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PDmrY, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PDrmY, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PDrrY, X86_INS_VPERMIL2PD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSmrY, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSrmY, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMIL2PSrrY, X86_INS_VPERMIL2PS, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPERMILPDYmi, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDYri, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDYrm, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDYrr, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDZmi, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMILPDZri, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMILPDmi, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDri, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDrm, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPDrr, X86_INS_VPERMILPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSYmi, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSYri, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSYrm, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSYrr, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSZmi, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMILPSZri, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMILPSmi, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSri, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSrm, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMILPSrr, X86_INS_VPERMILPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPERMPDYmi, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMPDYri, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMPDZmi, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMPDZri, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMPDZrm, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMPDZrr, X86_INS_VPERMPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMPSYrm, X86_INS_VPERMPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMPSYrr, X86_INS_VPERMPS, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMPSZrm, X86_INS_VPERMPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMPSZrr, X86_INS_VPERMPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMQYmi, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMQYri, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPERMQZmi, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMQZri, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMQZrm, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMQZrr, X86_INS_VPERMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2Drm, X86_INS_VPERMT2D, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2Drr, X86_INS_VPERMT2D, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2PDrm, X86_INS_VPERMT2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2PDrr, X86_INS_VPERMT2PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2PSrm, X86_INS_VPERMT2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2PSrr, X86_INS_VPERMT2PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2Qrm, X86_INS_VPERMT2Q, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPERMT2Qrr, X86_INS_VPERMT2Q, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPEXTRBmr, X86_INS_VPEXTRB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRBrr, X86_INS_VPEXTRB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRDmr, X86_INS_VPEXTRD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRDrr, X86_INS_VPEXTRD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRQmr, X86_INS_VPEXTRQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRQrr, X86_INS_VPEXTRQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRWmr, X86_INS_VPEXTRW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRWri, X86_INS_VPEXTRW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPEXTRWrr_REV, X86_INS_VPEXTRW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPGATHERDDYrm, X86_INS_VPGATHERDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERDDZrm, X86_INS_VPGATHERDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPGATHERDDrm, X86_INS_VPGATHERDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPGATHERDQrm, X86_INS_VPGATHERDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERQDYrm, X86_INS_VPGATHERQD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERQDZrm, X86_INS_VPGATHERQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPGATHERQDrm, X86_INS_VPGATHERQD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPGATHERQQrm, X86_INS_VPGATHERQQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDBDrm, X86_INS_VPHADDBD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDBDrr, X86_INS_VPHADDBD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDBQrm, X86_INS_VPHADDBQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDBQrr, X86_INS_VPHADDBQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDBWrm, X86_INS_VPHADDBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDBWrr, X86_INS_VPHADDBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDDQrm, X86_INS_VPHADDDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDDQrr, X86_INS_VPHADDDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDDYrm, X86_INS_VPHADDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDDYrr, X86_INS_VPHADDD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDDrm, X86_INS_VPHADDD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHADDDrr, X86_INS_VPHADDD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHADDSWrm128, X86_INS_VPHADDSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHADDSWrm256, X86_INS_VPHADDSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDSWrr128, X86_INS_VPHADDSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHADDSWrr256, X86_INS_VPHADDSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDUBDrm, X86_INS_VPHADDUBD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUBDrr, X86_INS_VPHADDUBD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUBQrm, X86_INS_VPHADDUBQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUBQrr, X86_INS_VPHADDUBQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUBWrm, X86_INS_VPHADDUBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUBWrr, X86_INS_VPHADDUBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUDQrm, X86_INS_VPHADDUDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUDQrr, X86_INS_VPHADDUDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUWDrm, X86_INS_VPHADDUWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUWDrr, X86_INS_VPHADDUWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUWQrm, X86_INS_VPHADDUWQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDUWQrr, X86_INS_VPHADDUWQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDWDrm, X86_INS_VPHADDWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDWDrr, X86_INS_VPHADDWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDWQrm, X86_INS_VPHADDWQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDWQrr, X86_INS_VPHADDWQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHADDWYrm, X86_INS_VPHADDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDWYrr, X86_INS_VPHADDW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHADDWrm, X86_INS_VPHADDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHADDWrr, X86_INS_VPHADDW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHMINPOSUWrm128, X86_INS_VPHMINPOSUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHMINPOSUWrr128, X86_INS_VPHMINPOSUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBBWrm, X86_INS_VPHSUBBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBBWrr, X86_INS_VPHSUBBW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBDQrm, X86_INS_VPHSUBDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBDQrr, X86_INS_VPHSUBDQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBDYrm, X86_INS_VPHSUBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBDYrr, X86_INS_VPHSUBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBDrm, X86_INS_VPHSUBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBDrr, X86_INS_VPHSUBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBSWrm128, X86_INS_VPHSUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBSWrm256, X86_INS_VPHSUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBSWrr128, X86_INS_VPHSUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBSWrr256, X86_INS_VPHSUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBWDrm, X86_INS_VPHSUBWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBWDrr, X86_INS_VPHSUBWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPHSUBWYrm, X86_INS_VPHSUBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBWYrr, X86_INS_VPHSUBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPHSUBWrm, X86_INS_VPHSUBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPHSUBWrr, X86_INS_VPHSUBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRBrm, X86_INS_VPINSRB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRBrr, X86_INS_VPINSRB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRDrm, X86_INS_VPINSRD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRDrr, X86_INS_VPINSRD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRQrm, X86_INS_VPINSRQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRQrr, X86_INS_VPINSRQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRWrmi, X86_INS_VPINSRW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPINSRWrri, X86_INS_VPINSRW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMACSDDrm, X86_INS_VPMACSDD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSDDrr, X86_INS_VPMACSDD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSDQHrm, X86_INS_VPMACSDQH, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSDQHrr, X86_INS_VPMACSDQH, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSDQLrm, X86_INS_VPMACSDQL, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSDQLrr, X86_INS_VPMACSDQL, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDDrm, X86_INS_VPMACSSDD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDDrr, X86_INS_VPMACSSDD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSWDrm, X86_INS_VPMACSSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSWDrr, X86_INS_VPMACSSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSWWrm, X86_INS_VPMACSSWW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSSWWrr, X86_INS_VPMACSSWW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSWDrm, X86_INS_VPMACSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSWDrr, X86_INS_VPMACSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSWWrm, X86_INS_VPMACSWW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMACSWWrr, X86_INS_VPMACSWW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMADCSWDrm, X86_INS_VPMADCSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMADCSWDrr, X86_INS_VPMADCSWD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPMADDUBSWrm128, X86_INS_VPMADDUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMADDUBSWrm256, X86_INS_VPMADDUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMADDUBSWrr128, X86_INS_VPMADDUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMADDUBSWrr256, X86_INS_VPMADDUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMADDWDYrm, X86_INS_VPMADDWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMADDWDYrr, X86_INS_VPMADDWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMADDWDrm, X86_INS_VPMADDWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMADDWDrr, X86_INS_VPMADDWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSBYrm, X86_INS_VPMAXSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSBYrr, X86_INS_VPMAXSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSBrm, X86_INS_VPMAXSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXSBrr, X86_INS_VPMAXSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXSDYrm, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSDYrr, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSDZrm, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSDZrmb, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSDZrr, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSDrm, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXSDrr, X86_INS_VPMAXSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXSQZrm, X86_INS_VPMAXSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSQZrmb, X86_INS_VPMAXSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSQZrr, X86_INS_VPMAXSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXSWYrm, X86_INS_VPMAXSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSWYrr, X86_INS_VPMAXSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXSWrm, X86_INS_VPMAXSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXSWrr, X86_INS_VPMAXSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUBYrm, X86_INS_VPMAXUB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUBYrr, X86_INS_VPMAXUB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUBrm, X86_INS_VPMAXUB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUBrr, X86_INS_VPMAXUB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUDYrm, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUDYrr, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUDZrm, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUDZrmb, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUDZrr, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUDrm, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUDrr, X86_INS_VPMAXUD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUQZrm, X86_INS_VPMAXUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUQZrmb, X86_INS_VPMAXUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUQZrr, X86_INS_VPMAXUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMAXUWYrm, X86_INS_VPMAXUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUWYrr, X86_INS_VPMAXUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMAXUWrm, X86_INS_VPMAXUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMAXUWrr, X86_INS_VPMAXUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSBYrm, X86_INS_VPMINSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSBYrr, X86_INS_VPMINSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSBrm, X86_INS_VPMINSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSBrr, X86_INS_VPMINSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSDYrm, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSDYrr, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSDZrm, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSDZrmb, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSDZrr, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSDrm, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSDrr, X86_INS_VPMINSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSQZrm, X86_INS_VPMINSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSQZrmb, X86_INS_VPMINSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSQZrr, X86_INS_VPMINSQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINSWYrm, X86_INS_VPMINSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSWYrr, X86_INS_VPMINSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINSWrm, X86_INS_VPMINSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINSWrr, X86_INS_VPMINSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUBYrm, X86_INS_VPMINUB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUBYrr, X86_INS_VPMINUB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUBrm, X86_INS_VPMINUB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUBrr, X86_INS_VPMINUB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUDYrm, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUDYrr, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUDZrm, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUDZrmb, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUDZrr, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUDrm, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUDrr, X86_INS_VPMINUD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUQZrm, X86_INS_VPMINUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUQZrmb, X86_INS_VPMINUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUQZrr, X86_INS_VPMINUQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMINUWYrm, X86_INS_VPMINUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUWYrr, X86_INS_VPMINUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMINUWrm, X86_INS_VPMINUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMINUWrr, X86_INS_VPMINUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVDBkrr, X86_INS_VPMOVDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVDBmr, X86_INS_VPMOVDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVDBrr, X86_INS_VPMOVDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVDWkrr, X86_INS_VPMOVDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVDWmr, X86_INS_VPMOVDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVDWrr, X86_INS_VPMOVDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVQBkrr, X86_INS_VPMOVQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQBmr, X86_INS_VPMOVQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQBrr, X86_INS_VPMOVQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQDkrr, X86_INS_VPMOVQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQDmr, X86_INS_VPMOVQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQDrr, X86_INS_VPMOVQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQWkrr, X86_INS_VPMOVQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQWmr, X86_INS_VPMOVQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVQWrr, X86_INS_VPMOVQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDBkrr, X86_INS_VPMOVSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDBmr, X86_INS_VPMOVSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDBrr, X86_INS_VPMOVSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDWkrr, X86_INS_VPMOVSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDWmr, X86_INS_VPMOVSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSDWrr, X86_INS_VPMOVSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQBkrr, X86_INS_VPMOVSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQBmr, X86_INS_VPMOVSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQBrr, X86_INS_VPMOVSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQDkrr, X86_INS_VPMOVSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQDmr, X86_INS_VPMOVSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQDrr, X86_INS_VPMOVSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQWkrr, X86_INS_VPMOVSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQWmr, X86_INS_VPMOVSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSQWrr, X86_INS_VPMOVSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVUSDBkrr, X86_INS_VPMOVUSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSDBmr, X86_INS_VPMOVUSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSDBrr, X86_INS_VPMOVUSDB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSDWkrr, X86_INS_VPMOVUSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSDWmr, X86_INS_VPMOVUSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSDWrr, X86_INS_VPMOVUSDW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQBkrr, X86_INS_VPMOVUSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQBmr, X86_INS_VPMOVUSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQBrr, X86_INS_VPMOVUSQB, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQDkrr, X86_INS_VPMOVUSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQDmr, X86_INS_VPMOVUSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQDrr, X86_INS_VPMOVUSQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQWkrr, X86_INS_VPMOVUSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQWmr, X86_INS_VPMOVUSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVUSQWrr, X86_INS_VPMOVUSQW, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULDQYrm, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULDQYrr, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULDQZrm, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULDQZrr, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULDQrm, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULDQrr, X86_INS_VPMULDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHRSWrm128, X86_INS_VPMULHRSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHRSWrm256, X86_INS_VPMULHRSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHRSWrr128, X86_INS_VPMULHRSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHRSWrr256, X86_INS_VPMULHRSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHUWYrm, X86_INS_VPMULHUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHUWYrr, X86_INS_VPMULHUW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHUWrm, X86_INS_VPMULHUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHUWrr, X86_INS_VPMULHUW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHWYrm, X86_INS_VPMULHW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHWYrr, X86_INS_VPMULHW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULHWrm, X86_INS_VPMULHW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULHWrr, X86_INS_VPMULHW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULLDYrm, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULLDYrr, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULLDZrm, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULLDZrmb, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULLDZrr, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULLDrm, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULLDrr, X86_INS_VPMULLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULLWYrm, X86_INS_VPMULLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULLWYrr, X86_INS_VPMULLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULLWrm, X86_INS_VPMULLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULLWrr, X86_INS_VPMULLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULUDQYrm, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULUDQYrr, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPMULUDQZrm, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULUDQZrr, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPMULUDQrm, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPMULUDQrr, X86_INS_VPMULUDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPORDZrm, X86_INS_VPORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORDZrmb, X86_INS_VPORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORDZrr, X86_INS_VPORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORQZrm, X86_INS_VPORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORQZrmb, X86_INS_VPORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORQZrr, X86_INS_VPORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPORYrm, X86_INS_VPOR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPORYrr, X86_INS_VPOR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPORrm, X86_INS_VPOR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPORrr, X86_INS_VPOR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPPERMmr, X86_INS_VPPERM, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPPERMrm, X86_INS_VPPERM, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPPERMrr, X86_INS_VPPERM, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTBmi, X86_INS_VPROTB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTBmr, X86_INS_VPROTB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTBri, X86_INS_VPROTB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTBrm, X86_INS_VPROTB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTBrr, X86_INS_VPROTB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTDmi, X86_INS_VPROTD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTDmr, X86_INS_VPROTD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTDri, X86_INS_VPROTD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTDrm, X86_INS_VPROTD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTDrr, X86_INS_VPROTD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTQmi, X86_INS_VPROTQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTQmr, X86_INS_VPROTQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTQri, X86_INS_VPROTQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTQrm, X86_INS_VPROTQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTQrr, X86_INS_VPROTQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTWmi, X86_INS_VPROTW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTWmr, X86_INS_VPROTW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTWri, X86_INS_VPROTW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTWrm, X86_INS_VPROTW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPROTWrr, X86_INS_VPROTW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSADBWYrm, X86_INS_VPSADBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSADBWYrr, X86_INS_VPSADBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSADBWrm, X86_INS_VPSADBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSADBWrr, X86_INS_VPSADBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSHABmr, X86_INS_VPSHAB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHABrm, X86_INS_VPSHAB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHABrr, X86_INS_VPSHAB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHADmr, X86_INS_VPSHAD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHADrm, X86_INS_VPSHAD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHADrr, X86_INS_VPSHAD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAQmr, X86_INS_VPSHAQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAQrm, X86_INS_VPSHAQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAQrr, X86_INS_VPSHAQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAWmr, X86_INS_VPSHAW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAWrm, X86_INS_VPSHAW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHAWrr, X86_INS_VPSHAW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLBmr, X86_INS_VPSHLB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLBrm, X86_INS_VPSHLB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLBrr, X86_INS_VPSHLB, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLDmr, X86_INS_VPSHLD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLDrm, X86_INS_VPSHLD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLDrr, X86_INS_VPSHLD, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLQmr, X86_INS_VPSHLQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLQrm, X86_INS_VPSHLQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLQrr, X86_INS_VPSHLQ, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLWmr, X86_INS_VPSHLW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLWrm, X86_INS_VPSHLW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHLWrr, X86_INS_VPSHLW, { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 },
- { X86_VPSHUFBYrm, X86_INS_VPSHUFB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFBYrr, X86_INS_VPSHUFB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFBrm, X86_INS_VPSHUFB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFBrr, X86_INS_VPSHUFB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFDYmi, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFDYri, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFDZmi, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSHUFDZri, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSHUFDmi, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFDri, X86_INS_VPSHUFD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFHWYmi, X86_INS_VPSHUFHW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFHWYri, X86_INS_VPSHUFHW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFHWmi, X86_INS_VPSHUFHW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFHWri, X86_INS_VPSHUFHW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFLWYmi, X86_INS_VPSHUFLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFLWYri, X86_INS_VPSHUFLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSHUFLWmi, X86_INS_VPSHUFLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSHUFLWri, X86_INS_VPSHUFLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNBYrm, X86_INS_VPSIGNB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNBYrr, X86_INS_VPSIGNB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNBrm, X86_INS_VPSIGNB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNBrr, X86_INS_VPSIGNB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNDYrm, X86_INS_VPSIGND, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNDYrr, X86_INS_VPSIGND, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNDrm, X86_INS_VPSIGND, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNDrr, X86_INS_VPSIGND, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNWYrm, X86_INS_VPSIGNW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNWYrr, X86_INS_VPSIGNW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSIGNWrm, X86_INS_VPSIGNW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSIGNWrr, X86_INS_VPSIGNW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLDQYri, X86_INS_VPSLLDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLDQri, X86_INS_VPSLLDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLDYri, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLDYrm, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLDYrr, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLDZmi, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZmik, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZri, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZrik, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZrm, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZrmk, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZrr, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDZrrk, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLDri, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLDrm, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLDrr, X86_INS_VPSLLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLQYri, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLQYrm, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLQYrr, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLQZmi, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZmik, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZri, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZrik, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZrm, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZrmk, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZrr, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQZrrk, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLQri, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLQrm, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLQrr, X86_INS_VPSLLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLVDYrm, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVDYrr, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVDZrm, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLVDZrr, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLVDrm, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVDrr, X86_INS_VPSLLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVQYrm, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVQYrr, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVQZrm, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLVQZrr, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSLLVQrm, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLVQrr, X86_INS_VPSLLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLWYri, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLWYrm, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLWYrr, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSLLWri, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLWrm, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSLLWrr, X86_INS_VPSLLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRADYri, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRADYrm, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRADYrr, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRADZmi, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZmik, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZri, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZrik, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZrm, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZrmk, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZrr, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADZrrk, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRADri, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRADrm, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRADrr, X86_INS_VPSRAD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRAQZmi, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZmik, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZri, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZrik, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZrm, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZrmk, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZrr, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAQZrrk, X86_INS_VPSRAQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAVDYrm, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAVDYrr, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAVDZrm, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAVDZrr, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAVDrm, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAVDrr, X86_INS_VPSRAVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAVQZrm, X86_INS_VPSRAVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAVQZrr, X86_INS_VPSRAVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRAWYri, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAWYrm, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAWYrr, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRAWri, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRAWrm, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRAWrr, X86_INS_VPSRAW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLDQYri, X86_INS_VPSRLDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLDQri, X86_INS_VPSRLDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLDYri, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLDYrm, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLDYrr, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLDZmi, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZmik, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZri, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZrik, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZrm, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZrmk, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZrr, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDZrrk, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLDri, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLDrm, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLDrr, X86_INS_VPSRLD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLQYri, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLQYrm, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLQYrr, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLQZmi, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZmik, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZri, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZrik, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZrm, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZrmk, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZrr, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQZrrk, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLQri, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLQrm, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLQrr, X86_INS_VPSRLQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLVDYrm, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVDYrr, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVDZrm, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLVDZrr, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLVDrm, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVDrr, X86_INS_VPSRLVD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVQYrm, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVQYrr, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVQZrm, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLVQZrr, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSRLVQrm, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLVQrr, X86_INS_VPSRLVQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLWYri, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLWYrm, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLWYrr, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSRLWri, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLWrm, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSRLWrr, X86_INS_VPSRLW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBBYrm, X86_INS_VPSUBB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBBYrr, X86_INS_VPSUBB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBBrm, X86_INS_VPSUBB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBBrr, X86_INS_VPSUBB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBDYrm, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBDYrr, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBDZrm, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBDZrmb, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBDZrr, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBDrm, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBDrr, X86_INS_VPSUBD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBQYrm, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBQYrr, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBQZrm, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBQZrmb, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBQZrr, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPSUBQrm, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBQrr, X86_INS_VPSUBQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBSBYrm, X86_INS_VPSUBSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBSBYrr, X86_INS_VPSUBSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBSBrm, X86_INS_VPSUBSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBSBrr, X86_INS_VPSUBSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBSWYrm, X86_INS_VPSUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBSWYrr, X86_INS_VPSUBSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBSWrm, X86_INS_VPSUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBSWrr, X86_INS_VPSUBSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBUSBYrm, X86_INS_VPSUBUSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBUSBYrr, X86_INS_VPSUBUSB, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBUSBrm, X86_INS_VPSUBUSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBUSBrr, X86_INS_VPSUBUSB, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBUSWYrm, X86_INS_VPSUBUSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBUSWYrr, X86_INS_VPSUBUSW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBUSWrm, X86_INS_VPSUBUSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBUSWrr, X86_INS_VPSUBUSW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBWYrm, X86_INS_VPSUBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBWYrr, X86_INS_VPSUBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPSUBWrm, X86_INS_VPSUBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPSUBWrr, X86_INS_VPSUBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPTESTMDZrm, X86_INS_VPTESTMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPTESTMDZrr, X86_INS_VPTESTMD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPTESTMQZrm, X86_INS_VPTESTMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPTESTMQZrr, X86_INS_VPTESTMQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPTESTNMDZrm, X86_INS_VPTESTNMD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPTESTNMDZrr, X86_INS_VPTESTNMD, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ, { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 },
- { X86_VPTESTYrm, X86_INS_VPTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPTESTYrr, X86_INS_VPTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPTESTrm, X86_INS_VPTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPTESTrr, X86_INS_VPTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPXORDZrm, X86_INS_VPXORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORDZrmb, X86_INS_VPXORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORDZrr, X86_INS_VPXORD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORQZrm, X86_INS_VPXORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORQZrmb, X86_INS_VPXORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORQZrr, X86_INS_VPXORQ, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VPXORYrm, X86_INS_VPXOR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPXORYrr, X86_INS_VPXOR, { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 },
- { X86_VPXORrm, X86_INS_VPXOR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VPXORrr, X86_INS_VPXOR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCP14PDZm, X86_INS_VRCP14PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14PDZr, X86_INS_VRCP14PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14PSZm, X86_INS_VRCP14PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14PSZr, X86_INS_VRCP14PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14SDrm, X86_INS_VRCP14SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14SDrr, X86_INS_VRCP14SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14SSrm, X86_INS_VRCP14SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP14SSrr, X86_INS_VRCP14SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRCP28PDZm, X86_INS_VRCP28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28PDZr, X86_INS_VRCP28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28PDZrb, X86_INS_VRCP28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28PSZm, X86_INS_VRCP28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28PSZr, X86_INS_VRCP28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28PSZrb, X86_INS_VRCP28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SDrm, X86_INS_VRCP28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SDrr, X86_INS_VRCP28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SDrrb, X86_INS_VRCP28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SSrm, X86_INS_VRCP28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SSrr, X86_INS_VRCP28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCP28SSrrb, X86_INS_VRCP28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRCPPSYm, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSYm_Int, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSYr, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSYr_Int, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSm, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSm_Int, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSr, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPPSr_Int, X86_INS_VRCPPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPSSm, X86_INS_VRCPSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPSSm_Int, X86_INS_VRCPSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRCPSSr, X86_INS_VRCPSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRNDSCALEPDZm, X86_INS_VRNDSCALEPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALEPDZr, X86_INS_VRNDSCALEPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALEPSZm, X86_INS_VRNDSCALEPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALEPSZr, X86_INS_VRNDSCALEPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALESDm, X86_INS_VRNDSCALESD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALESDr, X86_INS_VRNDSCALESD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALESSm, X86_INS_VRNDSCALESS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRNDSCALESSr, X86_INS_VRNDSCALESS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VROUNDPDm, X86_INS_VROUNDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDPDr, X86_INS_VROUNDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDPSm, X86_INS_VROUNDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDPSr, X86_INS_VROUNDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSDm, X86_INS_VROUNDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSDr, X86_INS_VROUNDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSDr_Int, X86_INS_VROUNDSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSSm, X86_INS_VROUNDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSSr, X86_INS_VROUNDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDSSr_Int, X86_INS_VROUNDSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDYPDm, X86_INS_VROUNDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDYPDr, X86_INS_VROUNDPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDYPSm, X86_INS_VROUNDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VROUNDYPSr, X86_INS_VROUNDPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14SDrm, X86_INS_VRSQRT14SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14SDrr, X86_INS_VRSQRT14SD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14SSrm, X86_INS_VRSQRT14SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT14SSrr, X86_INS_VRSQRT14SS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SDrm, X86_INS_VRSQRT28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SDrr, X86_INS_VRSQRT28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SDrrb, X86_INS_VRSQRT28SD, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SSrm, X86_INS_VRSQRT28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SSrr, X86_INS_VRSQRT28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRT28SSrrb, X86_INS_VRSQRT28SS, { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0 },
- { X86_VRSQRTPSYm, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSYm_Int, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSYr, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSYr_Int, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSm, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSm_Int, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSr, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTPSr_Int, X86_INS_VRSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTSSm, X86_INS_VRSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VRSQRTSSr, X86_INS_VRSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSHUFPDYrmi, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPDYrri, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPDZrmi, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSHUFPDZrri, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSHUFPDrmi, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPDrri, X86_INS_VSHUFPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPSYrmi, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPSYrri, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPSZrmi, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSHUFPSZrri, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSHUFPSrmi, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSHUFPSrri, X86_INS_VSHUFPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPDYm, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPDYr, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPDZm_Int, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPDZr_Int, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPDZrm, X86_INS_VSQRT, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPDZrr, X86_INS_VSQRT, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPDm, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPDr, X86_INS_VSQRTPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPSYm, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPSYr, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPSZm_Int, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPSZr_Int, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPSZrm, X86_INS_VSQRT, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPSZrr, X86_INS_VSQRT, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTPSm, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTPSr, X86_INS_VSQRTPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSDZm, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSDZm_Int, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSDZr, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSDZr_Int, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSDm, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSDm_Int, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSDr, X86_INS_VSQRTSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSSZm, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSSZm_Int, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSSZr, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSSZr_Int, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSQRTSSm, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSSm_Int, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSQRTSSr, X86_INS_VSQRTSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSTMXCSR, X86_INS_VSTMXCSR, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPDYrm, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPDYrr, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPDZrm, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPDZrmb, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPDZrr, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPDrm, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPDrr, X86_INS_VSUBPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPSYrm, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPSYrr, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPSZrm, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPSZrmb, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPSZrr, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBPSrm, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBPSrr, X86_INS_VSUBPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSDZrm, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBSDZrr, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBSDrm, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSDrm_Int, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSDrr, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSDrr_Int, X86_INS_VSUBSD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSSZrm, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBSSZrr, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VSUBSSrm, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSSrm_Int, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSSrr, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VSUBSSrr_Int, X86_INS_VSUBSS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPDYrm, X86_INS_VTESTPD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPDYrr, X86_INS_VTESTPD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPDrm, X86_INS_VTESTPD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPDrr, X86_INS_VTESTPD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPSYrm, X86_INS_VTESTPS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPSYrr, X86_INS_VTESTPS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPSrm, X86_INS_VTESTPS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VTESTPSrr, X86_INS_VTESTPS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUCOMISDZrm, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUCOMISDZrr, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUCOMISDrm, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUCOMISDrr, X86_INS_VUCOMISD, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUCOMISSZrm, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUCOMISSZrr, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUCOMISSrm, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUCOMISSrr, X86_INS_VUCOMISS, { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 },
- { X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPDYrm, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPDYrr, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPDrm, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPDrr, X86_INS_VXORPD, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPSYrm, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPSYrr, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPSrm, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VXORPSrr, X86_INS_VXORPS, { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VZEROALL, X86_INS_VZEROALL, { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_VZEROUPPER, X86_INS_VZEROUPPER, { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 },
- { X86_W64ALLOCA, X86_INS_CALL, { X86_REG_RSP, 0 }, { X86_REG_RAX, X86_REG_R10, X86_REG_R11, X86_REG_RSP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_WAIT, X86_INS_WAIT, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_WBINVD, X86_INS_WBINVD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_WRFSBASE, X86_INS_WRFSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_WRFSBASE64, X86_INS_WRFSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_WRGSBASE, X86_INS_WRGSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_WRGSBASE64, X86_INS_WRGSBASE, { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_WRMSR, X86_INS_WRMSR, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XABORT, X86_INS_XABORT, { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 },
- { X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE, { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 },
- { X86_XADD16rm, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD16rr, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD32rm, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD32rr, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD64rm, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD64rr, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD8rm, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XADD8rr, X86_INS_XADD, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XBEGIN_4, X86_INS_XBEGIN, { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_RTM, 0 }, 1, 0 },
- { X86_XCHG16ar, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG16rm, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG16rr, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG32ar, X86_INS_XCHG, { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 },
- { X86_XCHG32ar64, X86_INS_XCHG, { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_XCHG32rm, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG32rr, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG64ar, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG64rm, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG64rr, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG8rm, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCHG8rr, X86_INS_XCHG, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XCH_F, X86_INS_FXCH, { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 },
- { X86_XCRYPTCBC, X86_INS_XCRYPTCBC, { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XCRYPTCFB, X86_INS_XCRYPTCFB, { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XCRYPTCTR, X86_INS_XCRYPTCTR, { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XCRYPTECB, X86_INS_XCRYPTECB, { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XCRYPTOFB, X86_INS_XCRYPTOFB, { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XEND, X86_INS_XEND, { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 },
- { X86_XGETBV, X86_INS_XGETBV, { X86_REG_RCX, 0 }, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, 0, 0 },
- { X86_XLAT, X86_INS_XLATB, { 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XOR16i16, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16ri, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16ri8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16rm, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16rr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR16rr_REV, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32i32, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32ri, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32ri8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32rm, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32rr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR32rr_REV, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64i32, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64mi32, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64mi8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64ri32, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64ri8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64rm, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64rr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR64rr_REV, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8i8, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8mi, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8mr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8ri, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8rm, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8rr, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XOR8rr_REV, X86_INS_XOR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
- { X86_XORPDrm, X86_INS_XORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_XORPDrr, X86_INS_XORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
- { X86_XORPSrm, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_XORPSrr, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
- { X86_XRELEASE_PREFIX, X86_INS_XRELEASE, { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 },
- { X86_XRSTOR, X86_INS_XRSTOR, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XRSTOR64, X86_INS_XRSTOR64, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_XSAVE, X86_INS_XSAVE, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XSAVE64, X86_INS_XSAVE64, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_XSAVEOPT, X86_INS_XSAVEOPT, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XSAVEOPT64, X86_INS_XSAVEOPT64, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 },
- { X86_XSETBV, X86_INS_XSETBV, { X86_REG_RDX, X86_REG_RAX, X86_REG_RCX, 0 }, { 0 }, { 0 }, 0, 0 },
- { X86_XSHA1, X86_INS_XSHA1, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XSHA256, X86_INS_XSHA256, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XSTORE, X86_INS_XSTORE, { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0 },
- { X86_XTEST, X86_INS_XTEST, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
+ {
+ X86_AAA, X86_INS_AAA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AAD8i8, X86_INS_AAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AAM8i8, X86_INS_AAM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AAS, X86_INS_AAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ABS_F, X86_INS_FABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16i16, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16mi, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16mi8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16mr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16ri, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16ri8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16rm, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16rr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC16rr_REV, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32i32, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32mi, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32mi8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32mr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32ri, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32ri8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32rm, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32rr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC32rr_REV, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64i32, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64mi32, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64mi8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64mr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64ri32, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64ri8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64rm, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64rr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC64rr_REV, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8i8, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8mi, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8mr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8ri, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8rm, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8rr, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADC8rr_REV, X86_INS_ADC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADCX32rm, X86_INS_ADCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADCX32rr, X86_INS_ADCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADCX64rm, X86_INS_ADCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADCX64rr, X86_INS_ADCX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16i16, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16ri, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16ri8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16rm, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16rr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD16rr_REV, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32i32, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32ri, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32ri8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32rm, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32rr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD32rr_REV, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64i32, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64mi32, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64ri32, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64ri8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64rm, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64rr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD64rr_REV, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8i8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8ri, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8rm, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8rr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD8rr_REV, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDPDrm, X86_INS_ADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDPDrr, X86_INS_ADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDPSrm, X86_INS_ADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDPSrr, X86_INS_ADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSDrm, X86_INS_ADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSDrm_Int, X86_INS_ADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSDrr, X86_INS_ADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSDrr_Int, X86_INS_ADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSSrm, X86_INS_ADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSSrm_Int, X86_INS_ADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSSrr, X86_INS_ADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSSrr_Int, X86_INS_ADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSUBPDrm, X86_INS_ADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSUBPDrr, X86_INS_ADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSUBPSrm, X86_INS_ADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADDSUBPSrr, X86_INS_ADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_F32m, X86_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_F64m, X86_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_FI16m, X86_INS_FIADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_FI32m, X86_INS_FIADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_FPrST0, X86_INS_FADDP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_FST0r, X86_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADD_FrST0, X86_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADOX32rm, X86_INS_ADOX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADOX32rr, X86_INS_ADOX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADOX64rm, X86_INS_ADOX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ADOX64rr, X86_INS_ADOX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESDECLASTrm, X86_INS_AESDECLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESDECLASTrr, X86_INS_AESDECLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESDECrm, X86_INS_AESDEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESDECrr, X86_INS_AESDEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESENCLASTrm, X86_INS_AESENCLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESENCLASTrr, X86_INS_AESENCLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESENCrm, X86_INS_AESENC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESENCrr, X86_INS_AESENC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESIMCrm, X86_INS_AESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESIMCrr, X86_INS_AESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16i16, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16ri, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16ri8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16rm, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16rr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND16rr_REV, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32i32, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32ri, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32ri8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32rm, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32rr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND32rr_REV, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64i32, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64mi32, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64ri32, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64ri8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64rm, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64rr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND64rr_REV, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8i8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8ri, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8rm, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8rr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_AND8rr_REV, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDN32rm, X86_INS_ANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDN32rr, X86_INS_ANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDN64rm, X86_INS_ANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDN64rr, X86_INS_ANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDNPDrm, X86_INS_ANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDNPDrr, X86_INS_ANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDNPSrm, X86_INS_ANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDNPSrr, X86_INS_ANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDPDrm, X86_INS_ANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDPDrr, X86_INS_ANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDPSrm, X86_INS_ANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ANDPSrr, X86_INS_ANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ARPL16mr, X86_INS_ARPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ARPL16rr, X86_INS_ARPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTR32rm, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTR32rr, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTR64rm, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTR64rr, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTRI32mi, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTRI32ri, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTRI64mi, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BEXTRI64ri, X86_INS_BEXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCFILL32rm, X86_INS_BLCFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCFILL32rr, X86_INS_BLCFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCFILL64rm, X86_INS_BLCFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCFILL64rr, X86_INS_BLCFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCI32rm, X86_INS_BLCI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCI32rr, X86_INS_BLCI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCI64rm, X86_INS_BLCI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCI64rr, X86_INS_BLCI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCIC32rm, X86_INS_BLCIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCIC32rr, X86_INS_BLCIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCIC64rm, X86_INS_BLCIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCIC64rr, X86_INS_BLCIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCMSK32rm, X86_INS_BLCMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCMSK32rr, X86_INS_BLCMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCMSK64rm, X86_INS_BLCMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCMSK64rr, X86_INS_BLCMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCS32rm, X86_INS_BLCS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCS32rr, X86_INS_BLCS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCS64rm, X86_INS_BLCS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLCS64rr, X86_INS_BLCS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDPDrmi, X86_INS_BLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDPDrri, X86_INS_BLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDPSrmi, X86_INS_BLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDPSrri, X86_INS_BLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDVPDrm0, X86_INS_BLENDVPD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDVPDrr0, X86_INS_BLENDVPD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDVPSrm0, X86_INS_BLENDVPS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLENDVPSrr0, X86_INS_BLENDVPS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSFILL32rm, X86_INS_BLSFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSFILL32rr, X86_INS_BLSFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSFILL64rm, X86_INS_BLSFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSFILL64rr, X86_INS_BLSFILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSI32rm, X86_INS_BLSI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSI32rr, X86_INS_BLSI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSI64rm, X86_INS_BLSI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSI64rr, X86_INS_BLSI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSIC32rm, X86_INS_BLSIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSIC32rr, X86_INS_BLSIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSIC64rm, X86_INS_BLSIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSIC64rr, X86_INS_BLSIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSMSK32rm, X86_INS_BLSMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSMSK32rr, X86_INS_BLSMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSMSK64rm, X86_INS_BLSMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSMSK64rr, X86_INS_BLSMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSR32rm, X86_INS_BLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSR32rr, X86_INS_BLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSR64rm, X86_INS_BLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BLSR64rr, X86_INS_BLSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BOUNDS16rm, X86_INS_BOUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BOUNDS32rm, X86_INS_BOUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF16rm, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF16rr, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF32rm, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF32rr, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF64rm, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSF64rr, X86_INS_BSF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR16rm, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR16rr, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR32rm, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR32rr, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR64rm, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSR64rr, X86_INS_BSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSWAP32r, X86_INS_BSWAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BSWAP64r, X86_INS_BSWAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT16mi8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT16mr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT16ri8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT16rr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT32mi8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT32mr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT32ri8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT32rr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT64mi8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT64mr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT64ri8, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BT64rr, X86_INS_BT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC16mi8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC16mr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC16ri8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC16rr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC32mi8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC32mr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC32ri8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC32rr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC64mi8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC64mr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC64ri8, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTC64rr, X86_INS_BTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR16mi8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR16mr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR16ri8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR16rr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR32mi8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR32mr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR32ri8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR32rr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR64mi8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR64mr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR64ri8, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTR64rr, X86_INS_BTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS16mi8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS16mr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS16ri8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS16rr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS32mi8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS32mr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS32ri8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS32rr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS64mi8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS64mr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS64ri8, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BTS64rr, X86_INS_BTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BZHI32rm, X86_INS_BZHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BZHI32rr, X86_INS_BZHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BZHI64rm, X86_INS_BZHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_BZHI64rr, X86_INS_BZHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL16m, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL16r, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL32m, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL32r, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL64m, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL64pcrel32, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALL64r, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALLpcrel16, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CALLpcrel32, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CBW, X86_INS_CBW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CDQ, X86_INS_CDQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CDQE, X86_INS_CDQE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CHS_F, X86_INS_FCHS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLAC, X86_INS_CLAC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLC, X86_INS_CLC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLD, X86_INS_CLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLFLUSH, X86_INS_CLFLUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLGI, X86_INS_CLGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLI, X86_INS_CLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CLTS, X86_INS_CLTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMC, X86_INS_CMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA16rm, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA16rr, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA32rm, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA32rr, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA64rm, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVA64rr, X86_INS_CMOVA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE16rm, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE16rr, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE32rm, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE32rr, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE64rm, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVAE64rr, X86_INS_CMOVAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB16rm, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB16rr, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB32rm, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB32rr, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB64rm, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB64rr, X86_INS_CMOVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE16rm, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE16rr, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE32rm, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE32rr, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE64rm, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE64rr, X86_INS_CMOVBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVBE_F, X86_INS_FCMOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVB_F, X86_INS_FCMOVB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE16rm, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE16rr, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE32rm, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE32rr, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE64rm, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE64rr, X86_INS_CMOVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVE_F, X86_INS_FCMOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG16rm, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG16rr, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG32rm, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG32rr, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG64rm, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVG64rr, X86_INS_CMOVG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE16rm, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE16rr, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE32rm, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE32rr, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE64rm, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVGE64rr, X86_INS_CMOVGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL16rm, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL16rr, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL32rm, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL32rr, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL64rm, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVL64rr, X86_INS_CMOVL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE16rm, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE16rr, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE32rm, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE32rr, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE64rm, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVLE64rr, X86_INS_CMOVLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNBE_F, X86_INS_FCMOVNBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNB_F, X86_INS_FCMOVNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE16rm, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE16rr, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE32rm, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE32rr, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE64rm, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE64rr, X86_INS_CMOVNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNE_F, X86_INS_FCMOVNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO16rm, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO16rr, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO32rm, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO32rr, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO64rm, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNO64rr, X86_INS_CMOVNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP16rm, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP16rr, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP32rm, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP32rr, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP64rm, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP64rr, X86_INS_CMOVNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNP_F, X86_INS_FCMOVNU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS16rm, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS16rr, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS32rm, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS32rr, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS64rm, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVNS64rr, X86_INS_CMOVNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO16rm, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO16rr, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO32rm, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO32rr, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO64rm, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVO64rr, X86_INS_CMOVO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP16rm, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP16rr, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP32rm, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP32rr, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP64rm, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP64rr, X86_INS_CMOVP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVP_F, X86_INS_FCMOVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS16rm, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS16rr, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS32rm, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS32rr, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS64rm, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMOVS64rr, X86_INS_CMOVS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16i16, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16mi, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16mi8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16mr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16ri, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16ri8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16rm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16rr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP16rr_REV, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32i32, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32mi, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32mi8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32mr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32ri, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32ri8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32rm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32rr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP32rr_REV, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64i32, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64mi32, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64mi8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64mr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64ri32, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64ri8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64rm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64rr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP64rr_REV, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8i8, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8mi, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8mr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8ri, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8rm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8rr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMP8rr_REV, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPDrmi, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPDrmi_alt, X86_INS_CMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPDrri, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPDrri_alt, X86_INS_CMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPSrmi, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPSrmi_alt, X86_INS_CMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPSrri, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPPSrri_alt, X86_INS_CMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPS16, X86_INS_CMPSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPS32, X86_INS_CMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPS64, X86_INS_CMPSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPS8, X86_INS_CMPSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSDrm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSDrm_alt, X86_INS_CMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSDrr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSDrr_alt, X86_INS_CMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSSrm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSSrm_alt, X86_INS_CMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSSrr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPSSrr_alt, X86_INS_CMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG16B, X86_INS_CMPXCHG16B,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG16rm, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG16rr, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG32rm, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG32rr, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG64rm, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG64rr, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG8B, X86_INS_CMPXCHG8B,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG8rm, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CMPXCHG8rr, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COMISDrm, X86_INS_COMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COMISDrr, X86_INS_COMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COMISSrm, X86_INS_COMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COMISSrr, X86_INS_COMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COMP_FST0r, X86_INS_FCOMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COM_FIPr, X86_INS_FCOMPI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COM_FIr, X86_INS_FCOMI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COM_FST0r, X86_INS_FCOM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_COS_F, X86_INS_FCOS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CPUID32, X86_INS_CPUID,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CPUID64, X86_INS_CPUID,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RCX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CQO, X86_INS_CQO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32m16, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32m32, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32m8, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32r16, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32r32, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r32r8, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r64m64, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r64m8, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r64r64, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CRC32r64r8, X86_INS_CRC32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CS_PREFIX, X86_INS_CS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPD2DQrm, X86_INS_CVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPD2DQrr, X86_INS_CVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPD2PSrm, X86_INS_CVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPD2PSrr, X86_INS_CVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPS2DQrm, X86_INS_CVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPS2DQrr, X86_INS_CVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPS2PDrm, X86_INS_CVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTPS2PDrr, X86_INS_CVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SI64rm, X86_INS_CVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SI64rr, X86_INS_CVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SIrm, X86_INS_CVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SIrr, X86_INS_CVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SSrm, X86_INS_CVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSD2SSrr, X86_INS_CVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SD64rm, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SD64rr, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SDrm, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SDrr, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SS64rm, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SS64rr, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SSrm, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSI2SSrr, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SDrm, X86_INS_CVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SDrr, X86_INS_CVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SI64rm, X86_INS_CVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SI64rr, X86_INS_CVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SIrm, X86_INS_CVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTSS2SIrr, X86_INS_CVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CWD, X86_INS_CWD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_CWDE, X86_INS_CWDE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DAA, X86_INS_DAA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DAS, X86_INS_DAS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DATA16_PREFIX, X86_INS_DATA16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC16m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC16r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC32_16r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC32_32r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC32m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC32r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64_16m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64_16r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64_32m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64_32r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC64r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC8m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DEC8r, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV16m, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV16r, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV32m, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV32r, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV64m, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV64r, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV8m, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV8r, X86_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVPDrm, X86_INS_DIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVPDrr, X86_INS_DIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVPSrm, X86_INS_DIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVPSrr, X86_INS_DIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_F32m, X86_INS_FDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_F64m, X86_INS_FDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_FI16m, X86_INS_FIDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_FI32m, X86_INS_FIDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_FPrST0, X86_INS_FDIVRP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_FST0r, X86_INS_FDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVR_FrST0, X86_INS_FDIVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSDrm, X86_INS_DIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSDrm_Int, X86_INS_DIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSDrr, X86_INS_DIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSDrr_Int, X86_INS_DIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSSrm, X86_INS_DIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSSrm_Int, X86_INS_DIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSSrr, X86_INS_DIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIVSSrr_Int, X86_INS_DIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_F32m, X86_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_F64m, X86_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_FI16m, X86_INS_FIDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_FI32m, X86_INS_FIDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_FPrST0, X86_INS_FDIVP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_FST0r, X86_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DIV_FrST0, X86_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DPPDrmi, X86_INS_DPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DPPDrri, X86_INS_DPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DPPSrmi, X86_INS_DPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DPPSrri, X86_INS_DPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_DS_PREFIX, X86_INS_DS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ENTER, X86_INS_ENTER,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ES_PREFIX, X86_INS_ES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_EXTRACTPSmr, X86_INS_EXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_EXTRACTPSrr, X86_INS_EXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_EXTRQ, X86_INS_EXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_EXTRQI, X86_INS_EXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_F2XM1, X86_INS_F2XM1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARCALL16i, X86_INS_LCALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARCALL16m, X86_INS_LCALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARCALL32i, X86_INS_LCALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARCALL32m, X86_INS_LCALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARCALL64, X86_INS_LCALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FARJMP16i, X86_INS_LJMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ X86_FARJMP16m, X86_INS_LJMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ X86_FARJMP32i, X86_INS_LJMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ X86_FARJMP32m, X86_INS_LJMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ X86_FARJMP64, X86_INS_LJMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 1
+#endif
+ },
+ {
+ X86_FBLDm, X86_INS_FBLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FBSTPm, X86_INS_FBSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FCOM32m, X86_INS_FCOM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FCOM64m, X86_INS_FCOM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FCOMP32m, X86_INS_FCOMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FCOMP64m, X86_INS_FCOMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FCOMPP, X86_INS_FCOMPP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FDECSTP, X86_INS_FDECSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FEMMS, X86_INS_FEMMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FFREE, X86_INS_FFREE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FICOM16m, X86_INS_FICOM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FICOM32m, X86_INS_FICOM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FICOMP16m, X86_INS_FICOMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FICOMP32m, X86_INS_FICOMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FINCSTP, X86_INS_FINCSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDCW16m, X86_INS_FLDCW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDENVm, X86_INS_FLDENV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDL2E, X86_INS_FLDL2E,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDL2T, X86_INS_FLDL2T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDLG2, X86_INS_FLDLG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDLN2, X86_INS_FLDLN2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FLDPI, X86_INS_FLDPI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNCLEX, X86_INS_FNCLEX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNINIT, X86_INS_FNINIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNOP, X86_INS_FNOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNSTCW16m, X86_INS_FNSTCW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNSTSW16r, X86_INS_FNSTSW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_FPSW, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FNSTSWm, X86_INS_FNSTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FPATAN, X86_INS_FPATAN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FPREM, X86_INS_FPREM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FPREM1, X86_INS_FPREM1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FPTAN, X86_INS_FPTAN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FRNDINT, X86_INS_FRNDINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FRSTORm, X86_INS_FRSTOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FSAVEm, X86_INS_FNSAVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FSCALE, X86_INS_FSCALE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FSETPM, X86_INS_FSETPM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FSINCOS, X86_INS_FSINCOS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FSTENVm, X86_INS_FNSTENV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FS_PREFIX, X86_INS_FS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXAM, X86_INS_FXAM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXRSTOR, X86_INS_FXRSTOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXRSTOR64, X86_INS_FXRSTOR64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXSAVE, X86_INS_FXSAVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXSAVE64, X86_INS_FXSAVE64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FXTRACT, X86_INS_FXTRACT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FYL2X, X86_INS_FYL2X,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FYL2XP1, X86_INS_FYL2XP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDNPDrm, X86_INS_ANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDNPDrr, X86_INS_ANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDNPSrm, X86_INS_ANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDNPSrr, X86_INS_ANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDPDrm, X86_INS_ANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDPDrr, X86_INS_ANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDPSrm, X86_INS_ANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsANDPSrr, X86_INS_ANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsMOVAPDrm, X86_INS_MOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsMOVAPSrm, X86_INS_MOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsORPDrm, X86_INS_ORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsORPDrr, X86_INS_ORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsORPSrm, X86_INS_ORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsORPSrr, X86_INS_ORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsVMOVAPDrm, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsVMOVAPSrm, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsXORPDrm, X86_INS_XORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsXORPDrr, X86_INS_XORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsXORPSrm, X86_INS_XORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_FsXORPSrr, X86_INS_XORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_GETSEC, X86_INS_GETSEC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_GS_PREFIX, X86_INS_GS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HADDPDrm, X86_INS_HADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HADDPDrr, X86_INS_HADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HADDPSrm, X86_INS_HADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HADDPSrr, X86_INS_HADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HLT, X86_INS_HLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HSUBPDrm, X86_INS_HSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HSUBPDrr, X86_INS_HSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HSUBPSrm, X86_INS_HSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_HSUBPSrr, X86_INS_HSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV16m, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV16r, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV32m, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV32r, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV64m, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV64r, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV8m, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IDIV8r, X86_INS_IDIV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ILD_F16m, X86_INS_FILD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ILD_F32m, X86_INS_FILD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ILD_F64m, X86_INS_FILD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16m, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16r, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rm, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rmi, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rmi8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rr, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rri, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL16rri8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32m, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32r, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rm, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rmi, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rmi8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rr, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rri, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL32rri8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64m, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64r, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rm, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rmi32, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rmi8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rr, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rri32, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL64rri8, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL8m, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IMUL8r, X86_INS_IMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN16, X86_INS_INSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN16ri, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN16rr, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN32, X86_INS_INSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN32ri, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN32rr, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN8, X86_INS_INSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN8ri, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IN8rr, X86_INS_IN,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC16m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC16r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC32_16r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC32_32r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC32m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC32r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64_16m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64_16r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64_32m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64_32r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC64r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC8m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INC8r, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INSERTPSrm, X86_INS_INSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INSERTPSrr, X86_INS_INSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INSERTQ, X86_INS_INSERTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INSERTQI, X86_INS_INSERTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INT, X86_INS_INT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INT1, X86_INS_INT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INT3, X86_INS_INT3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INTO, X86_INS_INTO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVD, X86_INS_INVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVEPT32, X86_INS_INVEPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVEPT64, X86_INS_INVEPT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVLPG, X86_INS_INVLPG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVLPGA32, X86_INS_INVLPGA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVLPGA64, X86_INS_INVLPGA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVPCID32, X86_INS_INVPCID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVPCID64, X86_INS_INVPCID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVVPID32, X86_INS_INVVPID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_INVVPID64, X86_INS_INVVPID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IRET16, X86_INS_IRET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IRET32, X86_INS_IRETD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IRET64, X86_INS_IRETQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ISTT_FP16m, X86_INS_FISTTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ISTT_FP32m, X86_INS_FISTTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ISTT_FP64m, X86_INS_FISTTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IST_F16m, X86_INS_FIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IST_F32m, X86_INS_FIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IST_FP16m, X86_INS_FISTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IST_FP32m, X86_INS_FISTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_IST_FP64m, X86_INS_FISTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CMPSDrm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CMPSDrr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CMPSSrm, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CMPSSrr, X86_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_COMISDrm, X86_INS_COMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_COMISDrr, X86_INS_COMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_COMISSrm, X86_INS_COMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_COMISSrr, X86_INS_COMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSD2SSrm, X86_INS_CVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSD2SSrr, X86_INS_CVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SD64rm, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SD64rr, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SDrm, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SDrr, X86_INS_CVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SS64rm, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SS64rr, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SSrm, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSI2SSrr, X86_INS_CVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSS2SDrm, X86_INS_CVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTSS2SDrr, X86_INS_CVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSD2SI64rm, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSD2SI64rr, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSD2SIrm, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSD2SIrr, X86_INS_CVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSS2SI64rm, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSS2SI64rr, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSS2SIrm, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_CVTTSS2SIrr, X86_INS_CVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_UCOMISDrm, X86_INS_UCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_UCOMISDrr, X86_INS_UCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_UCOMISSrm, X86_INS_UCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_UCOMISSrr, X86_INS_UCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCMPSDrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCMPSDrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCMPSSrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCMPSSrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISDZrm, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISDZrr, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISDrm, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISDrr, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISSZrm, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISSZrr, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISSrm, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCOMISSrr, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSD2SSrm, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSD2SSrr, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SD64Zrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SD64Zrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SD64rm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SD64rr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SDZrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SDZrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SDrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SDrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SS64Zrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SS64Zrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SS64rm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SS64rr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SSZrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SSZrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SSrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSI2SSrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSS2SDrm, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTSS2SDrr, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SD64Zrm, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SD64Zrr, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SS64Zrm, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SS64Zrr, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISDZrm, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISDZrr, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISDrm, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISDrr, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISSZrm, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISSZrr, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISSrm, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_Int_VUCOMISSrr, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_JAE_1, X86_INS_JAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JAE_2, X86_INS_JAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JAE_4, X86_INS_JAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JA_1, X86_INS_JA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JA_2, X86_INS_JA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JA_4, X86_INS_JA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JBE_1, X86_INS_JBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JBE_2, X86_INS_JBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JBE_4, X86_INS_JBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JB_1, X86_INS_JB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JB_2, X86_INS_JB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JB_4, X86_INS_JB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JCXZ, X86_INS_JCXZ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JECXZ_32, X86_INS_JECXZ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JECXZ_64, X86_INS_JECXZ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JE_1, X86_INS_JE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JE_2, X86_INS_JE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JE_4, X86_INS_JE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JGE_1, X86_INS_JGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JGE_2, X86_INS_JGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JGE_4, X86_INS_JGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JG_1, X86_INS_JG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JG_2, X86_INS_JG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JG_4, X86_INS_JG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JLE_1, X86_INS_JLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JLE_2, X86_INS_JLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JLE_4, X86_INS_JLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JL_1, X86_INS_JL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JL_2, X86_INS_JL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JL_4, X86_INS_JL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JMP16m, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP16r, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP32m, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP32r, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP64m, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP64r, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1
+#endif
+ },
+ {
+ X86_JMP_1, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JMP_2, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JMP_4, X86_INS_JMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNE_1, X86_INS_JNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNE_2, X86_INS_JNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNE_4, X86_INS_JNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNO_1, X86_INS_JNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNO_2, X86_INS_JNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNO_4, X86_INS_JNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNP_1, X86_INS_JNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNP_2, X86_INS_JNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNP_4, X86_INS_JNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNS_1, X86_INS_JNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNS_2, X86_INS_JNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JNS_4, X86_INS_JNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JO_1, X86_INS_JO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JO_2, X86_INS_JO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JO_4, X86_INS_JO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JP_1, X86_INS_JP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JP_2, X86_INS_JP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JP_4, X86_INS_JP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JRCXZ, X86_INS_JRCXZ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JS_1, X86_INS_JS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JS_2, X86_INS_JS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_JS_4, X86_INS_JS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
+#endif
+ },
+ {
+ X86_KANDNWrr, X86_INS_KANDNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KANDWrr, X86_INS_KANDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KMOVWkk, X86_INS_KMOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KMOVWkm, X86_INS_KMOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KMOVWkr, X86_INS_KMOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KMOVWmk, X86_INS_KMOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KMOVWrk, X86_INS_KMOVW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KNOTWrr, X86_INS_KNOTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KORTESTWrr, X86_INS_KORTESTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KORWrr, X86_INS_KORW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KSHIFTLWri, X86_INS_KSHIFTLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KSHIFTRWri, X86_INS_KSHIFTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KUNPCKBWrr, X86_INS_KUNPCKBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KXNORWrr, X86_INS_KXNORW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_KXORWrr, X86_INS_KXORW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAHF, X86_INS_LAHF,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR16rm, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR16rr, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR32rm, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR32rr, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR64rm, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LAR64rr, X86_INS_LAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG16, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG16B, X86_INS_CMPXCHG16B,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG32, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG64, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG8, X86_INS_CMPXCHG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LCMPXCHG8B, X86_INS_CMPXCHG8B,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LDDQUrm, X86_INS_LDDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LDMXCSR, X86_INS_LDMXCSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LDS16rm, X86_INS_LDS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LDS32rm, X86_INS_LDS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_F0, X86_INS_FLDZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_F1, X86_INS_FLD1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_F32m, X86_INS_FLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_F64m, X86_INS_FLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_F80m, X86_INS_FLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LD_Frr, X86_INS_FLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEA16r, X86_INS_LEA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEA32r, X86_INS_LEA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEA64_32r, X86_INS_LEA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEA64r, X86_INS_LEA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEAVE, X86_INS_LEAVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LEAVE64, X86_INS_LEAVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LES16rm, X86_INS_LES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LES32rm, X86_INS_LES,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LFENCE, X86_INS_LFENCE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LFS16rm, X86_INS_LFS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LFS32rm, X86_INS_LFS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LFS64rm, X86_INS_LFS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGDT16m, X86_INS_LGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGDT32m, X86_INS_LGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGDT64m, X86_INS_LGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGS16rm, X86_INS_LGS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGS32rm, X86_INS_LGS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LGS64rm, X86_INS_LGS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LIDT16m, X86_INS_LIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LIDT32m, X86_INS_LIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LIDT64m, X86_INS_LIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LLDT16m, X86_INS_LLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LLDT16r, X86_INS_LLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LMSW16m, X86_INS_LMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LMSW16r, X86_INS_LMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD16mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD16mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD16mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD32mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD32mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD32mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD64mi32, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD64mi8, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD64mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD8mi, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_ADD8mr, X86_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND16mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND16mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND16mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND32mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND32mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND32mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND64mi32, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND64mi8, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND64mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND8mi, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_AND8mr, X86_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_DEC16m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_DEC32m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_DEC64m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_DEC8m, X86_INS_DEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_INC16m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_INC32m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_INC64m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_INC8m, X86_INS_INC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR16mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR16mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR16mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR32mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR32mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR32mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR64mi32, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR64mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR64mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR8mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_OR8mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_PREFIX, X86_INS_LOCK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB16mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB16mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB16mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB32mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB32mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB32mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB64mi32, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB64mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB64mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB8mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_SUB8mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR16mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR16mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR16mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR32mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR32mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR32mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR64mi32, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR64mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR64mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR8mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOCK_XOR8mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LODSB, X86_INS_LODSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LODSL, X86_INS_LODSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LODSQ, X86_INS_LODSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LODSW, X86_INS_LODSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOOP, X86_INS_LOOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOOPE, X86_INS_LOOPE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LOOPNE, X86_INS_LOOPNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETIL, X86_INS_RETF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETIQ, X86_INS_RETFQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETIW, X86_INS_RETF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETL, X86_INS_RETF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETQ, X86_INS_RETFQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LRETW, X86_INS_RETF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL16rm, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL16rr, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL32rm, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL32rr, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL64rm, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSL64rr, X86_INS_LSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSS16rm, X86_INS_LSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSS32rm, X86_INS_LSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LSS64rm, X86_INS_LSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LTRm, X86_INS_LTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LTRr, X86_INS_LTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LXADD16, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LXADD32, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LXADD64, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LXADD8, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT16rm, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT16rr, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT32rm, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT32rr, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT64rm, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_LZCNT64rr, X86_INS_LZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MASKMOVDQU, X86_INS_MASKMOVDQU,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MASKMOVDQU64, X86_INS_MASKMOVDQU,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCPDrm, X86_INS_MAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCPDrr, X86_INS_MAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCPSrm, X86_INS_MAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCPSrr, X86_INS_MAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCSDrm, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCSDrr, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCSSrm, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXCSSrr, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXPDrm, X86_INS_MAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXPDrr, X86_INS_MAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXPSrm, X86_INS_MAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXPSrr, X86_INS_MAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSDrm, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSDrm_Int, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSDrr, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSDrr_Int, X86_INS_MAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSSrm, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSSrm_Int, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSSrr, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MAXSSrr_Int, X86_INS_MAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MFENCE, X86_INS_MFENCE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCPDrm, X86_INS_MINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCPDrr, X86_INS_MINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCPSrm, X86_INS_MINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCPSrr, X86_INS_MINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCSDrm, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCSDrr, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCSSrm, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINCSSrr, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINPDrm, X86_INS_MINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINPDrr, X86_INS_MINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINPSrm, X86_INS_MINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINPSrr, X86_INS_MINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSDrm, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSDrm_Int, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSDrr, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSDrr_Int, X86_INS_MINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSSrm, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSSrm_Int, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSSrr, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MINSSrr_Int, X86_INS_MINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_EMMS, X86_INS_EMMS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64from64rr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64grr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64mr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64rm, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64rr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVD64to64rr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVNTQmr, X86_INS_MOVNTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVQ64mr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVQ64rm, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_MOVQ64rr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSBrm64, X86_INS_PABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSBrr64, X86_INS_PABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSDrm64, X86_INS_PABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSDrr64, X86_INS_PABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSWrm64, X86_INS_PABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PABSWrr64, X86_INS_PABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDBirm, X86_INS_PADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDBirr, X86_INS_PADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDDirm, X86_INS_PADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDDirr, X86_INS_PADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDQirm, X86_INS_PADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDQirr, X86_INS_PADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDSBirm, X86_INS_PADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDSBirr, X86_INS_PADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDSWirm, X86_INS_PADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDSWirr, X86_INS_PADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDUSBirm, X86_INS_PADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDUSBirr, X86_INS_PADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDUSWirm, X86_INS_PADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDUSWirr, X86_INS_PADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDWirm, X86_INS_PADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PADDWirr, X86_INS_PADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PALIGNR64irm, X86_INS_PALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PALIGNR64irr, X86_INS_PALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PANDNirm, X86_INS_PANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PANDNirr, X86_INS_PANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PANDirm, X86_INS_PAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PANDirr, X86_INS_PAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PAVGBirm, X86_INS_PAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PAVGBirr, X86_INS_PAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PAVGWirm, X86_INS_PAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PAVGWirr, X86_INS_PAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PEXTRWirri, X86_INS_PEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDSWrm64, X86_INS_PHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDSWrr64, X86_INS_PHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDWrm64, X86_INS_PHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDWrr64, X86_INS_PHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDrm64, X86_INS_PHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHADDrr64, X86_INS_PHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBDrm64, X86_INS_PHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBDrr64, X86_INS_PHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBSWrm64, X86_INS_PHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBSWrr64, X86_INS_PHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBWrm64, X86_INS_PHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PHSUBWrr64, X86_INS_PHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PINSRWirmi, X86_INS_PINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PINSRWirri, X86_INS_PINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMADDUBSWrm64, X86_INS_PMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMADDUBSWrr64, X86_INS_PMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMADDWDirm, X86_INS_PMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMADDWDirr, X86_INS_PMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMAXSWirm, X86_INS_PMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMAXSWirr, X86_INS_PMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMAXUBirm, X86_INS_PMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMAXUBirr, X86_INS_PMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMINSWirm, X86_INS_PMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMINSWirr, X86_INS_PMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMINUBirm, X86_INS_PMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMINUBirr, X86_INS_PMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHRSWrm64, X86_INS_PMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHRSWrr64, X86_INS_PMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHUWirm, X86_INS_PMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHUWirr, X86_INS_PMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHWirm, X86_INS_PMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULHWirr, X86_INS_PMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULLWirm, X86_INS_PMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULLWirr, X86_INS_PMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULUDQirm, X86_INS_PMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PMULUDQirr, X86_INS_PMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PORirm, X86_INS_POR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PORirr, X86_INS_POR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSADBWirm, X86_INS_PSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSADBWirr, X86_INS_PSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSHUFBrm64, X86_INS_PSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSHUFBrr64, X86_INS_PSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSHUFWmi, X86_INS_PSHUFW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSHUFWri, X86_INS_PSHUFW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNBrm64, X86_INS_PSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNBrr64, X86_INS_PSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNDrm64, X86_INS_PSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNDrr64, X86_INS_PSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNWrm64, X86_INS_PSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSIGNWrr64, X86_INS_PSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLDri, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLDrm, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLDrr, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLQri, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLQrm, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLQrr, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLWri, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLWrm, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSLLWrr, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRADri, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRADrm, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRADrr, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRAWri, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRAWrm, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRAWrr, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLDri, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLDrm, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLDrr, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLQri, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLQrm, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLQrr, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLWri, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLWrm, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSRLWrr, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBBirm, X86_INS_PSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBBirr, X86_INS_PSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBDirm, X86_INS_PSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBDirr, X86_INS_PSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBQirm, X86_INS_PSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBQirr, X86_INS_PSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBSBirm, X86_INS_PSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBSBirr, X86_INS_PSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBSWirm, X86_INS_PSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBSWirr, X86_INS_PSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBWirm, X86_INS_PSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PSUBWirr, X86_INS_PSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PXORirm, X86_INS_PXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MMX_PXORirr, X86_INS_PXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MONITORrrr, X86_INS_MONITOR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MONTMUL, X86_INS_MONTMUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16ao16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16ao16_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16mi, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16mr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16ms, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16o16a, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16o16a_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16ri, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16rm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16rr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16rr_REV, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16rs, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16sm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV16sr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32ao32, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32ao32_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32cr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32dr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32mi, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32mr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32ms, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32o32a, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32o32a_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rc, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rd, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32ri, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rr_REV, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32rs, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32sm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV32sr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ao16, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ao32, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ao64, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ao8, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64cr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64dr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64mi32, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64mr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ms, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64o16a, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64o32a, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64o64a, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64o8a, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rc, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rd, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ri, X86_INS_MOVABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64ri32, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rr_REV, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64rs, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64sm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64sr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64toPQIrr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64toSDrm, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV64toSDrr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8ao8, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8ao8_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8mi, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8mr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8o8a, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE32, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8o8a_16, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_16BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8ri, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8rm, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8rr, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOV8rr_REV, X86_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPDmr, X86_INS_MOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPDrm, X86_INS_MOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPDrr, X86_INS_MOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPDrr_REV, X86_INS_MOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPSmr, X86_INS_MOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPSrm, X86_INS_MOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPSrr, X86_INS_MOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVAPSrr_REV, X86_INS_MOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE16mr, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE16rm, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE32mr, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE32rm, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE64mr, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVBE64rm, X86_INS_MOVBE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDDUPrm, X86_INS_MOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDDUPrr, X86_INS_MOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDI2PDIrm, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDI2PDIrr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDI2SSrm, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDI2SSrr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQAmr, X86_INS_MOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQArm, X86_INS_MOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQArr, X86_INS_MOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQArr_REV, X86_INS_MOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQUmr, X86_INS_MOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQUrm, X86_INS_MOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQUrr, X86_INS_MOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVDQUrr_REV, X86_INS_MOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVHLPSrr, X86_INS_MOVHLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVHPDmr, X86_INS_MOVHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVHPDrm, X86_INS_MOVHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVHPSmr, X86_INS_MOVHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVHPSrm, X86_INS_MOVHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVLHPSrr, X86_INS_MOVLHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVLPDmr, X86_INS_MOVLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVLPDrm, X86_INS_MOVLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVLPSmr, X86_INS_MOVLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVLPSrm, X86_INS_MOVLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVMSKPDrr, X86_INS_MOVMSKPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVMSKPSrr, X86_INS_MOVMSKPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTDQArm, X86_INS_MOVNTDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTDQmr, X86_INS_MOVNTDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTI_64mr, X86_INS_MOVNTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTImr, X86_INS_MOVNTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTPDmr, X86_INS_MOVNTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTPSmr, X86_INS_MOVNTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTSD, X86_INS_MOVNTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVNTSS, X86_INS_MOVNTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVPDI2DImr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVPDI2DIrr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVPQI2QImr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVPQI2QIrr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVPQIto64rr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVQI2PQIrm, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSB, X86_INS_MOVSB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDmr, X86_INS_MOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDrm, X86_INS_MOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDrr, X86_INS_MOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDrr_REV, X86_INS_MOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDto64mr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSDto64rr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSHDUPrm, X86_INS_MOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSHDUPrr, X86_INS_MOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSL, X86_INS_MOVSD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSLDUPrm, X86_INS_MOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSLDUPrr, X86_INS_MOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSQ, X86_INS_MOVSQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSS2DImr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSS2DIrr, X86_INS_MOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSSmr, X86_INS_MOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSSrm, X86_INS_MOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSSrr, X86_INS_MOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSSrr_REV, X86_INS_MOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSW, X86_INS_MOVSW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX16rm8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX16rr8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX32rm16, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX32rm8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX32rr16, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX32rr8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rm16, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rm32, X86_INS_MOVSXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rm8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rr16, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rr32, X86_INS_MOVSXD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVSX64rr8, X86_INS_MOVSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPDmr, X86_INS_MOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPDrm, X86_INS_MOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPDrr, X86_INS_MOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPDrr_REV, X86_INS_MOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPSmr, X86_INS_MOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPSrm, X86_INS_MOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPSrr, X86_INS_MOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVUPSrr_REV, X86_INS_MOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZPQILo2PQIrm, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZPQILo2PQIrr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZQI2PQIrm, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZQI2PQIrr, X86_INS_MOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX16rm8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX16rr8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32_NOREXrm8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32_NOREXrr8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32rm16, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32rm8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32rr16, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX32rr8, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX64rm16_Q, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX64rm8_Q, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX64rr16_Q, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MOVZX64rr8_Q, X86_INS_MOVZX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MPSADBWrmi, X86_INS_MPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MPSADBWrri, X86_INS_MPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL16m, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL16r, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL32m, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL32r, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL64m, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL64r, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL8m, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL8r, X86_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULPDrm, X86_INS_MULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULPDrr, X86_INS_MULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULPSrm, X86_INS_MULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULPSrr, X86_INS_MULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSDrm, X86_INS_MULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSDrm_Int, X86_INS_MULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSDrr, X86_INS_MULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSDrr_Int, X86_INS_MULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSSrm, X86_INS_MULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSSrm_Int, X86_INS_MULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSSrr, X86_INS_MULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULSSrr_Int, X86_INS_MULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULX32rm, X86_INS_MULX,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULX32rr, X86_INS_MULX,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULX64rm, X86_INS_MULX,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MULX64rr, X86_INS_MULX,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_F32m, X86_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_F64m, X86_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_FI16m, X86_INS_FIMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_FI32m, X86_INS_FIMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_FPrST0, X86_INS_FMULP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_FST0r, X86_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MUL_FrST0, X86_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_MWAITrr, X86_INS_MWAIT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EAX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG16m, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG16r, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG32m, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG32r, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG64m, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG64r, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG8m, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NEG8r, X86_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOOP, X86_INS_NOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOOPL, X86_INS_NOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOOPW, X86_INS_NOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT16m, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT16r, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT32m, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT32r, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT64m, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT64r, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT8m, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_NOT8r, X86_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16i16, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16ri, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16ri8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16rm, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16rr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR16rr_REV, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32i32, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32mrLocked, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32ri, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32ri8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32rm, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32rr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR32rr_REV, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64i32, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64mi32, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64mi8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64ri32, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64ri8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64rm, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64rr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR64rr_REV, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8i8, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8mi, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8mr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8ri, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8rm, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8rr, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OR8rr_REV, X86_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ORPDrm, X86_INS_ORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ORPDrr, X86_INS_ORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ORPSrm, X86_INS_ORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ORPSrr, X86_INS_ORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT16ir, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT16rr, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT32ir, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT32rr, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT8ir, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUT8rr, X86_INS_OUT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUTSB, X86_INS_OUTSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUTSL, X86_INS_OUTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_OUTSW, X86_INS_OUTSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSBrm128, X86_INS_PABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSBrr128, X86_INS_PABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSDrm128, X86_INS_PABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSDrr128, X86_INS_PABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSWrm128, X86_INS_PABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PABSWrr128, X86_INS_PABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKSSDWrm, X86_INS_PACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKSSDWrr, X86_INS_PACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKSSWBrm, X86_INS_PACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKSSWBrr, X86_INS_PACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKUSDWrm, X86_INS_PACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKUSDWrr, X86_INS_PACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKUSWBrm, X86_INS_PACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PACKUSWBrr, X86_INS_PACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDBrm, X86_INS_PADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDBrr, X86_INS_PADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDDrm, X86_INS_PADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDDrr, X86_INS_PADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDQrm, X86_INS_PADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDQrr, X86_INS_PADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDSBrm, X86_INS_PADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDSBrr, X86_INS_PADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDSWrm, X86_INS_PADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDSWrr, X86_INS_PADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDUSBrm, X86_INS_PADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDUSBrr, X86_INS_PADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDUSWrm, X86_INS_PADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDUSWrr, X86_INS_PADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDWrm, X86_INS_PADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PADDWrr, X86_INS_PADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PALIGNR128rm, X86_INS_PALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PALIGNR128rr, X86_INS_PALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PANDNrm, X86_INS_PANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PANDNrr, X86_INS_PANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PANDrm, X86_INS_PAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PANDrr, X86_INS_PAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAUSE, X86_INS_PAUSE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGBrm, X86_INS_PAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGBrr, X86_INS_PAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGUSBrm, X86_INS_PAVGUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGUSBrr, X86_INS_PAVGUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGWrm, X86_INS_PAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PAVGWrr, X86_INS_PAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PBLENDVBrm0, X86_INS_PBLENDVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PBLENDVBrr0, X86_INS_PBLENDVB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PBLENDWrmi, X86_INS_PBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PBLENDWrri, X86_INS_PBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCLMULQDQrm, X86_INS_PCLMULQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCLMULQDQrr, X86_INS_PCLMULQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQBrm, X86_INS_PCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQBrr, X86_INS_PCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQDrm, X86_INS_PCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQDrr, X86_INS_PCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQQrm, X86_INS_PCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQQrr, X86_INS_PCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQWrm, X86_INS_PCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPEQWrr, X86_INS_PCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPESTRIrm, X86_INS_PCMPESTRI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPESTRIrr, X86_INS_PCMPESTRI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPESTRM128rm, X86_INS_PCMPESTRM,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPESTRM128rr, X86_INS_PCMPESTRM,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTBrm, X86_INS_PCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTBrr, X86_INS_PCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTDrm, X86_INS_PCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTDrr, X86_INS_PCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTQrm, X86_INS_PCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTQrr, X86_INS_PCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTWrm, X86_INS_PCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPGTWrr, X86_INS_PCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPISTRIrm, X86_INS_PCMPISTRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPISTRIrr, X86_INS_PCMPISTRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPISTRM128rm, X86_INS_PCMPISTRM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PCMPISTRM128rr, X86_INS_PCMPISTRM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PDEP32rm, X86_INS_PDEP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PDEP32rr, X86_INS_PDEP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PDEP64rm, X86_INS_PDEP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PDEP64rr, X86_INS_PDEP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXT32rm, X86_INS_PEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXT32rr, X86_INS_PEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXT64rm, X86_INS_PEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXT64rr, X86_INS_PEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRBmr, X86_INS_PEXTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRBrr, X86_INS_PEXTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRDmr, X86_INS_PEXTRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRDrr, X86_INS_PEXTRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRQmr, X86_INS_PEXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRQrr, X86_INS_PEXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRWmr, X86_INS_PEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRWri, X86_INS_PEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PEXTRWrr_REV, X86_INS_PEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PF2IDrm, X86_INS_PF2ID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PF2IDrr, X86_INS_PF2ID,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PF2IWrm, X86_INS_PF2IW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PF2IWrr, X86_INS_PF2IW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFACCrm, X86_INS_PFACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFACCrr, X86_INS_PFACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFADDrm, X86_INS_PFADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFADDrr, X86_INS_PFADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPEQrm, X86_INS_PFCMPEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPEQrr, X86_INS_PFCMPEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPGErm, X86_INS_PFCMPGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPGErr, X86_INS_PFCMPGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPGTrm, X86_INS_PFCMPGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFCMPGTrr, X86_INS_PFCMPGT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMAXrm, X86_INS_PFMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMAXrr, X86_INS_PFMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMINrm, X86_INS_PFMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMINrr, X86_INS_PFMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMULrm, X86_INS_PFMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFMULrr, X86_INS_PFMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFNACCrm, X86_INS_PFNACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFNACCrr, X86_INS_PFNACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFPNACCrm, X86_INS_PFPNACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFPNACCrr, X86_INS_PFPNACC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPIT1rm, X86_INS_PFRCPIT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPIT1rr, X86_INS_PFRCPIT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPIT2rm, X86_INS_PFRCPIT2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPIT2rr, X86_INS_PFRCPIT2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPrm, X86_INS_PFRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRCPrr, X86_INS_PFRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRSQIT1rm, X86_INS_PFRSQIT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRSQIT1rr, X86_INS_PFRSQIT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRSQRTrm, X86_INS_PFRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFRSQRTrr, X86_INS_PFRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFSUBRrm, X86_INS_PFSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFSUBRrr, X86_INS_PFSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFSUBrm, X86_INS_PFSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PFSUBrr, X86_INS_PFSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDDrm, X86_INS_PHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDDrr, X86_INS_PHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDSWrm128, X86_INS_PHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDSWrr128, X86_INS_PHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDWrm, X86_INS_PHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHADDWrr, X86_INS_PHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHMINPOSUWrm128, X86_INS_PHMINPOSUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHMINPOSUWrr128, X86_INS_PHMINPOSUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBDrm, X86_INS_PHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBDrr, X86_INS_PHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBSWrm128, X86_INS_PHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBSWrr128, X86_INS_PHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBWrm, X86_INS_PHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PHSUBWrr, X86_INS_PHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PI2FDrm, X86_INS_PI2FD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PI2FDrr, X86_INS_PI2FD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PI2FWrm, X86_INS_PI2FW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PI2FWrr, X86_INS_PI2FW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRBrm, X86_INS_PINSRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRBrr, X86_INS_PINSRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRDrm, X86_INS_PINSRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRDrr, X86_INS_PINSRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRQrm, X86_INS_PINSRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRQrr, X86_INS_PINSRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRWrmi, X86_INS_PINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PINSRWrri, X86_INS_PINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMADDUBSWrm128, X86_INS_PMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMADDUBSWrr128, X86_INS_PMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMADDWDrm, X86_INS_PMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMADDWDrr, X86_INS_PMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSBrm, X86_INS_PMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSBrr, X86_INS_PMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSDrm, X86_INS_PMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSDrr, X86_INS_PMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSWrm, X86_INS_PMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXSWrr, X86_INS_PMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUBrm, X86_INS_PMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUBrr, X86_INS_PMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUDrm, X86_INS_PMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUDrr, X86_INS_PMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUWrm, X86_INS_PMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMAXUWrr, X86_INS_PMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSBrm, X86_INS_PMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSBrr, X86_INS_PMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSDrm, X86_INS_PMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSDrr, X86_INS_PMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSWrm, X86_INS_PMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINSWrr, X86_INS_PMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUBrm, X86_INS_PMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUBrr, X86_INS_PMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUDrm, X86_INS_PMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUDrr, X86_INS_PMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUWrm, X86_INS_PMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMINUWrr, X86_INS_PMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVMSKBrr, X86_INS_PMOVMSKB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBDrm, X86_INS_PMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBDrr, X86_INS_PMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBQrm, X86_INS_PMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBQrr, X86_INS_PMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBWrm, X86_INS_PMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXBWrr, X86_INS_PMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXDQrm, X86_INS_PMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXDQrr, X86_INS_PMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXWDrm, X86_INS_PMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXWDrr, X86_INS_PMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXWQrm, X86_INS_PMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVSXWQrr, X86_INS_PMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBDrm, X86_INS_PMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBDrr, X86_INS_PMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBQrm, X86_INS_PMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBQrr, X86_INS_PMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBWrm, X86_INS_PMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXBWrr, X86_INS_PMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXDQrm, X86_INS_PMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXDQrr, X86_INS_PMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXWDrm, X86_INS_PMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXWDrr, X86_INS_PMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXWQrm, X86_INS_PMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMOVZXWQrr, X86_INS_PMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULDQrm, X86_INS_PMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULDQrr, X86_INS_PMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHRSWrm128, X86_INS_PMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHRSWrr128, X86_INS_PMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHRWrm, X86_INS_PMULHRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHRWrr, X86_INS_PMULHRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHUWrm, X86_INS_PMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHUWrr, X86_INS_PMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHWrm, X86_INS_PMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULHWrr, X86_INS_PMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULLDrm, X86_INS_PMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULLDrr, X86_INS_PMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULLWrm, X86_INS_PMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULLWrr, X86_INS_PMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULUDQrm, X86_INS_PMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PMULUDQrr, X86_INS_PMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP16r, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP16rmm, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP16rmr, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP32r, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP32rmm, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP32rmr, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP64r, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP64rmm, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POP64rmr, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPA16, X86_INS_POPAW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPA32, X86_INS_POPAL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT16rm, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT16rr, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT32rm, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT32rr, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT64rm, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPCNT64rr, X86_INS_POPCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPDS16, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPDS32, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPES16, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPES32, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPF16, X86_INS_POPF,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPF32, X86_INS_POPFD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPF64, X86_INS_POPFQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPFS16, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPFS32, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPFS64, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPGS16, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPGS32, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPGS64, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPSS16, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_POPSS32, X86_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PORrm, X86_INS_POR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PORrr, X86_INS_POR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCH, X86_INS_PREFETCH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCHNTA, X86_INS_PREFETCHNTA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCHT0, X86_INS_PREFETCHT0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCHT1, X86_INS_PREFETCHT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCHT2, X86_INS_PREFETCHT2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PREFETCHW, X86_INS_PREFETCHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSADBWrm, X86_INS_PSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSADBWrr, X86_INS_PSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFBrm, X86_INS_PSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFBrr, X86_INS_PSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFDmi, X86_INS_PSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFDri, X86_INS_PSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFHWmi, X86_INS_PSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFHWri, X86_INS_PSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFLWmi, X86_INS_PSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSHUFLWri, X86_INS_PSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNBrm, X86_INS_PSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNBrr, X86_INS_PSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNDrm, X86_INS_PSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNDrr, X86_INS_PSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNWrm, X86_INS_PSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSIGNWrr, X86_INS_PSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLDQri, X86_INS_PSLLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLDri, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLDrm, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLDrr, X86_INS_PSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLQri, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLQrm, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLQrr, X86_INS_PSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLWri, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLWrm, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSLLWrr, X86_INS_PSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRADri, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRADrm, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRADrr, X86_INS_PSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRAWri, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRAWrm, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRAWrr, X86_INS_PSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLDQri, X86_INS_PSRLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLDri, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLDrm, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLDrr, X86_INS_PSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLQri, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLQrm, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLQrr, X86_INS_PSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLWri, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLWrm, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSRLWrr, X86_INS_PSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBBrm, X86_INS_PSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBBrr, X86_INS_PSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBDrm, X86_INS_PSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBDrr, X86_INS_PSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBQrm, X86_INS_PSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBQrr, X86_INS_PSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBSBrm, X86_INS_PSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBSBrr, X86_INS_PSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBSWrm, X86_INS_PSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBSWrr, X86_INS_PSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBUSBrm, X86_INS_PSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBUSBrr, X86_INS_PSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBUSWrm, X86_INS_PSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBUSWrr, X86_INS_PSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBWrm, X86_INS_PSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSUBWrr, X86_INS_PSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSWAPDrm, X86_INS_PSWAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PSWAPDrr, X86_INS_PSWAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PTESTrm, X86_INS_PTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PTESTrr, X86_INS_PTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH16i8, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH16r, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH16rmm, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH16rmr, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH32i8, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH32r, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH32rmm, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH32rmr, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64i16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64i32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64i8, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64r, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64rmm, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSH64rmr, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHA16, X86_INS_PUSHAW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHA32, X86_INS_PUSHAL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHCS16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHCS32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHDS16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHDS32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHES16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHES32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHF16, X86_INS_PUSHF,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHF32, X86_INS_PUSHFD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHF64, X86_INS_PUSHFQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHFS16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHFS32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHFS64, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHGS16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHGS32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHGS64, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHSS16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHSS32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHi16, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PUSHi32, X86_INS_PUSH,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PXORrm, X86_INS_PXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_PXORrr, X86_INS_PXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16m1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16mCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16mi, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16r1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16rCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL16ri, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32m1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32mCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32mi, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32r1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32rCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL32ri, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64m1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64mCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64mi, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64r1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64rCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL64ri, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8m1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8mCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8mi, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8r1, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8rCL, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCL8ri, X86_INS_RCL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPPSm, X86_INS_RCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPPSm_Int, X86_INS_RCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPPSr, X86_INS_RCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPPSr_Int, X86_INS_RCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPSSm, X86_INS_RCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPSSm_Int, X86_INS_RCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPSSr, X86_INS_RCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCPSSr_Int, X86_INS_RCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16m1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16mCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16mi, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16r1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16rCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR16ri, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32m1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32mCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32mi, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32r1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32rCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR32ri, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64m1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64mCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64mi, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64r1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64rCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR64ri, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8m1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8mCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8mi, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8r1, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8rCL, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RCR8ri, X86_INS_RCR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDFSBASE, X86_INS_RDFSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDFSBASE64, X86_INS_RDFSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDGSBASE, X86_INS_RDGSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDGSBASE64, X86_INS_RDGSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDMSR, X86_INS_RDMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDPMC, X86_INS_RDPMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDRAND16r, X86_INS_RDRAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDRAND32r, X86_INS_RDRAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDRAND64r, X86_INS_RDRAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDSEED16r, X86_INS_RDSEED,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDSEED32r, X86_INS_RDSEED,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDSEED64r, X86_INS_RDSEED,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDTSC, X86_INS_RDTSC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RDTSCP, X86_INS_RDTSCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REPNE_PREFIX, X86_INS_REPNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_REG_ECX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSB_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSB_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSD_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSD_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSQ_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSW_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_REG_ECX, X86_REG_EDI, X86_REG_ESI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_MOVSW_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_REG_RCX, X86_REG_RDI, X86_REG_RSI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_PREFIX, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_REG_ECX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSB_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSB_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSD_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSD_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSQ_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSW_32, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_ECX, X86_REG_EDI, 0 }, { X86_REG_ECX, X86_REG_EDI, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REP_STOSW_64, X86_INS_REP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_RCX, X86_REG_RDI, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETIL, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETIQ, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETIW, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETL, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETQ, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RETW, X86_INS_RET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_REX64_PREFIX, X86_INS_REX64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16m1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16mCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16mi, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16r1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16rCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL16ri, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32m1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32mCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32mi, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32r1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32rCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL32ri, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64m1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64mCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64mi, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64r1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64rCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL64ri, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8m1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8mCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8mi, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8r1, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8rCL, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROL8ri, X86_INS_ROL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16m1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16mCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16mi, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16r1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16rCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR16ri, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32m1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32mCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32mi, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32r1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32rCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR32ri, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64m1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64mCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64mi, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64r1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64rCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR64ri, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8m1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8mCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8mi, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8r1, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8rCL, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROR8ri, X86_INS_ROR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RORX32mi, X86_INS_RORX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RORX32ri, X86_INS_RORX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RORX64mi, X86_INS_RORX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RORX64ri, X86_INS_RORX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDPDm, X86_INS_ROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDPDr, X86_INS_ROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDPSm, X86_INS_ROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDPSr, X86_INS_ROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSDm, X86_INS_ROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSDr, X86_INS_ROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSDr_Int, X86_INS_ROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSSm, X86_INS_ROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSSr, X86_INS_ROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ROUNDSSr_Int, X86_INS_ROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSM, X86_INS_RSM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTPSm, X86_INS_RSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTPSm_Int, X86_INS_RSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTPSr, X86_INS_RSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTPSr_Int, X86_INS_RSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTSSm, X86_INS_RSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTSSm_Int, X86_INS_RSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTSSr, X86_INS_RSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_RSQRTSSr_Int, X86_INS_RSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAHF, X86_INS_SAHF,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SALC, X86_INS_SALC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16m1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16mCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16mi, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16r1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16rCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR16ri, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32m1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32mCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32mi, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32r1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32rCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR32ri, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64m1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64mCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64mi, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64r1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64rCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR64ri, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8m1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8mCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8mi, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8r1, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8rCL, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SAR8ri, X86_INS_SAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SARX32rm, X86_INS_SARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SARX32rr, X86_INS_SARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SARX64rm, X86_INS_SARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SARX64rr, X86_INS_SARX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16i16, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16mi, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16mi8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16mr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16ri, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16ri8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16rm, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16rr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB16rr_REV, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32i32, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32mi, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32mi8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32mr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32ri, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32ri8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32rm, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32rr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB32rr_REV, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64i32, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64mi32, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64mi8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64mr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64ri32, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64ri8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64rm, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64rr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB64rr_REV, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8i8, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8mi, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8mr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8ri, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8rm, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8rr, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SBB8rr_REV, X86_INS_SBB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SCAS16, X86_INS_SCASW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SCAS32, X86_INS_SCASD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SCAS64, X86_INS_SCASQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SCAS8, X86_INS_SCASB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETAEm, X86_INS_SETAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETAEr, X86_INS_SETAE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETAm, X86_INS_SETA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETAr, X86_INS_SETA,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETBEm, X86_INS_SETBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETBEr, X86_INS_SETBE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETBm, X86_INS_SETB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETBr, X86_INS_SETB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETEm, X86_INS_SETE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETEr, X86_INS_SETE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETGEm, X86_INS_SETGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETGEr, X86_INS_SETGE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETGm, X86_INS_SETG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETGr, X86_INS_SETG,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETLEm, X86_INS_SETLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETLEr, X86_INS_SETLE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETLm, X86_INS_SETL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETLr, X86_INS_SETL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNEm, X86_INS_SETNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNEr, X86_INS_SETNE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNOm, X86_INS_SETNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNOr, X86_INS_SETNO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNPm, X86_INS_SETNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNPr, X86_INS_SETNP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNSm, X86_INS_SETNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETNSr, X86_INS_SETNS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETOm, X86_INS_SETO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETOr, X86_INS_SETO,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETPm, X86_INS_SETP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETPr, X86_INS_SETP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETSm, X86_INS_SETS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SETSr, X86_INS_SETS,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SFENCE, X86_INS_SFENCE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SGDT16m, X86_INS_SGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SGDT32m, X86_INS_SGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SGDT64m, X86_INS_SGDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1MSG1rm, X86_INS_SHA1MSG1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1MSG1rr, X86_INS_SHA1MSG1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1MSG2rm, X86_INS_SHA1MSG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1MSG2rr, X86_INS_SHA1MSG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1NEXTErm, X86_INS_SHA1NEXTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1NEXTErr, X86_INS_SHA1NEXTE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256MSG1rm, X86_INS_SHA256MSG1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256MSG1rr, X86_INS_SHA256MSG1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256MSG2rm, X86_INS_SHA256MSG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256MSG2rr, X86_INS_SHA256MSG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2,
+#ifndef CAPSTONE_DIET
+ { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16m1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16mCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16mi, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16r1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16rCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL16ri, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32m1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32mCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32mi, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32r1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32rCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL32ri, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64m1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64mCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64mi, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64r1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64rCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL64ri, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8m1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8mCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8mi, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8r1, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8rCL, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHL8ri, X86_INS_SHL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD16mrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD16mri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD16rrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD16rri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD32mrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD32mri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD32rrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD32rri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD64mrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD64mri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD64rrCL, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLD64rri8, X86_INS_SHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLX32rm, X86_INS_SHLX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLX32rr, X86_INS_SHLX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLX64rm, X86_INS_SHLX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHLX64rr, X86_INS_SHLX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16m1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16mCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16mi, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16r1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16rCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR16ri, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32m1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32mCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32mi, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32r1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32rCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR32ri, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64m1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64mCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64mi, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64r1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64rCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR64ri, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8m1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8mCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8mi, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8r1, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8rCL, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHR8ri, X86_INS_SHR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD16mrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD16mri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD16rrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD16rri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD32mrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD32mri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD32rrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD32rri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD64mrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD64mri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD64rrCL, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRD64rri8, X86_INS_SHRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRX32rm, X86_INS_SHRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRX32rr, X86_INS_SHRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRX64rm, X86_INS_SHRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHRX64rr, X86_INS_SHRX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHUFPDrmi, X86_INS_SHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHUFPDrri, X86_INS_SHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHUFPSrmi, X86_INS_SHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SHUFPSrri, X86_INS_SHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SIDT16m, X86_INS_SIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SIDT32m, X86_INS_SIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SIDT64m, X86_INS_SIDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SIN_F, X86_INS_FSIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SKINIT, X86_INS_SKINIT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SLDT16m, X86_INS_SLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SLDT16r, X86_INS_SLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SLDT32r, X86_INS_SLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SLDT64m, X86_INS_SLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SLDT64r, X86_INS_SLDT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SMSW16m, X86_INS_SMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SMSW16r, X86_INS_SMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SMSW32r, X86_INS_SMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SMSW64r, X86_INS_SMSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTPDm, X86_INS_SQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTPDr, X86_INS_SQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTPSm, X86_INS_SQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTPSr, X86_INS_SQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSDm, X86_INS_SQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSDm_Int, X86_INS_SQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSDr, X86_INS_SQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSDr_Int, X86_INS_SQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSSm, X86_INS_SQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSSm_Int, X86_INS_SQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSSr, X86_INS_SQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRTSSr_Int, X86_INS_SQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SQRT_F, X86_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SS_PREFIX, X86_INS_SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STAC, X86_INS_STAC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STC, X86_INS_STC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STD, X86_INS_STD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STGI, X86_INS_STGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STI, X86_INS_STI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STMXCSR, X86_INS_STMXCSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STOSB, X86_INS_STOSB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STOSL, X86_INS_STOSD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STOSQ, X86_INS_STOSQ,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STOSW, X86_INS_STOSW,
+#ifndef CAPSTONE_DIET
+ { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STR16r, X86_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STR32r, X86_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STR64r, X86_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_STRm, X86_INS_STR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_F32m, X86_INS_FST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_F64m, X86_INS_FST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_FP32m, X86_INS_FSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_FP64m, X86_INS_FSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_FP80m, X86_INS_FSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_FPrr, X86_INS_FSTP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_ST_Frr, X86_INS_FST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16i16, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16ri, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16ri8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16rm, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16rr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB16rr_REV, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32i32, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32ri, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32ri8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32rm, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32rr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB32rr_REV, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64i32, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64mi32, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64mi8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64ri32, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64ri8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64rm, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64rr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB64rr_REV, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8i8, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8mi, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8mr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8ri, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8rm, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8rr, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB8rr_REV, X86_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBPDrm, X86_INS_SUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBPDrr, X86_INS_SUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBPSrm, X86_INS_SUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBPSrr, X86_INS_SUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_F32m, X86_INS_FSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_F64m, X86_INS_FSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_FI16m, X86_INS_FISUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_FI32m, X86_INS_FISUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_FPrST0, X86_INS_FSUBRP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_FST0r, X86_INS_FSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBR_FrST0, X86_INS_FSUBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSDrm, X86_INS_SUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSDrm_Int, X86_INS_SUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSDrr, X86_INS_SUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSDrr_Int, X86_INS_SUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSSrm, X86_INS_SUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSSrm_Int, X86_INS_SUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSSrr, X86_INS_SUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUBSSrr_Int, X86_INS_SUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_F32m, X86_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_F64m, X86_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_FI16m, X86_INS_FISUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_FI32m, X86_INS_FISUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_FPrST0, X86_INS_FSUBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_FST0r, X86_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SUB_FrST0, X86_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SWAPGS, X86_INS_SWAPGS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSCALL, X86_INS_SYSCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSENTER, X86_INS_SYSENTER,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSEXIT, X86_INS_SYSEXIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSEXIT64, X86_INS_SYSEXIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSRET, X86_INS_SYSRET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_SYSRET64, X86_INS_SYSRET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_T1MSKC32rm, X86_INS_T1MSKC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_T1MSKC32rr, X86_INS_T1MSKC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_T1MSKC64rm, X86_INS_T1MSKC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_T1MSKC64rr, X86_INS_T1MSKC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST16i16, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST16mi, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST16ri, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST16rm, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST16rr, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST32i32, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST32mi, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST32ri, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST32rm, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST32rr, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST64i32, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST64mi32, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST64ri32, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST64rm, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST64rr, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST8i8, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST8mi, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST8ri, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST8rm, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TEST8rr, X86_INS_TEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TRAP, X86_INS_UD2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TST_F, X86_INS_FTST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT16rm, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT16rr, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT32rm, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT32rr, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT64rm, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZCNT64rr, X86_INS_TZCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZMSK32rm, X86_INS_TZMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZMSK32rr, X86_INS_TZMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZMSK64rm, X86_INS_TZMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_TZMSK64rr, X86_INS_TZMSK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOMISDrm, X86_INS_UCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOMISDrr, X86_INS_UCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOMISSrm, X86_INS_UCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOMISSrr, X86_INS_UCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOM_FIPr, X86_INS_FUCOMPI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOM_FIr, X86_INS_FUCOMI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOM_FPPr, X86_INS_FUCOMPP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOM_FPr, X86_INS_FUCOMP,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UCOM_Fr, X86_INS_FUCOM,
+#ifndef CAPSTONE_DIET
+ { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UD2B, X86_INS_UD2B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKHPDrm, X86_INS_UNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKHPDrr, X86_INS_UNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKHPSrm, X86_INS_UNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKHPSrr, X86_INS_UNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKLPDrm, X86_INS_UNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKLPDrr, X86_INS_UNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKLPSrm, X86_INS_UNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_UNPCKLPSrr, X86_INS_UNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDYrm, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDYrr, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDZrm, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDZrmb, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDZrr, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDrm, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPDrr, X86_INS_VADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSYrm, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSYrr, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSZrm, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSZrmb, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSZrr, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSrm, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDPSrr, X86_INS_VADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDZrm, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDZrr, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDrm, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDrm_Int, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDrr, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSDrr_Int, X86_INS_VADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSZrm, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSZrr, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSrm, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSrm_Int, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSrr, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSSrr_Int, X86_INS_VADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPDYrm, X86_INS_VADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPDYrr, X86_INS_VADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPDrm, X86_INS_VADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPDrr, X86_INS_VADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPSYrm, X86_INS_VADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPSYrr, X86_INS_VADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPSrm, X86_INS_VADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VADDSUBPSrr, X86_INS_VADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESDECLASTrm, X86_INS_VAESDECLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESDECLASTrr, X86_INS_VAESDECLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESDECrm, X86_INS_VAESDEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESDECrr, X86_INS_VAESDEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESENCLASTrm, X86_INS_VAESENCLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESENCLASTrr, X86_INS_VAESENCLAST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESENCrm, X86_INS_VAESENC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESENCrr, X86_INS_VAESENC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESIMCrm, X86_INS_VAESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESIMCrr, X86_INS_VAESIMC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VALIGNDrmi, X86_INS_VALIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VALIGNDrri, X86_INS_VALIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VALIGNQrmi, X86_INS_VALIGNQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VALIGNQrri, X86_INS_VALIGNQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPDYrm, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPDYrr, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPDrm, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPDrr, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPSYrm, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPSYrr, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPSrm, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDNPSrr, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPDYrm, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPDYrr, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPDrm, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPDrr, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPSYrm, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPSYrr, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPSrm, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VANDPSrr, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDMPDZrm, X86_INS_VBLENDMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDMPDZrr, X86_INS_VBLENDMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDMPSZrm, X86_INS_VBLENDMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDMPSZrr, X86_INS_VBLENDMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPDYrmi, X86_INS_VBLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPDYrri, X86_INS_VBLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPDrmi, X86_INS_VBLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPDrri, X86_INS_VBLENDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPSYrmi, X86_INS_VBLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPSYrri, X86_INS_VBLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPSrmi, X86_INS_VBLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDPSrri, X86_INS_VBLENDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPDYrm, X86_INS_VBLENDVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPDYrr, X86_INS_VBLENDVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPDrm, X86_INS_VBLENDVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPDrr, X86_INS_VBLENDVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPSYrm, X86_INS_VBLENDVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPSYrr, X86_INS_VBLENDVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPSrm, X86_INS_VBLENDVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBLENDVPSrr, X86_INS_VBLENDVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTF128, X86_INS_VBROADCASTF128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTI128, X86_INS_VBROADCASTI128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSDZrm, X86_INS_VBROADCASTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSDZrr, X86_INS_VBROADCASTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSZrm, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSZrr, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDYrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDYrmi_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDYrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDYrri_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDZrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDZrmi_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDZrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDZrri_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDZrrib, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDrmi_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPDrri_alt, X86_INS_VCMPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSYrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSYrmi_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSYrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSYrri_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSZrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSZrmi_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSZrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSZrri_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSZrrib, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSrmi, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSrmi_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSrri, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPPSrri_alt, X86_INS_VCMPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDZrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDZrmi_alt, X86_INS_VCMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDZrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDZrri_alt, X86_INS_VCMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDrm_alt, X86_INS_VCMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSDrr_alt, X86_INS_VCMPSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSZrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSZrmi_alt, X86_INS_VCMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSZrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSZrri_alt, X86_INS_VCMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSrm, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSrm_alt, X86_INS_VCMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSrr, X86_INS_VCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCMPSSrr_alt, X86_INS_VCMPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISDZrm, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISDZrr, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISDrm, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISDrr, X86_INS_VCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISSZrm, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISSZrr, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISSrm, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCOMISSrr, X86_INS_VCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQXrm, X86_INS_VCVTPD2DQX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSXrm, X86_INS_VCVTPD2PSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SI64Zrm, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SI64Zrr, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SI64rm, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SI64rr, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SIZrm, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SIZrr, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SIrm, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SIrr, X86_INS_VCVTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2USI64Zrm, X86_INS_VCVTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2USI64Zrr, X86_INS_VCVTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2USIZrm, X86_INS_VCVTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSD2USIZrr, X86_INS_VCVTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SD64rm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SD64rr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SS64rm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SS64rr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SI64Zrm, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SI64Zrr, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SI64rm, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SI64rr, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SIZrm, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SIZrr, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SIrm, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2SIrr, X86_INS_VCVTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2USI64Zrm, X86_INS_VCVTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2USI64Zrr, X86_INS_VCVTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2USIZrm, X86_INS_VCVTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTSS2USIZrr, X86_INS_VCVTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQXrm, X86_INS_VCVTTPD2DQX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDYrm, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDYrr, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDZrm, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDZrmb, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDZrr, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDrm, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPDrr, X86_INS_VDIVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSYrm, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSYrr, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSZrm, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSZrmb, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSZrr, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSrm, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVPSrr, X86_INS_VDIVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDZrm, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDZrr, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDrm, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDrm_Int, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDrr, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSDrr_Int, X86_INS_VDIVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSZrm, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSZrr, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSrm, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSrm_Int, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSrr, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDIVSSrr_Int, X86_INS_VDIVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPDrmi, X86_INS_VDPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPDrri, X86_INS_VDPPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPSYrmi, X86_INS_VDPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPSYrri, X86_INS_VDPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPSrmi, X86_INS_VDPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VDPPSrri, X86_INS_VDPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VERRm, X86_INS_VERR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VERRr, X86_INS_VERR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VERWm, X86_INS_VERW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VERWr, X86_INS_VERW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF32x4mr, X86_INS_VEXTRACTF32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF32x4rr, X86_INS_VEXTRACTF32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF64x4mr, X86_INS_VEXTRACTF64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTF64x4rr, X86_INS_VEXTRACTF64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI32x4mr, X86_INS_VEXTRACTI32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI32x4rr, X86_INS_VEXTRACTI32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI64x4mr, X86_INS_VEXTRACTI64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTI64x4rr, X86_INS_VEXTRACTI64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTPSzmr, X86_INS_VEXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VEXTRACTPSzrr, X86_INS_VEXTRACTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD132PDZm, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD132PDZmb, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD132PSZm, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD132PSZmb, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PDZm, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PDZmb, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PDZr, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PSZm, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PSZmb, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADD213PSZr, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4mr, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4mrY, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rm, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rmY, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rr, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rrY, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rrY_REV, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr132m, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr132mY, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr132r, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr132rY, X86_INS_VFMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr213m, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr213mY, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr213r, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr213rY, X86_INS_VFMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr231m, X86_INS_VFMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr231mY, X86_INS_VFMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr231r, X86_INS_VFMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPDr231rY, X86_INS_VFMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4mr, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4mrY, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rm, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rmY, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rr, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rrY, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rrY_REV, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr132m, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr132mY, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr132r, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr132rY, X86_INS_VFMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr213m, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr213mY, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr213r, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr213rY, X86_INS_VFMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr231m, X86_INS_VFMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr231mY, X86_INS_VFMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr231r, X86_INS_VFMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDPSr231rY, X86_INS_VFMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4mr, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4rm, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4rr, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDZm, X86_INS_VFMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDZr, X86_INS_VFMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr132m, X86_INS_VFMADD132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr132r, X86_INS_VFMADD132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr213m, X86_INS_VFMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr213r, X86_INS_VFMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr231m, X86_INS_VFMADD231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSDr231r, X86_INS_VFMADD231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4mr, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4rm, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4rr, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSZm, X86_INS_VFMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSZr, X86_INS_VFMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr132m, X86_INS_VFMADD132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr132r, X86_INS_VFMADD132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr213m, X86_INS_VFMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr213r, X86_INS_VFMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr231m, X86_INS_VFMADD231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSSr231r, X86_INS_VFMADD231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4mrY, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rmY, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rrY, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rrY_REV, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr132m, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr132mY, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr132r, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr132rY, X86_INS_VFMADDSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr213m, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr213mY, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr213r, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr213rY, X86_INS_VFMADDSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr231m, X86_INS_VFMADDSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr231mY, X86_INS_VFMADDSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr231r, X86_INS_VFMADDSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPDr231rY, X86_INS_VFMADDSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4mrY, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rmY, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rrY, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rrY_REV, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr132m, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr132mY, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr132r, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr132rY, X86_INS_VFMADDSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr213m, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr213mY, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr213r, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr213rY, X86_INS_VFMADDSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr231m, X86_INS_VFMADDSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr231mY, X86_INS_VFMADDSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr231r, X86_INS_VFMADDSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMADDSUBPSr231rY, X86_INS_VFMADDSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4mrY, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rmY, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rrY, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rrY_REV, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr132m, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr132mY, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr132r, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr132rY, X86_INS_VFMSUBADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr213m, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr213mY, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr213r, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr213rY, X86_INS_VFMSUBADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr231m, X86_INS_VFMSUBADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr231mY, X86_INS_VFMSUBADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr231r, X86_INS_VFMSUBADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPDr231rY, X86_INS_VFMSUBADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4mrY, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rmY, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rrY, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rrY_REV, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr132m, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr132mY, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr132r, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr132rY, X86_INS_VFMSUBADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr213m, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr213mY, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr213r, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr213rY, X86_INS_VFMSUBADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr231m, X86_INS_VFMSUBADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr231mY, X86_INS_VFMSUBADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr231r, X86_INS_VFMSUBADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBADDPSr231rY, X86_INS_VFMSUBADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4mr, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4mrY, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rm, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rmY, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rr, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rrY, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rrY_REV, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr132m, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr132mY, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr132r, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr132rY, X86_INS_VFMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr213m, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr213mY, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr213r, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr213rY, X86_INS_VFMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr231m, X86_INS_VFMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr231mY, X86_INS_VFMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr231r, X86_INS_VFMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPDr231rY, X86_INS_VFMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4mr, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4mrY, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rm, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rmY, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rr, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rrY, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rrY_REV, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr132m, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr132mY, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr132r, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr132rY, X86_INS_VFMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr213m, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr213mY, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr213r, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr213rY, X86_INS_VFMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr231m, X86_INS_VFMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr231mY, X86_INS_VFMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr231r, X86_INS_VFMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBPSr231rY, X86_INS_VFMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4mr, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4rm, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4rr, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDZm, X86_INS_VFMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDZr, X86_INS_VFMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr132m, X86_INS_VFMSUB132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr132r, X86_INS_VFMSUB132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr213m, X86_INS_VFMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr213r, X86_INS_VFMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr231m, X86_INS_VFMSUB231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSDr231r, X86_INS_VFMSUB231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4mr, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4rm, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4rr, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSZm, X86_INS_VFMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSZr, X86_INS_VFMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr132m, X86_INS_VFMSUB132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr132r, X86_INS_VFMSUB132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr213m, X86_INS_VFMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr213r, X86_INS_VFMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr231m, X86_INS_VFMSUB231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFMSUBSSr231r, X86_INS_VFMSUB231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4mr, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4mrY, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rm, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rmY, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rr, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rrY, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rrY_REV, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr132m, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr132mY, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr132r, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr132rY, X86_INS_VFNMADD132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr213m, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr213mY, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr213r, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr213rY, X86_INS_VFNMADD213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr231m, X86_INS_VFNMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr231mY, X86_INS_VFNMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr231r, X86_INS_VFNMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPDr231rY, X86_INS_VFNMADD231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4mr, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4mrY, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rm, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rmY, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rr, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rrY, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rrY_REV, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr132m, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr132mY, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr132r, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr132rY, X86_INS_VFNMADD132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr213m, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr213mY, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr213r, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr213rY, X86_INS_VFNMADD213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr231m, X86_INS_VFNMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr231mY, X86_INS_VFNMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr231r, X86_INS_VFNMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDPSr231rY, X86_INS_VFNMADD231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4mr, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4rm, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4rr, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDZm, X86_INS_VFNMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDZr, X86_INS_VFNMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr132m, X86_INS_VFNMADD132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr132r, X86_INS_VFNMADD132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr213m, X86_INS_VFNMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr213r, X86_INS_VFNMADD213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr231m, X86_INS_VFNMADD231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSDr231r, X86_INS_VFNMADD231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4mr, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4rm, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4rr, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSZm, X86_INS_VFNMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSZr, X86_INS_VFNMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr132m, X86_INS_VFNMADD132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr132r, X86_INS_VFNMADD132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr213m, X86_INS_VFNMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr213r, X86_INS_VFNMADD213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr231m, X86_INS_VFNMADD231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMADDSSr231r, X86_INS_VFNMADD231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4mrY, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rmY, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rrY, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rrY_REV, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr132m, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr132mY, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr132r, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr132rY, X86_INS_VFNMSUB132PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr213m, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr213mY, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr213r, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr213rY, X86_INS_VFNMSUB213PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr231m, X86_INS_VFNMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr231mY, X86_INS_VFNMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr231r, X86_INS_VFNMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPDr231rY, X86_INS_VFNMSUB231PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4mrY, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rmY, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rrY, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rrY_REV, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr132m, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr132mY, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr132r, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr132rY, X86_INS_VFNMSUB132PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr213m, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr213mY, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr213r, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr213rY, X86_INS_VFNMSUB213PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr231m, X86_INS_VFNMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr231mY, X86_INS_VFNMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr231r, X86_INS_VFNMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBPSr231rY, X86_INS_VFNMSUB231PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDZm, X86_INS_VFNMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDZr, X86_INS_VFNMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr132m, X86_INS_VFNMSUB132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr132r, X86_INS_VFNMSUB132SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr213m, X86_INS_VFNMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr213r, X86_INS_VFNMSUB213SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr231m, X86_INS_VFNMSUB231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSDr231r, X86_INS_VFNMSUB231SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSZm, X86_INS_VFNMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSZr, X86_INS_VFNMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr132m, X86_INS_VFNMSUB132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr132r, X86_INS_VFNMSUB132SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr213m, X86_INS_VFNMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr213r, X86_INS_VFNMSUB213SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr231m, X86_INS_VFNMSUB231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFNMSUBSSr231r, X86_INS_VFNMSUB231SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FMA, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPDrm, X86_INS_VFRCZPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPDrmY, X86_INS_VFRCZPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPDrr, X86_INS_VFRCZPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPDrrY, X86_INS_VFRCZPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPSrm, X86_INS_VFRCZPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPSrmY, X86_INS_VFRCZPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPSrr, X86_INS_VFRCZPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZPSrrY, X86_INS_VFRCZPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZSDrm, X86_INS_VFRCZSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZSDrr, X86_INS_VFRCZSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZSSrm, X86_INS_VFRCZSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFRCZSSrr, X86_INS_VFRCZSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDNPDrm, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDNPDrr, X86_INS_VANDNPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDNPSrm, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDNPSrr, X86_INS_VANDNPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDPDrm, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDPDrr, X86_INS_VANDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDPSrm, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsANDPSrr, X86_INS_VANDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsORPDrm, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsORPDrr, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsORPSrm, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsORPSrr, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsXORPDrm, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsXORPDrr, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsXORPSrm, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VFsXORPSrr, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPDYrm, X86_INS_VGATHERDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPDZrm, X86_INS_VGATHERDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPDrm, X86_INS_VGATHERDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPSYrm, X86_INS_VGATHERDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPSZrm, X86_INS_VGATHERDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERDPSrm, X86_INS_VGATHERDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPDYrm, X86_INS_VGATHERQPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPDZrm, X86_INS_VGATHERQPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPDrm, X86_INS_VGATHERQPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPSYrm, X86_INS_VGATHERQPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPSZrm, X86_INS_VGATHERQPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VGATHERQPSrm, X86_INS_VGATHERQPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPDYrm, X86_INS_VHADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPDYrr, X86_INS_VHADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPDrm, X86_INS_VHADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPDrr, X86_INS_VHADDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPSYrm, X86_INS_VHADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPSYrr, X86_INS_VHADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPSrm, X86_INS_VHADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHADDPSrr, X86_INS_VHADDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPDYrm, X86_INS_VHSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPDYrr, X86_INS_VHSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPDrm, X86_INS_VHSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPDrr, X86_INS_VHSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPSYrm, X86_INS_VHSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPSYrr, X86_INS_VHSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPSrm, X86_INS_VHSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VHSUBPSrr, X86_INS_VHSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF128rm, X86_INS_VINSERTF128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF128rr, X86_INS_VINSERTF128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF32x4rm, X86_INS_VINSERTF32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF32x4rr, X86_INS_VINSERTF32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF64x4rm, X86_INS_VINSERTF64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTF64x4rr, X86_INS_VINSERTF64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI128rm, X86_INS_VINSERTI128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI128rr, X86_INS_VINSERTI128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI32x4rm, X86_INS_VINSERTI32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI32x4rr, X86_INS_VINSERTI32X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI64x4rm, X86_INS_VINSERTI64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTI64x4rr, X86_INS_VINSERTI64X4,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTPSrm, X86_INS_VINSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTPSrr, X86_INS_VINSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTPSzrm, X86_INS_VINSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VINSERTPSzrr, X86_INS_VINSERTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VLDDQUYrm, X86_INS_VLDDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VLDDQUrm, X86_INS_VLDDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VLDMXCSR, X86_INS_VLDMXCSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPDYrm, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPDYrr, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPDrm, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPDrr, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPSYrm, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPSYrr, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPSrm, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCPSrr, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCSDrm, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCSDrr, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCSSrm, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXCSSrr, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDYrm, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDYrr, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDZrm, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDZrmb, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDZrr, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDrm, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPDrr, X86_INS_VMAXPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSYrm, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSYrr, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSZrm, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSZrmb, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSZrr, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSrm, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXPSrr, X86_INS_VMAXPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDZrm, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDZrr, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDrm, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDrm_Int, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDrr, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSDrr_Int, X86_INS_VMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSZrm, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSZrr, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSrm, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSrm_Int, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSrr, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMAXSSrr_Int, X86_INS_VMAXSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMCALL, X86_INS_VMCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMCLEARm, X86_INS_VMCLEAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMFUNC, X86_INS_VMFUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPDYrm, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPDYrr, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPDrm, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPDrr, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPSYrm, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPSYrr, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPSrm, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCPSrr, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCSDrm, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCSDrr, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCSSrm, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINCSSrr, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDYrm, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDYrr, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDZrm, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDZrmb, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDZrr, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDrm, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPDrr, X86_INS_VMINPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSYrm, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSYrr, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSZrm, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSZrmb, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSZrr, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSrm, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINPSrr, X86_INS_VMINPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDZrm, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDZrr, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDrm, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDrm_Int, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDrr, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSDrr_Int, X86_INS_VMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSZrm, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSZrr, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSrm, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSrm_Int, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSrr, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMINSSrr_Int, X86_INS_VMINSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMLAUNCH, X86_INS_VMLAUNCH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMLOAD32, X86_INS_VMLOAD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMLOAD64, X86_INS_VMLOAD,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMMCALL, X86_INS_VMMCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOV64toPQIZrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOV64toPQIrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOV64toSDZrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOV64toSDrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOV64toSDrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDYmr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDYrm, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDYrr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDZmr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDZrm, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDZrmk, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDZrr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDZrrk, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDmr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDrm, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDrr, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPDrr_REV, X86_INS_VMOVAPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSYmr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSYrm, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSYrr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSZmr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSZrm, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSZrmk, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSZrr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSZrrk, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSmr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSrm, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSrr, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVAPSrr_REV, X86_INS_VMOVAPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPYrm, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPYrr, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPZrm, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPZrr, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPrm, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDDUPrr, X86_INS_VMOVDDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2PDIZrm, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2PDIZrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2PDIrm, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2PDIrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2SSZrm, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2SSZrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2SSrm, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDI2SSrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA32mr, X86_INS_VMOVDQA32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA32rm, X86_INS_VMOVDQA32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA32rr, X86_INS_VMOVDQA32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA64mr, X86_INS_VMOVDQA64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA64rm, X86_INS_VMOVDQA64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQA64rr, X86_INS_VMOVDQA64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQAYmr, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQAYrm, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQAYrr, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQAmr, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQArm, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQArr, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQArr_REV, X86_INS_VMOVDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32mr, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32rm, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32rmk, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32rr, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32rrk, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU32rrkz, X86_INS_VMOVDQU32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64mr, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64rm, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64rmk, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64rr, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64rrk, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQU64rrkz, X86_INS_VMOVDQU64,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUYmr, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUYrm, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUYrr, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUmr, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUrm, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUrr, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVDQUrr_REV, X86_INS_VMOVDQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHLPSZrr, X86_INS_VMOVHLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHLPSrr, X86_INS_VMOVHLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHPDmr, X86_INS_VMOVHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHPDrm, X86_INS_VMOVHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHPSmr, X86_INS_VMOVHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVHPSrm, X86_INS_VMOVHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLHPSZrr, X86_INS_VMOVLHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLHPSrr, X86_INS_VMOVLHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLPDmr, X86_INS_VMOVLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLPDrm, X86_INS_VMOVLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLPSmr, X86_INS_VMOVLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVLPSrm, X86_INS_VMOVLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTDQArm, X86_INS_VMOVNTDQA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTDQmr, X86_INS_VMOVNTDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTPDYmr, X86_INS_VMOVNTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTPDmr, X86_INS_VMOVNTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTPSYmr, X86_INS_VMOVNTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVNTPSmr, X86_INS_VMOVNTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPDI2DIZmr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPDI2DIZrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPDI2DImr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPDI2DIrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPQI2QImr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPQI2QIrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPQIto64Zmr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPQIto64Zrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVPQIto64rr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVQI2PQIZrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVQI2PQIrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDZmr, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDZrm, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDZrr, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDZrr_REV, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDZrrk, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDmr, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDrm, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDrr, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDrr_REV, X86_INS_VMOVSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDto64Zmr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDto64Zrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDto64mr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSDto64rr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSS2DIZmr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSS2DIZrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSS2DImr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSS2DIrr, X86_INS_VMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSZmr, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSZrm, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSZrr, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSZrr_REV, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSZrrk, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSmr, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSrm, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSrr, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVSSrr_REV, X86_INS_VMOVSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDYmr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDYrm, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDYrr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDZmr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDZrm, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDZrmk, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDZrr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDZrrk, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDmr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDrm, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDrr, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPDrr_REV, X86_INS_VMOVUPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSYmr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSYrm, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSYrr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSZmr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSZrm, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSZrmk, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSZrr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSZrrk, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSmr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSrm, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSrr, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVUPSrr_REV, X86_INS_VMOVUPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZPQILo2PQIZrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZPQILo2PQIrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZQI2PQIrm, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMOVZQI2PQIrr, X86_INS_VMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPSADBWYrmi, X86_INS_VMPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPSADBWYrri, X86_INS_VMPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPSADBWrmi, X86_INS_VMPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPSADBWrri, X86_INS_VMPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPTRLDm, X86_INS_VMPTRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMPTRSTm, X86_INS_VMPTRST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMREAD32rm, X86_INS_VMREAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMREAD32rr, X86_INS_VMREAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMREAD64rm, X86_INS_VMREAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMREAD64rr, X86_INS_VMREAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMRESUME, X86_INS_VMRESUME,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMRUN32, X86_INS_VMRUN,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMRUN64, X86_INS_VMRUN,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMSAVE32, X86_INS_VMSAVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMSAVE64, X86_INS_VMSAVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDYrm, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDYrr, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDZrm, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDZrmb, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDZrr, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDrm, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPDrr, X86_INS_VMULPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSYrm, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSYrr, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSZrm, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSZrmb, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSZrr, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSrm, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULPSrr, X86_INS_VMULPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDZrm, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDZrr, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDrm, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDrm_Int, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDrr, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSDrr_Int, X86_INS_VMULSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSZrm, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSZrr, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSrm, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSrm_Int, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSrr, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMULSSrr_Int, X86_INS_VMULSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMWRITE32rm, X86_INS_VMWRITE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMWRITE32rr, X86_INS_VMWRITE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMWRITE64rm, X86_INS_VMWRITE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMWRITE64rr, X86_INS_VMWRITE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMXOFF, X86_INS_VMXOFF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VMXON, X86_INS_VMXON,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPDYrm, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPDYrr, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPDrm, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPDrr, X86_INS_VORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPSYrm, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPSYrr, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPSrm, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VORPSrr, X86_INS_VORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSBrm128, X86_INS_VPABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSBrm256, X86_INS_VPABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSBrr128, X86_INS_VPABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSBrr256, X86_INS_VPABSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrm, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrm128, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrm256, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrr, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrr128, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSDrr256, X86_INS_VPABSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSQrm, X86_INS_VPABSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSQrr, X86_INS_VPABSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSWrm128, X86_INS_VPABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSWrm256, X86_INS_VPABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSWrr128, X86_INS_VPABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPABSWrr256, X86_INS_VPABSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSDWYrm, X86_INS_VPACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSDWYrr, X86_INS_VPACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSDWrm, X86_INS_VPACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSDWrr, X86_INS_VPACKSSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSWBYrm, X86_INS_VPACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSWBYrr, X86_INS_VPACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSWBrm, X86_INS_VPACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKSSWBrr, X86_INS_VPACKSSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSDWYrm, X86_INS_VPACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSDWYrr, X86_INS_VPACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSDWrm, X86_INS_VPACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSDWrr, X86_INS_VPACKUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSWBYrm, X86_INS_VPACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSWBYrr, X86_INS_VPACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSWBrm, X86_INS_VPACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPACKUSWBrr, X86_INS_VPACKUSWB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDBYrm, X86_INS_VPADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDBYrr, X86_INS_VPADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDBrm, X86_INS_VPADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDBrr, X86_INS_VPADDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDYrm, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDYrr, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDZrm, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDZrmb, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDZrr, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDrm, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDDrr, X86_INS_VPADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQYrm, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQYrr, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQZrm, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQZrmb, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQZrr, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQrm, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDQrr, X86_INS_VPADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSBYrm, X86_INS_VPADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSBYrr, X86_INS_VPADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSBrm, X86_INS_VPADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSBrr, X86_INS_VPADDSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSWYrm, X86_INS_VPADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSWYrr, X86_INS_VPADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSWrm, X86_INS_VPADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDSWrr, X86_INS_VPADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSBYrm, X86_INS_VPADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSBYrr, X86_INS_VPADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSBrm, X86_INS_VPADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSBrr, X86_INS_VPADDUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSWYrm, X86_INS_VPADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSWYrr, X86_INS_VPADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSWrm, X86_INS_VPADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDUSWrr, X86_INS_VPADDUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDWYrm, X86_INS_VPADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDWYrr, X86_INS_VPADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDWrm, X86_INS_VPADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPADDWrr, X86_INS_VPADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPALIGNR128rm, X86_INS_VPALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPALIGNR128rr, X86_INS_VPALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPALIGNR256rm, X86_INS_VPALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPALIGNR256rr, X86_INS_VPALIGNR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDDZrm, X86_INS_VPANDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDDZrmb, X86_INS_VPANDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDDZrr, X86_INS_VPANDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNDZrm, X86_INS_VPANDND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNDZrmb, X86_INS_VPANDND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNDZrr, X86_INS_VPANDND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNQZrm, X86_INS_VPANDNQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNQZrmb, X86_INS_VPANDNQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNQZrr, X86_INS_VPANDNQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNYrm, X86_INS_VPANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNYrr, X86_INS_VPANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNrm, X86_INS_VPANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDNrr, X86_INS_VPANDN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDQZrm, X86_INS_VPANDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDQZrmb, X86_INS_VPANDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDQZrr, X86_INS_VPANDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDYrm, X86_INS_VPAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDYrr, X86_INS_VPAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDrm, X86_INS_VPAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPANDrr, X86_INS_VPAND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGBYrm, X86_INS_VPAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGBYrr, X86_INS_VPAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGBrm, X86_INS_VPAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGBrr, X86_INS_VPAVGB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGWYrm, X86_INS_VPAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGWYrr, X86_INS_VPAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGWrm, X86_INS_VPAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPAVGWrr, X86_INS_VPAVGW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDDYrmi, X86_INS_VPBLENDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDDYrri, X86_INS_VPBLENDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDDrmi, X86_INS_VPBLENDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDDrri, X86_INS_VPBLENDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDMDZrm, X86_INS_VPBLENDMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDMDZrr, X86_INS_VPBLENDMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDVBYrm, X86_INS_VPBLENDVB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDVBYrr, X86_INS_VPBLENDVB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDVBrm, X86_INS_VPBLENDVB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDVBrr, X86_INS_VPBLENDVB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDWYrmi, X86_INS_VPBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDWYrri, X86_INS_VPBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDWrmi, X86_INS_VPBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBLENDWrri, X86_INS_VPBLENDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDZkrm, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDZkrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDZrm, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDZrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDrZkrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDrZrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTMB2Qrr, X86_INS_VPBROADCASTMB2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTMW2Drr, X86_INS_VPBROADCASTMW2D,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQZkrm, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQZkrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQZrm, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQZrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQrZkrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQrZrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVmr, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVmrY, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVrm, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVrmY, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVrr, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMOVrrY, X86_INS_VPCMOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPDZrmi, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPDZrmi_alt, X86_INS_VPCMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPDZrri, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPDZrri_alt, X86_INS_VPCMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQBYrm, X86_INS_VPCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQBYrr, X86_INS_VPCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQBrm, X86_INS_VPCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQBrr, X86_INS_VPCMPEQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDYrm, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDYrr, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDZrm, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDZrr, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDrm, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQDrr, X86_INS_VPCMPEQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQrm, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQQrr, X86_INS_VPCMPEQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQWYrm, X86_INS_VPCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQWYrr, X86_INS_VPCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQWrm, X86_INS_VPCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPEQWrr, X86_INS_VPCMPEQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPESTRM128rm, X86_INS_VPCMPESTRM,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPESTRM128rr, X86_INS_VPCMPESTRM,
+#ifndef CAPSTONE_DIET
+ { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTBYrm, X86_INS_VPCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTBYrr, X86_INS_VPCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTBrm, X86_INS_VPCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTBrr, X86_INS_VPCMPGTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDYrm, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDYrr, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDZrm, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDZrr, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDrm, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTDrr, X86_INS_VPCMPGTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQrm, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTQrr, X86_INS_VPCMPGTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTWYrm, X86_INS_VPCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTWYrr, X86_INS_VPCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTWrm, X86_INS_VPCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPGTWrr, X86_INS_VPCMPGTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPISTRM128rm, X86_INS_VPCMPISTRM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPISTRM128rr, X86_INS_VPCMPISTRM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_XMM0, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPQZrmi, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPQZrri, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPQZrri_alt, X86_INS_VPCMPQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUDZrmi, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUDZrri, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUQZrmi, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUQZrri, X86_INS_VPCMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMBmi, X86_INS_VPCOMB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMBri, X86_INS_VPCOMB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMDmi, X86_INS_VPCOMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMDri, X86_INS_VPCOMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMQmi, X86_INS_VPCOMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMQri, X86_INS_VPCOMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUBmi, X86_INS_VPCOMUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUBri, X86_INS_VPCOMUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUDmi, X86_INS_VPCOMUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUDri, X86_INS_VPCOMUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUQmi, X86_INS_VPCOMUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUQri, X86_INS_VPCOMUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUWmi, X86_INS_VPCOMUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMUWri, X86_INS_VPCOMUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMWmi, X86_INS_VPCOMW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCOMWri, X86_INS_VPCOMW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrm, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrmb, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrmbk, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrmbkz, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrmk, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrmkz, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrr, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrrk, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTDrrkz, X86_INS_VPCONFLICTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrm, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrmb, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrmbk, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrmbkz, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrmk, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrmkz, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrr, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrrk, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPCONFLICTQrrkz, X86_INS_VPCONFLICTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERM2F128rm, X86_INS_VPERM2F128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERM2F128rr, X86_INS_VPERM2F128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERM2I128rm, X86_INS_VPERM2I128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERM2I128rr, X86_INS_VPERM2I128,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMDYrm, X86_INS_VPERMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMDYrr, X86_INS_VPERMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMDZrm, X86_INS_VPERMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMDZrr, X86_INS_VPERMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2Drm, X86_INS_VPERMI2D,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2Drr, X86_INS_VPERMI2D,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2PDrm, X86_INS_VPERMI2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2PDrr, X86_INS_VPERMI2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2PSrm, X86_INS_VPERMI2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2PSrr, X86_INS_VPERMI2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2Qrm, X86_INS_VPERMI2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMI2Qrr, X86_INS_VPERMI2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDmrY, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDrmY, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PDrrY, X86_INS_VPERMIL2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSmrY, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSrmY, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMIL2PSrrY, X86_INS_VPERMIL2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDYmi, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDYri, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDYrm, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDYrr, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDZmi, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDZri, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDmi, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDri, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDrm, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPDrr, X86_INS_VPERMILPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSYmi, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSYri, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSYrm, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSYrr, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSZmi, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSZri, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSmi, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSri, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSrm, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMILPSrr, X86_INS_VPERMILPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDYmi, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDYri, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDZmi, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDZri, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDZrm, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPDZrr, X86_INS_VPERMPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPSYrm, X86_INS_VPERMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPSYrr, X86_INS_VPERMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPSZrm, X86_INS_VPERMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMPSZrr, X86_INS_VPERMPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQYmi, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQYri, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQZmi, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQZri, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQZrm, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMQZrr, X86_INS_VPERMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2Drm, X86_INS_VPERMT2D,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2Drr, X86_INS_VPERMT2D,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2PDrm, X86_INS_VPERMT2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2PDrr, X86_INS_VPERMT2PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2PSrm, X86_INS_VPERMT2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2PSrr, X86_INS_VPERMT2PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2Qrm, X86_INS_VPERMT2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPERMT2Qrr, X86_INS_VPERMT2Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRBmr, X86_INS_VPEXTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRBrr, X86_INS_VPEXTRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRDmr, X86_INS_VPEXTRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRDrr, X86_INS_VPEXTRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRQmr, X86_INS_VPEXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRQrr, X86_INS_VPEXTRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRWmr, X86_INS_VPEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRWri, X86_INS_VPEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPEXTRWrr_REV, X86_INS_VPEXTRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDDYrm, X86_INS_VPGATHERDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDDZrm, X86_INS_VPGATHERDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDDrm, X86_INS_VPGATHERDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERDQrm, X86_INS_VPGATHERDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQDYrm, X86_INS_VPGATHERQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQDZrm, X86_INS_VPGATHERQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQDrm, X86_INS_VPGATHERQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPGATHERQQrm, X86_INS_VPGATHERQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBDrm, X86_INS_VPHADDBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBDrr, X86_INS_VPHADDBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBQrm, X86_INS_VPHADDBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBQrr, X86_INS_VPHADDBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBWrm, X86_INS_VPHADDBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDBWrr, X86_INS_VPHADDBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDQrm, X86_INS_VPHADDDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDQrr, X86_INS_VPHADDDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDYrm, X86_INS_VPHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDYrr, X86_INS_VPHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDrm, X86_INS_VPHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDDrr, X86_INS_VPHADDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDSWrm128, X86_INS_VPHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDSWrm256, X86_INS_VPHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDSWrr128, X86_INS_VPHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDSWrr256, X86_INS_VPHADDSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBDrm, X86_INS_VPHADDUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBDrr, X86_INS_VPHADDUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBQrm, X86_INS_VPHADDUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBQrr, X86_INS_VPHADDUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBWrm, X86_INS_VPHADDUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUBWrr, X86_INS_VPHADDUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUDQrm, X86_INS_VPHADDUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUDQrr, X86_INS_VPHADDUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUWDrm, X86_INS_VPHADDUWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUWDrr, X86_INS_VPHADDUWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUWQrm, X86_INS_VPHADDUWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDUWQrr, X86_INS_VPHADDUWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWDrm, X86_INS_VPHADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWDrr, X86_INS_VPHADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWQrm, X86_INS_VPHADDWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWQrr, X86_INS_VPHADDWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWYrm, X86_INS_VPHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWYrr, X86_INS_VPHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWrm, X86_INS_VPHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHADDWrr, X86_INS_VPHADDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHMINPOSUWrm128, X86_INS_VPHMINPOSUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHMINPOSUWrr128, X86_INS_VPHMINPOSUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBBWrm, X86_INS_VPHSUBBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBBWrr, X86_INS_VPHSUBBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDQrm, X86_INS_VPHSUBDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDQrr, X86_INS_VPHSUBDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDYrm, X86_INS_VPHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDYrr, X86_INS_VPHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDrm, X86_INS_VPHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBDrr, X86_INS_VPHSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBSWrm128, X86_INS_VPHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBSWrm256, X86_INS_VPHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBSWrr128, X86_INS_VPHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBSWrr256, X86_INS_VPHSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWDrm, X86_INS_VPHSUBWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWDrr, X86_INS_VPHSUBWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWYrm, X86_INS_VPHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWYrr, X86_INS_VPHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWrm, X86_INS_VPHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPHSUBWrr, X86_INS_VPHSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRBrm, X86_INS_VPINSRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRBrr, X86_INS_VPINSRB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRDrm, X86_INS_VPINSRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRDrr, X86_INS_VPINSRD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRQrm, X86_INS_VPINSRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRQrr, X86_INS_VPINSRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRWrmi, X86_INS_VPINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPINSRWrri, X86_INS_VPINSRW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDDrm, X86_INS_VPMACSDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDDrr, X86_INS_VPMACSDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDQHrm, X86_INS_VPMACSDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDQHrr, X86_INS_VPMACSDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDQLrm, X86_INS_VPMACSDQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSDQLrr, X86_INS_VPMACSDQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDDrm, X86_INS_VPMACSSDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDDrr, X86_INS_VPMACSSDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSWDrm, X86_INS_VPMACSSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSWDrr, X86_INS_VPMACSSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSWWrm, X86_INS_VPMACSSWW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSSWWrr, X86_INS_VPMACSSWW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSWDrm, X86_INS_VPMACSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSWDrr, X86_INS_VPMACSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSWWrm, X86_INS_VPMACSWW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMACSWWrr, X86_INS_VPMACSWW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADCSWDrm, X86_INS_VPMADCSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADCSWDrr, X86_INS_VPMADCSWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDUBSWrm128, X86_INS_VPMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDUBSWrm256, X86_INS_VPMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDUBSWrr128, X86_INS_VPMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDUBSWrr256, X86_INS_VPMADDUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDWDYrm, X86_INS_VPMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDWDYrr, X86_INS_VPMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDWDrm, X86_INS_VPMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMADDWDrr, X86_INS_VPMADDWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSBYrm, X86_INS_VPMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSBYrr, X86_INS_VPMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSBrm, X86_INS_VPMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSBrr, X86_INS_VPMAXSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDYrm, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDYrr, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDZrm, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDZrmb, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDZrr, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDrm, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSDrr, X86_INS_VPMAXSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSQZrm, X86_INS_VPMAXSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSQZrmb, X86_INS_VPMAXSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSQZrr, X86_INS_VPMAXSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSWYrm, X86_INS_VPMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSWYrr, X86_INS_VPMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSWrm, X86_INS_VPMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXSWrr, X86_INS_VPMAXSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUBYrm, X86_INS_VPMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUBYrr, X86_INS_VPMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUBrm, X86_INS_VPMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUBrr, X86_INS_VPMAXUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDYrm, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDYrr, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDZrm, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDZrmb, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDZrr, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDrm, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUDrr, X86_INS_VPMAXUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUQZrm, X86_INS_VPMAXUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUQZrmb, X86_INS_VPMAXUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUQZrr, X86_INS_VPMAXUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUWYrm, X86_INS_VPMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUWYrr, X86_INS_VPMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUWrm, X86_INS_VPMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMAXUWrr, X86_INS_VPMAXUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSBYrm, X86_INS_VPMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSBYrr, X86_INS_VPMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSBrm, X86_INS_VPMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSBrr, X86_INS_VPMINSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDYrm, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDYrr, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDZrm, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDZrmb, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDZrr, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDrm, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSDrr, X86_INS_VPMINSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSQZrm, X86_INS_VPMINSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSQZrmb, X86_INS_VPMINSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSQZrr, X86_INS_VPMINSQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSWYrm, X86_INS_VPMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSWYrr, X86_INS_VPMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSWrm, X86_INS_VPMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINSWrr, X86_INS_VPMINSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUBYrm, X86_INS_VPMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUBYrr, X86_INS_VPMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUBrm, X86_INS_VPMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUBrr, X86_INS_VPMINUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDYrm, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDYrr, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDZrm, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDZrmb, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDZrr, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDrm, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUDrr, X86_INS_VPMINUD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUQZrm, X86_INS_VPMINUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUQZrmb, X86_INS_VPMINUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUQZrr, X86_INS_VPMINUQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUWYrm, X86_INS_VPMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUWYrr, X86_INS_VPMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUWrm, X86_INS_VPMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMINUWrr, X86_INS_VPMINUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDBkrr, X86_INS_VPMOVDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDBmr, X86_INS_VPMOVDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDBrr, X86_INS_VPMOVDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDWkrr, X86_INS_VPMOVDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDWmr, X86_INS_VPMOVDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVDWrr, X86_INS_VPMOVDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQBkrr, X86_INS_VPMOVQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQBmr, X86_INS_VPMOVQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQBrr, X86_INS_VPMOVQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQDkrr, X86_INS_VPMOVQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQDmr, X86_INS_VPMOVQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQDrr, X86_INS_VPMOVQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQWkrr, X86_INS_VPMOVQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQWmr, X86_INS_VPMOVQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVQWrr, X86_INS_VPMOVQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDBkrr, X86_INS_VPMOVSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDBmr, X86_INS_VPMOVSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDBrr, X86_INS_VPMOVSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDWkrr, X86_INS_VPMOVSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDWmr, X86_INS_VPMOVSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSDWrr, X86_INS_VPMOVSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQBkrr, X86_INS_VPMOVSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQBmr, X86_INS_VPMOVSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQBrr, X86_INS_VPMOVSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQDkrr, X86_INS_VPMOVSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQDmr, X86_INS_VPMOVSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQDrr, X86_INS_VPMOVSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQWkrr, X86_INS_VPMOVSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQWmr, X86_INS_VPMOVSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSQWrr, X86_INS_VPMOVSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDBkrr, X86_INS_VPMOVUSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDBmr, X86_INS_VPMOVUSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDBrr, X86_INS_VPMOVUSDB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDWkrr, X86_INS_VPMOVUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDWmr, X86_INS_VPMOVUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSDWrr, X86_INS_VPMOVUSDW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQBkrr, X86_INS_VPMOVUSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQBmr, X86_INS_VPMOVUSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQBrr, X86_INS_VPMOVUSQB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQDkrr, X86_INS_VPMOVUSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQDmr, X86_INS_VPMOVUSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQDrr, X86_INS_VPMOVUSQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQWkrr, X86_INS_VPMOVUSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQWmr, X86_INS_VPMOVUSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVUSQWrr, X86_INS_VPMOVUSQW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQYrm, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQYrr, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQZrm, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQZrr, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQrm, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULDQrr, X86_INS_VPMULDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHRSWrm128, X86_INS_VPMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHRSWrm256, X86_INS_VPMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHRSWrr128, X86_INS_VPMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHRSWrr256, X86_INS_VPMULHRSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHUWYrm, X86_INS_VPMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHUWYrr, X86_INS_VPMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHUWrm, X86_INS_VPMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHUWrr, X86_INS_VPMULHUW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHWYrm, X86_INS_VPMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHWYrr, X86_INS_VPMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHWrm, X86_INS_VPMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULHWrr, X86_INS_VPMULHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDYrm, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDYrr, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDZrm, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDZrmb, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDZrr, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDrm, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLDrr, X86_INS_VPMULLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLWYrm, X86_INS_VPMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLWYrr, X86_INS_VPMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLWrm, X86_INS_VPMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULLWrr, X86_INS_VPMULLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQYrm, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQYrr, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQZrm, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQZrr, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQrm, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPMULUDQrr, X86_INS_VPMULUDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORDZrm, X86_INS_VPORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORDZrmb, X86_INS_VPORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORDZrr, X86_INS_VPORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORQZrm, X86_INS_VPORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORQZrmb, X86_INS_VPORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORQZrr, X86_INS_VPORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORYrm, X86_INS_VPOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORYrr, X86_INS_VPOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORrm, X86_INS_VPOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPORrr, X86_INS_VPOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPPERMmr, X86_INS_VPPERM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPPERMrm, X86_INS_VPPERM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPPERMrr, X86_INS_VPPERM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTBmi, X86_INS_VPROTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTBmr, X86_INS_VPROTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTBri, X86_INS_VPROTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTBrm, X86_INS_VPROTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTBrr, X86_INS_VPROTB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTDmi, X86_INS_VPROTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTDmr, X86_INS_VPROTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTDri, X86_INS_VPROTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTDrm, X86_INS_VPROTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTDrr, X86_INS_VPROTD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTQmi, X86_INS_VPROTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTQmr, X86_INS_VPROTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTQri, X86_INS_VPROTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTQrm, X86_INS_VPROTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTQrr, X86_INS_VPROTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTWmi, X86_INS_VPROTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTWmr, X86_INS_VPROTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTWri, X86_INS_VPROTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTWrm, X86_INS_VPROTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPROTWrr, X86_INS_VPROTW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSADBWYrm, X86_INS_VPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSADBWYrr, X86_INS_VPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSADBWrm, X86_INS_VPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSADBWrr, X86_INS_VPSADBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHABmr, X86_INS_VPSHAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHABrm, X86_INS_VPSHAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHABrr, X86_INS_VPSHAB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHADmr, X86_INS_VPSHAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHADrm, X86_INS_VPSHAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHADrr, X86_INS_VPSHAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAQmr, X86_INS_VPSHAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAQrm, X86_INS_VPSHAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAQrr, X86_INS_VPSHAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAWmr, X86_INS_VPSHAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAWrm, X86_INS_VPSHAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHAWrr, X86_INS_VPSHAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLBmr, X86_INS_VPSHLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLBrm, X86_INS_VPSHLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLBrr, X86_INS_VPSHLB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLDmr, X86_INS_VPSHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLDrm, X86_INS_VPSHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLDrr, X86_INS_VPSHLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLQmr, X86_INS_VPSHLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLQrm, X86_INS_VPSHLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLQrr, X86_INS_VPSHLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLWmr, X86_INS_VPSHLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLWrm, X86_INS_VPSHLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHLWrr, X86_INS_VPSHLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFBYrm, X86_INS_VPSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFBYrr, X86_INS_VPSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFBrm, X86_INS_VPSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFBrr, X86_INS_VPSHUFB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDYmi, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDYri, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDZmi, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDZri, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDmi, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFDri, X86_INS_VPSHUFD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFHWYmi, X86_INS_VPSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFHWYri, X86_INS_VPSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFHWmi, X86_INS_VPSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFHWri, X86_INS_VPSHUFHW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFLWYmi, X86_INS_VPSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFLWYri, X86_INS_VPSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFLWmi, X86_INS_VPSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSHUFLWri, X86_INS_VPSHUFLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNBYrm, X86_INS_VPSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNBYrr, X86_INS_VPSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNBrm, X86_INS_VPSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNBrr, X86_INS_VPSIGNB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNDYrm, X86_INS_VPSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNDYrr, X86_INS_VPSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNDrm, X86_INS_VPSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNDrr, X86_INS_VPSIGND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNWYrm, X86_INS_VPSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNWYrr, X86_INS_VPSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNWrm, X86_INS_VPSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSIGNWrr, X86_INS_VPSIGNW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDQYri, X86_INS_VPSLLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDQri, X86_INS_VPSLLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDYri, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDYrm, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDYrr, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZmi, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZmik, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZri, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZrik, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZrm, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZrmk, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZrr, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDZrrk, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDri, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDrm, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLDrr, X86_INS_VPSLLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQYri, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQYrm, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQYrr, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZmi, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZmik, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZri, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZrik, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZrm, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZrmk, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZrr, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQZrrk, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQri, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQrm, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLQrr, X86_INS_VPSLLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDYrm, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDYrr, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDZrm, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDZrr, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDrm, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVDrr, X86_INS_VPSLLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQYrm, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQYrr, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQZrm, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQZrr, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQrm, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLVQrr, X86_INS_VPSLLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWYri, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWYrm, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWYrr, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWri, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWrm, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSLLWrr, X86_INS_VPSLLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADYri, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADYrm, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADYrr, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZmi, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZmik, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZri, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZrik, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZrm, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZrmk, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZrr, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADZrrk, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADri, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADrm, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRADrr, X86_INS_VPSRAD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZmi, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZmik, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZri, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZrik, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZrm, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZrmk, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZrr, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAQZrrk, X86_INS_VPSRAQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDYrm, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDYrr, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDZrm, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDZrr, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDrm, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVDrr, X86_INS_VPSRAVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVQZrm, X86_INS_VPSRAVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAVQZrr, X86_INS_VPSRAVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWYri, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWYrm, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWYrr, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWri, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWrm, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRAWrr, X86_INS_VPSRAW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDQYri, X86_INS_VPSRLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDQri, X86_INS_VPSRLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDYri, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDYrm, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDYrr, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZmi, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZmik, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZri, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZrik, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZrm, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZrmk, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZrr, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDZrrk, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDri, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDrm, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLDrr, X86_INS_VPSRLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQYri, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQYrm, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQYrr, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZmi, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZmik, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZri, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZrik, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZrm, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZrmk, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZrr, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQZrrk, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQri, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQrm, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLQrr, X86_INS_VPSRLQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDYrm, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDYrr, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDZrm, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDZrr, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDrm, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVDrr, X86_INS_VPSRLVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQYrm, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQYrr, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQZrm, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQZrr, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQrm, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLVQrr, X86_INS_VPSRLVQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWYri, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWYrm, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWYrr, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWri, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWrm, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSRLWrr, X86_INS_VPSRLW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBBYrm, X86_INS_VPSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBBYrr, X86_INS_VPSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBBrm, X86_INS_VPSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBBrr, X86_INS_VPSUBB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDYrm, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDYrr, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDZrm, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDZrmb, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDZrr, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDrm, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBDrr, X86_INS_VPSUBD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQYrm, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQYrr, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQZrm, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQZrmb, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQZrr, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQrm, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBQrr, X86_INS_VPSUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSBYrm, X86_INS_VPSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSBYrr, X86_INS_VPSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSBrm, X86_INS_VPSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSBrr, X86_INS_VPSUBSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSWYrm, X86_INS_VPSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSWYrr, X86_INS_VPSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSWrm, X86_INS_VPSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBSWrr, X86_INS_VPSUBSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSBYrm, X86_INS_VPSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSBYrr, X86_INS_VPSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSBrm, X86_INS_VPSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSBrr, X86_INS_VPSUBUSB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSWYrm, X86_INS_VPSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSWYrr, X86_INS_VPSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSWrm, X86_INS_VPSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBUSWrr, X86_INS_VPSUBUSW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBWYrm, X86_INS_VPSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBWYrr, X86_INS_VPSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBWrm, X86_INS_VPSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPSUBWrr, X86_INS_VPSUBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTMDZrm, X86_INS_VPTESTMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTMDZrr, X86_INS_VPTESTMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTMQZrm, X86_INS_VPTESTMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTMQZrr, X86_INS_VPTESTMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTNMDZrm, X86_INS_VPTESTNMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTNMDZrr, X86_INS_VPTESTNMD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTYrm, X86_INS_VPTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTYrr, X86_INS_VPTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTrm, X86_INS_VPTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPTESTrr, X86_INS_VPTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORDZrm, X86_INS_VPXORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORDZrmb, X86_INS_VPXORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORDZrr, X86_INS_VPXORD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORQZrm, X86_INS_VPXORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORQZrmb, X86_INS_VPXORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORQZrr, X86_INS_VPXORQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORYrm, X86_INS_VPXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORYrr, X86_INS_VPXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORrm, X86_INS_VPXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VPXORrr, X86_INS_VPXOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14PDZm, X86_INS_VRCP14PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14PDZr, X86_INS_VRCP14PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14PSZm, X86_INS_VRCP14PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14PSZr, X86_INS_VRCP14PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14SDrm, X86_INS_VRCP14SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14SDrr, X86_INS_VRCP14SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14SSrm, X86_INS_VRCP14SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP14SSrr, X86_INS_VRCP14SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PDZm, X86_INS_VRCP28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PDZr, X86_INS_VRCP28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PDZrb, X86_INS_VRCP28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PSZm, X86_INS_VRCP28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PSZr, X86_INS_VRCP28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28PSZrb, X86_INS_VRCP28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SDrm, X86_INS_VRCP28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SDrr, X86_INS_VRCP28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SDrrb, X86_INS_VRCP28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SSrm, X86_INS_VRCP28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SSrr, X86_INS_VRCP28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCP28SSrrb, X86_INS_VRCP28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSYm, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSYm_Int, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSYr, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSYr_Int, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSm, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSm_Int, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSr, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPPSr_Int, X86_INS_VRCPPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPSSm, X86_INS_VRCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPSSm_Int, X86_INS_VRCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRCPSSr, X86_INS_VRCPSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALEPDZm, X86_INS_VRNDSCALEPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALEPDZr, X86_INS_VRNDSCALEPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALEPSZm, X86_INS_VRNDSCALEPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALEPSZr, X86_INS_VRNDSCALEPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALESDm, X86_INS_VRNDSCALESD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALESDr, X86_INS_VRNDSCALESD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALESSm, X86_INS_VRNDSCALESS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRNDSCALESSr, X86_INS_VRNDSCALESS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDPDm, X86_INS_VROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDPDr, X86_INS_VROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDPSm, X86_INS_VROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDPSr, X86_INS_VROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSDm, X86_INS_VROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSDr, X86_INS_VROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSDr_Int, X86_INS_VROUNDSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSSm, X86_INS_VROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSSr, X86_INS_VROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDSSr_Int, X86_INS_VROUNDSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDYPDm, X86_INS_VROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDYPDr, X86_INS_VROUNDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDYPSm, X86_INS_VROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VROUNDYPSr, X86_INS_VROUNDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14SDrm, X86_INS_VRSQRT14SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14SDrr, X86_INS_VRSQRT14SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14SSrm, X86_INS_VRSQRT14SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT14SSrr, X86_INS_VRSQRT14SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SDrm, X86_INS_VRSQRT28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SDrr, X86_INS_VRSQRT28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SDrrb, X86_INS_VRSQRT28SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SSrm, X86_INS_VRSQRT28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SSrr, X86_INS_VRSQRT28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRT28SSrrb, X86_INS_VRSQRT28SS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_ERI, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSYm, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSYm_Int, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSYr, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSYr_Int, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSm, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSm_Int, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSr, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTPSr_Int, X86_INS_VRSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTSSm, X86_INS_VRSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VRSQRTSSr, X86_INS_VRSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDYrmi, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDYrri, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDZrmi, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDZrri, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDrmi, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPDrri, X86_INS_VSHUFPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSYrmi, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSYrri, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSZrmi, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSZrri, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSrmi, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSHUFPSrri, X86_INS_VSHUFPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDYm, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDYr, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDZm_Int, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDZr_Int, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDZrm, X86_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDZrr, X86_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDm, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPDr, X86_INS_VSQRTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSYm, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSYr, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSZm_Int, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSZr_Int, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSZrm, X86_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSZrr, X86_INS_VSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSm, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTPSr, X86_INS_VSQRTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDZm, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDZm_Int, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDZr, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDZr_Int, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDm, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDm_Int, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSDr, X86_INS_VSQRTSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSZm, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSZm_Int, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSZr, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSZr_Int, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSm, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSm_Int, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSQRTSSr, X86_INS_VSQRTSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSTMXCSR, X86_INS_VSTMXCSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDYrm, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDYrr, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDZrm, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDZrmb, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDZrr, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDrm, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPDrr, X86_INS_VSUBPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSYrm, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSYrr, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSZrm, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSZrmb, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSZrr, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSrm, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBPSrr, X86_INS_VSUBPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDZrm, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDZrr, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDrm, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDrm_Int, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDrr, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSDrr_Int, X86_INS_VSUBSD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSZrm, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSZrr, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSrm, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSrm_Int, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSrr, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VSUBSSrr_Int, X86_INS_VSUBSS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPDYrm, X86_INS_VTESTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPDYrr, X86_INS_VTESTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPDrm, X86_INS_VTESTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPDrr, X86_INS_VTESTPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPSYrm, X86_INS_VTESTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPSYrr, X86_INS_VTESTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPSrm, X86_INS_VTESTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VTESTPSrr, X86_INS_VTESTPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISDZrm, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISDZrr, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISDrm, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISDrr, X86_INS_VUCOMISD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISSZrm, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISSZrr, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISSrm, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUCOMISSrr, X86_INS_VUCOMISS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPDYrm, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPDYrr, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPDrm, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPDrr, X86_INS_VXORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPSYrm, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPSYrr, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPSrm, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VXORPSrr, X86_INS_VXORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VZEROALL, X86_INS_VZEROALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_VZEROUPPER, X86_INS_VZEROUPPER,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_W64ALLOCA, X86_INS_CALL,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RSP, 0 }, { X86_REG_RAX, X86_REG_R10, X86_REG_R11, X86_REG_RSP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WAIT, X86_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WBINVD, X86_INS_WBINVD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WRFSBASE, X86_INS_WRFSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WRFSBASE64, X86_INS_WRFSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WRGSBASE, X86_INS_WRGSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WRGSBASE64, X86_INS_WRGSBASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_WRMSR, X86_INS_WRMSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XABORT, X86_INS_XABORT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD16rm, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD16rr, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD32rm, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD32rr, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD64rm, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD64rr, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD8rm, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XADD8rr, X86_INS_XADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XBEGIN_4, X86_INS_XBEGIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_RTM, 0 }, 1, 0
+#endif
+ },
+ {
+ X86_XCHG16ar, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG16rm, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG16rr, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG32ar, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG32ar64, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG32rm, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG32rr, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG64ar, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG64rm, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG64rr, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG8rm, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCHG8rr, X86_INS_XCHG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCH_F, X86_INS_FXCH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCRYPTCBC, X86_INS_XCRYPTCBC,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCRYPTCFB, X86_INS_XCRYPTCFB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCRYPTCTR, X86_INS_XCRYPTCTR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCRYPTECB, X86_INS_XCRYPTECB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XCRYPTOFB, X86_INS_XCRYPTOFB,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XEND, X86_INS_XEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XGETBV, X86_INS_XGETBV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RCX, 0 }, { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XLAT, X86_INS_XLATB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16i16, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16ri, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16ri8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16rm, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16rr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR16rr_REV, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32i32, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32ri, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32ri8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32rm, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32rr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR32rr_REV, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64i32, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64mi32, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64mi8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64ri32, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64ri8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64rm, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64rr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR64rr_REV, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8i8, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8mi, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8mr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8ri, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8rm, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8rr, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XOR8rr_REV, X86_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XORPDrm, X86_INS_XORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XORPDrr, X86_INS_XORPD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XORPSrm, X86_INS_XORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XORPSrr, X86_INS_XORPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XRELEASE_PREFIX, X86_INS_XRELEASE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XRSTOR, X86_INS_XRSTOR,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XRSTOR64, X86_INS_XRSTOR64,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSAVE, X86_INS_XSAVE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSAVE64, X86_INS_XSAVE64,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSAVEOPT, X86_INS_XSAVEOPT,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSAVEOPT64, X86_INS_XSAVEOPT64,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSETBV, X86_INS_XSETBV,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RAX, X86_REG_RCX, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSHA1, X86_INS_XSHA1,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSHA256, X86_INS_XSHA256,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XSTORE, X86_INS_XSTORE,
+#ifndef CAPSTONE_DIET
+ { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0
+#endif
+ },
+ {
+ X86_XTEST, X86_INS_XTEST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0
+#endif
+ },
};
// post printer for X86. put all the hacky stuff here
@@ -6653,6 +31757,7 @@
insn->id = insns[i].mapid;
if (h->detail) {
+#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
@@ -6667,6 +31772,7 @@
insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP;
insn->detail->groups_count++;
}
+#endif
}
}
}
diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h
index d9ea845..7dcae0f 100644
--- a/arch/X86/X86Mapping.h
+++ b/arch/X86/X86Mapping.h
@@ -29,9 +29,6 @@
// return insn name, given insn id
const char *X86_insn_name(csh handle, unsigned int id);
-// return insn id, given insn mnemonic
-x86_reg X86_map_insn(const char *mnem);
-
// post printer for X86.
void X86_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm);
diff --git a/config.mk b/config.mk
index 2ec3dac..28fb3cd 100644
--- a/config.mk
+++ b/config.mk
@@ -1,9 +1,22 @@
+################################################################################
+# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library
+# more compact.
+# This setup will remove all the mnemonic & op_str data, thus reduces the binary
+# size by around 200KB.
+# NOTE: we still keep @mnemonic & @op_str fields in cs_insn structure regardless,
+# but they will not be updated (i.e blank) at the output of disassemble APIs.
+CAPSTONE_DIET = no
+
+
+################################################################################
# Comment out the line below 'USE_SYS_DYN_MEM = yes' if you do not want to use
# system's malloc()/calloc()/realloc()/free() for internal dynamic memory management.
# NOTE: in that case, your program must specify your own malloc/calloc/realloc/free
# functions with cs_option(), using CS_OPT_MEM option type.
USE_SYS_DYN_MEM = yes
+
+################################################################################
# Specify which archs you want to compile in
# DO NOT touch the line below.
CAPSTONE_ARCHS =
diff --git a/cs.c b/cs.c
index cd9507e..42df944 100644
--- a/cs.c
+++ b/cs.c
@@ -230,6 +230,7 @@
if (postprinter)
postprinter((csh)handle, insn, buffer);
+#ifndef CAPSTONE_DIET
// fill in mnemonic & operands
// find first space or tab
char *sp = buffer;
@@ -248,6 +249,7 @@
strncpy(insn->mnemonic, buffer, sizeof(insn->mnemonic) - 1);
insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0';
+#endif
}
cs_err cs_option(csh ud, cs_opt_type type, size_t value)
diff --git a/include/capstone.h b/include/capstone.h
index b8ed34a..74ed83c 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -14,6 +14,8 @@
#include <stdbool.h>
#include <stdlib.h>
+#include "diet.h"
+
#ifdef _MSC_VER
#pragma warning(disable:4201)
#pragma warning(disable:4100)
@@ -305,6 +307,9 @@
Return friendly name of regiser in a string
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ NOTE: when CAPTONE_DIET is defined, this API is irrelevant because engine does not
+ store register name.
+
@handle: handle returned by cs_open()
@reg: register id
@return: string name of the register, or NULL if @reg_id is invalid.
@@ -315,6 +320,9 @@
Return friendly name of an instruction in a string
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ NOTE: when CAPTONE_DIET is defined, this API is irrelevant because engine does not
+ store instruction name.
+
@handle: handle returned by cs_open()
@insn: instruction id
@@ -328,6 +336,8 @@
Internally, this simply verifies if @group_id matches any member of insn->groups array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
+ Besides, when CAPTONE_DIET is defined, this API is irrelevant because engine does not
+ update @groups array.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@@ -343,6 +353,8 @@
Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
+ Besides, when CAPTONE_DIET is defined, this API is irrelevant because engine does not
+ update @regs_read array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@reg_id: register that you want to check if this instruction used it.
@@ -357,6 +369,8 @@
Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
+ Besides, when CAPTONE_DIET is defined, this API is irrelevant because engine does not
+ update @regs_write array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@reg_id: register that you want to check if this instruction modified it.
diff --git a/utils.h b/utils.h
index e942d90..cc41dc3 100644
--- a/utils.h
+++ b/utils.h
@@ -14,11 +14,13 @@
typedef struct insn_map {
unsigned short id;
unsigned short mapid;
+#ifndef CAPSTONE_DIET
unsigned char regs_use[12]; // list of implicit registers used by this instruction
unsigned char regs_mod[20]; // list of implicit registers modified by this instruction
unsigned char groups[8]; // list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
+#endif
} insn_map;
// return the position of a string in a list of strings