Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | #!/usr/bin/env python |
| 2 | |
| 3 | # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com> |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 4 | from __future__ import print_function |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 5 | from capstone import * |
| 6 | |
Nguyen Anh Quynh | 1098329 | 2014-05-17 09:51:15 +0800 | [diff] [blame] | 7 | |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 8 | X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" |
| 9 | X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00" |
| 10 | X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00" |
| 11 | ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3" |
| 12 | ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3" |
| 13 | THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68" |
| 14 | THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88" |
Nguyen Anh Quynh | 2e40e69 | 2014-11-11 21:54:22 +0800 | [diff] [blame] | 15 | THUMB_MCLASS = b"\xef\xf3\x02\x80" |
| 16 | ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5" |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 17 | MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56" |
| 18 | MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00" |
Nguyen Anh Quynh | 248519e | 2014-11-09 14:07:07 +0800 | [diff] [blame] | 19 | MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0" |
| 20 | MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0" |
Nguyen Anh Quynh | 5166236 | 2014-08-25 17:28:34 +0800 | [diff] [blame] | 21 | ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c" |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 22 | PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21" |
Nguyen Anh Quynh | 749046b | 2014-04-12 01:15:10 +0800 | [diff] [blame] | 23 | SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03" |
| 24 | SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0" |
| 25 | SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78" |
Nguyen Anh Quynh | 553bb48 | 2014-05-26 23:47:04 +0800 | [diff] [blame] | 26 | XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 27 | |
| 28 | all_tests = ( |
Nguyen Anh Quynh | 4649071 | 2013-12-06 00:44:44 +0800 | [diff] [blame] | 29 | (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0), |
| 30 | (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT), |
| 31 | (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0), |
| 32 | (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0), |
| 33 | (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0), |
| 34 | (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0), |
| 35 | (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0), |
| 36 | (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0), |
Nguyen Anh Quynh | 2e40e69 | 2014-11-11 21:54:22 +0800 | [diff] [blame] | 37 | (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", 0), |
| 38 | (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", 0), |
Nguyen Anh Quynh | 4649071 | 2013-12-06 00:44:44 +0800 | [diff] [blame] | 39 | (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0), |
| 40 | (CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0), |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 41 | (CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0), |
Nguyen Anh Quynh | 7e75ca6 | 2014-11-13 11:17:38 +0800 | [diff] [blame^] | 42 | (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0), |
| 43 | (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0), |
Nguyen Anh Quynh | 5cd6b34 | 2014-01-05 01:07:14 +0800 | [diff] [blame] | 44 | (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0), |
Nguyen Anh Quynh | 30a9d54 | 2014-03-10 14:40:48 +0800 | [diff] [blame] | 45 | (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0), |
Nguyen Anh Quynh | ea9f4b1 | 2014-03-10 20:38:01 +0800 | [diff] [blame] | 46 | (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0), |
Nguyen Anh Quynh | 1c8405d | 2014-03-23 11:17:24 +0800 | [diff] [blame] | 47 | (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", 0), |
Nguyen Anh Quynh | 553bb48 | 2014-05-26 23:47:04 +0800 | [diff] [blame] | 48 | (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", 0), |
Nguyen Anh Quynh | 749046b | 2014-04-12 01:15:10 +0800 | [diff] [blame] | 49 | ) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 50 | |
| 51 | |
Nguyen Anh Quynh | 7e22936 | 2014-06-03 13:14:34 +0700 | [diff] [blame] | 52 | def print_detail(insn): |
Nguyen Anh Quynh | 0de6783 | 2014-06-24 23:00:16 +0800 | [diff] [blame] | 53 | print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \ |
| 54 | % (insn.address, insn.mnemonic, insn.op_str, insn.id, \ |
| 55 | insn.insn_name())) |
| 56 | |
Nguyen Anh Quynh | 7e22936 | 2014-06-03 13:14:34 +0700 | [diff] [blame] | 57 | # "data" instruction generated by SKIPDATA option has no detail |
| 58 | if insn.id == 0: |
| 59 | return |
| 60 | |
| 61 | if len(insn.regs_read) > 0: |
| 62 | print("\tImplicit registers read: ", end=''), |
| 63 | for m in insn.regs_read: |
| 64 | print("%s " % insn.reg_name(m), end=''), |
| 65 | print() |
| 66 | |
| 67 | if len(insn.regs_write) > 0: |
| 68 | print("\tImplicit registers modified: ", end=''), |
| 69 | for m in insn.regs_write: |
| 70 | print("%s " % insn.reg_name(m), end=''), |
| 71 | print() |
| 72 | |
| 73 | if len(insn.groups) > 0: |
Nguyen Anh Quynh | 4fe5995 | 2014-06-17 13:59:08 +0800 | [diff] [blame] | 74 | print("\tThis instruction belongs to groups: ", end=''), |
Nguyen Anh Quynh | 7e22936 | 2014-06-03 13:14:34 +0700 | [diff] [blame] | 75 | for m in insn.groups: |
Nguyen Anh Quynh | 839890b | 2014-10-01 10:51:18 +0800 | [diff] [blame] | 76 | print("%s " % insn.group_name(m), end=''), |
Nguyen Anh Quynh | 7e22936 | 2014-06-03 13:14:34 +0700 | [diff] [blame] | 77 | print() |
| 78 | |
| 79 | |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 80 | # ## Test class Cs |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 81 | def test_class(): |
Nguyen Anh Quynh | 4649071 | 2013-12-06 00:44:44 +0800 | [diff] [blame] | 82 | for (arch, mode, code, comment, syntax) in all_tests: |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 83 | print('*' * 40) |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 84 | print("Platform: %s" % comment) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 85 | print("Disasm:") |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 86 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 87 | try: |
Nguyen Anh Quynh | 520c361 | 2013-12-06 15:26:07 +0800 | [diff] [blame] | 88 | md = Cs(arch, mode) |
Nguyen Anh Quynh | 428fdcd | 2014-01-07 23:39:40 +0800 | [diff] [blame] | 89 | md.detail = True |
Nguyen Anh Quynh | c618db4 | 2013-12-04 00:05:04 +0800 | [diff] [blame] | 90 | |
Nguyen Anh Quynh | 4649071 | 2013-12-06 00:44:44 +0800 | [diff] [blame] | 91 | if syntax != 0: |
| 92 | md.syntax = syntax |
Nguyen Anh Quynh | c618db4 | 2013-12-04 00:05:04 +0800 | [diff] [blame] | 93 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 94 | for insn in md.disasm(code, 0x1000): |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 95 | print_detail(insn) |
| 96 | |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 97 | print() |
Nguyen Anh Quynh | f1618bc | 2013-12-06 20:58:04 +0800 | [diff] [blame] | 98 | except CsError as e: |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 99 | print("ERROR: %s" % e) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 100 | |
fenuks | 110ab1d | 2014-04-11 11:00:33 +0200 | [diff] [blame] | 101 | if __name__ == '__main__': |
| 102 | test_class() |