Blame - arch/ARM/ARMInstPrinter.c - platform/external/capstone

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Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1	//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	//
				10	// This class prints an ARM MCInst to a .s file.
				11	//
				12	//===----------------------------------------------------------------------===//
				13
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	14	/* Capstone Disassembly Engine */
Nguyen Anh Quynh	bfcaba5	2015-03-04 17:45:23 +0800	[diff] [blame]	15	/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	16
				17	#ifdef CAPSTONE_HAS_ARM
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	18
				19	#include <stdio.h> // DEBUG
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	20	#include <stdlib.h>
				21	#include <string.h>
Cr4sh	19ee2d1	2015-03-29 18:29:06 +0800	[diff] [blame]	22	#include "../../myinttypes.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	23
				24	#include "ARMInstPrinter.h"
				25	#include "ARMAddressingModes.h"
				26	#include "ARMBaseInfo.h"
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	27	#include "ARMDisassembler.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	28	#include "../../MCInst.h"
				29	#include "../../SStream.h"
				30	#include "../../MCRegisterInfo.h"
				31	#include "../../utils.h"
Nguyen Anh Quynh	3732725	2014-01-20 09:47:21 +0800	[diff] [blame]	32	#include "ARMMapping.h"
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	33
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	34	#define GET_SUBTARGETINFO_ENUM
				35	#include "ARMGenSubtargetInfo.inc"
				36
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	37	static void printRegName(cs_struct h, SStream OS, unsigned RegNo);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	38
				39	// Autogenerated by tblgen.
				40	static void printInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI);
				41	static void printOperand(MCInst MI, unsigned OpNo, SStream O);
				42	static void printSORegRegOperand(MCInst MI, unsigned OpNum, SStream O);
				43	static void printSORegImmOperand(MCInst MI, unsigned OpNum, SStream O);
				44
				45	static void printAddrModeTBB(MCInst MI, unsigned OpNum, SStream O);
				46	static void printAddrModeTBH(MCInst MI, unsigned OpNum, SStream O);
				47	static void printAddrMode2Operand(MCInst MI, unsigned OpNum, SStream O);
				48	static void printAM2PreOrOffsetIndexOp(MCInst MI, unsigned OpNum, SStream O);
				49	static void printAddrMode2OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				50	static void printAddrMode3Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				51	static void printAddrMode3OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	52	static void printAM3PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O, bool AlwaysPrintImm0);
				53	static void printPostIdxImm8Operand(MCInst MI, unsigned OpNum, SStream O);
				54	static void printPostIdxRegOperand(MCInst MI, unsigned OpNum, SStream O);
				55	static void printPostIdxImm8s4Operand(MCInst MI, unsigned OpNum, SStream O);
				56	static void printAddrMode5Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				57	static void printAddrMode6Operand(MCInst MI, unsigned OpNum, SStream O);
				58	static void printAddrMode7Operand(MCInst MI, unsigned OpNum, SStream O);
				59	static void printAddrMode6OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				60
				61	static void printBitfieldInvMaskImmOperand(MCInst MI, unsigned OpNum, SStream O);
				62	static void printMemBOption(MCInst MI, unsigned OpNum, SStream O);
				63	static void printShiftImmOperand(MCInst MI, unsigned OpNum, SStream O);
				64	static void printPKHLSLShiftImm(MCInst MI, unsigned OpNum, SStream O);
				65	static void printPKHASRShiftImm(MCInst MI, unsigned OpNum, SStream O);
				66	static void printAdrLabelOperand(MCInst MI, unsigned OpNum, SStream O, unsigned);
				67	static void printThumbS4ImmOperand(MCInst MI, unsigned OpNum, SStream O);
				68	static void printThumbSRImm(MCInst MI, unsigned OpNum, SStream O);
				69	static void printThumbITMask(MCInst MI, unsigned OpNum, SStream O);
				70	static void printThumbAddrModeRROperand(MCInst MI, unsigned OpNum, SStream O);
				71	static void printThumbAddrModeImm5SOperand(MCInst MI, unsigned OpNum, SStream O, unsigned Scale);
				72	static void printThumbAddrModeImm5S1Operand(MCInst MI, unsigned OpNum, SStream O);
				73	static void printThumbAddrModeImm5S2Operand(MCInst MI, unsigned OpNum, SStream O);
				74	static void printThumbAddrModeImm5S4Operand(MCInst MI, unsigned OpNum, SStream O);
				75	static void printThumbAddrModeSPOperand(MCInst MI, unsigned OpNum, SStream O);
				76	static void printT2SOOperand(MCInst MI, unsigned OpNum, SStream O);
				77	static void printAddrModeImm12Operand(MCInst MI, unsigned OpNum, SStream O, bool AlwaysPrintImm0);
				78	static void printT2AddrModeImm8Operand(MCInst MI, unsigned OpNum, SStream O, bool);
				79	static void printT2AddrModeImm8s4Operand(MCInst MI, unsigned OpNum, SStream O, bool);
				80	static void printT2AddrModeImm0_1020s4Operand(MCInst MI, unsigned OpNum, SStream O);
				81	static void printT2AddrModeImm8OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				82	static void printT2AddrModeImm8s4OffsetOperand(MCInst MI, unsigned OpNum, SStream O);
				83	static void printT2AddrModeSoRegOperand(MCInst MI, unsigned OpNum, SStream O);
				84	static void printSetendOperand(MCInst MI, unsigned OpNum, SStream O);
				85	static void printCPSIMod(MCInst MI, unsigned OpNum, SStream O);
				86	static void printCPSIFlag(MCInst MI, unsigned OpNum, SStream O);
				87	static void printMSRMaskOperand(MCInst MI, unsigned OpNum, SStream O);
				88	static void printPredicateOperand(MCInst MI, unsigned OpNum, SStream O);
				89	static void printMandatoryPredicateOperand(MCInst MI, unsigned OpNum, SStream O);
				90	static void printSBitModifierOperand(MCInst MI, unsigned OpNum, SStream O);
				91	static void printRegisterList(MCInst MI, unsigned OpNum, SStream O);
				92	static void printNoHashImmediate(MCInst MI, unsigned OpNum, SStream O);
				93	static void printPImmediate(MCInst MI, unsigned OpNum, SStream O);
				94	static void printCImmediate(MCInst MI, unsigned OpNum, SStream O);
				95	static void printCoprocOptionImm(MCInst MI, unsigned OpNum, SStream O);
				96	static void printFPImmOperand(MCInst MI, unsigned OpNum, SStream O);
				97	static void printNEONModImmOperand(MCInst MI, unsigned OpNum, SStream O);
				98	static void printImmPlusOneOperand(MCInst MI, unsigned OpNum, SStream O);
				99	static void printRotImmOperand(MCInst MI, unsigned OpNum, SStream O);
				100	static void printGPRPairOperand(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				101	static void printThumbLdrLabelOperand(MCInst MI, unsigned OpNum, SStream O);
				102	static void printFBits16(MCInst MI, unsigned OpNum, SStream O);
				103	static void printFBits32(MCInst MI, unsigned OpNum, SStream O);
				104	static void printVectorIndex(MCInst MI, unsigned OpNum, SStream O);
				105	static void printVectorListOne(MCInst MI, unsigned OpNum, SStream O);
				106	static void printVectorListTwo(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				107	static void printVectorListTwoSpaced(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *RI);
				108	static void printVectorListThree(MCInst MI, unsigned OpNum, SStream O);
				109	static void printVectorListFour(MCInst MI, unsigned OpNum, SStream O);
				110	static void printVectorListOneAllLanes(MCInst MI, unsigned OpNum, SStream O);
				111	static void printVectorListTwoAllLanes(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *RI);
				112	static void printVectorListThreeAllLanes(MCInst MI, unsigned OpNum, SStream O);
				113	static void printVectorListFourAllLanes(MCInst MI, unsigned OpNum, SStream O);
				114	static void printVectorListTwoSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O, MCRegisterInfo *MRI);
				115	static void printVectorListThreeSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O);
				116	static void printVectorListFourSpacedAllLanes(MCInst MI, unsigned OpNum, SStream O);
				117	static void printVectorListThreeSpaced(MCInst MI, unsigned OpNum, SStream O);
				118	static void printVectorListFourSpaced(MCInst MI, unsigned OpNum, SStream O);
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	119	static void printBankedRegOperand(MCInst MI, unsigned OpNum, SStream O);
				120	static void printModImmOperand(MCInst MI, unsigned OpNum, SStream O);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	121
				122	static void printInstSyncBOption(MCInst MI, unsigned OpNum, SStream O);
				123
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	124	// copy & normalize access info
				125	static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
				126	{
				127	#ifndef CAPSTONE_DIET
				128	uint8_t *arr = ARM_get_op_access(h, id);
				129
				130	if (arr[index] == CS_AC_IGNORE)
				131	return 0;
				132
				133	return arr[index];
				134	#else
				135	return 0;
				136	#endif
				137	}
				138
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	139	static void set_mem_access(MCInst *MI, bool status)
				140	{
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	141	if (MI->csh->detail != CS_OPT_ON)
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	142	return;
				143
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	144	MI->csh->doing_mem = status;
				145	if (status) {
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	146	#ifndef CAPSTONE_DIET
				147	uint8_t access;
				148	#endif
				149
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	150	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				151	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
				152	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				153	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				154	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	155
				156	#ifndef CAPSTONE_DIET
				157	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				158	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				159	MI->ac_idx++;
				160	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	161	} else {
				162	// done, create the next operand slot
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	163	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	164	}
				165	}
				166
Nguyen Anh Quynh	ebe2443	2014-06-17 13:56:01 +0800	[diff] [blame]	167	static void op_addImm(MCInst *MI, int v)
				168	{
Nguyen Anh Quynh	73eb5d5	2014-06-17 18:08:29 +0800	[diff] [blame]	169	if (MI->csh->detail) {
				170	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				171	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
				172	MI->flat_insn->detail->arm.op_count++;
				173	}
Nguyen Anh Quynh	ebe2443	2014-06-17 13:56:01 +0800	[diff] [blame]	174	}
				175
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	176	#define GET_INSTRINFO_ENUM
				177	#include "ARMGenInstrInfo.inc"
				178
				179	//#define PRINT_ALIAS_INSTR
				180	#include "ARMGenAsmWriter.inc"
				181
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	182	void ARM_getRegName(cs_struct *handle, int value)
				183	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	184	if (value == CS_OPT_SYNTAX_NOREGNAME) {
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	185	handle->get_regname = getRegisterName2;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	186	handle->reg_name = ARM_reg_name2;;
				187	} else {
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	188	handle->get_regname = getRegisterName;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	189	handle->reg_name = ARM_reg_name;;
				190	}
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	191	}
				192
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	193	/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
				194	///
				195	/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
				196	static unsigned translateShiftImm(unsigned imm)
				197	{
				198	// lsr #32 and asr #32 exist, but should be encoded as a 0.
				199	//assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
				200	if (imm == 0)
				201	return 32;
				202	return imm;
				203	}
				204
				205	/// Prints the shift value with an immediate value.
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	206	static void printRegImmShift(MCInst MI, SStream O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	207	{
				208	if (ShOpc == ARM_AM_no_shift \|\| (ShOpc == ARM_AM_lsl && !ShImm))
				209	return;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	210	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	211
				212	//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	213	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	214	if (MI->csh->detail) {
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	215	if (MI->csh->doing_mem)
				216	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
				217	else
				218	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	219	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	220
				221	if (ShOpc != ARM_AM_rrx) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	222	SStream_concat0(O, " ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	223	SStream_concat(O, "#%u", translateShiftImm(ShImm));
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	224	if (MI->csh->detail) {
				225	if (MI->csh->doing_mem)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	226	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	227	else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	228	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
Nguyen Anh Quynh	c70442e	2014-06-01 11:35:34 +0700	[diff] [blame]	229	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	230	}
				231	}
				232
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	233	static void printRegName(cs_struct h, SStream OS, unsigned RegNo)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	234	{
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	235	#ifndef CAPSTONE_DIET
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	236	SStream_concat0(OS, h->get_regname(RegNo));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	237	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	238	}
				239
				240	static name_map insn_update_flgs[] = {
				241	{ ARM_INS_CMN, "cmn" },
				242	{ ARM_INS_CMP, "cmp" },
				243	{ ARM_INS_TEQ, "teq" },
				244	{ ARM_INS_TST, "tst" },
				245
				246	{ ARM_INS_ADC, "adcs" },
				247	{ ARM_INS_ADD, "adds" },
				248	{ ARM_INS_AND, "ands" },
				249	{ ARM_INS_ASR, "asrs" },
				250	{ ARM_INS_BIC, "bics" },
				251	{ ARM_INS_EOR, "eors" },
				252	{ ARM_INS_LSL, "lsls" },
				253	{ ARM_INS_LSR, "lsrs" },
				254	{ ARM_INS_MLA, "mlas" },
				255	{ ARM_INS_MOV, "movs" },
				256	{ ARM_INS_MUL, "muls" },
				257	{ ARM_INS_MVN, "mvns" },
				258	{ ARM_INS_ORN, "orns" },
				259	{ ARM_INS_ORR, "orrs" },
				260	{ ARM_INS_ROR, "rors" },
				261	{ ARM_INS_RRX, "rrxs" },
				262	{ ARM_INS_RSB, "rsbs" },
				263	{ ARM_INS_RSC, "rscs" },
				264	{ ARM_INS_SBC, "sbcs" },
				265	{ ARM_INS_SMLAL, "smlals" },
				266	{ ARM_INS_SMULL, "smulls" },
				267	{ ARM_INS_SUB, "subs" },
				268	{ ARM_INS_UMLAL, "umlals" },
				269	{ ARM_INS_UMULL, "umulls" },
				270	};
				271
Nguyen Anh Quynh	6456481	2014-05-19 16:46:31 +0800	[diff] [blame]	272	void ARM_post_printer(csh ud, cs_insn insn, char insn_asm, MCInst *mci)
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	273	{
Nguyen Anh Quynh	5ef633c	2014-01-04 10:41:17 +0800	[diff] [blame]	274	if (((cs_struct *)ud)->detail != CS_OPT_ON)
				275	return;
				276
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	277	// check if this insn requests write-back
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	278	if (mci->writeback \|\| (strrchr(insn_asm, '!')) != NULL) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	279	insn->detail->arm.writeback = true;
Nguyen Anh Quynh	5719eb5	2015-01-21 12:16:15 +0800	[diff] [blame]	280	} else if (mci->csh->mode & CS_MODE_THUMB) {
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	281	// handle some special instructions with writeback
				282	switch(mci->Opcode) {
				283	default:
				284	break;
				285	case ARM_t2LDC2L_PRE:
				286	case ARM_t2LDC2_PRE:
				287	case ARM_t2LDCL_PRE:
				288	case ARM_t2LDC_PRE:
				289
				290	case ARM_t2LDRB_PRE:
				291	case ARM_t2LDRD_PRE:
				292	case ARM_t2LDRH_PRE:
				293	case ARM_t2LDRSB_PRE:
				294	case ARM_t2LDRSH_PRE:
				295	case ARM_t2LDR_PRE:
				296
				297	case ARM_t2STC2L_PRE:
				298	case ARM_t2STC2_PRE:
				299	case ARM_t2STCL_PRE:
				300	case ARM_t2STC_PRE:
				301
				302	case ARM_t2STRB_PRE:
				303	case ARM_t2STRD_PRE:
				304	case ARM_t2STRH_PRE:
				305	case ARM_t2STR_PRE:
				306
				307	case ARM_t2LDC2L_POST:
				308	case ARM_t2LDC2_POST:
				309	case ARM_t2LDCL_POST:
				310	case ARM_t2LDC_POST:
				311
				312	case ARM_t2LDRB_POST:
				313	case ARM_t2LDRD_POST:
				314	case ARM_t2LDRH_POST:
				315	case ARM_t2LDRSB_POST:
				316	case ARM_t2LDRSH_POST:
				317	case ARM_t2LDR_POST:
				318
				319	case ARM_t2STC2L_POST:
				320	case ARM_t2STC2_POST:
				321	case ARM_t2STCL_POST:
				322	case ARM_t2STC_POST:
				323
				324	case ARM_t2STRB_POST:
				325	case ARM_t2STRD_POST:
				326	case ARM_t2STRH_POST:
				327	case ARM_t2STR_POST:
				328	insn->detail->arm.writeback = true;
				329	break;
				330	}
				331	} else { // ARM mode
				332	// handle some special instructions with writeback
				333	switch(mci->Opcode) {
				334	default:
				335	break;
				336	case ARM_LDC2L_PRE:
				337	case ARM_LDC2_PRE:
				338	case ARM_LDCL_PRE:
				339	case ARM_LDC_PRE:
				340
				341	case ARM_LDRD_PRE:
				342	case ARM_LDRH_PRE:
				343	case ARM_LDRSB_PRE:
				344	case ARM_LDRSH_PRE:
				345
				346	case ARM_STC2L_PRE:
				347	case ARM_STC2_PRE:
				348	case ARM_STCL_PRE:
				349	case ARM_STC_PRE:
				350
				351	case ARM_STRD_PRE:
				352	case ARM_STRH_PRE:
				353
				354	case ARM_LDC2L_POST:
				355	case ARM_LDC2_POST:
				356	case ARM_LDCL_POST:
				357	case ARM_LDC_POST:
				358
				359	case ARM_LDRBT_POST:
				360	case ARM_LDRD_POST:
				361	case ARM_LDRH_POST:
				362	case ARM_LDRSB_POST:
				363	case ARM_LDRSH_POST:
				364
				365	case ARM_STC2L_POST:
				366	case ARM_STC2_POST:
				367	case ARM_STCL_POST:
				368	case ARM_STC_POST:
				369
				370	case ARM_STRBT_POST:
				371	case ARM_STRD_POST:
				372	case ARM_STRH_POST:
Nguyen Anh Quynh	58fbf2f	2015-01-21 12:25:36 +0800	[diff] [blame]	373
				374	case ARM_LDRB_POST_IMM:
				375	case ARM_LDR_POST_IMM:
				376	case ARM_STRB_POST_IMM:
				377	case ARM_STR_POST_IMM:
				378
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	379	insn->detail->arm.writeback = true;
				380	break;
				381	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	382	}
				383
				384	// check if this insn requests update flags
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	385	if (insn->detail->arm.update_flags == false) {
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	386	// some insn still update flags, regardless of tabgen info
Nguyen Anh Quynh	f6c7cbc	2014-03-12 12:50:54 +0800	[diff] [blame]	387	unsigned int i, j;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	388
				389	for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	390	if (insn->id == insn_update_flgs[i].id &&
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	391	!strncmp(insn_asm, insn_update_flgs[i].name,
				392	strlen(insn_update_flgs[i].name))) {
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	393	insn->detail->arm.update_flags = true;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	394	// we have to update regs_write array as well
Nguyen Anh Quynh	4fe224b	2013-12-24 16:49:36 +0800	[diff] [blame]	395	for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
				396	if (insn->detail->regs_write[j] == 0) {
				397	insn->detail->regs_write[j] = ARM_REG_CPSR;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	398	break;
				399	}
				400	}
				401	break;
				402	}
				403	}
				404	}
Nguyen Anh Quynh	48b6cb4	2014-06-01 09:45:19 +0700	[diff] [blame]	405
				406	// instruction should not have invalid CC
				407	if (insn->detail->arm.cc == ARM_CC_INVALID) {
				408	insn->detail->arm.cc = ARM_CC_AL;
				409	}
				410
Nguyen Anh Quynh	6eb55cf	2014-06-01 10:03:14 +0700	[diff] [blame]	411	// manual fix for some special instructions
				412	// printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
				413	switch(mci->Opcode) {
				414	default:
				415	break;
				416	case ARM_MOVPCLR:
				417	insn->detail->arm.operands[0].type = ARM_OP_REG;
				418	insn->detail->arm.operands[0].reg = ARM_REG_PC;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	419	insn->detail->arm.operands[0].access = CS_AC_READ;
Nguyen Anh Quynh	6eb55cf	2014-06-01 10:03:14 +0700	[diff] [blame]	420	insn->detail->arm.operands[1].type = ARM_OP_REG;
				421	insn->detail->arm.operands[1].reg = ARM_REG_LR;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	422	insn->detail->arm.operands[1].access = CS_AC_WRITE;
Nguyen Anh Quynh	6eb55cf	2014-06-01 10:03:14 +0700	[diff] [blame]	423	insn->detail->arm.op_count = 2;
				424	break;
				425	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	426	}
				427
				428	void ARM_printInst(MCInst MI, SStream O, void *Info)
				429	{
				430	MCRegisterInfo MRI = (MCRegisterInfo )Info;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	431	unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	432
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	433
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	434	switch(Opcode) {
				435	// Check for HINT instructions w/ canonical names.
				436	case ARM_HINT:
				437	case ARM_tHINT:
				438	case ARM_t2HINT:
				439	switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	440	case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break;
				441	case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break;
				442	case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break;
				443	case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break;
				444	case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	445	case 5:
Nguyen Anh Quynh	2593e22	2014-11-10 16:35:38 +0800	[diff] [blame]	446	if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
				447	SStream_concat0(O, "sevl");
				448	pubOpcode = ARM_INS_SEVL;
				449	break;
				450	}
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	451	// Fallthrough for non-v8
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	452	default:
				453	// Anything else should just print normally.
				454	printInstruction(MI, O, MRI);
				455	return;
				456	}
				457	printPredicateOperand(MI, 1, O);
				458	if (Opcode == ARM_t2HINT)
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	459	SStream_concat0(O, ".w");
				460
				461	MCInst_setOpcodePub(MI, pubOpcode);
				462
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	463	return;
				464
				465	// Check for MOVs and print canonical forms, instead.
				466	case ARM_MOVsr: {
				467	// FIXME: Thumb variants?
				468	MCOperand *Dst = MCInst_getOperand(MI, 0);
				469	MCOperand *MO1 = MCInst_getOperand(MI, 1);
				470	MCOperand *MO2 = MCInst_getOperand(MI, 2);
				471	MCOperand *MO3 = MCInst_getOperand(MI, 3);
				472
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	473	SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	474	printSBitModifierOperand(MI, 6, O);
				475	printPredicateOperand(MI, 4, O);
				476
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	477	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	478	printRegName(MI->csh, O, MCOperand_getReg(Dst));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	479	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	480	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				481	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	482	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	483	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	484	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	485
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	486	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	487	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	488
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	489	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	490	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				491	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	492	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	493	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	494	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	495
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	496	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	497	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	498	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	499	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				500	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	501	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	502	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	503	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	504	//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
				505	return;
				506	}
				507
				508	case ARM_MOVsi: {
				509	// FIXME: Thumb variants?
				510	MCOperand *Dst = MCInst_getOperand(MI, 0);
				511	MCOperand *MO1 = MCInst_getOperand(MI, 1);
				512	MCOperand *MO2 = MCInst_getOperand(MI, 2);
				513
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	514	SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	515	printSBitModifierOperand(MI, 5, O);
				516	printPredicateOperand(MI, 3, O);
				517
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	518	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	519	printRegName(MI->csh, O, MCOperand_getReg(Dst));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	520	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	521	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				522	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	523	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	524	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	525	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	526
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	527	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	528	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	529	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	530	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				531	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	532	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	533	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	534	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	535
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	536	if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	537	//printAnnotation(O, Annot);
				538	return;
				539	}
				540
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	541	SStream_concat0(O, ", ");
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	542	tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	543	if (tmp > HEX_THRESHOLD)
				544	SStream_concat(O, "#0x%x", tmp);
				545	else
				546	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	547	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	548	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	549	(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	550	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	551	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	552	return;
				553	}
				554
				555	// A8.6.123 PUSH
				556	case ARM_STMDB_UPD:
				557	case ARM_t2STMDB_UPD:
				558	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
				559	MCInst_getNumOperands(MI) > 5) {
				560	// Should only print PUSH if there are at least two registers in the list.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	561	SStream_concat0(O, "push");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	562	MCInst_setOpcodePub(MI, ARM_INS_PUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	563	printPredicateOperand(MI, 2, O);
				564	if (Opcode == ARM_t2STMDB_UPD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	565	SStream_concat0(O, ".w");
				566	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	567	printRegisterList(MI, 4, O);
				568	return;
				569	}
				570	break;
				571
				572	case ARM_STR_PRE_IMM:
				573	if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
				574	MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	575	SStream_concat0(O, "push");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	576	MCInst_setOpcodePub(MI, ARM_INS_PUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	577	printPredicateOperand(MI, 4, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	578	SStream_concat0(O, "\t{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	579	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	580	if (MI->csh->detail) {
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	581	#ifndef CAPSTONE_DIET
				582	uint8_t access;
				583	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	584	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				585	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	586	#ifndef CAPSTONE_DIET
				587	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				588	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				589	MI->ac_idx++;
				590	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	591	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	592	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	593	SStream_concat0(O, "}");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	594	return;
				595	}
				596	break;
				597
				598	// A8.6.122 POP
				599	case ARM_LDMIA_UPD:
				600	case ARM_t2LDMIA_UPD:
				601	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
				602	MCInst_getNumOperands(MI) > 5) {
				603	// Should only print POP if there are at least two registers in the list.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	604	SStream_concat0(O, "pop");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	605	MCInst_setOpcodePub(MI, ARM_INS_POP);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	606	printPredicateOperand(MI, 2, O);
				607	if (Opcode == ARM_t2LDMIA_UPD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	608	SStream_concat0(O, ".w");
				609	SStream_concat0(O, "\t");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	610	if (MI->csh->detail) {
				611	MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
				612	MI->flat_insn->detail->regs_read_count++;
				613	MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
				614	MI->flat_insn->detail->regs_write_count++;
				615	}
				616
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	617	printRegisterList(MI, 4, O);
				618	return;
				619	}
				620	break;
				621
				622	case ARM_LDR_POST_IMM:
Nguyen Anh Quynh	3caf837	2014-11-27 14:34:40 +0800	[diff] [blame]	623	if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) {
				624	MCOperand *MO2 = MCInst_getOperand(MI, 4);
				625	if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add &&
				626	getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) \|\|
				627	MCOperand_getImm(MO2) == 4) {
				628	SStream_concat0(O, "pop");
				629	MCInst_setOpcodePub(MI, ARM_INS_POP);
				630	printPredicateOperand(MI, 5, O);
				631	SStream_concat0(O, "\t{");
				632	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
				633	if (MI->csh->detail) {
				634	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				635	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	636	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	3caf837	2014-11-27 14:34:40 +0800	[diff] [blame]	637	MI->flat_insn->detail->arm.op_count++;
				638	}
				639	SStream_concat0(O, "}");
				640	return;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	641	}
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	642	}
				643	break;
				644
				645	// A8.6.355 VPUSH
				646	case ARM_VSTMSDB_UPD:
				647	case ARM_VSTMDDB_UPD:
				648	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	649	SStream_concat0(O, "vpush");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	650	MCInst_setOpcodePub(MI, ARM_INS_VPUSH);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	651	printPredicateOperand(MI, 2, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	652	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	653	printRegisterList(MI, 4, O);
				654	return;
				655	}
				656	break;
				657
				658	// A8.6.354 VPOP
				659	case ARM_VLDMSIA_UPD:
				660	case ARM_VLDMDIA_UPD:
				661	if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	662	SStream_concat0(O, "vpop");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	663	MCInst_setOpcodePub(MI, ARM_INS_VPOP);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	664	printPredicateOperand(MI, 2, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	665	SStream_concat0(O, "\t");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	666	printRegisterList(MI, 4, O);
				667	return;
				668	}
				669	break;
				670
				671	case ARM_tLDMIA: {
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	672	bool Writeback = true;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	673	unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
				674	unsigned i;
				675	for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
				676	if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
				677	Writeback = false;
				678	}
				679
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	680	SStream_concat0(O, "ldm");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	681	MCInst_setOpcodePub(MI, ARM_INS_LDM);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	682
				683	printPredicateOperand(MI, 1, O);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	684	SStream_concat0(O, "\t");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	685	printRegName(MI->csh, O, BaseReg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	686	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	687	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				688	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	689	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	690	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	691	}
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	692	if (Writeback) {
				693	MI->writeback = true;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	694	SStream_concat0(O, "!");
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	695	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	696	SStream_concat0(O, ", ");
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	697	printRegisterList(MI, 3, O);
				698	return;
				699	}
				700
				701	// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
				702	// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
				703	// a single GPRPair reg operand is used in the .td file to replace the two
				704	// GPRs. However, when decoding them, the two GRPs cannot be automatically
				705	// expressed as a GPRPair, so we have to manually merge them.
				706	// FIXME: We would really like to be able to tablegen'erate this.
				707	case ARM_LDREXD:
				708	case ARM_STREXD:
				709	case ARM_LDAEXD:
				710	case ARM_STLEXD: {
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	711	MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
				712	bool isStore = Opcode == ARM_STREXD \|\| Opcode == ARM_STLEXD;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	713	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	714
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	715	if (MCRegisterClass_contains(MRC, Reg)) {
				716	MCInst NewMI;
Nguyen Anh Quynh	5e2e660	2014-05-30 17:43:36 +0800	[diff] [blame]	717
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	718	MCInst_Init(&NewMI);
				719	MCInst_setOpcode(&NewMI, Opcode);
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	720
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	721	if (isStore)
				722	MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	723
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	724	MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
				725	MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
Nguyen Anh Quynh	9678705	2014-06-10 13:59:55 +0700	[diff] [blame]	726
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	727	// Copy the rest operands into NewMI.
				728	for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
				729	MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
Nguyen Anh Quynh	9678705	2014-06-10 13:59:55 +0700	[diff] [blame]	730
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	731	printInstruction(&NewMI, O, MRI);
				732	return;
Nguyen Anh Quynh	173ed2b	2013-12-01 22:19:27 +0800	[diff] [blame]	733	}
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	734	break;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	735	}
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	736	// B9.3.3 ERET (Thumb)
				737	// For a target that has Virtualization Extensions, ERET is the preferred
				738	// disassembly of SUBS PC, LR, #0
				739	case ARM_t2SUBS_PC_LR: {
				740	MCOperand *opc = MCInst_getOperand(MI, 0);
				741	if (MCInst_getNumOperands(MI) == 3 &&
				742	MCOperand_isImm(opc) &&
				743	MCOperand_getImm(opc) == 0 &&
				744	(ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureVirtualization)) {
				745	SStream_concat0(O, "eret");
				746	MCInst_setOpcodePub(MI, ARM_INS_ERET);
				747	printPredicateOperand(MI, 1, O);
				748	return;
				749	}
				750	break;
				751	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	752	}
				753
				754	//if (printAliasInstr(MI, O, MRI))
				755	// printInstruction(MI, O, MRI);
				756	printInstruction(MI, O, MRI);
				757	}
				758
				759	static void printOperand(MCInst MI, unsigned OpNo, SStream O)
				760	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	761	int32_t imm;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	762	MCOperand *Op = MCInst_getOperand(MI, OpNo);
				763	if (MCOperand_isReg(Op)) {
				764	unsigned Reg = MCOperand_getReg(Op);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	765	printRegName(MI->csh, O, Reg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	766	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	767	if (MI->csh->doing_mem) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	768	if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
				769	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	770	else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	771	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	772	} else {
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	773	#ifndef CAPSTONE_DIET
				774	uint8_t access;
				775	#endif
				776
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	777	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				778	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	779	#ifndef CAPSTONE_DIET
				780	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				781	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				782	MI->ac_idx++;
				783	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	784	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	785	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	786	}
				787	} else if (MCOperand_isImm(Op)) {
Nguyen Anh Quynh	0c235e1	2014-07-31 21:16:54 +0800	[diff] [blame]	788	unsigned int opc = MCInst_getOpcode(MI);
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	789
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	790	imm = (int32_t)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	791
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	792	// relative branch only has relative offset, so we have to update it
				793	// to reflect absolute address.
				794	// Note: in ARM, PC is always 2 instructions ahead, so we have to
				795	// add 8 in ARM mode, or 4 in Thumb mode
Nguyen Anh Quynh	bc80b3d	2014-05-09 17:31:41 +0800	[diff] [blame]	796	// printf(">> opcode: %u\n", MCInst_getOpcode(MI));
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	797	if (ARM_rel_branch(MI->csh, opc)) {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	798	// only do this for relative branch
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	799	if (MI->csh->mode & CS_MODE_THUMB) {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	800	imm += (int32_t)MI->address + 4;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	801	if (ARM_blx_to_arm_mode(MI->csh, opc)) {
Nguyen Anh Quynh	0c235e1	2014-07-31 21:16:54 +0800	[diff] [blame]	802	// here need to align down to the nearest 4-byte address
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	803	#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	804	imm = _ALIGN_DOWN(imm, 4);
flyingsymbols	298d413	2014-06-30 01:45:40 -0400	[diff] [blame]	805	#undef _ALIGN_DOWN
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	806	}
				807	} else {
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	808	imm += (int32_t)MI->address + 8;
Nguyen Anh Quynh	26dfbc6	2014-07-31 18:24:51 +0800	[diff] [blame]	809	}
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	810
				811	if (imm >= 0) {
				812	if (imm > HEX_THRESHOLD)
				813	SStream_concat(O, "#0x%x", imm);
				814	else
				815	SStream_concat(O, "#%u", imm);
				816	} else {
Nguyen Anh Quynh	4e87675	2014-09-23 16:49:12 +0800	[diff] [blame]	817	SStream_concat(O, "#0x%x", imm);
Nguyen Anh Quynh	79e1dcb	2014-05-07 14:12:50 +0800	[diff] [blame]	818	}
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	819	} else {
Nguyen Anh Quynh	278e727	2014-11-11 12:50:43 +0800	[diff] [blame]	820	switch(MI->flat_insn->id) {
				821	default:
				822	if (imm >= 0) {
				823	if (imm > HEX_THRESHOLD)
				824	SStream_concat(O, "#0x%x", imm);
				825	else
				826	SStream_concat(O, "#%u", imm);
				827	} else {
				828	if (imm < -HEX_THRESHOLD)
				829	SStream_concat(O, "#-0x%x", -imm);
				830	else
				831	SStream_concat(O, "#-%u", -imm);
				832	}
				833	break;
				834	case ARM_INS_AND:
				835	case ARM_INS_ORR:
				836	case ARM_INS_EOR:
				837	case ARM_INS_BIC:
Nguyen Anh Quynh	a2934a7	2014-11-25 21:02:18 +0800	[diff] [blame]	838	case ARM_INS_MVN:
Nguyen Anh Quynh	278e727	2014-11-11 12:50:43 +0800	[diff] [blame]	839	// do not print number in negative form
				840	if (imm >= 0 && imm <= HEX_THRESHOLD)
				841	SStream_concat(O, "#%u", imm);
				842	else
				843	SStream_concat(O, "#0x%x", imm);
				844	break;
				845	}
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	846	}
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	847
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	848	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	849	if (MI->csh->doing_mem)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	850	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	851	else {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	852	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				853	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
				854	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	855	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	856	}
				857	}
				858	}
				859
				860	static void printThumbLdrLabelOperand(MCInst MI, unsigned OpNum, SStream O)
				861	{
				862	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	863	int32_t OffImm;
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	864	bool isSub;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	865	SStream_concat0(O, "[pc, ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	866
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	867	OffImm = (int32_t)MCOperand_getImm(MO1);
				868	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	869
				870	// Special value for #-0. All others are normal.
				871	if (OffImm == INT32_MIN)
				872	OffImm = 0;
				873	if (isSub) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	874	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	875	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	876	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	877	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	878	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	879	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	880	}
				881
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	882	SStream_concat0(O, "]");
Nguyen Anh Quynh	bb71c13	2014-06-01 10:14:31 +0700	[diff] [blame]	883
				884	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	885	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				886	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
				887	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				888	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				889	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	890	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	891	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	bb71c13	2014-06-01 10:14:31 +0700	[diff] [blame]	892	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	893	}
				894
				895	// so_reg is a 4-operand unit corresponding to register forms of the A5.1
				896	// "Addressing Mode 1 - Data-processing operands" forms. This includes:
				897	// REG 0 0 - e.g. R5
				898	// REG REG 0,SH_OPC - e.g. R5, ROR R3
				899	// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
				900	static void printSORegRegOperand(MCInst MI, unsigned OpNum, SStream O)
				901	{
				902	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				903	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				904	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	905	ARM_AM_ShiftOpc ShOpc;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	906
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	907	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	908
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	909	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	910	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				911	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	912	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	913
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	914	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
				915	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	916	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	917
				918	// Print the shift opc.
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	919	ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	920	SStream_concat0(O, ", ");
				921	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	922	if (ShOpc == ARM_AM_rrx)
				923	return;
				924
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	925	SStream_concat0(O, " ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	926	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	927	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	928	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	929	//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
				930	}
				931
				932	static void printSORegImmOperand(MCInst MI, unsigned OpNum, SStream O)
				933	{
				934	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				935	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				936
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	937	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	938	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	939	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				940	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	941	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	942	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
				943	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
				944	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	945	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	946
				947	// Print the shift opc.
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	948	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	949	getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	950	}
				951
				952	//===--------------------------------------------------------------------===//
				953	// Addressing Mode #2
				954	//===--------------------------------------------------------------------===//
				955
				956	static void printAM2PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O)
				957	{
				958	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				959	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
				960	MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	961	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	962
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	963	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	964	set_mem_access(MI, true);
				965
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	966	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	967	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	968	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	969	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	970
				971	if (!MCOperand_getReg(MO2)) {
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	972	unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	973	if (tmp) { // Don't print +0.
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	974	subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
				975
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	976	SStream_concat0(O, ", ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	977	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	978	SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	979	else
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	980	SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	981	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	982	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
				983	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	984	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	985	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	986	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	987	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	988	set_mem_access(MI, false);
				989	return;
				990	}
				991
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	992	SStream_concat0(O, ", ");
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	993	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	994	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	995	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	996	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	997	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	998	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	999
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1000	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	1001	getAM2Offset((unsigned int)MCOperand_getImm(MO3)));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1002	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1003	set_mem_access(MI, false);
				1004	}
				1005
				1006	static void printAddrModeTBB(MCInst MI, unsigned Op, SStream O)
				1007	{
				1008	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1009	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1010	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1011	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1012	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1013	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1014	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1015	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1016	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1017	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1018	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1019	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1020	set_mem_access(MI, false);
				1021	}
				1022
				1023	static void printAddrModeTBH(MCInst MI, unsigned Op, SStream O)
				1024	{
				1025	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1026	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1027	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1028	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1029	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1030	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1031	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1032	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1033	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1034	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1035	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1036	SStream_concat0(O, ", lsl #1]");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1037	if (MI->csh->detail) {
Nguyen Anh Quynh	706b808	2015-01-12 15:27:29 +0800	[diff] [blame]	1038	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1039	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1040	set_mem_access(MI, false);
				1041	}
				1042
				1043	static void printAddrMode2Operand(MCInst MI, unsigned Op, SStream O)
				1044	{
				1045	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1046
				1047	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1048	printOperand(MI, Op, O);
				1049	return;
				1050	}
				1051
				1052	printAM2PreOrOffsetIndexOp(MI, Op, O);
				1053	}
				1054
				1055	static void printAddrMode2OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				1056	{
				1057	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1058	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1059	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1060
				1061	if (!MCOperand_getReg(MO1)) {
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1062	unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1063	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1064	SStream_concat(O, "#%s0x%x",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1065	ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1066	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1067	SStream_concat(O, "#%s%u",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1068	ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1069	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1070	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1071	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1072	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1073	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1074	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1075	return;
				1076	}
				1077
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1078	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1079	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1080	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1081	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1082	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1083	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1084	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1085	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1086	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1087
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1088	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	1089	getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1090	}
				1091
				1092	//===--------------------------------------------------------------------===//
				1093	// Addressing Mode #3
				1094	//===--------------------------------------------------------------------===//
				1095
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1096	static void printAM3PreOrOffsetIndexOp(MCInst MI, unsigned Op, SStream O,
				1097	bool AlwaysPrintImm0)
				1098	{
				1099	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1100	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
				1101	MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1102	ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1103	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1104
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1105	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1106	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1107	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1108	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1109	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1110
				1111	if (MCOperand_getReg(MO2)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1112	SStream_concat0(O, ", ");
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1113	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1114	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1115	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1116	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1117	if (subtracted) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1118	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1119	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1120	}
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1121	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1122	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1123	set_mem_access(MI, false);
				1124	return;
				1125	}
				1126
				1127	//If the op is sub we have to print the immediate even if it is 0
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1128	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1129
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1130	if (AlwaysPrintImm0 \|\| ImmOffs \|\| (subtracted == ARM_AM_sub)) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1131	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1132	SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1133	else
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1134	SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1135	}
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1136
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1137	if (MI->csh->detail) {
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1138	if (subtracted) {
pzread	ced9a6e	2015-02-15 18:22:51 +0900	[diff] [blame]	1139	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1140	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1141	} else
Nguyen Anh Quynh	4b68d95	2015-02-25 18:01:02 +0800	[diff] [blame]	1142	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1143	}
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1144
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1145	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1146	set_mem_access(MI, false);
				1147	}
				1148
				1149	static void printAddrMode3Operand(MCInst MI, unsigned Op, SStream O,
				1150	bool AlwaysPrintImm0)
				1151	{
				1152	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1153	if (!MCOperand_isReg(MO1)) { // For label symbolic references.
				1154	printOperand(MI, Op, O);
				1155	return;
				1156	}
				1157
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1158	printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
				1159	}
				1160
				1161	static void printAddrMode3OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				1162	{
				1163	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1164	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1165	ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1166	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1167
				1168	if (MCOperand_getReg(MO1)) {
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1169	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1170	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1171	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1172	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
Nguyen Anh Quynh	8693fcd	2014-06-17 13:28:33 +0800	[diff] [blame]	1173	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1174	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1175	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1176	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1177	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1178	return;
				1179	}
				1180
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1181	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1182	if (ImmOffs > HEX_THRESHOLD)
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1183	SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1184	else
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1185	SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1186	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1187	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1188
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1189	if (subtracted) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1190	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1191	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
				1192	} else
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1193	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
Nguyen Anh Quynh	6677b99	2013-12-08 22:20:35 +0800	[diff] [blame]	1194
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1195	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1196	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1197	}
				1198
				1199	static void printPostIdxImm8Operand(MCInst MI, unsigned OpNum, SStream O)
				1200	{
				1201	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1202	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1203	if ((Imm & 0xff) > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1204	SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1205	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1206	SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1207	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1208	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1209	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
				1210	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1211	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1212	}
				1213
				1214	static void printPostIdxRegOperand(MCInst MI, unsigned OpNum, SStream O)
				1215	{
				1216	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1217	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				1218
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1219	SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1220	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1221	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1222	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1223	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1224	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1225	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1226	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1227	}
				1228
				1229	static void printPostIdxImm8s4Operand(MCInst MI, unsigned OpNum, SStream O)
				1230	{
				1231	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1232	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1233	if (((Imm & 0xff) << 2) > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1234	SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1235	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1236	SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1237	}
				1238
				1239	static void printAddrMode5Operand(MCInst MI, unsigned OpNum, SStream O,
				1240	bool AlwaysPrintImm0)
				1241	{
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1242	unsigned ImmOffs;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1243	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1244	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1245	ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1246
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1247	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1248	printOperand(MI, OpNum, O);
				1249	return;
				1250	}
				1251
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1252	SStream_concat0(O, "[");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1253	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1254
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1255	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1256	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
				1257	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
				1258	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
				1259	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
				1260	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1261	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1262	}
				1263
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1264	ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1265	if (AlwaysPrintImm0 \|\| ImmOffs \|\| subtracted == ARM_AM_sub) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1266	if (ImmOffs * 4 > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1267	SStream_concat(O, ", #%s0x%x",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1268	ARM_AM_getAddrOpcStr(subtracted),
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1269	ImmOffs * 4);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1270	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1271	SStream_concat(O, ", #%s%u",
Nguyen Anh Quynh	8fb2eab	2014-10-06 20:27:25 +0800	[diff] [blame]	1272	ARM_AM_getAddrOpcStr(subtracted),
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1273	ImmOffs * 4);
Nguyen Anh Quynh	a04ee4f	2014-06-01 10:52:01 +0700	[diff] [blame]	1274	if (MI->csh->detail) {
Nguyen Anh Quynh	6acaaa5	2014-11-10 17:41:05 +0800	[diff] [blame]	1275	if (subtracted)
				1276	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
				1277	else
Nguyen Anh Quynh	51888c3	2014-11-11 23:59:23 +0800	[diff] [blame]	1278	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4;
Nguyen Anh Quynh	a04ee4f	2014-06-01 10:52:01 +0700	[diff] [blame]	1279	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1280	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1281	SStream_concat0(O, "]");
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1282
				1283	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1284	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	b79d915	2014-06-01 10:48:55 +0700	[diff] [blame]	1285	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1286	}
				1287
				1288	static void printAddrMode6Operand(MCInst MI, unsigned OpNum, SStream O)
				1289	{
				1290	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1291	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1292	unsigned tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1293
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1294	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1295	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1296	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1297	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1298	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1299	tmp = (unsigned int)MCOperand_getImm(MO2);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1300	if (tmp) {
				1301	if (tmp << 3 > HEX_THRESHOLD)
				1302	SStream_concat(O, ":0x%x", (tmp << 3));
				1303	else
				1304	SStream_concat(O, ":%u", (tmp << 3));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1305	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1306	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1307	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1308	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1309	set_mem_access(MI, false);
				1310	}
				1311
				1312	static void printAddrMode7Operand(MCInst MI, unsigned OpNum, SStream O)
				1313	{
				1314	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1315	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1316	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1317	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1318	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1319	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1320	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1321	set_mem_access(MI, false);
				1322	}
				1323
				1324	static void printAddrMode6OffsetOperand(MCInst MI, unsigned OpNum, SStream O)
				1325	{
				1326	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	1327	if (MCOperand_getReg(MO) == 0) {
				1328	MI->writeback = true;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1329	SStream_concat0(O, "!");
Nguyen Anh Quynh	03e5e10	2015-01-21 12:15:14 +0800	[diff] [blame]	1330	} else {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1331	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1332	printRegName(MI->csh, O, MCOperand_getReg(MO));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1333	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1334	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1335	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1336	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1337	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1338	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1339	}
				1340	}
				1341
				1342	static void printBitfieldInvMaskImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1343	{
				1344	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1345	uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1346	int32_t lsb = CountTrailingZeros_32(v);
				1347	int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1348
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1349	//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1350	if (lsb > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1351	SStream_concat(O, "#0x%x", lsb);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1352	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1353	SStream_concat(O, "#%u", lsb);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1354
				1355	if (width > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1356	SStream_concat(O, ", #0x%x", width);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1357	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1358	SStream_concat(O, ", #%u", width);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1359
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1360	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1361	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1362	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
				1363	MI->flat_insn->detail->arm.op_count++;
				1364	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1365	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
				1366	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1367	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1368	}
				1369
				1370	static void printMemBOption(MCInst MI, unsigned OpNum, SStream O)
				1371	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1372	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1373	SStream_concat0(O, ARM_MB_MemBOptToString(val + 1,
Nguyen Anh Quynh	1ffc1b2	2014-11-12 13:33:15 +0800	[diff] [blame]	1374	(ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)));
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1375
				1376	if (MI->csh->detail) {
Nguyen Anh Quynh	51888c3	2014-11-11 23:59:23 +0800	[diff] [blame]	1377	MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1);
Nguyen Anh Quynh	8cdafda	2014-11-11 22:30:30 +0800	[diff] [blame]	1378	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1379	}
				1380
				1381	void printInstSyncBOption(MCInst MI, unsigned OpNum, SStream O)
				1382	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1383	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1384	SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1385	}
				1386
				1387	static void printShiftImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1388	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1389	unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1390	bool isASR = (ShiftOp & (1 << 5)) != 0;
				1391	unsigned Amt = ShiftOp & 0x1f;
				1392	if (isASR) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1393	unsigned tmp = Amt == 0 ? 32 : Amt;
				1394	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1395	SStream_concat(O, ", asr #0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1396	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1397	SStream_concat(O, ", asr #%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1398	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1399	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
				1400	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1401	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1402	} else if (Amt) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1403	if (Amt > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1404	SStream_concat(O, ", lsl #0x%x", Amt);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1405	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1406	SStream_concat(O, ", lsl #%u", Amt);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1407	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1408	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
				1409	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1410	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1411	}
				1412	}
				1413
				1414	static void printPKHLSLShiftImm(MCInst MI, unsigned OpNum, SStream O)
				1415	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1416	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1417	if (Imm == 0)
				1418	return;
				1419	//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1420	if (Imm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1421	SStream_concat(O, ", lsl #0x%x", Imm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1422	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1423	SStream_concat(O, ", lsl #%u", Imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1424	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1425	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
				1426	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1427	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1428	}
				1429
				1430	static void printPKHASRShiftImm(MCInst MI, unsigned OpNum, SStream O)
				1431	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1432	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1433	// A shift amount of 32 is encoded as 0.
				1434	if (Imm == 0)
				1435	Imm = 32;
				1436	//assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1437	if (Imm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1438	SStream_concat(O, ", asr #0x%x", Imm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1439	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1440	SStream_concat(O, ", asr #%u", Imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1441	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1442	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
				1443	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1444	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1445	}
				1446
				1447	// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
				1448	static void printRegisterList(MCInst MI, unsigned OpNum, SStream O)
				1449	{
Nguyen Anh Quynh	42706a3	2014-05-09 07:33:35 +0800	[diff] [blame]	1450	unsigned i, e;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1451	#ifndef CAPSTONE_DIET
Ole André Vadla Ravnås	d2e6b5a	2015-04-23 12:19:38 +0200	[diff] [blame^]	1452	uint8_t access = 0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1453	#endif
				1454
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1455	SStream_concat0(O, "{");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1456
				1457	#ifndef CAPSTONE_DIET
				1458	if (MI->csh->detail) {
				1459	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				1460	}
				1461	#endif
				1462
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1463	for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1464	if (i != OpNum) SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1465	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1466	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1467	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1468	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1469	#ifndef CAPSTONE_DIET
				1470	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				1471	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1472	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1473	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1474	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1475	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1476
				1477	#ifndef CAPSTONE_DIET
				1478	if (MI->csh->detail) {
				1479	MI->ac_idx++;
				1480	}
				1481	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1482	}
				1483
				1484	static void printGPRPairOperand(MCInst MI, unsigned OpNum, SStream O,
				1485	MCRegisterInfo *MRI)
				1486	{
				1487	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1488	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1489	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1490	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1491	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
				1492	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1493	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1494	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1495	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1496	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1497	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1498	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
				1499	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1500	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1501	}
				1502
				1503	// SETEND BE/LE
				1504	static void printSetendOperand(MCInst MI, unsigned OpNum, SStream O)
				1505	{
				1506	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1507	if (MCOperand_getImm(Op)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1508	SStream_concat0(O, "be");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1509	if (MI->csh->detail) {
				1510	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
				1511	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE;
				1512	MI->flat_insn->detail->arm.op_count++;
				1513	}
				1514	} else {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1515	SStream_concat0(O, "le");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1516	if (MI->csh->detail) {
				1517	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
				1518	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE;
				1519	MI->flat_insn->detail->arm.op_count++;
				1520	}
				1521	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1522	}
				1523
				1524	static void printCPSIMod(MCInst MI, unsigned OpNum, SStream O)
				1525	{
				1526	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1527	unsigned int mode = (unsigned int)MCOperand_getImm(Op);
				1528
				1529	SStream_concat0(O, ARM_PROC_IModToString(mode));
				1530
				1531	if (MI->csh->detail) {
				1532	MI->flat_insn->detail->arm.cps_mode = mode;
				1533	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1534	}
				1535
				1536	static void printCPSIFlag(MCInst MI, unsigned OpNum, SStream O)
				1537	{
				1538	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1539	unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1540	int i;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1541
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1542	for (i = 2; i >= 0; --i)
				1543	if (IFlags & (1 << i)) {
				1544	SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
				1545	}
				1546
				1547	if (IFlags == 0) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1548	SStream_concat0(O, "none");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1549	IFlags = ARM_CPSFLAG_NONE;
				1550	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1551
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1552	if (MI->csh->detail) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1553	MI->flat_insn->detail->arm.cps_flag = IFlags;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1554	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1555	}
				1556
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1557	static void printMSRMaskOperand(MCInst MI, unsigned OpNum, SStream O)
				1558	{
				1559	MCOperand *Op = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	07c92ec	2014-08-26 15:35:11 +0800	[diff] [blame]	1560	unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1561	unsigned Mask = MCOperand_getImm(Op) & 0xf;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1562	unsigned reg;
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1563	uint64_t FeatureBits = ARM_getFeatureBits(MI->csh->mode);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1564
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1565	if (FeatureBits & ARM_FeatureMClass) {
Nguyen Anh Quynh	07c92ec	2014-08-26 15:35:11 +0800	[diff] [blame]	1566	unsigned SYSm = (unsigned)MCOperand_getImm(Op);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1567	unsigned Opcode = MCInst_getOpcode(MI);
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1568
				1569	// For writes, handle extended mask bits if the DSP extension is present.
				1570	if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_FeatureDSPThumb2)) {
				1571	switch (SYSm) {
				1572	case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
				1573	case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
				1574	case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return;
				1575	case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return;
				1576	case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return;
				1577	case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return;
				1578	case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return;
				1579	case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return;
				1580	}
				1581	}
				1582
				1583	// Handle the basic 8-bit mask.
				1584	SYSm &= 0xff;
				1585
				1586	if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_HasV7Ops)) {
				1587	// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
				1588	// alias for MSR APSR_nzcvq.
				1589	switch (SYSm) {
				1590	case 0: SStream_concat0(O, "apsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
				1591	case 1: SStream_concat0(O, "iapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQ); return;
				1592	case 2: SStream_concat0(O, "eapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQ); return;
				1593	case 3: SStream_concat0(O, "xpsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQ); return;
				1594	}
				1595	}
				1596
				1597
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1598	switch (SYSm) {
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1599	default: //llvm_unreachable("Unexpected mask value!");
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	1600	case 0: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return;
				1601	case 1: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return;
				1602	case 2: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return;
				1603	case 3: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return;
				1604	case 5: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return;
				1605	case 6: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return;
				1606	case 7: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return;
				1607	case 8: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return;
				1608	case 9: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return;
				1609	case 16: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return;
				1610	case 17: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return;
				1611	case 18: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return;
				1612	case 19: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return;
				1613	case 20: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1614	}
				1615	}
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1616
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1617	// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
				1618	// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
				1619	if (!SpecRegRBit && (Mask == 8 \|\| Mask == 4 \|\| Mask == 12)) {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1620	SStream_concat0(O, "apsr_");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1621	switch (Mask) {
Nguyen Anh Quynh	b52f11f	2014-08-13 22:38:15 +0800	[diff] [blame]	1622	default: // llvm_unreachable("Unexpected mask value!");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1623	case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
				1624	case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
				1625	case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1626	}
				1627	}
				1628
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1629	reg = 0;
				1630	if (SpecRegRBit) {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1631	SStream_concat0(O, "spsr");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1632	if (Mask) {
				1633	SStream_concat0(O, "_");
				1634	if (Mask & 8) {
				1635	SStream_concat0(O, "f");
				1636	reg += ARM_SYSREG_SPSR_F;
				1637	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1638
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1639	if (Mask & 4) {
				1640	SStream_concat0(O, "s");
				1641	reg += ARM_SYSREG_SPSR_S;
				1642	}
				1643
				1644	if (Mask & 2) {
				1645	SStream_concat0(O, "x");
				1646	reg += ARM_SYSREG_SPSR_X;
				1647	}
				1648
				1649	if (Mask & 1) {
				1650	SStream_concat0(O, "c");
				1651	reg += ARM_SYSREG_SPSR_C;
				1652	}
				1653	ARM_addSysReg(MI, reg);
				1654	}
				1655	} else {
Nguyen Anh Quynh	d865f39	2014-11-10 16:38:17 +0800	[diff] [blame]	1656	SStream_concat0(O, "cpsr");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1657	if (Mask) {
				1658	SStream_concat0(O, "_");
				1659	if (Mask & 8) {
				1660	SStream_concat0(O, "f");
				1661	reg += ARM_SYSREG_CPSR_F;
				1662	}
				1663
				1664	if (Mask & 4) {
				1665	SStream_concat0(O, "s");
				1666	reg += ARM_SYSREG_CPSR_S;
				1667	}
				1668
				1669	if (Mask & 2) {
				1670	SStream_concat0(O, "x");
				1671	reg += ARM_SYSREG_CPSR_X;
				1672	}
				1673
				1674	if (Mask & 1) {
				1675	SStream_concat0(O, "c");
				1676	reg += ARM_SYSREG_CPSR_C;
				1677	}
				1678	ARM_addSysReg(MI, reg);
				1679	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1680	}
				1681	}
				1682
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1683	static void printBankedRegOperand(MCInst MI, unsigned OpNum, SStream O)
				1684	{
				1685	uint32_t Banked = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1686	uint32_t R = (Banked & 0x20) >> 5;
				1687	uint32_t SysM = Banked & 0x1f;
				1688	char *RegNames[] = {
				1689	"r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "",
				1690	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "",
				1691	"lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und",
				1692	"", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"
				1693	};
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	1694	arm_sysreg RegIds[] = {
				1695	ARM_SYSREG_R8_USR, ARM_SYSREG_R9_USR, ARM_SYSREG_R10_USR,
				1696	ARM_SYSREG_R11_USR, ARM_SYSREG_R12_USR, ARM_SYSREG_SP_USR,
				1697	ARM_SYSREG_LR_USR, 0, ARM_SYSREG_R8_FIQ, ARM_SYSREG_R9_FIQ,
				1698	ARM_SYSREG_R10_FIQ, ARM_SYSREG_R11_FIQ, ARM_SYSREG_R12_FIQ,
				1699	ARM_SYSREG_SP_FIQ, ARM_SYSREG_LR_FIQ, 0, ARM_SYSREG_LR_IRQ,
				1700	ARM_SYSREG_SP_IRQ, ARM_SYSREG_LR_SVC, ARM_SYSREG_SP_SVC,
				1701	ARM_SYSREG_LR_ABT, ARM_SYSREG_SP_ABT, ARM_SYSREG_LR_UND,
				1702	ARM_SYSREG_SP_UND, 0, 0, 0, 0, ARM_SYSREG_LR_MON, ARM_SYSREG_SP_MON,
				1703	ARM_SYSREG_ELR_HYP, ARM_SYSREG_SP_HYP,
				1704	};
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1705	char *Name = RegNames[SysM];
				1706
				1707	// Nothing much we can do about this, the encodings are specified in B9.2.3 of
				1708	// the ARM ARM v7C, and are all over the shop.
				1709	if (R) {
				1710	SStream_concat0(O, "SPSR_");
				1711
				1712	switch(SysM) {
				1713	default: // llvm_unreachable("Invalid banked SPSR register");
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	1714	case 0x0e: SStream_concat0(O, "fiq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_FIQ); return;
				1715	case 0x10: SStream_concat0(O, "irq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_IRQ); return;
				1716	case 0x12: SStream_concat0(O, "svc"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_SVC); return;
				1717	case 0x14: SStream_concat0(O, "abt"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_ABT); return;
				1718	case 0x16: SStream_concat0(O, "und"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_UND); return;
				1719	case 0x1c: SStream_concat0(O, "mon"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_MON); return;
				1720	case 0x1e: SStream_concat0(O, "hyp"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_HYP); return;
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1721	}
				1722	}
				1723
				1724	//assert(!R && "should have dealt with SPSR regs");
				1725	//assert(Name[0] && "invalid banked register operand");
				1726
				1727	SStream_concat0(O, Name);
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	1728	ARM_addSysReg(MI, RegIds[SysM]);
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	1729	}
				1730
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1731	static void printPredicateOperand(MCInst MI, unsigned OpNum, SStream O)
				1732	{
				1733	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1734	// Handle the undefined 15 CC value here for printing so we don't abort().
				1735	if ((unsigned)CC == 15) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1736	SStream_concat0(O, "<und>");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1737	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1738	MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1739	} else {
				1740	if (CC != ARMCC_AL) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1741	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1742	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1743	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1744	MI->flat_insn->detail->arm.cc = CC + 1;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1745	}
				1746	}
				1747
				1748	// TODO: test this
				1749	static void printMandatoryPredicateOperand(MCInst MI, unsigned OpNum, SStream O)
				1750	{
				1751	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1752	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1753	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1754	MI->flat_insn->detail->arm.cc = CC + 1;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1755	}
				1756
				1757	static void printSBitModifierOperand(MCInst MI, unsigned OpNum, SStream O)
				1758	{
				1759	if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
				1760	//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
				1761	// "Expect ARM CPSR register!");
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1762	SStream_concat0(O, "s");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1763	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1764	MI->flat_insn->detail->arm.update_flags = true;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1765	}
				1766	}
				1767
				1768	static void printNoHashImmediate(MCInst MI, unsigned OpNum, SStream O)
				1769	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1770	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1771	if (tmp > HEX_THRESHOLD)
				1772	SStream_concat(O, "0x%x", tmp);
				1773	else
				1774	SStream_concat(O, "%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1775	if (MI->csh->detail) {
Nguyen Anh Quynh	19b0de3	2013-12-31 22:40:04 +0800	[diff] [blame]	1776	if (MI->csh->doing_mem) {
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1777	MI->flat_insn->detail->arm.op_count--;
				1778	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = tmp;
				1779	MI->ac_idx--; // consecutive operands share the same access right
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1780	} else {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1781	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1782	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1783	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1784	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1785	}
				1786	}
				1787
				1788	static void printPImmediate(MCInst MI, unsigned OpNum, SStream O)
				1789	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1790	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1791
				1792	SStream_concat(O, "p%u", imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1793	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1794	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1795	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1796	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1797	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1798	}
				1799
				1800	static void printCImmediate(MCInst MI, unsigned OpNum, SStream O)
				1801	{
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1802	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1803
				1804	SStream_concat(O, "c%u", imm);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1805	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1806	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	1807	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1808	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1809	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1810	}
				1811
				1812	static void printCoprocOptionImm(MCInst MI, unsigned OpNum, SStream O)
				1813	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1814	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1815	if (tmp > HEX_THRESHOLD)
				1816	SStream_concat(O, "{0x%x}", tmp);
				1817	else
				1818	SStream_concat(O, "{%u}", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1819	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1820	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1821	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1822	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1823	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1824	}
				1825
				1826	static void printAdrLabelOperand(MCInst MI, unsigned OpNum, SStream O, unsigned scale)
				1827	{
				1828	MCOperand *MO = MCInst_getOperand(MI, OpNum);
				1829
				1830	int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
				1831
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1832	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1833	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1834	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1835	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1836	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				1837	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1838	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1839	} else {
				1840	if (OffImm < 0)
Nguyen Anh Quynh	741a9de	2013-11-28 16:02:08 +0800	[diff] [blame]	1841	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1842	else {
				1843	if (OffImm > HEX_THRESHOLD)
				1844	SStream_concat(O, "#0x%x", OffImm);
				1845	else
				1846	SStream_concat(O, "#%u", OffImm);
				1847	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1848	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1849	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1850	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				1851	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1852	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1853	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1854	}
				1855
				1856	static void printThumbS4ImmOperand(MCInst MI, unsigned OpNum, SStream O)
				1857	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1858	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1859	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1860	SStream_concat(O, "#0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1861	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1862	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1863	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1864	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1865	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1866	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	1867	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1868	}
				1869
				1870	static void printThumbSRImm(MCInst MI, unsigned OpNum, SStream O)
				1871	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1872	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1873	unsigned tmp = Imm == 0 ? 32 : Imm;
				1874	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1875	SStream_concat(O, "#0x%x", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1876	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1877	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1878
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1879	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1880	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				1881	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				1882	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1883	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1884	}
				1885
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1886	static void printThumbITMask(MCInst MI, unsigned OpNum, SStream O)
				1887	{
				1888	// (3 - the number of trailing zeros) is the number of then / else.
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	1889	unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
				1890	unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1891	unsigned CondBit0 = Firstcond & 1;
				1892	unsigned NumTZ = CountTrailingZeros_32(Mask);
				1893	//assert(NumTZ <= 3 && "Invalid IT mask!");
				1894	unsigned Pos, e;
				1895	for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
				1896	bool T = ((Mask >> Pos) & 1) == CondBit0;
				1897	if (T)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1898	SStream_concat0(O, "t");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1899	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1900	SStream_concat0(O, "e");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1901	}
				1902	}
				1903
				1904	static void printThumbAddrModeRROperand(MCInst MI, unsigned Op, SStream O)
				1905	{
				1906	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1907	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1908	unsigned RegNum;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1909
				1910	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1911	printOperand(MI, Op, O);
				1912	return;
				1913	}
				1914
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1915	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1916	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1917	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1918	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1919	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1920	RegNum = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1921	if (RegNum) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1922	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1923	printRegName(MI->csh, O, RegNum);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1924	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1925	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1926	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1927	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1928	set_mem_access(MI, false);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1929	}
				1930
				1931	static void printThumbAddrModeImm5SOperand(MCInst MI, unsigned Op, SStream O,
				1932	unsigned Scale)
				1933	{
				1934	MCOperand *MO1 = MCInst_getOperand(MI, Op);
				1935	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	1936	unsigned ImmOffs, tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1937
				1938	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				1939	printOperand(MI, Op, O);
				1940	return;
				1941	}
				1942
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1943	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1944	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1945	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1946	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1947	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1948	ImmOffs = (unsigned int)MCOperand_getImm(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1949	if (ImmOffs) {
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	1950	tmp = ImmOffs * Scale;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1951	SStream_concat0(O, ", ");
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	1952	if (tmp > HEX_THRESHOLD)
				1953	SStream_concat(O, "#0x%x", tmp);
				1954	else
				1955	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1956	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1957	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1958	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	1959	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1960	set_mem_access(MI, false);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	1961	}
				1962
				1963	static void printThumbAddrModeImm5S1Operand(MCInst MI, unsigned Op, SStream O)
				1964	{
				1965	printThumbAddrModeImm5SOperand(MI, Op, O, 1);
				1966	}
				1967
				1968	static void printThumbAddrModeImm5S2Operand(MCInst MI, unsigned Op, SStream O)
				1969	{
				1970	printThumbAddrModeImm5SOperand(MI, Op, O, 2);
				1971	}
				1972
				1973	static void printThumbAddrModeImm5S4Operand(MCInst MI, unsigned Op, SStream O)
				1974	{
				1975	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
				1976	}
				1977
				1978	static void printThumbAddrModeSPOperand(MCInst MI, unsigned Op, SStream O)
				1979	{
				1980	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
				1981	}
				1982
				1983	// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
				1984	// register with shift forms.
				1985	// REG 0 0 - e.g. R5
				1986	// REG IMM, SH_OPC - e.g. R5, LSL #3
				1987	static void printT2SOOperand(MCInst MI, unsigned OpNum, SStream O)
				1988	{
				1989	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				1990	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				1991
				1992	unsigned Reg = MCOperand_getReg(MO1);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	1993	printRegName(MI->csh, O, Reg);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	1994	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1995	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				1996	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	1997	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	1998	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	1999	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2000
				2001	// Print the shift opc.
				2002	//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2003	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
Nguyen Anh Quynh	8c1104b	2014-06-10 00:39:06 +0700	[diff] [blame]	2004	getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2005	}
				2006
				2007	static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
				2008	SStream *O, bool AlwaysPrintImm0)
				2009	{
				2010	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2011	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	2012	int32_t OffImm;
				2013	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2014
				2015	if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
				2016	printOperand(MI, OpNum, O);
				2017	return;
				2018	}
				2019
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2020	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2021	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2022	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2023
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2024	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2025	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2026
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2027	OffImm = (int32_t)MCOperand_getImm(MO2);
				2028	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2029	// Special value for #-0. All others are normal.
				2030	if (OffImm == INT32_MIN)
				2031	OffImm = 0;
				2032	if (isSub) {
Nguyen Anh Quynh	a247dc1	2014-04-12 00:19:42 +0800	[diff] [blame]	2033	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2034	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	a247dc1	2014-04-12 00:19:42 +0800	[diff] [blame]	2035	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2036	SStream_concat(O, ", #-%u", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2037	} else if (AlwaysPrintImm0 \|\| OffImm > 0) {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2038	if (OffImm >= 0) {
				2039	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2040	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2041	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2042	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2043	} else {
				2044	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2045	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2046	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2047	SStream_concat(O, ", #-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2048	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2049	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2050	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2051	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2052	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2053	set_mem_access(MI, false);
				2054	}
				2055
				2056	static void printT2AddrModeImm8Operand(MCInst MI, unsigned OpNum, SStream O,
				2057	bool AlwaysPrintImm0)
				2058	{
				2059	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2060	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	2061	int32_t OffImm;
				2062	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2063
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2064	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2065	set_mem_access(MI, true);
				2066
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2067	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2068	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2069	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2070
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2071	OffImm = (int32_t)MCOperand_getImm(MO2);
				2072	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2073	// Don't print +0.
				2074	if (OffImm == INT32_MIN)
				2075	OffImm = 0;
				2076
				2077	if (isSub)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2078	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2079	else if (AlwaysPrintImm0 \|\| OffImm > 0) {
				2080	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2081	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2082	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2083	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2084	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2085
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2086	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2087	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2088	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2089	set_mem_access(MI, false);
				2090	}
				2091
				2092	static void printT2AddrModeImm8s4Operand(MCInst *MI,
				2093	unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
				2094	{
				2095	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2096	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	aa078a1	2014-01-23 22:29:04 +0800	[diff] [blame]	2097	int32_t OffImm;
				2098	bool isSub;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2099
				2100	if (!MCOperand_isReg(MO1)) { // For label symbolic references.
				2101	printOperand(MI, OpNum, O);
				2102	return;
				2103	}
				2104
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2105	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2106	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2107	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2108	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2109	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2110
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2111	OffImm = (int32_t)MCOperand_getImm(MO2);
				2112	isSub = OffImm < 0;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2113
				2114	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
				2115
				2116	// Don't print +0.
				2117	if (OffImm == INT32_MIN)
				2118	OffImm = 0;
				2119	if (isSub) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2120	SStream_concat(O, ", #-0x%x", -OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2121	} else if (AlwaysPrintImm0 \|\| OffImm > 0) {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2122	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2123	SStream_concat(O, ", #0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2124	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2125	SStream_concat(O, ", #%u", OffImm);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2126	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2127	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2128	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2129
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2130	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2131	set_mem_access(MI, false);
				2132	}
				2133
				2134	static void printT2AddrModeImm0_1020s4Operand(MCInst MI, unsigned OpNum, SStream O)
				2135	{
				2136	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2137	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2138	unsigned tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2139
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2140	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2141	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2142	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2143	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2144	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2145	if (MCOperand_getImm(MO2)) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2146	SStream_concat0(O, ", ");
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2147	tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2148	if (tmp > HEX_THRESHOLD)
				2149	SStream_concat(O, "#0x%x", tmp);
				2150	else
				2151	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2152	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2153	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2154	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2155	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2156	set_mem_access(MI, false);
				2157	}
				2158
				2159	static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
				2160	unsigned OpNum, SStream *O)
				2161	{
				2162	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2163	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2164	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2165	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2166	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2167	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2168	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2169	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				2170	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2171	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2172	} else {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2173	if (OffImm < 0) {
				2174	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2175	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2176	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2177	SStream_concat(O, "#-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2178	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2179	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2180	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2181	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2182	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2183	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2184	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2185	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2186	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				2187	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2188	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2189	}
				2190	}
				2191
				2192	static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
				2193	unsigned OpNum, SStream *O)
				2194	{
				2195	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2196	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
				2197
				2198	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
				2199
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2200	SStream_concat0(O, ", ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2201	if (OffImm == INT32_MIN) {
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2202	SStream_concat0(O, "#-0");
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2203	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2204	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2205	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
				2206	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2207	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2208	} else {
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2209	if (OffImm < 0) {
				2210	if (OffImm < -HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2211	SStream_concat(O, "#-0x%x", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2212	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2213	SStream_concat(O, "#-%u", -OffImm);
Nguyen Anh Quynh	ffff756	2014-03-26 16:21:31 +0800	[diff] [blame]	2214	} else {
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2215	if (OffImm > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2216	SStream_concat(O, "#0x%x", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2217	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2218	SStream_concat(O, "#%u", OffImm);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2219	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2220	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2221	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2222	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
				2223	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2224	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2225	}
				2226	}
				2227
				2228	static void printT2AddrModeSoRegOperand(MCInst *MI,
				2229	unsigned OpNum, SStream *O)
				2230	{
				2231	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
				2232	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
				2233	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2234	unsigned ShAmt;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2235
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2236	SStream_concat0(O, "[");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2237	set_mem_access(MI, true);
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2238	printRegName(MI->csh, O, MCOperand_getReg(MO1));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2239	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2240	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2241
				2242	//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2243	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2244	printRegName(MI->csh, O, MCOperand_getReg(MO2));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2245	if (MI->csh->detail)
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2246	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2247
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2248	ShAmt = (unsigned int)MCOperand_getImm(MO3);
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2249	if (ShAmt) {
				2250	//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2251	SStream_concat0(O, ", lsl ");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2252	SStream_concat(O, "#%d", ShAmt);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2253	if (MI->csh->detail) {
Nguyen Anh Quynh	706b808	2015-01-12 15:27:29 +0800	[diff] [blame]	2254	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = ShAmt;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2255	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2256	}
				2257
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2258	SStream_concat0(O, "]");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2259	set_mem_access(MI, false);
				2260	}
				2261
				2262	static void printFPImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2263	{
				2264	MCOperand *MO = MCInst_getOperand(MI, OpNum);
Nguyen Anh Quynh	2ac5d79	2014-11-10 21:46:34 +0800	[diff] [blame]	2265	SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2266	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2267	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
				2268	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
				2269	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2270	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2271	}
				2272
				2273	static void printNEONModImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2274	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2275	unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2276	unsigned EltBits;
				2277	uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2278	if (Val > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2279	SStream_concat(O, "#0x%"PRIx64, Val);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2280	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2281	SStream_concat(O, "#%"PRIu64, Val);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2282	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2283	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2284	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
				2285	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2286	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2287	}
				2288
				2289	static void printImmPlusOneOperand(MCInst MI, unsigned OpNum, SStream O)
				2290	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2291	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2292	if (Imm + 1 > HEX_THRESHOLD)
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2293	SStream_concat(O, "#0x%x", Imm + 1);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2294	else
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2295	SStream_concat(O, "#%u", Imm + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2296	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2297	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2298	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
				2299	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2300	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2301	}
				2302
				2303	static void printRotImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2304	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2305	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2306	if (Imm == 0)
				2307	return;
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2308	SStream_concat0(O, ", ror #");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2309	switch (Imm) {
				2310	default: //assert (0 && "illegal ror immediate!");
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2311	case 1: SStream_concat0(O, "8"); break;
				2312	case 2: SStream_concat0(O, "16"); break;
				2313	case 3: SStream_concat0(O, "24"); break;
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2314	}
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2315	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2316	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
				2317	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2318	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2319	}
				2320
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	2321	static void printModImmOperand(MCInst MI, unsigned OpNum, SStream O)
				2322	{
				2323	MCOperand *Op = MCInst_getOperand(MI, OpNum);
				2324	unsigned Bits = MCOperand_getImm(Op) & 0xFF;
				2325	unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7;
				2326	int32_t Rotated;
				2327
				2328	bool PrintUnsigned = false;
				2329	switch (MCInst_getOpcode(MI)) {
				2330	case ARM_MOVi:
				2331	// Movs to PC should be treated unsigned
				2332	PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC);
				2333	break;
				2334	case ARM_MSRi:
				2335	// Movs to special registers should be treated unsigned
				2336	PrintUnsigned = true;
				2337	break;
				2338	}
				2339
				2340	Rotated = rotr32(Bits, Rot);
				2341	if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) {
				2342	// #rot has the least possible value
Nguyen Anh Quynh	e0329dd	2015-03-08 00:29:20 +0800	[diff] [blame]	2343	if (PrintUnsigned) {
				2344	if (Rotated > HEX_THRESHOLD \|\| Rotated < -HEX_THRESHOLD)
				2345	SStream_concat(O, "#0x%x", Rotated);
				2346	else
				2347	SStream_concat(O, "#%u", Rotated);
				2348	} else if (Rotated >= 0) {
Nguyen Anh Quynh	b8b8348	2015-03-07 00:26:24 +0800	[diff] [blame]	2349	if (Rotated > HEX_THRESHOLD)
				2350	SStream_concat(O, "#0x%x", Rotated);
				2351	else
				2352	SStream_concat(O, "#%u", Rotated);
				2353	} else {
				2354	SStream_concat(O, "#0x%x", Rotated);
				2355	}
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	2356	if (MI->csh->detail) {
				2357	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2358	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated;
				2359	MI->flat_insn->detail->arm.op_count++;
				2360	}
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	2361	return;
				2362	}
				2363
				2364	// Explicit #bits, #rot implied
Nguyen Anh Quynh	7e25609	2015-03-03 18:28:10 +0800	[diff] [blame]	2365	SStream_concat(O, "#%u, #%u", Bits, Rot);
				2366	if (MI->csh->detail) {
				2367	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2368	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits;
				2369	MI->flat_insn->detail->arm.op_count++;
				2370	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2371	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot;
				2372	MI->flat_insn->detail->arm.op_count++;
				2373	}
Nguyen Anh Quynh	d1fc2bd	2015-03-03 16:26:32 +0800	[diff] [blame]	2374	}
				2375
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2376	static void printFBits16(MCInst MI, unsigned OpNum, SStream O)
				2377	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2378	unsigned tmp;
				2379
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2380	tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2381	if (tmp > HEX_THRESHOLD)
				2382	SStream_concat(O, "#0x%x", tmp);
				2383	else
				2384	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2385	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2386	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2387	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				2388	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2389	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2390	}
				2391
				2392	static void printFBits32(MCInst MI, unsigned OpNum, SStream O)
				2393	{
Nguyen Anh Quynh	bb0744d	2014-05-12 13:41:49 +0800	[diff] [blame]	2394	unsigned tmp;
				2395
Axel 0vercl0k Souchet	779d4c7	2014-05-08 23:44:49 +0100	[diff] [blame]	2396	tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2397	if (tmp > HEX_THRESHOLD)
				2398	SStream_concat(O, "#0x%x", tmp);
				2399	else
				2400	SStream_concat(O, "#%u", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2401	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2402	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
				2403	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
				2404	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2405	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2406	}
				2407
				2408	static void printVectorIndex(MCInst MI, unsigned OpNum, SStream O)
				2409	{
Alex Ionescu	46018db	2014-01-22 09:45:00 -0800	[diff] [blame]	2410	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2411	if (tmp > HEX_THRESHOLD)
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2412	SStream_concat(O, "[0x%x]", tmp);
Nguyen Anh Quynh	462f291	2013-12-11 17:35:27 +0800	[diff] [blame]	2413	else
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2414	SStream_concat(O, "[%u]", tmp);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2415	if (MI->csh->detail) {
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	2416	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2417	}
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2418	}
				2419
				2420	static void printVectorListOne(MCInst MI, unsigned OpNum, SStream O)
				2421	{
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2422	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2423	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2424	if (MI->csh->detail) {
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2425	#ifndef CAPSTONE_DIET
				2426	uint8_t access;
				2427
				2428	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2429	#endif
				2430
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2431	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2432	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2433	#ifndef CAPSTONE_DIET
				2434	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2435	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2436	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2437
				2438	#ifndef CAPSTONE_DIET
				2439	MI->ac_idx++;
				2440	#endif
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2441	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2442	SStream_concat0(O, "}");
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2443	}
				2444
				2445	static void printVectorListTwo(MCInst *MI, unsigned OpNum,
				2446	SStream O, MCRegisterInfo MRI)
				2447	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2448	#ifndef CAPSTONE_DIET
				2449	uint8_t access;
				2450	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2451	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2452	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2453	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2454
				2455	#ifndef CAPSTONE_DIET
				2456	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2457	#endif
				2458
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2459	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2460	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2461	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2462	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2463	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2464	#ifndef CAPSTONE_DIET
				2465	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2466	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2467	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2468	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2469	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2470	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2471	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2472	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2473	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2474	#ifndef CAPSTONE_DIET
				2475	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2476	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2477	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2478	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2479	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2480
				2481	#ifndef CAPSTONE_DIET
				2482	MI->ac_idx++;
				2483	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2484	}
				2485
				2486	static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
				2487	SStream O, MCRegisterInfo MRI)
				2488	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2489	#ifndef CAPSTONE_DIET
				2490	uint8_t access;
				2491	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2492	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2493	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2494	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2495
				2496	#ifndef CAPSTONE_DIET
				2497	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2498	#endif
				2499
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2500	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2501	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2502	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2503	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2504	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2505	#ifndef CAPSTONE_DIET
				2506	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2507	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2508	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2509	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2510	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2511	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2512	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2513	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2514	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2515	#ifndef CAPSTONE_DIET
				2516	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2517	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2518	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2519	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2520	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2521
				2522	#ifndef CAPSTONE_DIET
				2523	MI->ac_idx++;
				2524	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2525	}
				2526
				2527	static void printVectorListThree(MCInst MI, unsigned OpNum, SStream O)
				2528	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2529	#ifndef CAPSTONE_DIET
				2530	uint8_t access;
				2531
				2532	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2533	#endif
				2534
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2535	// Normally, it's not safe to use register enum values directly with
				2536	// addition to get the next register, but for VFP registers, the
				2537	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2538	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2539	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2540	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2541	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2542	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2543	#ifndef CAPSTONE_DIET
				2544	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2545	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2546	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2547	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2548	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2549	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2550	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2551	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2552	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2553	#ifndef CAPSTONE_DIET
				2554	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2555	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2556	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2557	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2558	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2559	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2560	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2561	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2562	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2563	#ifndef CAPSTONE_DIET
				2564	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2565	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2566	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2567	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2568	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2569
				2570	#ifndef CAPSTONE_DIET
				2571	MI->ac_idx++;
				2572	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2573	}
				2574
				2575	static void printVectorListFour(MCInst MI, unsigned OpNum, SStream O)
				2576	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2577	#ifndef CAPSTONE_DIET
				2578	uint8_t access;
				2579
				2580	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2581	#endif
				2582
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2583	// Normally, it's not safe to use register enum values directly with
				2584	// addition to get the next register, but for VFP registers, the
				2585	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2586	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2587	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2588	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2589	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2590	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2591	#ifndef CAPSTONE_DIET
				2592	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2593	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2594	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2595	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2596	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2597	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2598	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2599	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2600	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2601	#ifndef CAPSTONE_DIET
				2602	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2603	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2604	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2605	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2606	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2607	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2608	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2609	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2610	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2611	#ifndef CAPSTONE_DIET
				2612	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2613	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2614	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2615	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2616	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2617	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2618	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2619	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2620	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2621	#ifndef CAPSTONE_DIET
				2622	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2623	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2624	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2625	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2626	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2627
				2628	#ifndef CAPSTONE_DIET
				2629	MI->ac_idx++;
				2630	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2631	}
				2632
				2633	static void printVectorListOneAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2634	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2635	#ifndef CAPSTONE_DIET
				2636	uint8_t access;
				2637
				2638	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2639	#endif
				2640
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2641	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2642	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2643	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2644	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2645	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2646	#ifndef CAPSTONE_DIET
				2647	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2648	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2649	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2650	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2651	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2652
				2653	#ifndef CAPSTONE_DIET
				2654	MI->ac_idx++;
				2655	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2656	}
				2657
				2658	static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
				2659	SStream O, MCRegisterInfo MRI)
				2660	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2661	#ifndef CAPSTONE_DIET
				2662	uint8_t access;
				2663	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2664	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2665	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2666	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2667
				2668	#ifndef CAPSTONE_DIET
				2669	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2670	#endif
				2671
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2672	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2673	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2674	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2675	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2676	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2677	#ifndef CAPSTONE_DIET
				2678	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2679	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2680	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2681	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2682	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2683	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2684	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2685	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2686	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2687	#ifndef CAPSTONE_DIET
				2688	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2689	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2690	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2691	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2692	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2693
				2694	#ifndef CAPSTONE_DIET
				2695	MI->ac_idx++;
				2696	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2697	}
				2698
				2699	static void printVectorListThreeAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2700	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2701	#ifndef CAPSTONE_DIET
				2702	uint8_t access;
				2703
				2704	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2705	#endif
				2706
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2707	// Normally, it's not safe to use register enum values directly with
				2708	// addition to get the next register, but for VFP registers, the
				2709	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2710	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2711	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2712	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2713	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2714	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2715	#ifndef CAPSTONE_DIET
				2716	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2717	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2718	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2719	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2720	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2721	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2722	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2723	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2724	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2725	#ifndef CAPSTONE_DIET
				2726	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2727	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2728	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2729	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2730	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2731	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2732	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2733	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2734	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2735	#ifndef CAPSTONE_DIET
				2736	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2737	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2738	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2739	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2740	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2741
				2742	#ifndef CAPSTONE_DIET
				2743	MI->ac_idx++;
				2744	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2745	}
				2746
				2747	static void printVectorListFourAllLanes(MCInst MI, unsigned OpNum, SStream O)
				2748	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2749	#ifndef CAPSTONE_DIET
				2750	uint8_t access;
				2751
				2752	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2753	#endif
				2754
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2755	// Normally, it's not safe to use register enum values directly with
				2756	// addition to get the next register, but for VFP registers, the
				2757	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2758	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2759	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2760	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2761	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2762	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2763	#ifndef CAPSTONE_DIET
				2764	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2765	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2766	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2767	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2768	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2769	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2770	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2771	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2772	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2773	#ifndef CAPSTONE_DIET
				2774	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2775	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2776	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2777	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2778	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2779	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2780	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2781	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2782	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2783	#ifndef CAPSTONE_DIET
				2784	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2785	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2786	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2787	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2788	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2789	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2790	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2791	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2792	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2793	#ifndef CAPSTONE_DIET
				2794	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2795	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2796	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2797	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2798	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2799
				2800	#ifndef CAPSTONE_DIET
				2801	MI->ac_idx++;
				2802	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2803	}
				2804
				2805	static void printVectorListTwoSpacedAllLanes(MCInst *MI,
				2806	unsigned OpNum, SStream O, MCRegisterInfo MRI)
				2807	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2808	#ifndef CAPSTONE_DIET
				2809	uint8_t access;
				2810	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2811	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
				2812	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
				2813	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2814
				2815	#ifndef CAPSTONE_DIET
				2816	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2817	#endif
				2818
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2819	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2820	printRegName(MI->csh, O, Reg0);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2821	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2822	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2823	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2824	#ifndef CAPSTONE_DIET
				2825	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2826	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2827	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2828	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2829	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2830	printRegName(MI->csh, O, Reg1);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2831	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2832	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2833	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2834	#ifndef CAPSTONE_DIET
				2835	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2836	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2837	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2838	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2839	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2840
				2841	#ifndef CAPSTONE_DIET
				2842	MI->ac_idx++;
				2843	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2844	}
				2845
				2846	static void printVectorListThreeSpacedAllLanes(MCInst *MI,
				2847	unsigned OpNum, SStream *O)
				2848	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2849	#ifndef CAPSTONE_DIET
				2850	uint8_t access;
				2851
				2852	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2853	#endif
				2854
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2855	// Normally, it's not safe to use register enum values directly with
				2856	// addition to get the next register, but for VFP registers, the
				2857	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2858	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2859	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2860	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2861	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2862	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2863	#ifndef CAPSTONE_DIET
				2864	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2865	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2866	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2867	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2868	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2869	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2870	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2871	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2872	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2873	#ifndef CAPSTONE_DIET
				2874	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2875	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2876	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2877	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2878	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2879	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2880	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2881	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2882	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2883	#ifndef CAPSTONE_DIET
				2884	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2885	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2886	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2887	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2888	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2889
				2890	#ifndef CAPSTONE_DIET
				2891	MI->ac_idx++;
				2892	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2893	}
				2894
				2895	static void printVectorListFourSpacedAllLanes(MCInst *MI,
				2896	unsigned OpNum, SStream *O)
				2897	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2898	#ifndef CAPSTONE_DIET
				2899	uint8_t access;
				2900
				2901	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2902	#endif
				2903
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2904	// Normally, it's not safe to use register enum values directly with
				2905	// addition to get the next register, but for VFP registers, the
				2906	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2907	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2908	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2909	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2910	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2911	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2912	#ifndef CAPSTONE_DIET
				2913	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2914	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2915	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2916	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2917	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2918	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2919	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2920	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2921	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2922	#ifndef CAPSTONE_DIET
				2923	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2924	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2925	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2926	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2927	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2928	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2929	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2930	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2931	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2932	#ifndef CAPSTONE_DIET
				2933	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2934	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2935	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2936	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2937	SStream_concat0(O, "[], ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2938	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2939	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2940	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2941	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2942	#ifndef CAPSTONE_DIET
				2943	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2944	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2945	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2946	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2947	SStream_concat0(O, "[]}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2948
				2949	#ifndef CAPSTONE_DIET
				2950	MI->ac_idx++;
				2951	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2952	}
				2953
				2954	static void printVectorListThreeSpaced(MCInst MI, unsigned OpNum, SStream O)
				2955	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2956	#ifndef CAPSTONE_DIET
				2957	uint8_t access;
				2958
				2959	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				2960	#endif
				2961
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	2962	// Normally, it's not safe to use register enum values directly with
				2963	// addition to get the next register, but for VFP registers, the
				2964	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2965	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2966	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2967	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2968	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2969	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2970	#ifndef CAPSTONE_DIET
				2971	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2972	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2973	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2974	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2975	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2976	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2977	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2978	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2979	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2980	#ifndef CAPSTONE_DIET
				2981	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2982	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2983	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2984	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2985	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	2986	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	2987	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2988	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				2989	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2990	#ifndef CAPSTONE_DIET
				2991	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				2992	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	2993	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	2994	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	2995	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	2996
				2997	#ifndef CAPSTONE_DIET
				2998	MI->ac_idx++;
				2999	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	3000	}
				3001
				3002	static void printVectorListFourSpaced(MCInst MI, unsigned OpNum, SStream O)
				3003	{
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3004	#ifndef CAPSTONE_DIET
				3005	uint8_t access;
				3006
				3007	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
				3008	#endif
				3009
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	3010	// Normally, it's not safe to use register enum values directly with
				3011	// addition to get the next register, but for VFP registers, the
				3012	// sort order is guaranteed because they're all of the form D<n>.
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	3013	SStream_concat0(O, "{");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	3014	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	3015	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3016	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				3017	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3018	#ifndef CAPSTONE_DIET
				3019	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				3020	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3021	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	3022	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	3023	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	3024	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	3025	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3026	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				3027	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3028	#ifndef CAPSTONE_DIET
				3029	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				3030	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3031	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	3032	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	3033	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	3034	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	3035	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3036	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				3037	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3038	#ifndef CAPSTONE_DIET
				3039	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				3040	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3041	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	3042	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	3043	SStream_concat0(O, ", ");
Nguyen Anh Quynh	2ff665a	2014-03-11 00:18:50 +0800	[diff] [blame]	3044	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
Nguyen Anh Quynh	42c6b1a	2013-12-30 00:15:25 +0800	[diff] [blame]	3045	if (MI->csh->detail) {
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3046	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				3047	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3048	#ifndef CAPSTONE_DIET
				3049	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
				3050	#endif
Nguyen Anh Quynh	29fd0f6	2014-06-09 08:00:18 +0700	[diff] [blame]	3051	MI->flat_insn->detail->arm.op_count++;
Nguyen Anh Quynh	a209e67	2013-12-14 00:23:41 +0800	[diff] [blame]	3052	}
Nguyen Anh Quynh	dd9225b	2014-06-10 00:37:53 +0700	[diff] [blame]	3053	SStream_concat0(O, "}");
Nguyen Anh Quynh	29f777b	2015-04-07 11:59:26 +0800	[diff] [blame]	3054
				3055	#ifndef CAPSTONE_DIET
				3056	MI->ac_idx++;
				3057	#endif
Nguyen Anh Quynh	26ee41a	2013-11-27 12:11:31 +0800	[diff] [blame]	3058	}
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	3059
Nguyen Anh Quynh	04d9f8e	2014-09-01 23:27:24 +0800	[diff] [blame]	3060	void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)
				3061	{
				3062	if (MI->csh->detail) {
				3063	MI->flat_insn->detail->arm.vector_data = vd;
				3064	}
				3065	}
				3066
				3067	void ARM_addVectorDataSize(MCInst *MI, int size)
				3068	{
				3069	if (MI->csh->detail) {
				3070	MI->flat_insn->detail->arm.vector_size = size;
				3071	}
				3072	}
				3073
				3074	void ARM_addReg(MCInst *MI, int reg)
				3075	{
				3076	if (MI->csh->detail) {
				3077	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
				3078	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
				3079	MI->flat_insn->detail->arm.op_count++;
				3080	}
				3081	}
				3082
				3083	void ARM_addUserMode(MCInst *MI)
				3084	{
				3085	if (MI->csh->detail) {
				3086	MI->flat_insn->detail->arm.usermode = true;
				3087	}
				3088	}
				3089
				3090	void ARM_addSysReg(MCInst *MI, arm_sysreg reg)
				3091	{
				3092	if (MI->csh->detail) {
				3093	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG;
				3094	MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
				3095	MI->flat_insn->detail->arm.op_count++;
				3096	}
				3097	}
				3098
Nguyen Anh Quynh	8598a21	2014-05-14 11:26:41 +0800	[diff] [blame]	3099	#endif