Nguyen Anh Quynh | dd40750 | 2014-01-19 23:51:34 +0800 | [diff] [blame] | 1 | #ifndef CAPSTONE_ARM64_H |
| 2 | #define CAPSTONE_ARM64_H |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3 | |
Nguyen Anh Quynh | 7751fbe | 2014-04-28 11:23:14 +0800 | [diff] [blame] | 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include <stdint.h> |
Nguyen Anh Quynh | cb59106 | 2014-05-15 21:51:02 +0800 | [diff] [blame] | 12 | #include "platform.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 13 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 14 | #ifdef _MSC_VER |
| 15 | #pragma warning(disable:4201) |
| 16 | #endif |
| 17 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 18 | //> ARM64 shift type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 19 | typedef enum arm64_shifter { |
| 20 | ARM64_SFT_INVALID = 0, |
| 21 | ARM64_SFT_LSL = 1, |
| 22 | ARM64_SFT_MSL = 2, |
| 23 | ARM64_SFT_LSR = 3, |
| 24 | ARM64_SFT_ASR = 4, |
Nguyen Anh Quynh | f8db76a | 2013-12-04 12:37:55 +0800 | [diff] [blame] | 25 | ARM64_SFT_ROR = 5, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 26 | } arm64_shifter; |
| 27 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 28 | //> ARM64 extender type |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 29 | typedef enum arm64_extender { |
| 30 | ARM64_EXT_INVALID = 0, |
| 31 | ARM64_EXT_UXTB = 1, |
| 32 | ARM64_EXT_UXTH = 2, |
| 33 | ARM64_EXT_UXTW = 3, |
| 34 | ARM64_EXT_UXTX = 4, |
| 35 | ARM64_EXT_SXTB = 5, |
| 36 | ARM64_EXT_SXTH = 6, |
| 37 | ARM64_EXT_SXTW = 7, |
| 38 | ARM64_EXT_SXTX = 8, |
| 39 | } arm64_extender; |
| 40 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 41 | //> ARM64 condition code |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 42 | typedef enum arm64_cc { |
| 43 | ARM64_CC_INVALID = 0, |
| 44 | ARM64_CC_EQ = 1, // Equal |
| 45 | ARM64_CC_NE = 2, // Not equal: Not equal, or unordered |
| 46 | ARM64_CC_HS = 3, // Unsigned higher or same: >, ==, or unordered |
| 47 | ARM64_CC_LO = 4, // Unsigned lower or same: Less than |
| 48 | ARM64_CC_MI = 5, // Minus, negative: Less than |
| 49 | ARM64_CC_PL = 6, // Plus, positive or zero: >, ==, or unordered |
| 50 | ARM64_CC_VS = 7, // Overflow: Unordered |
| 51 | ARM64_CC_VC = 8, // No overflow: Ordered |
| 52 | ARM64_CC_HI = 9, // Unsigned higher: Greater than, or unordered |
| 53 | ARM64_CC_LS = 10, // Unsigned lower or same: Less than or equal |
| 54 | ARM64_CC_GE = 11, // Greater than or equal: Greater than or equal |
| 55 | ARM64_CC_LT = 12, // Less than: Less than, or unordered |
| 56 | ARM64_CC_GT = 13, // Signed greater than: Greater than |
| 57 | ARM64_CC_LE = 14, // Signed less than or equal: <, ==, or unordered |
| 58 | ARM64_CC_AL = 15, // Always (unconditional): Always (unconditional) |
| 59 | ARM64_CC_NV = 16, // Always (unconditional): Always (unconditional) |
| 60 | // Note the NV exists purely to disassemble 0b1111. Execution |
| 61 | // is "always". |
| 62 | } arm64_cc; |
| 63 | |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 64 | //> System registers |
| 65 | typedef enum arm64_mrs_reg { |
| 66 | //> System registers for MRS |
| 67 | ARM64_SYSREG_INVALID = 0, |
| 68 | ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 |
| 69 | ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 |
| 70 | ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 |
| 71 | ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 |
| 72 | ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 |
| 73 | ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 |
| 74 | ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 |
| 75 | ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 |
| 76 | ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 |
| 77 | ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 |
| 78 | ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 |
| 79 | ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 |
| 80 | ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 |
| 81 | ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 |
| 82 | ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 |
| 83 | ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 |
| 84 | ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 |
| 85 | ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 |
| 86 | ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 |
| 87 | ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 |
| 88 | ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 |
| 89 | ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 |
| 90 | ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 |
| 91 | ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 |
| 92 | ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 |
| 93 | ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 |
| 94 | ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 |
| 95 | ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 |
| 96 | ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 |
| 97 | ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 |
| 98 | ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 |
| 99 | ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 |
| 100 | ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 |
| 101 | ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 |
| 102 | ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 |
| 103 | ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 |
| 104 | ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 |
| 105 | ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 |
| 106 | ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 |
| 107 | ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 |
| 108 | ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 |
| 109 | ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 |
| 110 | ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 |
| 111 | ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 |
| 112 | ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 |
| 113 | ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 |
| 114 | ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 |
| 115 | ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 |
| 116 | |
| 117 | // Trace registers |
| 118 | ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000 |
| 119 | ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 |
| 120 | ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 |
| 121 | ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 |
| 122 | ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 |
| 123 | ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 |
| 124 | ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 |
| 125 | ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 |
| 126 | ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 |
| 127 | ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 |
| 128 | ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 |
| 129 | ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 |
| 130 | ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 |
| 131 | ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 |
| 132 | ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 |
| 133 | ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 |
| 134 | ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 |
| 135 | ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 |
| 136 | ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 |
| 137 | ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110 |
| 138 | ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 |
| 139 | ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 |
| 140 | ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 |
| 141 | ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 |
| 142 | ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 |
| 143 | ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 |
| 144 | ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 |
| 145 | ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 |
| 146 | ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 |
| 147 | ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 |
| 148 | ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 |
| 149 | ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 |
| 150 | ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 |
| 151 | ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 |
| 152 | ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 |
| 153 | ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 |
| 154 | |
| 155 | // GICv3 registers |
| 156 | ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 |
| 157 | ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 |
| 158 | ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 |
| 159 | ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 |
| 160 | ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 |
| 161 | ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 |
| 162 | ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 |
Nguyen Anh Quynh | acbafc6 | 2014-09-25 12:46:17 +0800 | [diff] [blame] | 163 | ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101 |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 164 | } arm64_sysreg; |
| 165 | |
| 166 | typedef enum arm64_msr_reg { |
| 167 | //> System registers for MSR |
| 168 | ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 |
| 169 | ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 |
| 170 | ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 |
| 171 | |
| 172 | // Trace Registers |
| 173 | ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 |
| 174 | ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110 |
| 175 | |
| 176 | // GICv3 registers |
| 177 | ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 |
| 178 | ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 |
| 179 | ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 |
| 180 | ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 |
| 181 | ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 |
Nguyen Anh Quynh | acbafc6 | 2014-09-25 12:46:17 +0800 | [diff] [blame] | 182 | ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111 |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 183 | } arm64_msr_reg; |
| 184 | |
| 185 | //> System PState Field (MSR instruction) |
| 186 | typedef enum arm64_pstate { |
| 187 | ARM64_PSTATE_INVALID = 0, |
| 188 | ARM64_PSTATE_SPSEL = 0x05, |
| 189 | ARM64_PSTATE_DAIFSET = 0x1e, |
| 190 | ARM64_PSTATE_DAIFCLR = 0x1f |
| 191 | } arm64_pstate; |
| 192 | |
| 193 | //> Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) |
| 194 | typedef enum arm64_vas { |
| 195 | ARM64_VAS_INVALID = 0, |
| 196 | ARM64_VAS_8B, |
| 197 | ARM64_VAS_16B, |
| 198 | ARM64_VAS_4H, |
| 199 | ARM64_VAS_8H, |
| 200 | ARM64_VAS_2S, |
| 201 | ARM64_VAS_4S, |
| 202 | ARM64_VAS_1D, |
| 203 | ARM64_VAS_2D, |
| 204 | ARM64_VAS_1Q, |
| 205 | } arm64_vas; |
| 206 | |
| 207 | //> Vector element size specifier |
| 208 | typedef enum arm64_vess { |
| 209 | ARM64_VESS_INVALID = 0, |
| 210 | ARM64_VESS_B, |
| 211 | ARM64_VESS_H, |
| 212 | ARM64_VESS_S, |
| 213 | ARM64_VESS_D, |
| 214 | } arm64_vess; |
| 215 | |
| 216 | //> Memory barrier operands |
| 217 | typedef enum arm64_barrier_op { |
| 218 | ARM64_BARRIER_INVALID = 0, |
| 219 | ARM64_BARRIER_OSHLD = 0x1, |
| 220 | ARM64_BARRIER_OSHST = 0x2, |
| 221 | ARM64_BARRIER_OSH = 0x3, |
| 222 | ARM64_BARRIER_NSHLD = 0x5, |
| 223 | ARM64_BARRIER_NSHST = 0x6, |
| 224 | ARM64_BARRIER_NSH = 0x7, |
| 225 | ARM64_BARRIER_ISHLD = 0x9, |
| 226 | ARM64_BARRIER_ISHST = 0xa, |
| 227 | ARM64_BARRIER_ISH = 0xb, |
| 228 | ARM64_BARRIER_LD = 0xd, |
| 229 | ARM64_BARRIER_ST = 0xe, |
| 230 | ARM64_BARRIER_SY = 0xf |
| 231 | } arm64_barrier_op; |
| 232 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 233 | //> Operand type for instruction's operands |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 234 | typedef enum arm64_op_type { |
Nguyen Anh Quynh | c58e704 | 2014-10-31 13:55:18 +0800 | [diff] [blame] | 235 | ARM64_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). |
| 236 | ARM64_OP_REG, // = CS_OP_REG (Register operand). |
| 237 | ARM64_OP_IMM, // = CS_OP_IMM (Immediate operand). |
| 238 | ARM64_OP_MEM, // = CS_OP_MEM (Memory operand). |
| 239 | ARM64_OP_FP, // = CS_OP_FP (Floating-Point operand). |
Nguyen Anh Quynh | 21ac056 | 2014-10-31 13:08:28 +0800 | [diff] [blame] | 240 | ARM64_OP_CIMM = 64, // C-Immediate |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 241 | ARM64_OP_REG_MRS, // MRS register operand. |
| 242 | ARM64_OP_REG_MSR, // MSR register operand. |
| 243 | ARM64_OP_PSTATE, // PState operand. |
| 244 | ARM64_OP_SYS, // SYS operand for IC/DC/AT/TLBI instructions. |
| 245 | ARM64_OP_PREFETCH, // Prefetch operand (PRFM). |
| 246 | ARM64_OP_BARRIER, // Memory barrier operand (ISB/DMB/DSB instructions). |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 247 | } arm64_op_type; |
| 248 | |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 249 | //> TLBI operations |
| 250 | typedef enum arm64_tlbi_op { |
| 251 | ARM64_TLBI_INVALID = 0, |
| 252 | ARM64_TLBI_VMALLE1IS, |
| 253 | ARM64_TLBI_VAE1IS, |
| 254 | ARM64_TLBI_ASIDE1IS, |
| 255 | ARM64_TLBI_VAAE1IS, |
| 256 | ARM64_TLBI_VALE1IS, |
| 257 | ARM64_TLBI_VAALE1IS, |
| 258 | ARM64_TLBI_ALLE2IS, |
| 259 | ARM64_TLBI_VAE2IS, |
| 260 | ARM64_TLBI_ALLE1IS, |
| 261 | ARM64_TLBI_VALE2IS, |
| 262 | ARM64_TLBI_VMALLS12E1IS, |
| 263 | ARM64_TLBI_ALLE3IS, |
| 264 | ARM64_TLBI_VAE3IS, |
| 265 | ARM64_TLBI_VALE3IS, |
| 266 | ARM64_TLBI_IPAS2E1IS, |
| 267 | ARM64_TLBI_IPAS2LE1IS, |
| 268 | ARM64_TLBI_IPAS2E1, |
| 269 | ARM64_TLBI_IPAS2LE1, |
| 270 | ARM64_TLBI_VMALLE1, |
| 271 | ARM64_TLBI_VAE1, |
| 272 | ARM64_TLBI_ASIDE1, |
| 273 | ARM64_TLBI_VAAE1, |
| 274 | ARM64_TLBI_VALE1, |
| 275 | ARM64_TLBI_VAALE1, |
| 276 | ARM64_TLBI_ALLE2, |
| 277 | ARM64_TLBI_VAE2, |
| 278 | ARM64_TLBI_ALLE1, |
| 279 | ARM64_TLBI_VALE2, |
| 280 | ARM64_TLBI_VMALLS12E1, |
| 281 | ARM64_TLBI_ALLE3, |
| 282 | ARM64_TLBI_VAE3, |
| 283 | ARM64_TLBI_VALE3, |
| 284 | } arm64_tlbi_op; |
| 285 | |
| 286 | //> AT operations |
| 287 | typedef enum arm64_at_op { |
| 288 | ARM64_AT_S1E1R, |
| 289 | ARM64_AT_S1E1W, |
| 290 | ARM64_AT_S1E0R, |
| 291 | ARM64_AT_S1E0W, |
| 292 | ARM64_AT_S1E2R, |
| 293 | ARM64_AT_S1E2W, |
| 294 | ARM64_AT_S12E1R, |
| 295 | ARM64_AT_S12E1W, |
| 296 | ARM64_AT_S12E0R, |
| 297 | ARM64_AT_S12E0W, |
| 298 | ARM64_AT_S1E3R, |
| 299 | ARM64_AT_S1E3W, |
| 300 | } arm64_at_op; |
| 301 | |
| 302 | //> DC operations |
| 303 | typedef enum arm64_dc_op { |
| 304 | ARM64_DC_INVALID = 0, |
| 305 | ARM64_DC_ZVA, |
| 306 | ARM64_DC_IVAC, |
| 307 | ARM64_DC_ISW, |
| 308 | ARM64_DC_CVAC, |
| 309 | ARM64_DC_CSW, |
| 310 | ARM64_DC_CVAU, |
| 311 | ARM64_DC_CIVAC, |
| 312 | ARM64_DC_CISW, |
| 313 | } arm64_dc_op; |
| 314 | |
| 315 | //> IC operations |
| 316 | typedef enum arm64_ic_op { |
| 317 | ARM64_IC_INVALID = 0, |
| 318 | ARM64_IC_IALLUIS, |
| 319 | ARM64_IC_IALLU, |
| 320 | ARM64_IC_IVAU, |
| 321 | } arm64_ic_op; |
| 322 | |
| 323 | //> Prefetch operations (PRFM) |
| 324 | typedef enum arm64_prefetch_op { |
| 325 | ARM64_PRFM_INVALID = 0, |
| 326 | ARM64_PRFM_PLDL1KEEP = 0x00 + 1, |
| 327 | ARM64_PRFM_PLDL1STRM = 0x01 + 1, |
| 328 | ARM64_PRFM_PLDL2KEEP = 0x02 + 1, |
| 329 | ARM64_PRFM_PLDL2STRM = 0x03 + 1, |
| 330 | ARM64_PRFM_PLDL3KEEP = 0x04 + 1, |
| 331 | ARM64_PRFM_PLDL3STRM = 0x05 + 1, |
| 332 | ARM64_PRFM_PLIL1KEEP = 0x08 + 1, |
| 333 | ARM64_PRFM_PLIL1STRM = 0x09 + 1, |
| 334 | ARM64_PRFM_PLIL2KEEP = 0x0a + 1, |
| 335 | ARM64_PRFM_PLIL2STRM = 0x0b + 1, |
| 336 | ARM64_PRFM_PLIL3KEEP = 0x0c + 1, |
| 337 | ARM64_PRFM_PLIL3STRM = 0x0d + 1, |
| 338 | ARM64_PRFM_PSTL1KEEP = 0x10 + 1, |
| 339 | ARM64_PRFM_PSTL1STRM = 0x11 + 1, |
| 340 | ARM64_PRFM_PSTL2KEEP = 0x12 + 1, |
| 341 | ARM64_PRFM_PSTL2STRM = 0x13 + 1, |
| 342 | ARM64_PRFM_PSTL3KEEP = 0x14 + 1, |
| 343 | ARM64_PRFM_PSTL3STRM = 0x15 + 1, |
| 344 | } arm64_prefetch_op; |
| 345 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 346 | // Instruction's operand referring to memory |
| 347 | // This is associated with ARM64_OP_MEM operand type above |
| 348 | typedef struct arm64_op_mem { |
| 349 | unsigned int base; // base register |
| 350 | unsigned int index; // index register |
Nguyen Anh Quynh | 90acea3 | 2013-11-29 17:54:17 +0800 | [diff] [blame] | 351 | int32_t disp; // displacement/offset value |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 352 | } arm64_op_mem; |
| 353 | |
| 354 | // Instruction operand |
| 355 | typedef struct cs_arm64_op { |
Nguyen Anh Quynh | 4f0d704 | 2014-08-29 15:11:23 +0800 | [diff] [blame] | 356 | int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 357 | arm64_vas vas; // Vector Arrangement Specifier |
| 358 | arm64_vess vess; // Vector Element Size Specifier |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 359 | struct { |
| 360 | arm64_shifter type; // shifter type of this operand |
| 361 | unsigned int value; // shifter value of this operand |
| 362 | } shift; |
| 363 | arm64_extender ext; // extender type of this operand |
| 364 | arm64_op_type type; // operand type |
| 365 | union { |
| 366 | unsigned int reg; // register value for REG operand |
Nguyen Anh Quynh | 56128da | 2014-11-17 11:27:15 +0800 | [diff] [blame] | 367 | int64_t imm; // immediate value, or index for C-IMM or IMM operand |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 368 | double fp; // floating point value for FP operand |
| 369 | arm64_op_mem mem; // base/index/scale/disp value for MEM operand |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 370 | arm64_pstate pstate; // PState field of MSR instruction. |
| 371 | unsigned int sys; // IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) |
| 372 | arm64_prefetch_op prefetch; // PRFM operation. |
| 373 | arm64_barrier_op barrier; // Memory barrier operation (ISB/DMB/DSB instructions). |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 374 | }; |
| 375 | } cs_arm64_op; |
| 376 | |
| 377 | // Instruction structure |
| 378 | typedef struct cs_arm64 { |
| 379 | arm64_cc cc; // conditional code for this insn |
| 380 | bool update_flags; // does this insn update flags? |
| 381 | bool writeback; // does this insn request writeback? 'True' means 'yes' |
| 382 | |
| 383 | // Number of operands of this instruction, |
| 384 | // or 0 when instruction has no operand. |
| 385 | uint8_t op_count; |
| 386 | |
Nguyen Anh Quynh | f1656de | 2013-11-29 20:26:34 +0800 | [diff] [blame] | 387 | cs_arm64_op operands[8]; // operands for this instruction. |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 388 | } cs_arm64; |
| 389 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 390 | //> ARM64 registers |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 391 | typedef enum arm64_reg { |
| 392 | ARM64_REG_INVALID = 0, |
Nguyen Anh Quynh | ea5b79d | 2013-12-04 12:10:47 +0800 | [diff] [blame] | 393 | |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 394 | ARM64_REG_X29, |
| 395 | ARM64_REG_X30, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 396 | ARM64_REG_NZCV, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 397 | ARM64_REG_SP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 398 | ARM64_REG_WSP, |
Nguyen Anh Quynh | 9693450 | 2014-05-18 00:07:24 +0800 | [diff] [blame] | 399 | ARM64_REG_WZR, |
Nguyen Anh Quynh | 9693450 | 2014-05-18 00:07:24 +0800 | [diff] [blame] | 400 | ARM64_REG_XZR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 401 | ARM64_REG_B0, |
| 402 | ARM64_REG_B1, |
| 403 | ARM64_REG_B2, |
| 404 | ARM64_REG_B3, |
| 405 | ARM64_REG_B4, |
| 406 | ARM64_REG_B5, |
| 407 | ARM64_REG_B6, |
| 408 | ARM64_REG_B7, |
| 409 | ARM64_REG_B8, |
| 410 | ARM64_REG_B9, |
| 411 | ARM64_REG_B10, |
| 412 | ARM64_REG_B11, |
| 413 | ARM64_REG_B12, |
| 414 | ARM64_REG_B13, |
| 415 | ARM64_REG_B14, |
| 416 | ARM64_REG_B15, |
| 417 | ARM64_REG_B16, |
| 418 | ARM64_REG_B17, |
| 419 | ARM64_REG_B18, |
| 420 | ARM64_REG_B19, |
| 421 | ARM64_REG_B20, |
| 422 | ARM64_REG_B21, |
| 423 | ARM64_REG_B22, |
| 424 | ARM64_REG_B23, |
| 425 | ARM64_REG_B24, |
| 426 | ARM64_REG_B25, |
| 427 | ARM64_REG_B26, |
| 428 | ARM64_REG_B27, |
| 429 | ARM64_REG_B28, |
| 430 | ARM64_REG_B29, |
| 431 | ARM64_REG_B30, |
| 432 | ARM64_REG_B31, |
| 433 | ARM64_REG_D0, |
| 434 | ARM64_REG_D1, |
| 435 | ARM64_REG_D2, |
| 436 | ARM64_REG_D3, |
| 437 | ARM64_REG_D4, |
| 438 | ARM64_REG_D5, |
| 439 | ARM64_REG_D6, |
| 440 | ARM64_REG_D7, |
| 441 | ARM64_REG_D8, |
| 442 | ARM64_REG_D9, |
| 443 | ARM64_REG_D10, |
| 444 | ARM64_REG_D11, |
| 445 | ARM64_REG_D12, |
| 446 | ARM64_REG_D13, |
| 447 | ARM64_REG_D14, |
| 448 | ARM64_REG_D15, |
| 449 | ARM64_REG_D16, |
| 450 | ARM64_REG_D17, |
| 451 | ARM64_REG_D18, |
| 452 | ARM64_REG_D19, |
| 453 | ARM64_REG_D20, |
| 454 | ARM64_REG_D21, |
| 455 | ARM64_REG_D22, |
| 456 | ARM64_REG_D23, |
| 457 | ARM64_REG_D24, |
| 458 | ARM64_REG_D25, |
| 459 | ARM64_REG_D26, |
| 460 | ARM64_REG_D27, |
| 461 | ARM64_REG_D28, |
| 462 | ARM64_REG_D29, |
| 463 | ARM64_REG_D30, |
| 464 | ARM64_REG_D31, |
| 465 | ARM64_REG_H0, |
| 466 | ARM64_REG_H1, |
| 467 | ARM64_REG_H2, |
| 468 | ARM64_REG_H3, |
| 469 | ARM64_REG_H4, |
| 470 | ARM64_REG_H5, |
| 471 | ARM64_REG_H6, |
| 472 | ARM64_REG_H7, |
| 473 | ARM64_REG_H8, |
| 474 | ARM64_REG_H9, |
| 475 | ARM64_REG_H10, |
| 476 | ARM64_REG_H11, |
| 477 | ARM64_REG_H12, |
| 478 | ARM64_REG_H13, |
| 479 | ARM64_REG_H14, |
| 480 | ARM64_REG_H15, |
| 481 | ARM64_REG_H16, |
| 482 | ARM64_REG_H17, |
| 483 | ARM64_REG_H18, |
| 484 | ARM64_REG_H19, |
| 485 | ARM64_REG_H20, |
| 486 | ARM64_REG_H21, |
| 487 | ARM64_REG_H22, |
| 488 | ARM64_REG_H23, |
| 489 | ARM64_REG_H24, |
| 490 | ARM64_REG_H25, |
| 491 | ARM64_REG_H26, |
| 492 | ARM64_REG_H27, |
| 493 | ARM64_REG_H28, |
| 494 | ARM64_REG_H29, |
| 495 | ARM64_REG_H30, |
| 496 | ARM64_REG_H31, |
| 497 | ARM64_REG_Q0, |
| 498 | ARM64_REG_Q1, |
| 499 | ARM64_REG_Q2, |
| 500 | ARM64_REG_Q3, |
| 501 | ARM64_REG_Q4, |
| 502 | ARM64_REG_Q5, |
| 503 | ARM64_REG_Q6, |
| 504 | ARM64_REG_Q7, |
| 505 | ARM64_REG_Q8, |
| 506 | ARM64_REG_Q9, |
| 507 | ARM64_REG_Q10, |
| 508 | ARM64_REG_Q11, |
| 509 | ARM64_REG_Q12, |
| 510 | ARM64_REG_Q13, |
| 511 | ARM64_REG_Q14, |
| 512 | ARM64_REG_Q15, |
| 513 | ARM64_REG_Q16, |
| 514 | ARM64_REG_Q17, |
| 515 | ARM64_REG_Q18, |
| 516 | ARM64_REG_Q19, |
| 517 | ARM64_REG_Q20, |
| 518 | ARM64_REG_Q21, |
| 519 | ARM64_REG_Q22, |
| 520 | ARM64_REG_Q23, |
| 521 | ARM64_REG_Q24, |
| 522 | ARM64_REG_Q25, |
| 523 | ARM64_REG_Q26, |
| 524 | ARM64_REG_Q27, |
| 525 | ARM64_REG_Q28, |
| 526 | ARM64_REG_Q29, |
| 527 | ARM64_REG_Q30, |
| 528 | ARM64_REG_Q31, |
| 529 | ARM64_REG_S0, |
| 530 | ARM64_REG_S1, |
| 531 | ARM64_REG_S2, |
| 532 | ARM64_REG_S3, |
| 533 | ARM64_REG_S4, |
| 534 | ARM64_REG_S5, |
| 535 | ARM64_REG_S6, |
| 536 | ARM64_REG_S7, |
| 537 | ARM64_REG_S8, |
| 538 | ARM64_REG_S9, |
| 539 | ARM64_REG_S10, |
| 540 | ARM64_REG_S11, |
| 541 | ARM64_REG_S12, |
| 542 | ARM64_REG_S13, |
| 543 | ARM64_REG_S14, |
| 544 | ARM64_REG_S15, |
| 545 | ARM64_REG_S16, |
| 546 | ARM64_REG_S17, |
| 547 | ARM64_REG_S18, |
| 548 | ARM64_REG_S19, |
| 549 | ARM64_REG_S20, |
| 550 | ARM64_REG_S21, |
| 551 | ARM64_REG_S22, |
| 552 | ARM64_REG_S23, |
| 553 | ARM64_REG_S24, |
| 554 | ARM64_REG_S25, |
| 555 | ARM64_REG_S26, |
| 556 | ARM64_REG_S27, |
| 557 | ARM64_REG_S28, |
| 558 | ARM64_REG_S29, |
| 559 | ARM64_REG_S30, |
| 560 | ARM64_REG_S31, |
| 561 | ARM64_REG_W0, |
| 562 | ARM64_REG_W1, |
| 563 | ARM64_REG_W2, |
| 564 | ARM64_REG_W3, |
| 565 | ARM64_REG_W4, |
| 566 | ARM64_REG_W5, |
| 567 | ARM64_REG_W6, |
| 568 | ARM64_REG_W7, |
| 569 | ARM64_REG_W8, |
| 570 | ARM64_REG_W9, |
| 571 | ARM64_REG_W10, |
| 572 | ARM64_REG_W11, |
| 573 | ARM64_REG_W12, |
| 574 | ARM64_REG_W13, |
| 575 | ARM64_REG_W14, |
| 576 | ARM64_REG_W15, |
| 577 | ARM64_REG_W16, |
| 578 | ARM64_REG_W17, |
| 579 | ARM64_REG_W18, |
| 580 | ARM64_REG_W19, |
| 581 | ARM64_REG_W20, |
| 582 | ARM64_REG_W21, |
| 583 | ARM64_REG_W22, |
| 584 | ARM64_REG_W23, |
| 585 | ARM64_REG_W24, |
| 586 | ARM64_REG_W25, |
| 587 | ARM64_REG_W26, |
| 588 | ARM64_REG_W27, |
| 589 | ARM64_REG_W28, |
| 590 | ARM64_REG_W29, |
| 591 | ARM64_REG_W30, |
| 592 | ARM64_REG_X0, |
| 593 | ARM64_REG_X1, |
| 594 | ARM64_REG_X2, |
| 595 | ARM64_REG_X3, |
| 596 | ARM64_REG_X4, |
| 597 | ARM64_REG_X5, |
| 598 | ARM64_REG_X6, |
| 599 | ARM64_REG_X7, |
| 600 | ARM64_REG_X8, |
| 601 | ARM64_REG_X9, |
| 602 | ARM64_REG_X10, |
| 603 | ARM64_REG_X11, |
| 604 | ARM64_REG_X12, |
| 605 | ARM64_REG_X13, |
| 606 | ARM64_REG_X14, |
| 607 | ARM64_REG_X15, |
| 608 | ARM64_REG_X16, |
| 609 | ARM64_REG_X17, |
| 610 | ARM64_REG_X18, |
| 611 | ARM64_REG_X19, |
| 612 | ARM64_REG_X20, |
| 613 | ARM64_REG_X21, |
| 614 | ARM64_REG_X22, |
| 615 | ARM64_REG_X23, |
| 616 | ARM64_REG_X24, |
| 617 | ARM64_REG_X25, |
| 618 | ARM64_REG_X26, |
| 619 | ARM64_REG_X27, |
| 620 | ARM64_REG_X28, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 621 | |
| 622 | ARM64_REG_V0, |
| 623 | ARM64_REG_V1, |
| 624 | ARM64_REG_V2, |
| 625 | ARM64_REG_V3, |
| 626 | ARM64_REG_V4, |
| 627 | ARM64_REG_V5, |
| 628 | ARM64_REG_V6, |
| 629 | ARM64_REG_V7, |
| 630 | ARM64_REG_V8, |
| 631 | ARM64_REG_V9, |
| 632 | ARM64_REG_V10, |
| 633 | ARM64_REG_V11, |
| 634 | ARM64_REG_V12, |
| 635 | ARM64_REG_V13, |
| 636 | ARM64_REG_V14, |
| 637 | ARM64_REG_V15, |
| 638 | ARM64_REG_V16, |
| 639 | ARM64_REG_V17, |
| 640 | ARM64_REG_V18, |
| 641 | ARM64_REG_V19, |
| 642 | ARM64_REG_V20, |
| 643 | ARM64_REG_V21, |
| 644 | ARM64_REG_V22, |
| 645 | ARM64_REG_V23, |
| 646 | ARM64_REG_V24, |
| 647 | ARM64_REG_V25, |
| 648 | ARM64_REG_V26, |
| 649 | ARM64_REG_V27, |
| 650 | ARM64_REG_V28, |
| 651 | ARM64_REG_V29, |
| 652 | ARM64_REG_V30, |
| 653 | ARM64_REG_V31, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 654 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 655 | ARM64_REG_ENDING, // <-- mark the end of the list of registers |
Nguyen Anh Quynh | 7957ed1 | 2013-12-15 00:32:20 +0800 | [diff] [blame] | 656 | |
| 657 | //> alias registers |
| 658 | |
| 659 | ARM64_REG_IP1 = ARM64_REG_X16, |
| 660 | ARM64_REG_IP0 = ARM64_REG_X17, |
| 661 | ARM64_REG_FP = ARM64_REG_X29, |
| 662 | ARM64_REG_LR = ARM64_REG_X30, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 663 | } arm64_reg; |
| 664 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 665 | //> ARM64 instruction |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 666 | typedef enum arm64_insn { |
| 667 | ARM64_INS_INVALID = 0, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 668 | |
| 669 | ARM64_INS_ABS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 670 | ARM64_INS_ADC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 671 | ARM64_INS_ADDHN, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 672 | ARM64_INS_ADDHN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 673 | ARM64_INS_ADDP, |
| 674 | ARM64_INS_ADD, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 675 | ARM64_INS_ADDV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 676 | ARM64_INS_ADR, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 677 | ARM64_INS_ADRP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 678 | ARM64_INS_AESD, |
| 679 | ARM64_INS_AESE, |
| 680 | ARM64_INS_AESIMC, |
| 681 | ARM64_INS_AESMC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 682 | ARM64_INS_AND, |
| 683 | ARM64_INS_ASR, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 684 | ARM64_INS_B, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 685 | ARM64_INS_BFM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 686 | ARM64_INS_BIC, |
| 687 | ARM64_INS_BIF, |
| 688 | ARM64_INS_BIT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 689 | ARM64_INS_BL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 690 | ARM64_INS_BLR, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 691 | ARM64_INS_BR, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 692 | ARM64_INS_BRK, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 693 | ARM64_INS_BSL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 694 | ARM64_INS_CBNZ, |
| 695 | ARM64_INS_CBZ, |
| 696 | ARM64_INS_CCMN, |
| 697 | ARM64_INS_CCMP, |
| 698 | ARM64_INS_CLREX, |
| 699 | ARM64_INS_CLS, |
| 700 | ARM64_INS_CLZ, |
| 701 | ARM64_INS_CMEQ, |
| 702 | ARM64_INS_CMGE, |
| 703 | ARM64_INS_CMGT, |
| 704 | ARM64_INS_CMHI, |
| 705 | ARM64_INS_CMHS, |
| 706 | ARM64_INS_CMLE, |
| 707 | ARM64_INS_CMLT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 708 | ARM64_INS_CMTST, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 709 | ARM64_INS_CNT, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 710 | ARM64_INS_MOV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 711 | ARM64_INS_CRC32B, |
| 712 | ARM64_INS_CRC32CB, |
| 713 | ARM64_INS_CRC32CH, |
| 714 | ARM64_INS_CRC32CW, |
| 715 | ARM64_INS_CRC32CX, |
| 716 | ARM64_INS_CRC32H, |
| 717 | ARM64_INS_CRC32W, |
| 718 | ARM64_INS_CRC32X, |
| 719 | ARM64_INS_CSEL, |
| 720 | ARM64_INS_CSINC, |
| 721 | ARM64_INS_CSINV, |
| 722 | ARM64_INS_CSNEG, |
| 723 | ARM64_INS_DCPS1, |
| 724 | ARM64_INS_DCPS2, |
| 725 | ARM64_INS_DCPS3, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 726 | ARM64_INS_DMB, |
| 727 | ARM64_INS_DRPS, |
| 728 | ARM64_INS_DSB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 729 | ARM64_INS_DUP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 730 | ARM64_INS_EON, |
| 731 | ARM64_INS_EOR, |
| 732 | ARM64_INS_ERET, |
| 733 | ARM64_INS_EXTR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 734 | ARM64_INS_EXT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 735 | ARM64_INS_FABD, |
| 736 | ARM64_INS_FABS, |
| 737 | ARM64_INS_FACGE, |
| 738 | ARM64_INS_FACGT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 739 | ARM64_INS_FADD, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 740 | ARM64_INS_FADDP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 741 | ARM64_INS_FCCMP, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 742 | ARM64_INS_FCCMPE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 743 | ARM64_INS_FCMEQ, |
| 744 | ARM64_INS_FCMGE, |
| 745 | ARM64_INS_FCMGT, |
| 746 | ARM64_INS_FCMLE, |
| 747 | ARM64_INS_FCMLT, |
| 748 | ARM64_INS_FCMP, |
| 749 | ARM64_INS_FCMPE, |
| 750 | ARM64_INS_FCSEL, |
| 751 | ARM64_INS_FCVTAS, |
| 752 | ARM64_INS_FCVTAU, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 753 | ARM64_INS_FCVT, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 754 | ARM64_INS_FCVTL, |
| 755 | ARM64_INS_FCVTL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 756 | ARM64_INS_FCVTMS, |
| 757 | ARM64_INS_FCVTMU, |
| 758 | ARM64_INS_FCVTNS, |
| 759 | ARM64_INS_FCVTNU, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 760 | ARM64_INS_FCVTN, |
| 761 | ARM64_INS_FCVTN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 762 | ARM64_INS_FCVTPS, |
| 763 | ARM64_INS_FCVTPU, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 764 | ARM64_INS_FCVTXN, |
| 765 | ARM64_INS_FCVTXN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 766 | ARM64_INS_FCVTZS, |
| 767 | ARM64_INS_FCVTZU, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 768 | ARM64_INS_FDIV, |
| 769 | ARM64_INS_FMADD, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 770 | ARM64_INS_FMAX, |
| 771 | ARM64_INS_FMAXNM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 772 | ARM64_INS_FMAXNMP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 773 | ARM64_INS_FMAXNMV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 774 | ARM64_INS_FMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 775 | ARM64_INS_FMAXV, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 776 | ARM64_INS_FMIN, |
| 777 | ARM64_INS_FMINNM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 778 | ARM64_INS_FMINNMP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 779 | ARM64_INS_FMINNMV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 780 | ARM64_INS_FMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 781 | ARM64_INS_FMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 782 | ARM64_INS_FMLA, |
| 783 | ARM64_INS_FMLS, |
| 784 | ARM64_INS_FMOV, |
| 785 | ARM64_INS_FMSUB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 786 | ARM64_INS_FMUL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 787 | ARM64_INS_FMULX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 788 | ARM64_INS_FNEG, |
| 789 | ARM64_INS_FNMADD, |
| 790 | ARM64_INS_FNMSUB, |
| 791 | ARM64_INS_FNMUL, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 792 | ARM64_INS_FRECPE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 793 | ARM64_INS_FRECPS, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 794 | ARM64_INS_FRECPX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 795 | ARM64_INS_FRINTA, |
| 796 | ARM64_INS_FRINTI, |
| 797 | ARM64_INS_FRINTM, |
| 798 | ARM64_INS_FRINTN, |
| 799 | ARM64_INS_FRINTP, |
| 800 | ARM64_INS_FRINTX, |
| 801 | ARM64_INS_FRINTZ, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 802 | ARM64_INS_FRSQRTE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 803 | ARM64_INS_FRSQRTS, |
| 804 | ARM64_INS_FSQRT, |
| 805 | ARM64_INS_FSUB, |
| 806 | ARM64_INS_HINT, |
| 807 | ARM64_INS_HLT, |
| 808 | ARM64_INS_HVC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 809 | ARM64_INS_INS, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 810 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 811 | ARM64_INS_ISB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 812 | ARM64_INS_LD1, |
| 813 | ARM64_INS_LD1R, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 814 | ARM64_INS_LD2R, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 815 | ARM64_INS_LD2, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 816 | ARM64_INS_LD3R, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 817 | ARM64_INS_LD3, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 818 | ARM64_INS_LD4, |
| 819 | ARM64_INS_LD4R, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 820 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 821 | ARM64_INS_LDARB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 822 | ARM64_INS_LDARH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 823 | ARM64_INS_LDAR, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 824 | ARM64_INS_LDAXP, |
| 825 | ARM64_INS_LDAXRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 826 | ARM64_INS_LDAXRH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 827 | ARM64_INS_LDAXR, |
| 828 | ARM64_INS_LDNP, |
| 829 | ARM64_INS_LDP, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 830 | ARM64_INS_LDPSW, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 831 | ARM64_INS_LDRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 832 | ARM64_INS_LDR, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 833 | ARM64_INS_LDRH, |
| 834 | ARM64_INS_LDRSB, |
| 835 | ARM64_INS_LDRSH, |
| 836 | ARM64_INS_LDRSW, |
| 837 | ARM64_INS_LDTRB, |
| 838 | ARM64_INS_LDTRH, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 839 | ARM64_INS_LDTRSB, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 840 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 841 | ARM64_INS_LDTRSH, |
| 842 | ARM64_INS_LDTRSW, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 843 | ARM64_INS_LDTR, |
| 844 | ARM64_INS_LDURB, |
| 845 | ARM64_INS_LDUR, |
| 846 | ARM64_INS_LDURH, |
| 847 | ARM64_INS_LDURSB, |
| 848 | ARM64_INS_LDURSH, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 849 | ARM64_INS_LDURSW, |
| 850 | ARM64_INS_LDXP, |
| 851 | ARM64_INS_LDXRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 852 | ARM64_INS_LDXRH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 853 | ARM64_INS_LDXR, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 854 | ARM64_INS_LSL, |
| 855 | ARM64_INS_LSR, |
| 856 | ARM64_INS_MADD, |
| 857 | ARM64_INS_MLA, |
| 858 | ARM64_INS_MLS, |
| 859 | ARM64_INS_MOVI, |
| 860 | ARM64_INS_MOVK, |
| 861 | ARM64_INS_MOVN, |
| 862 | ARM64_INS_MOVZ, |
| 863 | ARM64_INS_MRS, |
| 864 | ARM64_INS_MSR, |
| 865 | ARM64_INS_MSUB, |
| 866 | ARM64_INS_MUL, |
| 867 | ARM64_INS_MVNI, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 868 | ARM64_INS_NEG, |
| 869 | ARM64_INS_NOT, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 870 | ARM64_INS_ORN, |
| 871 | ARM64_INS_ORR, |
| 872 | ARM64_INS_PMULL2, |
| 873 | ARM64_INS_PMULL, |
| 874 | ARM64_INS_PMUL, |
| 875 | ARM64_INS_PRFM, |
| 876 | ARM64_INS_PRFUM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 877 | ARM64_INS_RADDHN, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 878 | ARM64_INS_RADDHN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 879 | ARM64_INS_RBIT, |
| 880 | ARM64_INS_RET, |
| 881 | ARM64_INS_REV16, |
| 882 | ARM64_INS_REV32, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 883 | ARM64_INS_REV64, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 884 | ARM64_INS_REV, |
| 885 | ARM64_INS_ROR, |
| 886 | ARM64_INS_RSHRN2, |
| 887 | ARM64_INS_RSHRN, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 888 | ARM64_INS_RSUBHN, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 889 | ARM64_INS_RSUBHN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 890 | ARM64_INS_SABAL2, |
| 891 | ARM64_INS_SABAL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 892 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 893 | ARM64_INS_SABA, |
| 894 | ARM64_INS_SABDL2, |
| 895 | ARM64_INS_SABDL, |
| 896 | ARM64_INS_SABD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 897 | ARM64_INS_SADALP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 898 | ARM64_INS_SADDLP, |
| 899 | ARM64_INS_SADDLV, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 900 | ARM64_INS_SADDL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 901 | ARM64_INS_SADDL, |
| 902 | ARM64_INS_SADDW2, |
| 903 | ARM64_INS_SADDW, |
| 904 | ARM64_INS_SBC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 905 | ARM64_INS_SBFM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 906 | ARM64_INS_SCVTF, |
| 907 | ARM64_INS_SDIV, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 908 | ARM64_INS_SHA1C, |
| 909 | ARM64_INS_SHA1H, |
| 910 | ARM64_INS_SHA1M, |
| 911 | ARM64_INS_SHA1P, |
| 912 | ARM64_INS_SHA1SU0, |
| 913 | ARM64_INS_SHA1SU1, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 914 | ARM64_INS_SHA256H2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 915 | ARM64_INS_SHA256H, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 916 | ARM64_INS_SHA256SU0, |
| 917 | ARM64_INS_SHA256SU1, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 918 | ARM64_INS_SHADD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 919 | ARM64_INS_SHLL2, |
| 920 | ARM64_INS_SHLL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 921 | ARM64_INS_SHL, |
| 922 | ARM64_INS_SHRN2, |
| 923 | ARM64_INS_SHRN, |
| 924 | ARM64_INS_SHSUB, |
| 925 | ARM64_INS_SLI, |
| 926 | ARM64_INS_SMADDL, |
| 927 | ARM64_INS_SMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 928 | ARM64_INS_SMAXV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 929 | ARM64_INS_SMAX, |
| 930 | ARM64_INS_SMC, |
| 931 | ARM64_INS_SMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 932 | ARM64_INS_SMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 933 | ARM64_INS_SMIN, |
| 934 | ARM64_INS_SMLAL2, |
| 935 | ARM64_INS_SMLAL, |
| 936 | ARM64_INS_SMLSL2, |
| 937 | ARM64_INS_SMLSL, |
| 938 | ARM64_INS_SMOV, |
| 939 | ARM64_INS_SMSUBL, |
| 940 | ARM64_INS_SMULH, |
| 941 | ARM64_INS_SMULL2, |
| 942 | ARM64_INS_SMULL, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 943 | ARM64_INS_SQABS, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 944 | ARM64_INS_SQADD, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 945 | ARM64_INS_SQDMLAL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 946 | ARM64_INS_SQDMLAL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 947 | ARM64_INS_SQDMLSL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 948 | ARM64_INS_SQDMLSL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 949 | ARM64_INS_SQDMULH, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 950 | ARM64_INS_SQDMULL, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 951 | ARM64_INS_SQDMULL2, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 952 | ARM64_INS_SQNEG, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 953 | ARM64_INS_SQRDMULH, |
| 954 | ARM64_INS_SQRSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 955 | ARM64_INS_SQRSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 956 | ARM64_INS_SQRSHRN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 957 | ARM64_INS_SQRSHRUN, |
| 958 | ARM64_INS_SQRSHRUN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 959 | ARM64_INS_SQSHLU, |
| 960 | ARM64_INS_SQSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 961 | ARM64_INS_SQSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 962 | ARM64_INS_SQSHRN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 963 | ARM64_INS_SQSHRUN, |
| 964 | ARM64_INS_SQSHRUN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 965 | ARM64_INS_SQSUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 966 | ARM64_INS_SQXTN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 967 | ARM64_INS_SQXTN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 968 | ARM64_INS_SQXTUN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 969 | ARM64_INS_SQXTUN, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 970 | ARM64_INS_SRHADD, |
| 971 | ARM64_INS_SRI, |
| 972 | ARM64_INS_SRSHL, |
| 973 | ARM64_INS_SRSHR, |
| 974 | ARM64_INS_SRSRA, |
| 975 | ARM64_INS_SSHLL2, |
| 976 | ARM64_INS_SSHLL, |
| 977 | ARM64_INS_SSHL, |
| 978 | ARM64_INS_SSHR, |
| 979 | ARM64_INS_SSRA, |
| 980 | ARM64_INS_SSUBL2, |
| 981 | ARM64_INS_SSUBL, |
| 982 | ARM64_INS_SSUBW2, |
| 983 | ARM64_INS_SSUBW, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 984 | ARM64_INS_ST1, |
| 985 | ARM64_INS_ST2, |
| 986 | ARM64_INS_ST3, |
| 987 | ARM64_INS_ST4, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 988 | ARM64_INS_STLRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 989 | ARM64_INS_STLRH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 990 | ARM64_INS_STLR, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 991 | ARM64_INS_STLXP, |
| 992 | ARM64_INS_STLXRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 993 | ARM64_INS_STLXRH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 994 | ARM64_INS_STLXR, |
| 995 | ARM64_INS_STNP, |
| 996 | ARM64_INS_STP, |
| 997 | ARM64_INS_STRB, |
| 998 | ARM64_INS_STR, |
| 999 | ARM64_INS_STRH, |
| 1000 | ARM64_INS_STTRB, |
| 1001 | ARM64_INS_STTRH, |
| 1002 | ARM64_INS_STTR, |
| 1003 | ARM64_INS_STURB, |
| 1004 | ARM64_INS_STUR, |
| 1005 | ARM64_INS_STURH, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1006 | ARM64_INS_STXP, |
| 1007 | ARM64_INS_STXRB, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1008 | ARM64_INS_STXRH, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1009 | ARM64_INS_STXR, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1010 | ARM64_INS_SUBHN, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1011 | ARM64_INS_SUBHN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1012 | ARM64_INS_SUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1013 | ARM64_INS_SUQADD, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1014 | ARM64_INS_SVC, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1015 | ARM64_INS_SYSL, |
| 1016 | ARM64_INS_SYS, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1017 | ARM64_INS_TBL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1018 | ARM64_INS_TBNZ, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1019 | ARM64_INS_TBX, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1020 | ARM64_INS_TBZ, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1021 | ARM64_INS_TRN1, |
| 1022 | ARM64_INS_TRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1023 | ARM64_INS_UABAL2, |
| 1024 | ARM64_INS_UABAL, |
| 1025 | ARM64_INS_UABA, |
| 1026 | ARM64_INS_UABDL2, |
| 1027 | ARM64_INS_UABDL, |
| 1028 | ARM64_INS_UABD, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1029 | ARM64_INS_UADALP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1030 | ARM64_INS_UADDLP, |
| 1031 | ARM64_INS_UADDLV, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1032 | ARM64_INS_UADDL2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1033 | ARM64_INS_UADDL, |
| 1034 | ARM64_INS_UADDW2, |
| 1035 | ARM64_INS_UADDW, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1036 | ARM64_INS_UBFM, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1037 | ARM64_INS_UCVTF, |
| 1038 | ARM64_INS_UDIV, |
| 1039 | ARM64_INS_UHADD, |
| 1040 | ARM64_INS_UHSUB, |
| 1041 | ARM64_INS_UMADDL, |
| 1042 | ARM64_INS_UMAXP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1043 | ARM64_INS_UMAXV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1044 | ARM64_INS_UMAX, |
| 1045 | ARM64_INS_UMINP, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1046 | ARM64_INS_UMINV, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1047 | ARM64_INS_UMIN, |
| 1048 | ARM64_INS_UMLAL2, |
| 1049 | ARM64_INS_UMLAL, |
| 1050 | ARM64_INS_UMLSL2, |
| 1051 | ARM64_INS_UMLSL, |
| 1052 | ARM64_INS_UMOV, |
| 1053 | ARM64_INS_UMSUBL, |
| 1054 | ARM64_INS_UMULH, |
| 1055 | ARM64_INS_UMULL2, |
| 1056 | ARM64_INS_UMULL, |
| 1057 | ARM64_INS_UQADD, |
| 1058 | ARM64_INS_UQRSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1059 | ARM64_INS_UQRSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1060 | ARM64_INS_UQRSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1061 | ARM64_INS_UQSHL, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1062 | ARM64_INS_UQSHRN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1063 | ARM64_INS_UQSHRN2, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1064 | ARM64_INS_UQSUB, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1065 | ARM64_INS_UQXTN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1066 | ARM64_INS_UQXTN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1067 | ARM64_INS_URECPE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1068 | ARM64_INS_URHADD, |
| 1069 | ARM64_INS_URSHL, |
| 1070 | ARM64_INS_URSHR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1071 | ARM64_INS_URSQRTE, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1072 | ARM64_INS_URSRA, |
| 1073 | ARM64_INS_USHLL2, |
| 1074 | ARM64_INS_USHLL, |
| 1075 | ARM64_INS_USHL, |
| 1076 | ARM64_INS_USHR, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1077 | ARM64_INS_USQADD, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1078 | ARM64_INS_USRA, |
| 1079 | ARM64_INS_USUBL2, |
| 1080 | ARM64_INS_USUBL, |
| 1081 | ARM64_INS_USUBW2, |
| 1082 | ARM64_INS_USUBW, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1083 | ARM64_INS_UZP1, |
| 1084 | ARM64_INS_UZP2, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1085 | ARM64_INS_XTN2, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1086 | ARM64_INS_XTN, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1087 | ARM64_INS_ZIP1, |
| 1088 | ARM64_INS_ZIP2, |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 1089 | |
| 1090 | // alias insn |
| 1091 | ARM64_INS_MNEG, |
Nguyen Anh Quynh | 6b9b664 | 2013-11-30 12:28:56 +0800 | [diff] [blame] | 1092 | ARM64_INS_UMNEGL, |
| 1093 | ARM64_INS_SMNEGL, |
Nguyen Anh Quynh | 6b9b664 | 2013-11-30 12:28:56 +0800 | [diff] [blame] | 1094 | ARM64_INS_NOP, |
| 1095 | ARM64_INS_YIELD, |
| 1096 | ARM64_INS_WFE, |
| 1097 | ARM64_INS_WFI, |
| 1098 | ARM64_INS_SEV, |
| 1099 | ARM64_INS_SEVL, |
| 1100 | ARM64_INS_NGC, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1101 | ARM64_INS_SBFIZ, |
| 1102 | ARM64_INS_UBFIZ, |
| 1103 | ARM64_INS_SBFX, |
| 1104 | ARM64_INS_UBFX, |
| 1105 | ARM64_INS_BFI, |
| 1106 | ARM64_INS_BFXIL, |
| 1107 | ARM64_INS_CMN, |
| 1108 | ARM64_INS_MVN, |
| 1109 | ARM64_INS_TST, |
| 1110 | ARM64_INS_CSET, |
| 1111 | ARM64_INS_CINC, |
| 1112 | ARM64_INS_CSETM, |
| 1113 | ARM64_INS_CINV, |
| 1114 | ARM64_INS_CNEG, |
| 1115 | ARM64_INS_SXTB, |
| 1116 | ARM64_INS_SXTH, |
| 1117 | ARM64_INS_SXTW, |
| 1118 | ARM64_INS_CMP, |
| 1119 | ARM64_INS_UXTB, |
| 1120 | ARM64_INS_UXTH, |
| 1121 | ARM64_INS_UXTW, |
| 1122 | ARM64_INS_IC, |
| 1123 | ARM64_INS_DC, |
| 1124 | ARM64_INS_AT, |
| 1125 | ARM64_INS_TLBI, |
Nguyen Anh Quynh | 6b7abe3 | 2013-11-30 00:54:24 +0800 | [diff] [blame] | 1126 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 1127 | ARM64_INS_ENDING, // <-- mark the end of the list of insn |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1128 | } arm64_insn; |
| 1129 | |
Nguyen Anh Quynh | a2f825f | 2013-12-04 23:56:24 +0800 | [diff] [blame] | 1130 | //> Group of ARM64 instructions |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1131 | typedef enum arm64_insn_group { |
Nguyen Anh Quynh | 3ab5091 | 2014-10-31 14:40:45 +0800 | [diff] [blame] | 1132 | ARM64_GRP_INVALID = 0, // = CS_GRP_INVALID |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1133 | |
Nguyen Anh Quynh | 3ab5091 | 2014-10-31 14:40:45 +0800 | [diff] [blame] | 1134 | //> Generic groups |
| 1135 | // all jump instructions (conditional+direct+indirect jumps) |
| 1136 | ARM64_GRP_JUMP, // = CS_GRP_JUMP |
| 1137 | |
| 1138 | //> Architecture-specific groups |
| 1139 | ARM64_GRP_CRYPTO = 128, |
Nguyen Anh Quynh | 731bf2a | 2013-12-08 15:13:47 +0800 | [diff] [blame] | 1140 | ARM64_GRP_FPARMV8, |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1141 | ARM64_GRP_NEON, |
Nguyen Anh Quynh | 46a74e5 | 2014-08-25 16:47:12 +0800 | [diff] [blame] | 1142 | ARM64_GRP_CRC, |
Nguyen Anh Quynh | 3582bc1 | 2013-12-03 09:43:27 +0800 | [diff] [blame] | 1143 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 1144 | ARM64_GRP_ENDING, // <-- mark the end of the list of groups |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1145 | } arm64_insn_group; |
| 1146 | |
| 1147 | #ifdef __cplusplus |
| 1148 | } |
| 1149 | #endif |
| 1150 | |
| 1151 | #endif |