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gerrit-public.fairphone.software / platform / external / capstone / 3808eec03330341a09f8017c5370dbf6a4fa1c13 / arch
  1. 1d9615d Fix Thumb disassembler memory corruption with IT sequence (issue #385) by Nikolay Igotti · 9 years ago
  2. aceb2bb x86: fix value of access field for some instructions. bug reported by Ben Nagy by Nguyen Anh Quynh · 9 years ago
  3. 4caced6 arm: add missing group string for CALL & INT. bug reported by Ben Nagy by Nguyen Anh Quynh · 9 years ago
  4. aa17e37 Fix building by MSVC 2010 lacking inttypes.h by Yegor Derevenets · 9 years ago
  5. 106e0f1 arm: fix an warning on conversion from uint64_t to bool. issue reported by @yegord by Nguyen Anh Quynh · 9 years ago
  6. b6f0d44 arm64: print immediate as signed int64 for memory operands. suggested by @pancake by Nguyen Anh Quynh · 9 years ago
  7. a071b47 arm64: make the new code instroduced by David more friendly with MSVC & do check for valid detail pointer before updating writeback by Nguyen Anh Quynh · 9 years ago
  8. 320b383 Merge branch 'next' of https://github.com/DavidCallahan/capstone into DavidCallahan-next by Nguyen Anh Quynh · 9 years ago
  9. 19dc1ce fix stray typo by David Callahan · 9 years ago
  10. 4cd1885 reformat by David Callahan · 9 years ago
  11. 63542ab merge by David Callahan · 9 years ago
  12. 9c95bde fix setting writeback for post index memory accesses by David Callahan · 9 years ago
  13. fb59de4 x86: make all shifted instructions to support first operand in AT&T syntax. issue reported by @bipulr by Nguyen Anh Quynh · 9 years ago
  14. b0217f6 ppc: fix an warning on comparison of unsigned int by Nguyen Anh Quynh · 9 years ago
  15. 79cc044 Merge branch 'ppc64' of https://github.com/randomstuff/capstone into randomstuff-ppc64 by Nguyen Anh Quynh · 9 years ago
  16. 94fbce1 x86: CALL should modify stack pointer register. also, relative CALL should references instruction pointer. issue reported by @zachriggle by Nguyen Anh Quynh · 9 years ago
  17. 8102aac Make PowerPC imm 64 bit (instad 32 bit) by Gabriel Corona · 9 years ago
  18. 63547c7 fix setting writeback for post index memory accesses by David Callahan · 9 years ago
  19. c42effd arm: do not need to put ARM_GRP_JUMP into insns[], as it is autogenerated by Nguyen Anh Quynh · 9 years ago
  20. 227cdd1 arm: ARM_GRP_JUMP is generated at run-time, so do not include it in insn[] by Nguyen Anh Quynh · 9 years ago
  21. 01a744c arm: Added instruction group ARM_GRP_INT, ARM_INS_SVC is now using it. by derrek · 9 years ago
  22. 2dbe2e6 Merge branch 'next' of https://github.com/aquynh/capstone into next by derrek · 9 years ago
  23. 21b9b25 x86: fix 16bit address bound issue. reported by Oleksii Kuchma by Nguyen Anh Quynh · 10 years ago
  24. a118474 x86: save the immediates being changed for printing out (instructions INT/AND/OR/XOR) by Nguyen Anh Quynh · 10 years ago
  25. 52a6b8b arm: fix a similar issue with the last issue on MOVsr instructions by Nguyen Anh Quynh · 10 years ago
  26. 91a1cb4 arm: correct the alias instruction id for MOVsi instructions. bug reported by @joelpx by Nguyen Anh Quynh · 10 years ago
  27. 1182d25 simplify ARCH_group_name() by using lookup table as suggested by @learn_more. also added the missing group name for GRP_PRIVILEGE by Nguyen Anh Quynh · 10 years ago
  28. 5a3b9c1 Merge pull request #329 from frida/fix/warning by Nguyen Anh Quynh · 10 years ago
  29. d2e6b5a Fix warning reported by MSVC by Ole André Vadla Ravnås · 10 years ago
  30. a4f9da9 Fix handling of cmpxchg16b with lock prefix by Ole André Vadla Ravnås · 10 years ago
  31. 67aee91 arm: Changed CS_GRP_ prefix to ARM_GRP_ prefix, added ARM_GRP_CALL group. by derrek · 10 years ago
  32. cf959c0 coding style by Nguyen Anh Quynh · 10 years ago
  33. 49ff95b arm: Fixed implicit read/written registers for SVC instructions. by derrek · 10 years ago
  34. 5b78a6a Fixed/added ARM_GRP_JUMP and CS_GRP_CALL information. by derrek · 10 years ago
  35. 3c5d08f Merge pull request #316 from remittor/next3 by Nguyen Anh Quynh · 10 years ago
  36. 34c5ae3 arm: BLX should read PC & modify LR registers. bug reported by Zach Riggle by Nguyen Anh Quynh · 10 years ago
  37. 368c367 [x86] Fix decode opcode A0 and A1 (X86_MOV32ao16 + X86_MOV64ao32) by remittor · 10 years ago
  38. b5e0f13 Merge branch 'next' of https://github.com/aquynh/capstone into next by Vincent Bénony · 10 years ago
  39. d2f47d0 Remove enum for ASRS, LSRS, SUBS and MOVS by Vincent Bénony · 10 years ago
  40. 68d7f72 remove some variants by Vincent Bénony · 10 years ago
  41. 75bd853 Merge pull request #318 from captincook/next by Nguyen Anh Quynh · 10 years ago
  42. f59b3a7 [x86] Fix decode opcode A0 and A1 (movabs) by remittor · 10 years ago
  43. 72ee3c9 sparc: Improved displacement decoding for banching instructions by NighterMan · 10 years ago
  44. 26cb4aa x86: add more cases to print as unsigned 8bit imm by me · 10 years ago
  45. 89820c4 x86: print 8 bit immediate number in positive form. still need a more systematic approach to do same thing for other forms of immediates by Nguyen Anh Quynh · 10 years ago
  46. 160e198 Add support to embed Capstone 3.x branch into OS X kernel extensions. by reverser · 10 years ago
  47. 7289f15 x86: tighter check on return of consumeByte() & lookAtByte(). this fixes the segfault on the sole input of 0xf3 reported by windhl by Nguyen Anh Quynh · 10 years ago
  48. 29f777b arm: support cs_regs_access() API by Nguyen Anh Quynh · 10 years ago
  49. 7fc876a x86: add some FP instructions with st(0) register to insn_regs_att[] & insn_regs_intel[]. also add missing access info for these instructions to insn_ops[] by Nguyen Anh Quynh · 10 years ago
  50. ad18ed0 x86: fix issue #305. also correct arrays insn_regs_att[] & insn_regs_intel[] by Nguyen Anh Quynh · 10 years ago
  51. b023ffe x86: add missing CL register operand for shift rotate instructions involving CL (AT&T syntax) by Nguyen Anh Quynh · 10 years ago
  52. 3f1bfc9 x86: fix operand access info of string instructions by Nguyen Anh Quynh · 10 years ago
  53. 199ef42 x86: the exact registers (*SI/*DI) that string instructions access depend on hardware mode (16/32/64bit) by Nguyen Anh Quynh · 10 years ago
  54. fce28ce x86: revert the old change that check prefix location more strictly by Nguyen Anh Quynh · 10 years ago
  55. 85b194f Merge pull request #303 from bSr43/eflags-fix by Nguyen Anh Quynh · 10 years ago
  56. 1f33733 Same fix on the reduce table. by Vincent Bénony · 10 years ago
  57. 865dd8f Merge branch 'eflags-fix' of https://github.com/bSr43/capstone into t9 by Nguyen Anh Quynh · 10 years ago
  58. 7b02b12 Fix EFLAGS for the sar/sal/shr/shl instructions. by Vincent Bénony · 10 years ago
  59. 58eb073 x86: avoid duplicating registers returned by cs_regs_access(). also add *CX registers to regs_read[], regs_write[] for REP* instructions by Nguyen Anh Quynh · 10 years ago
  60. 9239967 x86: fix instruction 66f20f59ff reported by @maijin by Nguyen Anh Quynh · 10 years ago
  61. 6a4d277 x86: fix the pause instruction reported by @maijin in issue #298 by Nguyen Anh Quynh · 10 years ago
  62. d505d6d x86: initialize cs_x86.{xop_cc, eflags} by Nguyen Anh Quynh · 10 years ago
  63. 87d754d Merge branch 'next' of https://github.com/aquynh/capstone into next by Nguyen Anh Quynh · 10 years ago
  64. 228ec96 x86: LEA instruction should not access the second operand. bug reported by @chaplja by Nguyen Anh Quynh · 10 years ago
  65. 19ee2d1 inttypes.h fix by Cr4sh · 10 years ago
  66. efffe78 Add new API and start to provide access information for instruction operands by Nguyen Anh Quynh · 10 years ago
  67. 75e94a0 arm: fix some instructions in insn_ops[] where GPRwithAPSR & addr_offset_non should be considered for register access. issue reported by @derrekr by Nguyen Anh Quynh · 10 years ago
  68. 5e5b1f5 core: rename operand access symbols from CS_OP_* to CS_AC_* by Nguyen Anh Quynh · 10 years ago
  69. 6a77cc7 arm: some fixes for insn_ops[] where some registers should be considered for accessing. issue reported by @derrek by Nguyen Anh Quynh · 10 years ago
  70. c79a8a0 arm: fix lots of issues with insn_op[], and move it to a separate file ARMMappingInsnOp.inc by Nguyen Anh Quynh · 10 years ago
  71. 5b93f59 x86: more fix for lots of OP_NOREG in insn_ops[]. also renamed it to OP_IGNORE by Nguyen Anh Quynh · 10 years ago
  72. 1271684 x86: print interrupt number of INT instruction in positive form. bug reported by @pancake by Nguyen Anh Quynh · 10 years ago
  73. 8bb1f04 x86: fix lots of issues with insn_op[], and move it to a separate file X86MappingInsnOp.inc by Nguyen Anh Quynh · 10 years ago
  74. f970679 arm64: use symbol rather than constant (128) for calculating group name in AArch64_group_name() by Nguyen Anh Quynh · 10 years ago
  75. a6fb47b Merge branch 'AArch64Details' of https://github.com/DavidCallahan/capstone into test3 by Nguyen Anh Quynh · 10 years ago
  76. 9092e52 Change AArch64 GRP_JUMP to use a static table implementation by David Callahan · 10 years ago
  77. 2c1b7f1 x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx by Nguyen Anh Quynh · 10 years ago
  78. 21bf9ce Merge branch 'next' of https://github.com/aquynh/capstone into next by Nguyen Anh Quynh · 10 years ago
  79. 681070c Merge pull request #279 from radare/arm64-priv by Nguyen Anh Quynh · 10 years ago
  80. ba7bf10 Merge pull request #278 from radare/arm-priv by Nguyen Anh Quynh · 10 years ago
  81. b8ffb86 ppc: fix a bug in QPX mode & add some QPX alias instructions. by Nguyen Anh Quynh · 10 years ago
  82. 0cc0543 ppc: add missing groups to group_name_maps[]. bug reported by Coverity by Nguyen Anh Quynh · 10 years ago
  83. e171243 arm: add the missing Virtualization group to group_name_maps[]. bug reported by Coverity by Nguyen Anh Quynh · 10 years ago
  84. 09218a2 x86: remove unsed field @prefixLocations of InternalInstruction struct by Nguyen Anh Quynh · 10 years ago
  85. bcb75a2 x86: F2 can be a part of instruction encoding, but not a prefix by Nguyen Anh Quynh · 10 years ago
  86. 8c212fd ppc: add the missing Q0 register to reg_name_maps[]. bug reported by Coverity by Nguyen Anh Quynh · 10 years ago
  87. fcde1e1 Merge branch 'next' of https://github.com/aquynh/capstone into next by Nguyen Anh Quynh · 10 years ago
  88. 21b0bdd Fix indent issue by pancake · 10 years ago
  89. dae7c3e add ARM64_GRP_PRIVILEGE group and tag some instructions by pancake · 10 years ago
  90. cf74a14 add ARM_GRP_PRIVILEGE group and tag some instructions by pancake · 10 years ago
  91. 6791b26 arm: revert the last change on OperandInfo* in ARMGenInstrInfo.inc by Nguyen Anh Quynh · 10 years ago
  92. dfd1c0b arm: get rid of some useless variables in ARMGenInstrInfo.inc. this saves at lease 50KB by Nguyen Anh Quynh · 10 years ago
  93. a7837a4 sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus by Nguyen Anh Quynh · 10 years ago
  94. 037e01f core: remove unused Subregister indices for Sparc, PPC, SystemZ & Mips by Nguyen Anh Quynh · 10 years ago
  95. 914066b x86: CLI & STI are privileged instructions. issue reported by @pancake by Nguyen Anh Quynh · 10 years ago
  96. 0423562 x86: RDTSC is not a privilege instructions, but all VM instructions are by Nguyen Anh Quynh · 10 years ago
  97. 4dd0dcb add CS_GRP_PRIVILEGE group, and also add X86_GRP_PRIVILEGE group for bunch of X86 privileged instructions by Nguyen Anh Quynh · 10 years ago
  98. bb5dcce core: put insns[] into separate .inc files to make it easier to manage by Nguyen Anh Quynh · 10 years ago
  99. d3d574e x86: XCHG* do not implicitly access *AX registers (reduce mode) by Nguyen Anh Quynh · 10 years ago
  100. 8b8d762 x86: XCHG* do not implicitly access *AX registers by Nguyen Anh Quynh · 10 years ago