Update aosp/master clang for rebase to r230699.
Change-Id: I6a546ab3d4ae37119eebb735e102cca4f80ab520
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 0dbeb25..063a9be 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -25,7 +25,6 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
-#include "llvm/IR/Type.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
@@ -273,6 +272,12 @@
// On FreeBSD, wchar_t contains the number of the code point as
// used by the character set of the locale. These character sets are
// not necessarily a superset of ASCII.
+ //
+ // FIXME: This is wrong; the macro refers to the numerical values
+ // of wchar_t *literals*, which are not locale-dependent. However,
+ // FreeBSD systems apparently depend on us getting this wrong, and
+ // setting this to 1 is conforming even if all the basic source
+ // character literals have the same encoding as char and wchar_t.
Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
}
public:
@@ -519,6 +524,33 @@
}
};
+template <typename Target>
+class PS4OSTargetInfo : public OSTargetInfo<Target> {
+protected:
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__FreeBSD__", "9");
+ Builder.defineMacro("__FreeBSD_cc_version", "900001");
+ Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
+ DefineStd(Builder, "unix", Opts);
+ Builder.defineMacro("__ELF__");
+ Builder.defineMacro("__PS4__");
+ }
+public:
+ PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
+ this->WCharType = this->UnsignedShort;
+
+ this->UserLabelPrefix = "";
+
+ switch (Triple.getArch()) {
+ default:
+ case llvm::Triple::x86_64:
+ this->MCountName = ".mcount";
+ break;
+ }
+ }
+};
+
// Solaris target
template<typename Target>
class SolarisTargetInfo : public OSTargetInfo<Target> {
@@ -567,7 +599,7 @@
if (Opts.RTTIData)
Builder.defineMacro("_CPPRTTI");
- if (Opts.Exceptions)
+ if (Opts.CXXExceptions)
Builder.defineMacro("_CPPUNWIND");
}
@@ -653,11 +685,6 @@
this->DescriptionString = "e-p:32:32-i64:64";
}
}
- typename Target::CallingConvCheckResult checkCallingConvention(
- CallingConv CC) const override {
- return CC == CC_PnaclCall ? Target::CCCR_OK :
- Target::checkCallingConvention(CC);
- }
};
} // end anonymous namespace.
@@ -1133,9 +1160,6 @@
.Default(false);
Features["qpx"] = (CPU == "a2q");
-
- if (!ABI.empty())
- Features[ABI] = true;
}
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
@@ -1368,6 +1392,8 @@
1, // opencl_global
3, // opencl_local
4, // opencl_constant
+ // FIXME: generic has to be added to the target
+ 0, // opencl_generic
1, // cuda_device
4, // cuda_constant
3, // cuda_shared
@@ -1375,6 +1401,16 @@
class NVPTXTargetInfo : public TargetInfo {
static const char * const GCCRegNames[];
static const Builtin::Info BuiltinInfo[];
+
+ // The GPU profiles supported by the NVPTX backend
+ enum GPUKind {
+ GK_NONE,
+ GK_SM20,
+ GK_SM21,
+ GK_SM30,
+ GK_SM35,
+ } GPU;
+
public:
NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
BigEndian = false;
@@ -1385,11 +1421,34 @@
// Define available target features
// These must be defined in sorted order!
NoAsmVariants = true;
+ // Set the default GPU to sm20
+ GPU = GK_SM20;
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__PTX__");
Builder.defineMacro("__NVPTX__");
+ if (Opts.CUDAIsDevice) {
+ // Set __CUDA_ARCH__ for the GPU specified.
+ std::string CUDAArchCode;
+ switch (GPU) {
+ case GK_SM20:
+ CUDAArchCode = "200";
+ break;
+ case GK_SM21:
+ CUDAArchCode = "210";
+ break;
+ case GK_SM30:
+ CUDAArchCode = "300";
+ break;
+ case GK_SM35:
+ CUDAArchCode = "350";
+ break;
+ default:
+ llvm_unreachable("Unhandled target CPU");
+ }
+ Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
+ }
}
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
@@ -1432,14 +1491,14 @@
return TargetInfo::CharPtrBuiltinVaList;
}
bool setCPU(const std::string &Name) override {
- bool Valid = llvm::StringSwitch<bool>(Name)
- .Case("sm_20", true)
- .Case("sm_21", true)
- .Case("sm_30", true)
- .Case("sm_35", true)
- .Default(false);
+ GPU = llvm::StringSwitch<GPUKind>(Name)
+ .Case("sm_20", GK_SM20)
+ .Case("sm_21", GK_SM21)
+ .Case("sm_30", GK_SM30)
+ .Case("sm_35", GK_SM35)
+ .Default(GK_NONE);
- return Valid;
+ return GPU != GK_NONE;
}
};
@@ -1487,6 +1546,7 @@
1, // opencl_global
3, // opencl_local
2, // opencl_constant
+ 4, // opencl_generic
1, // cuda_device
2, // cuda_constant
3 // cuda_shared
@@ -1528,8 +1588,15 @@
public:
R600TargetInfo(const llvm::Triple &Triple)
- : TargetInfo(Triple), GPU(GK_R600) {
- DescriptionString = DescriptionStringR600;
+ : TargetInfo(Triple) {
+
+ if (Triple.getArch() == llvm::Triple::amdgcn) {
+ DescriptionString = DescriptionStringSI;
+ GPU = GK_SOUTHERN_ISLANDS;
+ } else {
+ DescriptionString = DescriptionStringR600;
+ GPU = GK_R600;
+ }
AddrSpaceMap = &R600AddrSpaceMap;
UseAddrSpaceMapMangling = true;
}
@@ -1799,28 +1866,42 @@
/// \name Atom
/// Atom processors
//@{
- CK_Atom,
+ CK_Bonnell,
CK_Silvermont,
//@}
/// \name Nehalem
/// Nehalem microarchitecture based processors.
- //@{
- CK_Corei7,
- CK_Corei7AVX,
- CK_CoreAVXi,
- CK_CoreAVX2,
+ CK_Nehalem,
+
+ /// \name Westmere
+ /// Westmere microarchitecture based processors.
+ CK_Westmere,
+
+ /// \name Sandy Bridge
+ /// Sandy Bridge microarchitecture based processors.
+ CK_SandyBridge,
+
+ /// \name Ivy Bridge
+ /// Ivy Bridge microarchitecture based processors.
+ CK_IvyBridge,
+
+ /// \name Haswell
+ /// Haswell microarchitecture based processors.
+ CK_Haswell,
+
+ /// \name Broadwell
+ /// Broadwell microarchitecture based processors.
CK_Broadwell,
- //@}
+
+ /// \name Skylake
+ /// Skylake microarchitecture based processors.
+ CK_Skylake,
/// \name Knights Landing
/// Knights Landing processor.
CK_KNL,
- /// \name Skylake Server
- /// Skylake server processor.
- CK_SKX,
-
/// \name K6
/// K6 architecture processors.
//@{
@@ -1990,15 +2071,23 @@
.Case("nocona", CK_Nocona)
.Case("core2", CK_Core2)
.Case("penryn", CK_Penryn)
- .Case("atom", CK_Atom)
- .Case("slm", CK_Silvermont)
- .Case("corei7", CK_Corei7)
- .Case("corei7-avx", CK_Corei7AVX)
- .Case("core-avx-i", CK_CoreAVXi)
- .Case("core-avx2", CK_CoreAVX2)
+ .Case("bonnell", CK_Bonnell)
+ .Case("atom", CK_Bonnell) // Legacy name.
+ .Case("silvermont", CK_Silvermont)
+ .Case("slm", CK_Silvermont) // Legacy name.
+ .Case("nehalem", CK_Nehalem)
+ .Case("corei7", CK_Nehalem) // Legacy name.
+ .Case("westmere", CK_Westmere)
+ .Case("sandybridge", CK_SandyBridge)
+ .Case("corei7-avx", CK_SandyBridge) // Legacy name.
+ .Case("ivybridge", CK_IvyBridge)
+ .Case("core-avx-i", CK_IvyBridge) // Legacy name.
+ .Case("haswell", CK_Haswell)
+ .Case("core-avx2", CK_Haswell) // Legacy name.
.Case("broadwell", CK_Broadwell)
+ .Case("skylake", CK_Skylake)
+ .Case("skx", CK_Skylake) // Legacy name.
.Case("knl", CK_KNL)
- .Case("skx", CK_SKX)
.Case("k6", CK_K6)
.Case("k6-2", CK_K6_2)
.Case("k6-3", CK_K6_3)
@@ -2014,6 +2103,7 @@
.Case("k8-sse3", CK_K8SSE3)
.Case("opteron", CK_Opteron)
.Case("opteron-sse3", CK_OpteronSSE3)
+ .Case("barcelona", CK_AMDFAM10)
.Case("amdfam10", CK_AMDFAM10)
.Case("btver1", CK_BTVER1)
.Case("btver2", CK_BTVER2)
@@ -2070,15 +2160,16 @@
case CK_Nocona:
case CK_Core2:
case CK_Penryn:
- case CK_Atom:
+ case CK_Bonnell:
case CK_Silvermont:
- case CK_Corei7:
- case CK_Corei7AVX:
- case CK_CoreAVXi:
- case CK_CoreAVX2:
+ case CK_Nehalem:
+ case CK_Westmere:
+ case CK_SandyBridge:
+ case CK_IvyBridge:
+ case CK_Haswell:
case CK_Broadwell:
+ case CK_Skylake:
case CK_KNL:
- case CK_SKX:
case CK_Athlon64:
case CK_Athlon64SSE3:
case CK_AthlonFX:
@@ -2169,7 +2260,7 @@
setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Core2:
- case CK_Atom:
+ case CK_Bonnell:
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
@@ -2177,7 +2268,7 @@
setFeatureEnabledImpl(Features, "sse4.1", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
- case CK_SKX:
+ case CK_Skylake:
setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true);
@@ -2188,7 +2279,7 @@
setFeatureEnabledImpl(Features, "rdseed", true);
setFeatureEnabledImpl(Features, "adx", true);
// FALLTHROUGH
- case CK_CoreAVX2:
+ case CK_Haswell:
setFeatureEnabledImpl(Features, "avx2", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "bmi", true);
@@ -2196,19 +2287,20 @@
setFeatureEnabledImpl(Features, "rtm", true);
setFeatureEnabledImpl(Features, "fma", true);
// FALLTHROUGH
- case CK_CoreAVXi:
+ case CK_IvyBridge:
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
// FALLTHROUGH
- case CK_Corei7AVX:
+ case CK_SandyBridge:
setFeatureEnabledImpl(Features, "avx", true);
// FALLTHROUGH
+ case CK_Westmere:
case CK_Silvermont:
setFeatureEnabledImpl(Features, "aes", true);
setFeatureEnabledImpl(Features, "pclmul", true);
// FALLTHROUGH
- case CK_Corei7:
+ case CK_Nehalem:
setFeatureEnabledImpl(Features, "sse4.2", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
@@ -2357,8 +2449,8 @@
Features["avx2"] = false;
case AVX512F:
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
- Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
- Features["avx512vl"] = false;
+ Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
+ Features["avx512vl"] = false;
}
}
@@ -2751,25 +2843,33 @@
case CK_Penryn:
defineCPUMacros(Builder, "core2");
break;
- case CK_Atom:
+ case CK_Bonnell:
defineCPUMacros(Builder, "atom");
break;
case CK_Silvermont:
defineCPUMacros(Builder, "slm");
break;
- case CK_Corei7:
- case CK_Corei7AVX:
- case CK_CoreAVXi:
- case CK_CoreAVX2:
+ case CK_Nehalem:
+ case CK_Westmere:
+ case CK_SandyBridge:
+ case CK_IvyBridge:
+ case CK_Haswell:
case CK_Broadwell:
+ // FIXME: Historically, we defined this legacy name, it would be nice to
+ // remove it at some point. We've never exposed fine-grained names for
+ // recent primary x86 CPUs, and we should keep it that way.
defineCPUMacros(Builder, "corei7");
break;
+ case CK_Skylake:
+ // FIXME: Historically, we defined this legacy name, it would be nice to
+ // remove it at some point. This is the only fine-grained CPU macro in the
+ // main intel CPU line, and it would be better to not have these and force
+ // people to use ISA macros.
+ defineCPUMacros(Builder, "skx");
+ break;
case CK_KNL:
defineCPUMacros(Builder, "knl");
break;
- case CK_SKX:
- defineCPUMacros(Builder, "skx");
- break;
case CK_K6_2:
Builder.defineMacro("__k6_2__");
Builder.defineMacro("__tune_k6_2__");
@@ -3033,6 +3133,28 @@
TargetInfo::ConstraintInfo &Info) const {
switch (*Name) {
default: return false;
+ case 'I':
+ Info.setRequiresImmediate(0, 31);
+ return true;
+ case 'J':
+ Info.setRequiresImmediate(0, 63);
+ return true;
+ case 'K':
+ Info.setRequiresImmediate(-128, 127);
+ return true;
+ case 'L':
+ // FIXME: properly analyze this constraint:
+ // must be one of 0xff, 0xffff, or 0xffffffff
+ return true;
+ case 'M':
+ Info.setRequiresImmediate(0, 3);
+ return true;
+ case 'N':
+ Info.setRequiresImmediate(0, 255);
+ return true;
+ case 'O':
+ Info.setRequiresImmediate(0, 127);
+ return true;
case 'Y': // first letter of a pair:
switch (*(Name+1)) {
default: return false;
@@ -3504,19 +3626,31 @@
IntPtrType = SignedLongLong;
this->UserLabelPrefix = "";
}
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
Builder.defineMacro("_WIN64");
}
+
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::CharPtrBuiltinVaList;
}
+
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
- return (CC == CC_C ||
- CC == CC_X86VectorCall ||
- CC == CC_IntelOclBicc ||
- CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
+ switch (CC) {
+ case CC_X86StdCall:
+ case CC_X86ThisCall:
+ case CC_X86FastCall:
+ return CCCR_Ignore;
+ case CC_C:
+ case CC_X86VectorCall:
+ case CC_IntelOclBicc:
+ case CC_X86_64SysV:
+ return CCCR_OK;
+ default:
+ return CCCR_Warning;
+ }
}
};
} // end anonymous namespace
@@ -3802,7 +3936,45 @@
// FIXME: Should we just treat this as a feature?
IsThumb = getTriple().getArchName().startswith("thumb");
- setABI("aapcs-linux");
+ // FIXME: This duplicates code from the driver that sets the -target-abi
+ // option - this code is used if -target-abi isn't passed and should
+ // be unified in some way.
+ if (Triple.isOSBinFormatMachO()) {
+ // The backend is hardwired to assume AAPCS for M-class processors, ensure
+ // the frontend matches that.
+ if (Triple.getEnvironment() == llvm::Triple::EABI ||
+ Triple.getOS() == llvm::Triple::UnknownOS ||
+ StringRef(CPU).startswith("cortex-m")) {
+ setABI("aapcs");
+ } else {
+ setABI("apcs-gnu");
+ }
+ } else if (Triple.isOSWindows()) {
+ // FIXME: this is invalid for WindowsCE
+ setABI("aapcs");
+ } else {
+ // Select the default based on the platform.
+ switch (Triple.getEnvironment()) {
+ case llvm::Triple::Android:
+ case llvm::Triple::GNUEABI:
+ case llvm::Triple::GNUEABIHF:
+ setABI("aapcs-linux");
+ break;
+ case llvm::Triple::EABIHF:
+ case llvm::Triple::EABI:
+ setABI("aapcs");
+ break;
+ case llvm::Triple::GNU:
+ setABI("apcs-gnu");
+ break;
+ default:
+ if (Triple.getOS() == llvm::Triple::NetBSD)
+ setABI("apcs-gnu");
+ else
+ setABI("aapcs");
+ break;
+ }
+ }
// ARM targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericARM);
@@ -3838,11 +4010,6 @@
}
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
- if (IsAAPCS)
- Features["aapcs"] = true;
- else
- Features["apcs"] = true;
-
StringRef ArchName = getTriple().getArchName();
if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
Features["vfp2"] = true;
@@ -3865,14 +4032,14 @@
Features["neon"] = true;
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
- } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
+ } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") {
Features["fp-armv8"] = true;
Features["neon"] = true;
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
Features["crc"] = true;
Features["crypto"] = true;
- } else if (CPU == "cortex-r5" ||
+ } else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
// Enable the hwdiv extension for all v8a AArch32 cores by
// default.
ArchName == "armv8a" || ArchName == "armv8" ||
@@ -3881,7 +4048,8 @@
ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
- } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
+ } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
+ CPU == "sc300") {
Features["hwdiv"] = true;
}
}
@@ -3981,13 +4149,13 @@
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
"7A")
- .Cases("cortex-r4", "cortex-r5", "7R")
+ .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R")
.Case("swift", "7S")
.Case("cyclone", "8A")
- .Case("cortex-m3", "7M")
+ .Cases("sc300", "cortex-m3", "7M")
.Cases("cortex-m4", "cortex-m7", "7EM")
- .Case("cortex-m0", "6M")
- .Cases("cortex-a53", "cortex-a57", "8A")
+ .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
+ .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
.Default(nullptr);
}
static const char *getCPUProfile(StringRef Name) {
@@ -3995,9 +4163,10 @@
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
"A")
- .Cases("cortex-a53", "cortex-a57", "A")
- .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
- .Cases("cortex-r4", "cortex-r5", "R")
+ .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A")
+ .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M")
+ .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M")
+ .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R")
.Default("");
}
bool setCPU(const std::string &Name) override {
@@ -4158,6 +4327,13 @@
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
+
+ bool is5EOrAbove = (CPUArchVer >= 6 ||
+ (CPUArchVer == 5 &&
+ CPUArch.find('E') != StringRef::npos));
+ bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
+ if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM"))
+ Builder.defineMacro("__ARM_FEATURE_DSP");
}
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
@@ -4182,6 +4358,13 @@
case 'P': // VFP Floating point register double precision
Info.setAllowsRegister();
return true;
+ case 'I':
+ case 'J':
+ case 'K':
+ case 'L':
+ case 'M':
+ // FIXME
+ return true;
case 'Q': // A memory address that is a single base register.
Info.setAllowsMemory();
return true;
@@ -4501,13 +4684,20 @@
MaxAtomicInlineWidth = 128;
MaxAtomicPromoteWidth = 128;
- LongDoubleWidth = LongDoubleAlign = 128;
+ LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad;
// {} in inline assembly are neon specifiers, not assembly variant
// specifiers.
NoAsmVariants = true;
+ // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
+ // contributes to the alignment of the containing aggregate in the same way
+ // a plain (non bit-field) member of that type would, without exception for
+ // zero-sized or anonymous bit-fields."
+ UseBitFieldTypeAlignment = true;
+ UseZeroLengthBitfieldAlignment = true;
+
// AArch64 targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
@@ -4524,7 +4714,7 @@
bool setCPU(const std::string &Name) override {
bool CPUKnown = llvm::StringSwitch<bool>(Name)
.Case("generic", true)
- .Cases("cortex-a53", "cortex-a57", true)
+ .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
.Case("cyclone", true)
.Default(false);
return CPUKnown;
@@ -4834,7 +5024,7 @@
WCharType = SignedInt;
UseSignedCharForObjCBool = false;
- LongDoubleWidth = LongDoubleAlign = 64;
+ LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
TheCXXABI.set(TargetCXXABI::iOS64);
@@ -5045,6 +5235,16 @@
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override {
// FIXME: Implement!
+ switch (*Name) {
+ case 'I': // Signed 13-bit constant
+ case 'J': // Zero
+ case 'K': // 32-bit constant with the low 12 bits clear
+ case 'L': // A constant in the range supported by movcc (11-bit signed imm)
+ case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
+ case 'N': // Same as 'K' but zext (required for SIMode)
+ case 'O': // The constant 4096
+ return true;
+ }
return false;
}
const char *getClobbers() const override {
@@ -5337,6 +5537,13 @@
bool
validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override {
+ // FIXME: implement
+ switch (*Name) {
+ case 'K': // the constant 1
+ case 'L': // constant -1^20 .. 1^19
+ case 'M': // constant 1-4:
+ return true;
+ }
// No target constraints for now.
return false;
}
@@ -5376,6 +5583,8 @@
3, // opencl_global
4, // opencl_local
5, // opencl_constant
+ // FIXME: generic has to be added to the target
+ 0, // opencl_generic
0, // cuda_device
0, // cuda_constant
0 // cuda_shared
@@ -5467,7 +5676,9 @@
const std::string &CPUStr)
: TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
- DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
+ DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
+ TheCXXABI.set(TargetCXXABI::GenericMIPS);
+ }
bool isNaN2008Default() const {
return CPU == "mips32r6" || CPU == "mips64r6";
@@ -5477,6 +5688,10 @@
return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
}
+ bool isNan2008() const override {
+ return IsNan2008;
+ }
+
StringRef getABI() const override { return ABI; }
bool setCPU(const std::string &Name) override {
bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
@@ -5490,23 +5705,19 @@
.Case("mips5", true)
.Case("mips32", IsMips32)
.Case("mips32r2", IsMips32)
+ .Case("mips32r3", IsMips32)
+ .Case("mips32r5", IsMips32)
.Case("mips32r6", IsMips32)
.Case("mips64", true)
.Case("mips64r2", true)
+ .Case("mips64r3", true)
+ .Case("mips64r5", true)
.Case("mips64r6", true)
.Case("octeon", true)
.Default(false);
}
const std::string& getCPU() const { return CPU; }
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
- // The backend enables certain ABI's by default according to the
- // architecture.
- // Disable both possible defaults so that we don't end up with multiple
- // ABI's selected and trigger an assertion.
- Features["o32"] = false;
- Features["n64"] = false;
-
- Features[ABI] = true;
if (CPU == "octeon")
Features["mips64r2"] = Features["cnmips"] = true;
else
@@ -5631,6 +5842,15 @@
case 'x': // hilo register pair
Info.setAllowsRegister();
return true;
+ case 'I': // Signed 16-bit constant
+ case 'J': // Integer 0
+ case 'K': // Unsigned 16-bit constant
+ case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
+ case 'M': // Constants not loadable via lui, addiu, or ori
+ case 'N': // Constant -1 to -65535
+ case 'O': // A signed 15-bit constant
+ case 'P': // A constant between 1 go 65535
+ return true;
case 'R': // An address that can be used in a non-macro load or store
Info.setAllowsMemory();
return true;
@@ -5638,8 +5858,28 @@
}
const char *getClobbers() const override {
- // FIXME: Implement!
- return "";
+ // In GCC, $1 is not widely used in generated code (it's used only in a few
+ // specific situations), so there is no real need for users to add it to
+ // the clobbers list if they want to use it in their inline assembly code.
+ //
+ // In LLVM, $1 is treated as a normal GPR and is always allocatable during
+ // code generation, so using it in inline assembly without adding it to the
+ // clobbers list can cause conflicts between the inline assembly code and
+ // the surrounding generated code.
+ //
+ // Another problem is that LLVM is allowed to choose $1 for inline assembly
+ // operands, which will conflict with the ".set at" assembler option (which
+ // we use only for inline assembly, in order to maintain compatibility with
+ // GCC) and will also conflict with the user's usage of $1.
+ //
+ // The easiest way to avoid these conflicts and keep $1 as an allocatable
+ // register for generated code is to automatically clobber $1 for all inline
+ // assembly code.
+ //
+ // FIXME: We should automatically clobber $1 only for inline assembly code
+ // which actually uses it. This would allow LLVM to use $1 for inline
+ // assembly operands if the user's assembly code doesn't use it.
+ return "~{$1}";
}
bool handleTargetFeatures(std::vector<std::string> &Features,
@@ -5711,6 +5951,8 @@
: MipsTargetInfoBase(Triple, "o32", "mips32r2") {
SizeType = UnsignedInt;
PtrDiffType = SignedInt;
+ Int64Type = SignedLongLong;
+ IntMaxType = Int64Type;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
}
bool setABI(const std::string &Name) override {
@@ -5732,6 +5974,12 @@
Builder.defineMacro("__mips_isa_rev", "1");
else if (CPUStr == "mips32r2")
Builder.defineMacro("__mips_isa_rev", "2");
+ else if (CPUStr == "mips32r3")
+ Builder.defineMacro("__mips_isa_rev", "3");
+ else if (CPUStr == "mips32r5")
+ Builder.defineMacro("__mips_isa_rev", "5");
+ else if (CPUStr == "mips32r6")
+ Builder.defineMacro("__mips_isa_rev", "6");
if (ABI == "o32") {
Builder.defineMacro("__mips_o32");
@@ -5838,6 +6086,8 @@
PointerWidth = PointerAlign = 64;
SizeType = UnsignedLong;
PtrDiffType = SignedLong;
+ Int64Type = SignedLong;
+ IntMaxType = Int64Type;
}
void setN32ABITypes() {
@@ -5845,6 +6095,8 @@
PointerWidth = PointerAlign = 32;
SizeType = UnsignedInt;
PtrDiffType = SignedInt;
+ Int64Type = SignedLongLong;
+ IntMaxType = Int64Type;
}
bool setABI(const std::string &Name) override {
@@ -5875,6 +6127,12 @@
Builder.defineMacro("__mips_isa_rev", "1");
else if (CPUStr == "mips64r2")
Builder.defineMacro("__mips_isa_rev", "2");
+ else if (CPUStr == "mips64r3")
+ Builder.defineMacro("__mips_isa_rev", "3");
+ else if (CPUStr == "mips64r5")
+ Builder.defineMacro("__mips_isa_rev", "5");
+ else if (CPUStr == "mips64r6")
+ Builder.defineMacro("__mips_isa_rev", "6");
if (ABI == "n32") {
Builder.defineMacro("__mips_n32");
@@ -6051,7 +6309,7 @@
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
DescriptionString =
- "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64";
+ "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
}
void getTargetDefines(const LangOptions &Opts,
@@ -6099,6 +6357,7 @@
1, // opencl_global
3, // opencl_local
2, // opencl_constant
+ 4, // opencl_generic
0, // cuda_device
0, // cuda_constant
0 // cuda_shared
@@ -6144,6 +6403,15 @@
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::VoidPtrBuiltinVaList;
}
+
+ CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
+ return (CC == CC_SpirFunction ||
+ CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
+ }
+
+ CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
+ return CC_SpirFunction;
+ }
};
@@ -6470,6 +6738,7 @@
case llvm::Triple::nvptx64:
return new NVPTX64TargetInfo(Triple);
+ case llvm::Triple::amdgcn:
case llvm::Triple::r600:
return new R600TargetInfo(Triple);
@@ -6595,6 +6864,8 @@
}
case llvm::Triple::NaCl:
return new NaClTargetInfo<X86_64TargetInfo>(Triple);
+ case llvm::Triple::PS4:
+ return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
default:
return new X86_64TargetInfo(Triple);
}