Update aosp/master Clang for rebase to r222490.
Change-Id: Ic557ac55e97fbf6ee08771c7b7c3594777b0aefd
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index c88fed1..0dbeb25 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -21,6 +21,7 @@
#include "clang/Basic/TargetOptions.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
@@ -93,7 +94,8 @@
Builder.defineMacro("OBJC_NEW_PROPERTIES");
// AddressSanitizer doesn't play well with source fortification, which is on
// by default on Darwin.
- if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
+ if (Opts.Sanitize.has(SanitizerKind::Address))
+ Builder.defineMacro("_FORTIFY_SOURCE", "0");
if (!Opts.ObjCAutoRefCount) {
// __weak is always defined, for use in blocks and with objc pointers.
@@ -155,12 +157,23 @@
// revision numbers). So, we limit them to the maximum representable
// version.
assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
- char Str[5];
- Str[0] = '0' + (Maj / 10);
- Str[1] = '0' + (Maj % 10);
- Str[2] = '0' + std::min(Min, 9U);
- Str[3] = '0' + std::min(Rev, 9U);
- Str[4] = '\0';
+ char Str[7];
+ if (Maj < 10 || (Maj == 10 && Min < 10)) {
+ Str[0] = '0' + (Maj / 10);
+ Str[1] = '0' + (Maj % 10);
+ Str[2] = '0' + std::min(Min, 9U);
+ Str[3] = '0' + std::min(Rev, 9U);
+ Str[4] = '\0';
+ } else {
+ // Handle versions > 10.9.
+ Str[0] = '0' + (Maj / 10);
+ Str[1] = '0' + (Maj % 10);
+ Str[2] = '0' + (Min / 10);
+ Str[3] = '0' + (Min % 10);
+ Str[4] = '0' + (Rev / 10);
+ Str[5] = '0' + (Rev % 10);
+ Str[6] = '\0';
+ }
Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
}
@@ -304,7 +317,8 @@
Builder.defineMacro("_GNU_SOURCE");
}
public:
- KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
+ KFreeBSDTargetInfo(const llvm::Triple &Triple)
+ : OSTargetInfo<Target>(Triple) {
this->UserLabelPrefix = "";
}
};
@@ -499,34 +513,12 @@
this->LongWidth = this->LongAlign = 32;
this->PointerWidth = this->PointerAlign = 32;
this->IntMaxType = TargetInfo::SignedLongLong;
- this->UIntMaxType = TargetInfo::UnsignedLongLong;
this->Int64Type = TargetInfo::SignedLongLong;
this->SizeType = TargetInfo::UnsignedInt;
this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
}
};
-// AuroraUX target
-template<typename Target>
-class AuroraUXTargetInfo : public OSTargetInfo<Target> {
-protected:
- void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
- MacroBuilder &Builder) const override {
- DefineStd(Builder, "sun", Opts);
- DefineStd(Builder, "unix", Opts);
- Builder.defineMacro("__ELF__");
- Builder.defineMacro("__svr4__");
- Builder.defineMacro("__SVR4");
- }
-public:
- AuroraUXTargetInfo(const llvm::Triple &Triple)
- : OSTargetInfo<Target>(Triple) {
- this->UserLabelPrefix = "";
- this->WCharType = this->SignedLong;
- // FIXME: WIntType should be SignedLong
- }
-};
-
// Solaris target
template<typename Target>
class SolarisTargetInfo : public OSTargetInfo<Target> {
@@ -541,8 +533,8 @@
// Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
// newer, but to 500 for everything else. feature_test.h has a check to
// ensure that you are not using C99 with an old version of X/Open or C89
- // with a new version.
- if (Opts.C99 || Opts.C11)
+ // with a new version.
+ if (Opts.C99)
Builder.defineMacro("_XOPEN_SOURCE", "600");
else
Builder.defineMacro("_XOPEN_SOURCE", "500");
@@ -587,9 +579,10 @@
if (Opts.POSIXThreads)
Builder.defineMacro("_MT");
- if (Opts.MSCVersion != 0) {
- Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion / 100000));
- Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCVersion));
+ if (Opts.MSCompatibilityVersion) {
+ Builder.defineMacro("_MSC_VER",
+ Twine(Opts.MSCompatibilityVersion / 100000));
+ Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
// FIXME We cannot encode the revision information into 32-bits
Builder.defineMacro("_MSC_BUILD", Twine(1));
}
@@ -635,7 +628,6 @@
this->PointerAlign = 32;
this->PointerWidth = 32;
this->IntMaxType = TargetInfo::SignedLongLong;
- this->UIntMaxType = TargetInfo::UnsignedLongLong;
this->Int64Type = TargetInfo::SignedLongLong;
this->DoubleAlign = 64;
this->LongDoubleWidth = 64;
@@ -648,7 +640,8 @@
// RegParmMax is inherited from the underlying architecture
this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
if (Triple.getArch() == llvm::Triple::arm) {
- this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128";
+ this->DescriptionString =
+ "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
} else if (Triple.getArch() == llvm::Triple::x86) {
this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
} else if (Triple.getArch() == llvm::Triple::x86_64) {
@@ -682,10 +675,14 @@
// Target cpu features.
bool HasVSX;
+ bool HasP8Vector;
+
+protected:
+ std::string ABI;
public:
PPCTargetInfo(const llvm::Triple &Triple)
- : TargetInfo(Triple), HasVSX(false) {
+ : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
@@ -771,6 +768,9 @@
return CPUKnown;
}
+
+ StringRef getABI() const override { return ABI; }
+
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
Records = BuiltinInfo;
@@ -922,11 +922,10 @@
#include "clang/Basic/BuiltinsPPC.def"
};
- /// handleTargetFeatures - Perform initialization based on the user
+/// handleTargetFeatures - Perform initialization based on the user
/// configured set of features.
bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) {
- // Remember the maximum enabled sselevel.
for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
// Ignore disabled features.
if (Features[i][0] == '-')
@@ -939,6 +938,11 @@
continue;
}
+ if (Feature == "power8-vector") {
+ HasP8Vector = true;
+ continue;
+ }
+
// TODO: Finish this list and add an assert that we've handled them
// all.
}
@@ -966,13 +970,18 @@
// Target properties.
if (getTriple().getArch() == llvm::Triple::ppc64le) {
Builder.defineMacro("_LITTLE_ENDIAN");
- Builder.defineMacro("_CALL_ELF","2");
} else {
if (getTriple().getOS() != llvm::Triple::NetBSD &&
getTriple().getOS() != llvm::Triple::OpenBSD)
Builder.defineMacro("_BIG_ENDIAN");
}
+ // ABI options.
+ if (ABI == "elfv1")
+ Builder.defineMacro("_CALL_ELF", "1");
+ if (ABI == "elfv2")
+ Builder.defineMacro("_CALL_ELF", "2");
+
// Subtarget options.
Builder.defineMacro("__NATURAL_ALIGNMENT__");
Builder.defineMacro("__REGISTER_PREFIX__", "");
@@ -1084,6 +1093,8 @@
if (HasVSX)
Builder.defineMacro("__VSX__");
+ if (HasP8Vector)
+ Builder.defineMacro("__POWER8_VECTOR__");
// FIXME: The following are not yet generated here by Clang, but are
// generated by GCC:
@@ -1122,13 +1133,19 @@
.Default(false);
Features["qpx"] = (CPU == "a2q");
+
+ if (!ABI.empty())
+ Features[ABI] = true;
}
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
- return Feature == "powerpc";
+ return llvm::StringSwitch<bool>(Feature)
+ .Case("powerpc", true)
+ .Case("vsx", HasVSX)
+ .Case("power8-vector", HasP8Vector)
+ .Default(false);
}
-
const char * const PPCTargetInfo::GCCRegNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
@@ -1275,20 +1292,28 @@
PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
Int64Type = SignedLong;
- if (getTriple().getOS() == llvm::Triple::FreeBSD) {
+ if ((Triple.getArch() == llvm::Triple::ppc64le)) {
+ DescriptionString = "e-m:e-i64:64-n32:64";
+ ABI = "elfv2";
+ } else {
+ DescriptionString = "E-m:e-i64:64-n32:64";
+ ABI = "elfv1";
+ }
+
+ switch (getTriple().getOS()) {
+ case llvm::Triple::FreeBSD:
LongDoubleWidth = LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
- DescriptionString = "E-m:e-i64:64-n32:64";
- } else {
- if ((Triple.getArch() == llvm::Triple::ppc64le)) {
- DescriptionString = "e-m:e-i64:64-n32:64";
- } else {
- DescriptionString = "E-m:e-i64:64-n32:64";
- }
-}
+ break;
+ case llvm::Triple::NetBSD:
+ IntMaxType = SignedLongLong;
+ Int64Type = SignedLongLong;
+ break;
+ default:
+ break;
+ }
// PPC64 supports atomics up to 8 bytes.
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
@@ -1296,6 +1321,14 @@
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::CharPtrBuiltinVaList;
}
+ // PPC64 Linux-specifc ABI options.
+ bool setABI(const std::string &Name) override {
+ if (Name == "elfv1" || Name == "elfv2") {
+ ABI = Name;
+ return true;
+ }
+ return false;
+ }
};
} // end anonymous namespace.
@@ -1308,7 +1341,7 @@
: DarwinTargetInfo<PPC32TargetInfo>(Triple) {
HasAlignMac68kSupport = true;
BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
- PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
+ PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
LongLongAlign = 32;
SuitableAlign = 128;
DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
@@ -1375,8 +1408,9 @@
Aliases = nullptr;
NumAliases = 0;
}
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
+ bool
+ validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) {
default: return false;
case 'c':
@@ -1430,7 +1464,8 @@
public:
NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
PointerWidth = PointerAlign = 32;
- SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
+ SizeType = PtrDiffType = TargetInfo::UnsignedInt;
+ IntPtrType = TargetInfo::SignedInt;
DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
}
};
@@ -1439,7 +1474,8 @@
public:
NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
PointerWidth = PointerAlign = 64;
- SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
+ SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
+ IntPtrType = TargetInfo::SignedLongLong;
DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
}
};
@@ -1456,6 +1492,9 @@
3 // cuda_shared
};
+// If you edit the description strings, make sure you update
+// getPointerWidthV().
+
static const char *DescriptionStringR600 =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
@@ -1495,6 +1534,20 @@
UseAddrSpaceMapMangling = true;
}
+ uint64_t getPointerWidthV(unsigned AddrSpace) const override {
+ if (GPU <= GK_CAYMAN)
+ return 32;
+
+ switch(AddrSpace) {
+ default:
+ return 64;
+ case 0:
+ case 3:
+ case 5:
+ return 32;
+ }
+ }
+
const char * getClobbers() const override {
return "";
}
@@ -1562,10 +1615,12 @@
.Case("pitcairn", GK_SOUTHERN_ISLANDS)
.Case("verde", GK_SOUTHERN_ISLANDS)
.Case("oland", GK_SOUTHERN_ISLANDS)
+ .Case("hainan", GK_SOUTHERN_ISLANDS)
.Case("bonaire", GK_SEA_ISLANDS)
.Case("kabini", GK_SEA_ISLANDS)
.Case("kaveri", GK_SEA_ISLANDS)
.Case("hawaii", GK_SEA_ISLANDS)
+ .Case("mullins", GK_SEA_ISLANDS)
.Default(GK_NONE);
if (GPU == GK_NONE) {
@@ -1657,16 +1712,19 @@
bool HasPCLMUL;
bool HasLZCNT;
bool HasRDRND;
+ bool HasFSGSBASE;
bool HasBMI;
bool HasBMI2;
bool HasPOPCNT;
bool HasRTM;
bool HasPRFCHW;
bool HasRDSEED;
+ bool HasADX;
bool HasTBM;
bool HasFMA;
bool HasF16C;
- bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
+ bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
+ HasAVX512VL;
bool HasSHA;
bool HasCX16;
@@ -1752,12 +1810,17 @@
CK_Corei7AVX,
CK_CoreAVXi,
CK_CoreAVX2,
+ CK_Broadwell,
//@}
/// \name Knights Landing
/// Knights Landing processor.
CK_KNL,
+ /// \name Skylake Server
+ /// Skylake server processor.
+ CK_SKX,
+
/// \name K6
/// K6 architecture processors.
//@{
@@ -1808,6 +1871,7 @@
/// This specification is deprecated and will be removed in the future.
/// Users should prefer \see CK_K8.
// FIXME: Warn on this when the CPU is set to it.
+ //@{
CK_x86_64,
//@}
@@ -1828,11 +1892,12 @@
X86TargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
- HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
- HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
- HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
- HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
- FPMath(FP_Default) {
+ HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
+ HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
+ HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
+ HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
+ HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
+ HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
BigEndian = false;
LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
}
@@ -1861,7 +1926,14 @@
NumNames = llvm::array_lengthof(AddlRegNames);
}
bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const override;
+ TargetInfo::ConstraintInfo &info) const override;
+
+ bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
+
+ bool validateInputSize(StringRef Constraint, unsigned Size) const override;
+
+ virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
+
std::string convertConstraint(const char *&Constraint) const override;
const char *getClobbers() const override {
return "~{dirflag},~{fpsr},~{flags}";
@@ -1924,7 +1996,9 @@
.Case("corei7-avx", CK_Corei7AVX)
.Case("core-avx-i", CK_CoreAVXi)
.Case("core-avx2", CK_CoreAVX2)
+ .Case("broadwell", CK_Broadwell)
.Case("knl", CK_KNL)
+ .Case("skx", CK_SKX)
.Case("k6", CK_K6)
.Case("k6-2", CK_K6_2)
.Case("k6-3", CK_K6_3)
@@ -2002,7 +2076,9 @@
case CK_Corei7AVX:
case CK_CoreAVXi:
case CK_CoreAVX2:
+ case CK_Broadwell:
case CK_KNL:
+ case CK_SKX:
case CK_Athlon64:
case CK_Athlon64SSE3:
case CK_AthlonFX:
@@ -2029,8 +2105,9 @@
// We accept all non-ARM calling conventions
return (CC == CC_X86ThisCall ||
CC == CC_X86FastCall ||
- CC == CC_X86StdCall ||
- CC == CC_C ||
+ CC == CC_X86StdCall ||
+ CC == CC_X86VectorCall ||
+ CC == CC_C ||
CC == CC_X86Pascal ||
CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
}
@@ -2070,10 +2147,13 @@
break;
case CK_PentiumMMX:
case CK_Pentium2:
+ case CK_K6:
+ case CK_WinChipC6:
setFeatureEnabledImpl(Features, "mmx", true);
break;
case CK_Pentium3:
case CK_Pentium3M:
+ case CK_C3_2:
setFeatureEnabledImpl(Features, "sse", true);
break;
case CK_PentiumM:
@@ -2089,6 +2169,7 @@
setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Core2:
+ case CK_Atom:
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
@@ -2096,44 +2177,39 @@
setFeatureEnabledImpl(Features, "sse4.1", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
- case CK_Atom:
- setFeatureEnabledImpl(Features, "ssse3", true);
- setFeatureEnabledImpl(Features, "cx16", true);
- break;
- case CK_Silvermont:
- setFeatureEnabledImpl(Features, "sse4.2", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "cx16", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
- break;
- case CK_Corei7:
- setFeatureEnabledImpl(Features, "sse4.2", true);
- setFeatureEnabledImpl(Features, "cx16", true);
- break;
- case CK_Corei7AVX:
- setFeatureEnabledImpl(Features, "avx", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "cx16", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
- break;
- case CK_CoreAVXi:
- setFeatureEnabledImpl(Features, "avx", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
- setFeatureEnabledImpl(Features, "rdrnd", true);
- setFeatureEnabledImpl(Features, "f16c", true);
- break;
+ case CK_SKX:
+ setFeatureEnabledImpl(Features, "avx512f", true);
+ setFeatureEnabledImpl(Features, "avx512cd", true);
+ setFeatureEnabledImpl(Features, "avx512dq", true);
+ setFeatureEnabledImpl(Features, "avx512bw", true);
+ setFeatureEnabledImpl(Features, "avx512vl", true);
+ // FALLTHROUGH
+ case CK_Broadwell:
+ setFeatureEnabledImpl(Features, "rdseed", true);
+ setFeatureEnabledImpl(Features, "adx", true);
+ // FALLTHROUGH
case CK_CoreAVX2:
setFeatureEnabledImpl(Features, "avx2", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
- setFeatureEnabledImpl(Features, "rdrnd", true);
- setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
setFeatureEnabledImpl(Features, "fma", true);
+ // FALLTHROUGH
+ case CK_CoreAVXi:
+ setFeatureEnabledImpl(Features, "rdrnd", true);
+ setFeatureEnabledImpl(Features, "f16c", true);
+ setFeatureEnabledImpl(Features, "fsgsbase", true);
+ // FALLTHROUGH
+ case CK_Corei7AVX:
+ setFeatureEnabledImpl(Features, "avx", true);
+ // FALLTHROUGH
+ case CK_Silvermont:
+ setFeatureEnabledImpl(Features, "aes", true);
+ setFeatureEnabledImpl(Features, "pclmul", true);
+ // FALLTHROUGH
+ case CK_Corei7:
+ setFeatureEnabledImpl(Features, "sse4.2", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_KNL:
@@ -2141,19 +2217,19 @@
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512er", true);
setFeatureEnabledImpl(Features, "avx512pf", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
+ setFeatureEnabledImpl(Features, "rdseed", true);
+ setFeatureEnabledImpl(Features, "adx", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
- setFeatureEnabledImpl(Features, "rdrnd", true);
- setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
setFeatureEnabledImpl(Features, "fma", true);
- break;
- case CK_K6:
- case CK_WinChipC6:
- setFeatureEnabledImpl(Features, "mmx", true);
+ setFeatureEnabledImpl(Features, "rdrnd", true);
+ setFeatureEnabledImpl(Features, "f16c", true);
+ setFeatureEnabledImpl(Features, "fsgsbase", true);
+ setFeatureEnabledImpl(Features, "aes", true);
+ setFeatureEnabledImpl(Features, "pclmul", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_K6_2:
case CK_K6_3:
@@ -2179,66 +2255,54 @@
setFeatureEnabledImpl(Features, "sse2", true);
setFeatureEnabledImpl(Features, "3dnowa", true);
break;
+ case CK_AMDFAM10:
+ setFeatureEnabledImpl(Features, "sse4a", true);
+ setFeatureEnabledImpl(Features, "lzcnt", true);
+ setFeatureEnabledImpl(Features, "popcnt", true);
+ // FALLTHROUGH
case CK_K8SSE3:
case CK_OpteronSSE3:
case CK_Athlon64SSE3:
setFeatureEnabledImpl(Features, "sse3", true);
setFeatureEnabledImpl(Features, "3dnowa", true);
break;
- case CK_AMDFAM10:
- setFeatureEnabledImpl(Features, "sse3", true);
- setFeatureEnabledImpl(Features, "sse4a", true);
- setFeatureEnabledImpl(Features, "3dnowa", true);
- setFeatureEnabledImpl(Features, "lzcnt", true);
- setFeatureEnabledImpl(Features, "popcnt", true);
- break;
+ case CK_BTVER2:
+ setFeatureEnabledImpl(Features, "avx", true);
+ setFeatureEnabledImpl(Features, "aes", true);
+ setFeatureEnabledImpl(Features, "pclmul", true);
+ setFeatureEnabledImpl(Features, "bmi", true);
+ setFeatureEnabledImpl(Features, "f16c", true);
+ // FALLTHROUGH
case CK_BTVER1:
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "sse4a", true);
- setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "popcnt", true);
setFeatureEnabledImpl(Features, "prfchw", true);
- break;
- case CK_BTVER2:
- setFeatureEnabledImpl(Features, "avx", true);
- setFeatureEnabledImpl(Features, "sse4a", true);
- setFeatureEnabledImpl(Features, "lzcnt", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
- setFeatureEnabledImpl(Features, "prfchw", true);
- setFeatureEnabledImpl(Features, "bmi", true);
- setFeatureEnabledImpl(Features, "f16c", true);
- setFeatureEnabledImpl(Features, "cx16", true);
- break;
- case CK_BDVER1:
- setFeatureEnabledImpl(Features, "xop", true);
- setFeatureEnabledImpl(Features, "lzcnt", true);
- setFeatureEnabledImpl(Features, "aes", true);
- setFeatureEnabledImpl(Features, "pclmul", true);
- setFeatureEnabledImpl(Features, "prfchw", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_BDVER4:
setFeatureEnabledImpl(Features, "avx2", true);
setFeatureEnabledImpl(Features, "bmi2", true);
// FALLTHROUGH
- case CK_BDVER2:
case CK_BDVER3:
+ setFeatureEnabledImpl(Features, "fsgsbase", true);
+ // FALLTHROUGH
+ case CK_BDVER2:
+ setFeatureEnabledImpl(Features, "bmi", true);
+ setFeatureEnabledImpl(Features, "fma", true);
+ setFeatureEnabledImpl(Features, "f16c", true);
+ setFeatureEnabledImpl(Features, "tbm", true);
+ // FALLTHROUGH
+ case CK_BDVER1:
+ // xop implies avx, sse4a and fma4.
setFeatureEnabledImpl(Features, "xop", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "aes", true);
setFeatureEnabledImpl(Features, "pclmul", true);
setFeatureEnabledImpl(Features, "prfchw", true);
- setFeatureEnabledImpl(Features, "bmi", true);
- setFeatureEnabledImpl(Features, "fma", true);
- setFeatureEnabledImpl(Features, "f16c", true);
- setFeatureEnabledImpl(Features, "tbm", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
- case CK_C3_2:
- setFeatureEnabledImpl(Features, "sse", true);
- break;
}
}
@@ -2293,7 +2357,8 @@
Features["avx2"] = false;
case AVX512F:
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
- Features["avx512pf"] = false;
+ Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
+ Features["avx512vl"] = false;
}
}
@@ -2392,7 +2457,8 @@
setSSELevel(Features, AVX2, Enabled);
} else if (Name == "avx512f") {
setSSELevel(Features, AVX512F, Enabled);
- } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
+ } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
+ || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
if (Enabled)
setSSELevel(Features, AVX512F, Enabled);
} else if (Name == "fma") {
@@ -2445,6 +2511,11 @@
continue;
}
+ if (Feature == "fsgsbase") {
+ HasFSGSBASE = true;
+ continue;
+ }
+
if (Feature == "bmi") {
HasBMI = true;
continue;
@@ -2475,6 +2546,11 @@
continue;
}
+ if (Feature == "adx") {
+ HasADX = true;
+ continue;
+ }
+
if (Feature == "tbm") {
HasTBM = true;
continue;
@@ -2505,6 +2581,21 @@
continue;
}
+ if (Feature == "avx512dq") {
+ HasAVX512DQ = true;
+ continue;
+ }
+
+ if (Feature == "avx512bw") {
+ HasAVX512BW = true;
+ continue;
+ }
+
+ if (Feature == "avx512vl") {
+ HasAVX512VL = true;
+ continue;
+ }
+
if (Feature == "sha") {
HasSHA = true;
continue;
@@ -2594,6 +2685,10 @@
Builder.defineMacro("__amd64");
Builder.defineMacro("__x86_64");
Builder.defineMacro("__x86_64__");
+ if (getTriple().getArchName() == "x86_64h") {
+ Builder.defineMacro("__x86_64h");
+ Builder.defineMacro("__x86_64h__");
+ }
} else {
DefineStd(Builder, "i386", Opts);
}
@@ -2666,11 +2761,15 @@
case CK_Corei7AVX:
case CK_CoreAVXi:
case CK_CoreAVX2:
+ case CK_Broadwell:
defineCPUMacros(Builder, "corei7");
break;
case CK_KNL:
defineCPUMacros(Builder, "knl");
break;
+ case CK_SKX:
+ defineCPUMacros(Builder, "skx");
+ break;
case CK_K6_2:
Builder.defineMacro("__k6_2__");
Builder.defineMacro("__tune_k6_2__");
@@ -2754,6 +2853,9 @@
if (HasRDRND)
Builder.defineMacro("__RDRND__");
+ if (HasFSGSBASE)
+ Builder.defineMacro("__FSGSBASE__");
+
if (HasBMI)
Builder.defineMacro("__BMI__");
@@ -2772,6 +2874,9 @@
if (HasRDSEED)
Builder.defineMacro("__RDSEED__");
+ if (HasADX)
+ Builder.defineMacro("__ADX__");
+
if (HasTBM)
Builder.defineMacro("__TBM__");
@@ -2798,6 +2903,12 @@
Builder.defineMacro("__AVX512ER__");
if (HasAVX512PF)
Builder.defineMacro("__AVX512PF__");
+ if (HasAVX512DQ)
+ Builder.defineMacro("__AVX512DQ__");
+ if (HasAVX512BW)
+ Builder.defineMacro("__AVX512BW__");
+ if (HasAVX512VL)
+ Builder.defineMacro("__AVX512VL__");
if (HasSHA)
Builder.defineMacro("__SHA__");
@@ -2881,23 +2992,26 @@
.Case("avx512cd", HasAVX512CD)
.Case("avx512er", HasAVX512ER)
.Case("avx512pf", HasAVX512PF)
+ .Case("avx512dq", HasAVX512DQ)
+ .Case("avx512bw", HasAVX512BW)
+ .Case("avx512vl", HasAVX512VL)
.Case("bmi", HasBMI)
.Case("bmi2", HasBMI2)
.Case("cx16", HasCX16)
.Case("f16c", HasF16C)
.Case("fma", HasFMA)
.Case("fma4", XOPLevel >= FMA4)
- .Case("tbm", HasTBM)
+ .Case("fsgsbase", HasFSGSBASE)
.Case("lzcnt", HasLZCNT)
- .Case("rdrnd", HasRDRND)
.Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
.Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
.Case("mmx", MMX3DNowLevel >= MMX)
.Case("pclmul", HasPCLMUL)
.Case("popcnt", HasPOPCNT)
- .Case("rtm", HasRTM)
.Case("prfchw", HasPRFCHW)
+ .Case("rdrnd", HasRDRND)
.Case("rdseed", HasRDSEED)
+ .Case("rtm", HasRTM)
.Case("sha", HasSHA)
.Case("sse", SSELevel >= SSE1)
.Case("sse2", SSELevel >= SSE2)
@@ -2906,6 +3020,7 @@
.Case("sse4.1", SSELevel >= SSE41)
.Case("sse4.2", SSELevel >= SSE42)
.Case("sse4a", XOPLevel >= SSE4A)
+ .Case("tbm", HasTBM)
.Case("x86", true)
.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
@@ -2927,6 +3042,13 @@
case 'm': // any MMX register, when inter-unit moves enabled.
break; // falls through to setAllowsRegister.
}
+ case 'f': // any x87 floating point stack register.
+ // Constraint 'f' cannot be used for output operands.
+ if (Info.ConstraintStr[0] == '=')
+ return false;
+
+ Info.setAllowsRegister();
+ return true;
case 'a': // eax.
case 'b': // ebx.
case 'c': // ecx.
@@ -2934,7 +3056,6 @@
case 'S': // esi.
case 'D': // edi.
case 'A': // edx:eax.
- case 'f': // any x87 floating point stack register.
case 't': // top of floating point stack.
case 'u': // second from top of floating point stack.
case 'q': // Any register accessible as [r]l: a, b, c, and d.
@@ -2956,6 +3077,39 @@
}
}
+bool X86TargetInfo::validateOutputSize(StringRef Constraint,
+ unsigned Size) const {
+ // Strip off constraint modifiers.
+ while (Constraint[0] == '=' ||
+ Constraint[0] == '+' ||
+ Constraint[0] == '&')
+ Constraint = Constraint.substr(1);
+
+ return validateOperandSize(Constraint, Size);
+}
+
+bool X86TargetInfo::validateInputSize(StringRef Constraint,
+ unsigned Size) const {
+ return validateOperandSize(Constraint, Size);
+}
+
+bool X86TargetInfo::validateOperandSize(StringRef Constraint,
+ unsigned Size) const {
+ switch (Constraint[0]) {
+ default: break;
+ case 'y':
+ return Size <= 64;
+ case 'f':
+ case 't':
+ case 'u':
+ return Size <= 128;
+ case 'x':
+ // 256-bit ymm registers can be used if target supports AVX.
+ return Size <= (SSELevel >= AVX ? 256U : 128U);
+ }
+
+ return true;
+}
std::string
X86TargetInfo::convertConstraint(const char *&Constraint) const {
@@ -3012,18 +3166,25 @@
if (RegNo == 1) return 2;
return -1;
}
- bool validateInputSize(StringRef Constraint,
- unsigned Size) const override {
+ bool validateOperandSize(StringRef Constraint,
+ unsigned Size) const override {
switch (Constraint[0]) {
default: break;
+ case 'R':
+ case 'q':
+ case 'Q':
case 'a':
case 'b':
case 'c':
case 'd':
+ case 'S':
+ case 'D':
return Size <= 32;
+ case 'A':
+ return Size <= 64;
}
- return true;
+ return X86TargetInfo::validateOperandSize(Constraint, Size);
}
};
} // end anonymous namespace
@@ -3272,7 +3433,7 @@
class X86_64TargetInfo : public X86TargetInfo {
public:
X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
- const bool IsX32{getTriple().getEnvironment() == llvm::Triple::GNUX32};
+ const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
LongDoubleWidth = 128;
LongDoubleAlign = 128;
@@ -3283,13 +3444,13 @@
PtrDiffType = IsX32 ? SignedInt : SignedLong;
IntPtrType = IsX32 ? SignedInt : SignedLong;
IntMaxType = IsX32 ? SignedLongLong : SignedLong;
- UIntMaxType = IsX32 ? UnsignedLongLong : UnsignedLong;
Int64Type = IsX32 ? SignedLongLong : SignedLong;
RegParmMax = 6;
+ // Pointers are 32-bit in x32.
DescriptionString = (IsX32)
- ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
- : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128";
+ ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
+ : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
// Use fpret only for long double.
RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
@@ -3313,6 +3474,7 @@
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
return (CC == CC_C ||
+ CC == CC_X86VectorCall ||
CC == CC_IntelOclBicc ||
CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
}
@@ -3321,6 +3483,8 @@
return CC_C;
}
+ // for x32 we need it here explicitly
+ bool hasInt128Type() const override { return true; }
};
} // end anonymous namespace
@@ -3334,7 +3498,6 @@
LongWidth = LongAlign = 32;
DoubleAlign = LongLongAlign = 64;
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
Int64Type = SignedLongLong;
SizeType = UnsignedLongLong;
PtrDiffType = SignedLongLong;
@@ -3351,6 +3514,7 @@
}
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
return (CC == CC_C ||
+ CC == CC_X86VectorCall ||
CC == CC_IntelOclBicc ||
CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
}
@@ -3388,6 +3552,10 @@
DefineStd(Builder, "WIN64", Opts);
Builder.defineMacro("__MINGW64__");
addMinGWDefines(Opts, Builder);
+
+ // GCC defines this macro when it is using __gxx_personality_seh0.
+ if (!Opts.SjLjExceptions)
+ Builder.defineMacro("__SEH__");
}
};
} // end anonymous namespace
@@ -3401,7 +3569,7 @@
MaxVectorAlign = 256;
// The 64-bit iOS simulator uses the builtin bool type for Objective-C.
llvm::Triple T = llvm::Triple(Triple);
- if (T.getOS() == llvm::Triple::IOS)
+ if (T.isiOS())
UseSignedCharForObjCBool = false;
DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
}
@@ -3414,7 +3582,6 @@
OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
: OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
Int64Type = SignedLongLong;
}
};
@@ -3426,7 +3593,6 @@
BitrigX86_64TargetInfo(const llvm::Triple &Triple)
: BitrigTargetInfo<X86_64TargetInfo>(Triple) {
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
Int64Type = SignedLongLong;
}
};
@@ -3478,6 +3644,14 @@
unsigned CRC : 1;
unsigned Crypto : 1;
+ // ACLE 6.5.1 Hardware floating point
+ enum {
+ HW_FP_HP = (1 << 1), /// half (16-bit)
+ HW_FP_SP = (1 << 2), /// single (32-bit)
+ HW_FP_DP = (1 << 3), /// double (64-bit)
+ };
+ uint32_t HW_FP;
+
static const Builtin::Info BuiltinInfo[];
static bool shouldUseInlineAtomic(const llvm::Triple &T) {
@@ -3517,8 +3691,8 @@
DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
const llvm::Triple &T = getTriple();
- // size_t is unsigned long on Darwin and NetBSD.
- if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD)
+ // size_t is unsigned long on MachO-derived environments and NetBSD.
+ if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
SizeType = UnsignedLong;
else
SizeType = UnsignedInt;
@@ -3541,42 +3715,27 @@
ZeroLengthBitfieldBoundary = 0;
- if (IsThumb) {
- // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
- // so set preferred for small types to 32.
- if (T.isOSBinFormatMachO()) {
- DescriptionString = BigEndian ?
- "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
- "v128:64:128-a:0:32-n32-S64" :
- "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
- "v128:64:128-a:0:32-n32-S64";
- } else if (T.isOSWindows()) {
- // FIXME: this is invalid for WindowsCE
- assert(!BigEndian && "Windows on ARM does not support big endian");
- DescriptionString = "e"
- "-m:e"
- "-p:32:32"
- "-i1:8:32-i8:8:32-i16:16:32-i64:64"
- "-v128:64:128"
- "-a:0:32"
- "-n32"
- "-S64";
- } else {
- DescriptionString = BigEndian ?
- "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
- "v128:64:128-a:0:32-n32-S64" :
- "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
- "v128:64:128-a:0:32-n32-S64";
- }
+ // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
+ // so set preferred for small types to 32.
+ if (T.isOSBinFormatMachO()) {
+ DescriptionString =
+ BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
+ } else if (T.isOSWindows()) {
+ // FIXME: this is invalid for WindowsCE
+ assert(!BigEndian && "Windows on ARM does not support big endian");
+ DescriptionString = "e"
+ "-m:e"
+ "-p:32:32"
+ "-i64:64"
+ "-v128:64:128"
+ "-a:0:32"
+ "-n32"
+ "-S64";
} else {
- if (T.isOSBinFormatMachO())
- DescriptionString = BigEndian ?
- "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" :
- "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64";
- else
- DescriptionString = BigEndian ?
- "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" :
- "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64";
+ DescriptionString =
+ BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
}
// FIXME: Enumerated types are variable width in straight AAPCS.
@@ -3607,31 +3766,16 @@
/// gcc.
ZeroLengthBitfieldBoundary = 32;
- if (IsThumb) {
- // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
- // so set preferred for small types to 32.
- if (T.isOSBinFormatMachO())
- DescriptionString = BigEndian ?
- "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
- "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
- "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
- "-v64:32:64-v128:32:128-a:0:32-n32-S32";
- else
- DescriptionString = BigEndian ?
- "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
- "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
- "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
- "-v64:32:64-v128:32:128-a:0:32-n32-S32";
- } else {
- if (T.isOSBinFormatMachO())
- DescriptionString = BigEndian ?
- "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
- "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
- else
- DescriptionString = BigEndian ?
- "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
- "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
- }
+ if (T.isOSBinFormatMachO())
+ DescriptionString =
+ BigEndian
+ ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+ : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
+ else
+ DescriptionString =
+ BigEndian
+ ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+ : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
// FIXME: Override "preferred align" for double and long long.
}
@@ -3639,7 +3783,7 @@
public:
ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
: TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
- IsAAPCS(true) {
+ IsAAPCS(true), HW_FP(0) {
BigEndian = IsBigEndian;
switch (getTriple().getOS()) {
@@ -3669,8 +3813,8 @@
MaxAtomicInlineWidth = 64;
// Do force alignment of members that follow zero length bitfields. If
- // the alignment of the zero-length bitfield is greater than the member
- // that follows it, `bar', `bar' will be aligned as the type of the
+ // the alignment of the zero-length bitfield is greater than the member
+ // that follows it, `bar', `bar' will be aligned as the type of the
// zero length bitfield.
UseZeroLengthBitfieldAlignment = true;
}
@@ -3702,8 +3846,7 @@
StringRef ArchName = getTriple().getArchName();
if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
Features["vfp2"] = true;
- else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
- CPU == "cortex-a9-mp") {
+ else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
Features["vfp3"] = true;
Features["neon"] = true;
}
@@ -3712,7 +3855,7 @@
Features["neon"] = true;
} else if (CPU == "swift" || CPU == "cortex-a7" ||
CPU == "cortex-a12" || CPU == "cortex-a15" ||
- CPU == "krait") {
+ CPU == "cortex-a17" || CPU == "krait") {
Features["vfp4"] = true;
Features["neon"] = true;
Features["hwdiv"] = true;
@@ -3738,7 +3881,7 @@
ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
- } else if (CPU == "cortex-m3" || CPU == "cortex-m4") {
+ } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
Features["hwdiv"] = true;
}
}
@@ -3750,31 +3893,40 @@
Crypto = 0;
SoftFloat = SoftFloatABI = false;
HWDiv = 0;
- for (unsigned i = 0, e = Features.size(); i != e; ++i) {
- if (Features[i] == "+soft-float")
+
+ for (const auto &Feature : Features) {
+ if (Feature == "+soft-float") {
SoftFloat = true;
- else if (Features[i] == "+soft-float-abi")
+ } else if (Feature == "+soft-float-abi") {
SoftFloatABI = true;
- else if (Features[i] == "+vfp2")
+ } else if (Feature == "+vfp2") {
FPU |= VFP2FPU;
- else if (Features[i] == "+vfp3")
+ HW_FP = HW_FP_SP | HW_FP_DP;
+ } else if (Feature == "+vfp3") {
FPU |= VFP3FPU;
- else if (Features[i] == "+vfp4")
+ HW_FP = HW_FP_SP | HW_FP_DP;
+ } else if (Feature == "+vfp4") {
FPU |= VFP4FPU;
- else if (Features[i] == "+fp-armv8")
+ HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
+ } else if (Feature == "+fp-armv8") {
FPU |= FPARMV8;
- else if (Features[i] == "+neon")
+ HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
+ } else if (Feature == "+neon") {
FPU |= NeonFPU;
- else if (Features[i] == "+long64")
+ HW_FP = HW_FP_SP | HW_FP_DP;
+ } else if (Feature == "+long64") {
LongWidth = LongAlign = 64; // RenderScript uses a 64-bit long type
- else if (Features[i] == "+hwdiv")
+ } else if (Feature == "+hwdiv") {
HWDiv |= HWDivThumb;
- else if (Features[i] == "+hwdiv-arm")
+ } else if (Feature == "+hwdiv-arm") {
HWDiv |= HWDivARM;
- else if (Features[i] == "+crc")
+ } else if (Feature == "+crc") {
CRC = 1;
- else if (Features[i] == "+crypto")
+ } else if (Feature == "+crypto") {
Crypto = 1;
+ } else if (Feature == "+fp-only-sp") {
+ HW_FP &= ~HW_FP_DP;
+ }
}
if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
@@ -3788,13 +3940,13 @@
Features.push_back("-neonfp");
// Remove front-end specific options which the backend handles differently.
- std::vector<std::string>::iterator it;
- it = std::find(Features.begin(), Features.end(), "+soft-float");
- if (it != Features.end())
- Features.erase(it);
- it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
- if (it != Features.end())
- Features.erase(it);
+ const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
+ for (const auto &FEFeature : FrontEndFeatures) {
+ auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
+ if (Feature != Features.end())
+ Features.erase(Feature);
+ }
+
return true;
}
@@ -3810,40 +3962,43 @@
}
// FIXME: Should we actually have some table instead of these switches?
static const char *getCPUDefineSuffix(StringRef Name) {
- return llvm::StringSwitch<const char*>(Name)
- .Cases("arm8", "arm810", "4")
- .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
- .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
- .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
- .Case("ep9312", "4T")
- .Cases("arm10tdmi", "arm1020t", "5T")
- .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
- .Case("arm926ej-s", "5TEJ")
- .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
- .Cases("xscale", "iwmmxt", "5TE")
- .Case("arm1136j-s", "6J")
- .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
- .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
- .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
- .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
- .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A")
- .Cases("cortex-r4", "cortex-r5", "7R")
- .Case("swift", "7S")
- .Case("cyclone", "8A")
- .Case("cortex-m3", "7M")
- .Case("cortex-m4", "7EM")
- .Case("cortex-m0", "6M")
- .Cases("cortex-a53", "cortex-a57", "8A")
- .Default(nullptr);
+ return llvm::StringSwitch<const char *>(Name)
+ .Cases("arm8", "arm810", "4")
+ .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
+ "4")
+ .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
+ .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
+ .Case("ep9312", "4T")
+ .Cases("arm10tdmi", "arm1020t", "5T")
+ .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
+ .Case("arm926ej-s", "5TEJ")
+ .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
+ .Cases("xscale", "iwmmxt", "5TE")
+ .Case("arm1136j-s", "6J")
+ .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
+ .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
+ .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
+ .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
+ .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
+ "7A")
+ .Cases("cortex-r4", "cortex-r5", "7R")
+ .Case("swift", "7S")
+ .Case("cyclone", "8A")
+ .Case("cortex-m3", "7M")
+ .Cases("cortex-m4", "cortex-m7", "7EM")
+ .Case("cortex-m0", "6M")
+ .Cases("cortex-a53", "cortex-a57", "8A")
+ .Default(nullptr);
}
static const char *getCPUProfile(StringRef Name) {
- return llvm::StringSwitch<const char*>(Name)
- .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
- .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A")
- .Cases("cortex-a53", "cortex-a57", "A")
- .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
- .Cases("cortex-r4", "cortex-r5", "R")
- .Default("");
+ return llvm::StringSwitch<const char *>(Name)
+ .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
+ .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
+ "A")
+ .Cases("cortex-a53", "cortex-a57", "A")
+ .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
+ .Cases("cortex-r4", "cortex-r5", "R")
+ .Default("");
}
bool setCPU(const std::string &Name) override {
if (!getCPUDefineSuffix(Name))
@@ -3883,9 +4038,8 @@
StringRef CPUArch = getCPUDefineSuffix(CPU);
unsigned int CPUArchVer;
- if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
+ if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
llvm_unreachable("Invalid char for architecture version number");
- }
Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
// ACLE 6.4.1 ARM/Thumb instruction set architecture
@@ -3894,6 +4048,10 @@
// __ARM_ARCH is defined as an integer value indicating the current ARM ISA
Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+ if (CPUArch[0] >= '8') {
+ Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
+ Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
+ }
// __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
// is not defined for the M-profile.
@@ -3919,6 +4077,10 @@
if (!CPUProfile.empty())
Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
+ // ACLE 6.5.1 Hardware Floating Point
+ if (HW_FP)
+ Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
+
// ACLE predefines.
Builder.defineMacro("__ARM_ACLE", "200");
@@ -4056,8 +4218,9 @@
}
return R;
}
- bool validateConstraintModifier(StringRef Constraint, const char Modifier,
- unsigned Size) const override {
+ bool
+ validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
+ std::string &SuggestedModifier) const override {
bool isOutput = (Constraint[0] == '=');
bool isInOut = (Constraint[0] == '+');
@@ -4285,7 +4448,8 @@
: DarwinTargetInfo<ARMleTargetInfo>(Triple) {
HasAlignMac68kSupport = true;
// iOS always has 64-bit atomic instructions.
- // FIXME: This should be based off of the target features in ARMleTargetInfo.
+ // FIXME: This should be based off of the target features in
+ // ARMleTargetInfo.
MaxAtomicInlineWidth = 64;
// Darwin on iOS uses a variant of the ARM C++ ABI.
@@ -4306,7 +4470,6 @@
NeonMode
};
- std::string CPU;
unsigned FPU;
unsigned CRC;
unsigned Crypto;
@@ -4326,12 +4489,10 @@
// across 64-bit targets.
Int64Type = SignedLongLong;
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
} else {
WCharType = UnsignedInt;
Int64Type = SignedLong;
IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
}
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
@@ -4352,7 +4513,7 @@
}
StringRef getABI() const override { return ABI; }
- virtual bool setABI(const std::string &Name) {
+ bool setABI(const std::string &Name) override {
if (Name != "aapcs" && Name != "darwinpcs")
return false;
@@ -4360,19 +4521,17 @@
return true;
}
- virtual bool setCPU(const std::string &Name) {
+ bool setCPU(const std::string &Name) override {
bool CPUKnown = llvm::StringSwitch<bool>(Name)
.Case("generic", true)
.Cases("cortex-a53", "cortex-a57", true)
.Case("cyclone", true)
.Default(false);
- if (CPUKnown)
- CPU = Name;
return CPUKnown;
}
virtual void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
+ MacroBuilder &Builder) const override {
// Target identification.
Builder.defineMacro("__aarch64__");
@@ -4393,6 +4552,10 @@
Builder.defineMacro("__ARM_FEATURE_CLZ");
Builder.defineMacro("__ARM_FEATURE_FMA");
Builder.defineMacro("__ARM_FEATURE_DIV");
+ Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
+ Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
+ Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
+ Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
@@ -4406,7 +4569,7 @@
if (Opts.FastMath || Opts.FiniteMathOnly)
Builder.defineMacro("__ARM_FP_FAST");
- if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
+ if (Opts.C99 && !Opts.Freestanding)
Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
@@ -4428,34 +4591,17 @@
}
virtual void getTargetBuiltins(const Builtin::Info *&Records,
- unsigned &NumRecords) const {
+ unsigned &NumRecords) const override {
Records = BuiltinInfo;
NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
}
- virtual bool hasFeature(StringRef Feature) const {
+ bool hasFeature(StringRef Feature) const override {
return Feature == "aarch64" ||
Feature == "arm64" ||
(Feature == "neon" && FPU == NeonMode);
}
- void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
-
- if (CPU == "cyclone") {
- Features["fp-armv8"] = true;
- Features["neon"] = true;
- Features["crypto"] = true;
- Features["crc"] = true;
- Features["zcm"] = true;
- Features["zcz"] = true;
- } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
- Features["fp-armv8"] = true;
- Features["neon"] = true;
- Features["crypto"] = true;
- Features["crc"] = true;
- }
-}
-
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
FPU = FPUMode;
@@ -4475,19 +4621,20 @@
return true;
}
- virtual bool isCLZForZeroUndef() const { return false; }
+ bool isCLZForZeroUndef() const override { return false; }
- virtual BuiltinVaListKind getBuiltinVaListKind() const {
+ BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::AArch64ABIBuiltinVaList;
}
virtual void getGCCRegNames(const char *const *&Names,
- unsigned &NumNames) const;
+ unsigned &NumNames) const override;
virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
- unsigned &NumAliases) const;
+ unsigned &NumAliases) const override;
- virtual bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const {
+ virtual bool
+ validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) {
default:
return false;
@@ -4510,11 +4657,11 @@
Info.setAllowsRegister();
return true;
case 'U':
- // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
- // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
- // Usa: An absolute symbolic address
- // Ush: The high part (bits 32:12) of a pc-relative symbolic address
- llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
+ // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
+ // Utf: A memory address suitable for ldp/stp in TF mode.
+ // Usa: An absolute symbolic address.
+ // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
+ llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
case 'z': // Zero register, wzr or xzr
Info.setAllowsRegister();
return true;
@@ -4525,9 +4672,40 @@
return false;
}
- virtual const char *getClobbers() const { return ""; }
+ bool
+ validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
+ std::string &SuggestedModifier) const override {
+ // Strip off constraint modifiers.
+ while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
+ Constraint = Constraint.substr(1);
- int getEHDataRegisterNumber(unsigned RegNo) const {
+ switch (Constraint[0]) {
+ default:
+ return true;
+ case 'z':
+ case 'r': {
+ switch (Modifier) {
+ case 'x':
+ case 'w':
+ // For now assume that the person knows what they're
+ // doing with the modifier.
+ return true;
+ default:
+ // By default an 'r' constraint will be in the 'x'
+ // registers.
+ if (Size == 64)
+ return true;
+
+ SuggestedModifier = "w";
+ return false;
+ }
+ }
+ }
+ }
+
+ const char *getClobbers() const override { return ""; }
+
+ int getEHDataRegisterNumber(unsigned RegNo) const override {
if (RegNo == 0)
return 0;
if (RegNo == 1)
@@ -4662,7 +4840,7 @@
TheCXXABI.set(TargetCXXABI::iOS64);
}
- virtual BuiltinVaListKind getBuiltinVaListKind() const {
+ BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::CharPtrBuiltinVaList;
}
};
@@ -4953,13 +5131,10 @@
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
// OpenBSD uses long long for int64_t and intmax_t.
- if (getTriple().getOS() == llvm::Triple::OpenBSD) {
+ if (getTriple().getOS() == llvm::Triple::OpenBSD)
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
- } else {
+ else
IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
- }
Int64Type = IntMaxType;
// The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
@@ -4975,10 +5150,8 @@
SparcTargetInfo::getTargetDefines(Opts, Builder);
Builder.defineMacro("__sparcv9");
Builder.defineMacro("__arch64__");
- // Solaris and its derivative AuroraUX don't need these variants, but the
- // BSDs do.
- if (getTriple().getOS() != llvm::Triple::Solaris &&
- getTriple().getOS() != llvm::Triple::AuroraUX) {
+ // Solaris doesn't need these variants, but the BSDs do.
+ if (getTriple().getOS() != llvm::Triple::Solaris) {
Builder.defineMacro("__sparc64__");
Builder.defineMacro("__sparc_v9__");
Builder.defineMacro("__sparcv9__");
@@ -5005,14 +5178,6 @@
} // end anonymous namespace.
namespace {
-class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
-public:
- AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
- : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
- SizeType = UnsignedInt;
- PtrDiffType = SignedInt;
- }
-};
class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
public:
SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
@@ -5141,11 +5306,10 @@
SuitableAlign = 16;
SizeType = UnsignedInt;
IntMaxType = SignedLongLong;
- UIntMaxType = UnsignedLongLong;
IntPtrType = SignedInt;
PtrDiffType = SignedInt;
SigAtomicType = SignedLong;
- DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16";
+ DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
@@ -5170,8 +5334,9 @@
Aliases = nullptr;
NumAliases = 0;
}
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const override {
+ bool
+ validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &info) const override {
// No target constraints for now.
return false;
}
@@ -5229,7 +5394,6 @@
SuitableAlign = 32;
SizeType = UnsignedInt;
IntMaxType = SignedLong;
- UIntMaxType = UnsignedLong;
IntPtrType = SignedInt;
PtrDiffType = SignedInt;
FloatWidth = 32;
@@ -5458,10 +5622,9 @@
switch (*Name) {
default:
return false;
-
case 'r': // CPU registers.
case 'd': // Equivalent to "r" unless generating MIPS16 code.
- case 'y': // Equivalent to "r", backwards compatibility only.
+ case 'y': // Equivalent to "r", backward compatibility only.
case 'f': // floating-point registers.
case 'c': // $25 for indirect jumps
case 'l': // lo register
@@ -5821,7 +5984,6 @@
this->PointerAlign = 32;
this->PointerWidth = 32;
this->IntMaxType = TargetInfo::SignedLongLong;
- this->UIntMaxType = TargetInfo::UnsignedLongLong;
this->Int64Type = TargetInfo::SignedLongLong;
this->DoubleAlign = 64;
this->LongDoubleWidth = 64;
@@ -5879,6 +6041,60 @@
} // end anonymous namespace.
namespace {
+class Le64TargetInfo : public TargetInfo {
+ static const Builtin::Info BuiltinInfo[];
+
+public:
+ Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
+ BigEndian = false;
+ NoAsmVariants = true;
+ LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
+ MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+ DescriptionString =
+ "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64";
+ }
+
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
+ DefineStd(Builder, "unix", Opts);
+ defineCPUMacros(Builder, "le64", /*Tuning=*/false);
+ Builder.defineMacro("__ELF__");
+ }
+ void getTargetBuiltins(const Builtin::Info *&Records,
+ unsigned &NumRecords) const override {
+ Records = BuiltinInfo;
+ NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
+ }
+ BuiltinVaListKind getBuiltinVaListKind() const override {
+ return TargetInfo::PNaClABIBuiltinVaList;
+ }
+ const char *getClobbers() const override { return ""; }
+ void getGCCRegNames(const char *const *&Names,
+ unsigned &NumNames) const override {
+ Names = nullptr;
+ NumNames = 0;
+ }
+ void getGCCRegAliases(const GCCRegAlias *&Aliases,
+ unsigned &NumAliases) const override {
+ Aliases = nullptr;
+ NumAliases = 0;
+ }
+ bool validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &Info) const override {
+ return false;
+ }
+
+ bool hasProtectedVisibility() const override { return false; }
+};
+} // end anonymous namespace.
+
+const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS) \
+ { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
+#include "clang/Basic/BuiltinsLe64.def"
+};
+
+namespace {
static const unsigned SPIRAddrSpaceMap[] = {
1, // opencl_global
3, // opencl_local
@@ -5918,8 +6134,9 @@
}
void getGCCRegNames(const char * const *&Names,
unsigned &NumNames) const override {}
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const override {
+ bool
+ validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &info) const override {
return true;
}
void getGCCRegAliases(const GCCRegAlias *&Aliases,
@@ -6047,11 +6264,12 @@
return new HexagonTargetInfo(Triple);
case llvm::Triple::aarch64:
- case llvm::Triple::arm64:
if (Triple.isOSDarwin())
return new DarwinAArch64TargetInfo(Triple);
switch (os) {
+ case llvm::Triple::FreeBSD:
+ return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
case llvm::Triple::Linux:
return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
case llvm::Triple::NetBSD:
@@ -6061,8 +6279,9 @@
}
case llvm::Triple::aarch64_be:
- case llvm::Triple::arm64_be:
switch (os) {
+ case llvm::Triple::FreeBSD:
+ return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
case llvm::Triple::Linux:
return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
case llvm::Triple::NetBSD:
@@ -6201,6 +6420,9 @@
return nullptr;
}
+ case llvm::Triple::le64:
+ return new Le64TargetInfo(Triple);
+
case llvm::Triple::ppc:
if (Triple.isOSDarwin())
return new DarwinPPC32TargetInfo(Triple);
@@ -6255,8 +6477,6 @@
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
- case llvm::Triple::AuroraUX:
- return new AuroraUXSparcV8TargetInfo(Triple);
case llvm::Triple::Solaris:
return new SolarisSparcV8TargetInfo(Triple);
case llvm::Triple::NetBSD:
@@ -6273,8 +6493,6 @@
switch (os) {
case llvm::Triple::Linux:
return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
- case llvm::Triple::AuroraUX:
- return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
case llvm::Triple::Solaris:
return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
case llvm::Triple::NetBSD:
@@ -6303,8 +6521,6 @@
return new DarwinI386TargetInfo(Triple);
switch (os) {
- case llvm::Triple::AuroraUX:
- return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
case llvm::Triple::Linux:
return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
case llvm::Triple::DragonFly:
@@ -6351,8 +6567,6 @@
return new DarwinX86_64TargetInfo(Triple);
switch (os) {
- case llvm::Triple::AuroraUX:
- return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
case llvm::Triple::Linux:
return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
case llvm::Triple::DragonFly: